CA1040541A - Method of, and apparatus for, printing grey-tone images - Google Patents

Method of, and apparatus for, printing grey-tone images

Info

Publication number
CA1040541A
CA1040541A CA231,750A CA231750A CA1040541A CA 1040541 A CA1040541 A CA 1040541A CA 231750 A CA231750 A CA 231750A CA 1040541 A CA1040541 A CA 1040541A
Authority
CA
Canada
Prior art keywords
clock
gates
gate
dot
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA231,750A
Other languages
French (fr)
Inventor
Ernst Bunge
Ulf Rothgordt
Bernd Ehlers
Herbert Piotrowski
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Gloeilampenfabrieken NV filed Critical Philips Gloeilampenfabrieken NV
Application granted granted Critical
Publication of CA1040541A publication Critical patent/CA1040541A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N1/00Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
    • H04N1/40Picture signal circuits
    • H04N1/405Halftoning, i.e. converting the picture signal of a continuous-tone original into a corresponding signal showing only two levels
    • H04N1/4051Halftoning, i.e. converting the picture signal of a continuous-tone original into a corresponding signal showing only two levels producing a dispersed dots halftone pattern, the dots having substantially the same size

Abstract

ABSTRACT OF THE DISCLOSURE

Method and apparatus for producing a grey-tone image having areas of different average density values which are given by an n-digit binary number, all the bits of the binary number being interrogated in parallel by clock patterns. For the area to be printed an elemental area containing 2n pulses is selected which is printed in a total cycle or 2n-1 clock pulses or the clock pattern. In this total cycle, at each clock pulse the drive of each pair of dots is determined in a manner such that the most-significant bit of the binary number is always used for driving while the remaining bits are used a number of times which depends upon their positional values. For this purpose, for each position of the binary number the clock pattern has a number of clock pulses which corresponds to the value of this position. The clock pulses for the individual positions are non-uniformly distributed in time, however, no clock pulses for the second and any further positions of the binary number coincide in time. Before each new print line the pattern will if required be shifted by additional clock pulses.

Description

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The invention relates to a method of printing grey-tone images having areas of different average den-sities by means of a printer which successively prints dot lines which extend at right angles to the paper feed direction.
In many graphic and recording devices and printers printing is effected in that the graphic in-formation to be displayed is composed of individual dots. These dots are produced in various manners, for example by printing needles driven electromagnetically or by charged pin-shaped electrodes which produce sub-stantially dot-shaped charges on the paper which subse-quently are developed and fixed. Each individual dot mostly provides a single density value only and no gradation for different grey tones. In order to produce images which have grey tones, i.e. areas of different densities, in the relevant area of the image not all the dots but, depending upon the desired density, only part of the dots are printed. Such grey-tone images are suitable, for example, when graphs of two indepen-dent variables are to be plotted, for exa~ple the variation with `time of the spectrum in dynamic acoustic ; processes. In such a graph the variables have discrete values and the energy in a plurality of frequency ranges . ,~

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P~D 7/11~8 11.7.75 - :~04~S41 is to be shown in individual periods of time. Thus the image to be printed is composed of separate areas which each con+ain the same number of dots. The number of pos-sible grey shades depends upon the individual areas and the possible number of dots therein. To obtain the im-pression of a substantially uniform grey value a large-ly random distribution of the dots to be printed in an area is required so as -to prevent -the occurrence of disturbing periodic structures.
,' 10 It is an object of the prosent invention to provido a method in which a density value :in the form of a b:Lnary num`ber is converted in the simpiest pos-sible manner into a dot pattern so that th0 number of ;'~ the dots printed in the area is linearly associated with the binary number and the distribution of the dots in a substantially statistic manner is effected without ~ disturbing periodicity of the dots printed. ~ccording to the invention this is achieved in that with a den-sity value given by a n~digit binary number an elemental area containing 2 dot;s is selected for each of a plu-rality o~ areas arranged in rows and columns, the binary number being so converted into two pulse pat-terns comprising a number of pulsesequal to the value of the binary number in a total cycle of 2n _ 1 clock periods that in the first pulse pattern when the most-,~ significant bit of the binary nwnber differs from zero a pulse is generated in each clock period whilst in the ~,-: . .
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. ~04~)Si4 second pulse pattern for each other bit which differs from zero, pulses are generated in a number equal to the positional value of this bit, in the second puls~
pattern the pulses generated for bits of different positional ~alues do not coincide in time, the pulses of the two pulse patterns being used after each clock . . .
period for causing another dot pair from the elemental "' ' area to be printed.
;~ The elemental area-appropriately is a rectangle . - `
~1 10 and consists of lines which each comprise the same even number of dots, oach sald dot pair comprising two juxta-positloned dots in a llne.
.: ~
¦ To approach even more closely to a statistical .. . .
, : distribution of the printed dots, the association of the two pulse patterns with the dots of a dot pair can be interchanged in statistical sequence between the clock -- periods. The pulses for each bit of the binary number are generated in fixed~y non-uniform distrlbution in time.
An apparatus for carrying out the method in-i ~ . , 3 cludes a clock pattern generator which has an ou-tput ,...
for each position of the binary number and the outputs ~-I except a first output generating a number of non-uni-: r. I
~ formly distributed clock pulses, which number corres-`~ 25 ponds to the positional value of the associated binary position. Each clock pulse output is connected to one .. .. .
" input of an AND gate to the other input of which is . ~,,;
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applied -the signal of the corresponding position of the binary number, the outputs of the AND gates delivering the signals for the circuits which cause the dots to be printed. ~ :
In accordance with the present invention there is provided .
a logic circuit for a gre~-tone image printer comprising a clock pattern generator having a plurality of outputs, each of said outputs producing a distinct clock pulse pattern with a dlfferent predetermined . ~:
.. ..
number of clock pulses within a predetermined time interval; input ;`
means for supplying a digital representation of the density value of .. ~:
an image to be printed; a first and second group of AND-gates, each of said groups comprising at least one AND-gate, each of said AND-gates ;~ .
having a first input to a correspondine bit of said digital representation, :;
a second input connected to a correspondine output o~ said clock pattern j. .:.
generator, and an output; and OR-gate, having a plurality of inputs connected to said outputs of said first group of said AND-gates, and .
an output; first and second driving circuits for printing a dot pair, .
.. . .i having first and second inputs respectively for activation of the corresponding driving circuits, said first driving circuit for printing ~;
. the first dot, and said second driving circuit for printing the second ;
, 20 dot of said dot pair; a change-over switch, connecting said first and ; second inputs of said drivine circuits ~ith said output of said OR-gate, and said outputs of said second group of AND-gates; and means for switching said change-over switch comprising a random signal generator with a synchronized output.
Embodiments of the inrention ~ill now be described, by way ; of e~ample, with reference to the accompanying diagrammatic drawings, , in which ~
Fig. 1 is a block schematic diagram of an apparatus for ~ :
converting the binary numbers into dot patterns, Fig. 2 shows the circuit arrangement for drlving the clock ~ .

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104~5~1 pulse pattern generator which provides the clock signals for the apparatus of Fig. 1, Fig. 3 sho~s a clock pulse pattern of the clock pulse pattern generator, and Fig. 4 sho~s the structure and the arrangement o~ the elemental areas.
Fig. 1 sho~s AND gates Gl, G2, G3, ...~ Gn which each ha~e t~o inputs, to one of ~hich Bl, B2~ B3, ..., Bn respecti~ely the signal of the corresponding position of a binary number is applied.
Thus the signal for the most-significant bit of an n-digit binary number is supplied to the input Bl, and the signal for the least-significan-t bit of the binary number is supplied to the input Bn.
This binary number may be supplied to the appara-tus from outside, ~or example by a computer, or it may be stored in parallel ~ .

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in a store, not shown, of the apparatus~To the other input of the AN~-gates G1, ..~, Gn a clock signal T1, ;~ T2, .... , Tn respectively is applied which may be generated, for example, by a clock pattern generator TMG shown in Fig. 2 at the respeciive output. In the i;: . .
- case of an n-digi-t binary number, for which according-ly each area contains 2 dots which are prin-ted in a total cycle of 2 1 clock periods o~ a main clock signal CP1, tho cLoclc signal T1 comprises a pulse lQ ~or each clock por:Lod of tho ma:ln clock slgna:L, the '.,~, .
elock signal T2 on average eomprises a elock pulse for every second clock period of the main clock sig-.,.................................... , . I
~ nal, the clock signal T3 comprises on average one ,.. ~, , .
clock pulse for every fourth clock period of the main ,, .
clock signal, and so on, and finally the clock signal Tn comprises only a single clock pulse in each entire ~ - cycle. rhe eLock pulses in the individual clock signals ,¦ T2 and so on are non-unif`ormly distributed in time, with ~ the exception of the final clock signal T~ for which ; 20 obviously non-uniform distribution is not possible.
~-~ An example of such a clock pattern is shown in Fig. 3 ;;l for n = 5.
In Fig. 1 the output of the AND gate G1 pro-vides a driving signal for one of two driving circuits 1 2~ A1, A2, and the outputs of the remaining AND gates G2, G3, ..., Gn are connected to an OR gate GO the output ~ of which provides the driving signal for the other of ;`~ .
:i :' ~oi~si~
th~ two driving circuits Al, A2. me two driving cir- `
cuits Al and A2, which each control the printing of a single dot, each have a change-over switch Sl and S2 ` respectively included in their signal input path which when changed over interchange the connecting lines to the driving circuits Al, A2. The switches Sl and S2 are controlled by a random signal generator ZG the output signal of which is synchronized with the main clock CPl. The switches Sl and S2 appropriately take the form of electronic switches.
Because the output signals of the AND gates ; G2 to Gn are all applled to the OR gate GO, it will be clear that the clock pulses in the clock signals T2, T3, ..., Tn must not occur simultaneously, because otherwise only a single dot would be printed for the simultaneously occurring clock pulses. A possible clock pattern is shown in Figure 3 and comprises a total cycle of 16 (=2n-1 with n = 5) clock periods which conse-quently enables at most 31 (=2n - 1) dots to be printed in an elemental area. ` `
The said clock pattern is generated in the , clock pattern generator TMG which is shown in Figure 2 and may be constructed in a usual manner as a binary counter with suitable decoding. During printing this clock pattern is controlled by a main clock signal CPl which is applied to the clock pattern generator ; TMG via an AND gate G10 and an OR gate G13 and controls `
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the printing operation from dot pair to dot pair or is synchronized therewith. Furthermore the clock pulse generator TMG has further clock signals ~CP2) applied to it which are necessary because conventional dot ;printers, particularly electrostatic dot printers, do not complete the printing of an entire elemental ... . .
;- area before beginning with the next entire elemental area, but print one row of dots after the other, which rows aro corresponding rows of a sequence of juxtaposed elemental areas. This will be explained ; more ~ully wi-th ro~`eronce to Fig. 1~, Flg. I~ shows by way of example a graph in , which amplitudes of a plurality of frequency ranges are plotted against time t. The paper is fed forward in the direction of the axis t and printing is effected in the direction of the axis f. The elemental areas El, E2, E3, ..., Ek are arranged side by side in the direc-tion of the printing lines. Each elementary area contains 2n = 32 dots for n = 5 which are arranged in a rectangle .; . . .
the sides of which are 2 = ~l and 2 = 8 dots in length respectively, where 1 = 2, m = 3 and 1 t m = n = 5.
.:~
Thus a 5-digit binary number can be linearly converted into density values. Fig. 4 corresponds with a grey-::~
~I tone image with a medium grey gradation according to ;l 25 the binary number 10000.

; Consequently in a printer which prints com-plete dot rows corresponding lines o~ the juxtaposed : .
' .1 , . , ~ - .

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P~ID 71~128 1107.75 . .~ .

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elemental areas E1, E2, E3, ..., Ek are printed conse-cutively. Because a line of each elemental area comprises 4 dots and hence 2 dot pairs only, printing of a line of an elemental area takes only a fractional part of the duration of the entire cycle of the clock pattern-` Thus for the next elemen-tal area the clock pattern commences at a corresponding different place; however, initially this is not of importance, because it is only required that in each elomental area the clock pattern is completely passed through onco. If, however, the number k of the ~uxtaposed eleltlental areas :Ls equal to the :Line nurnber 2 or to an integral multiple there-of, at the beginning of a new printing line the clock ~ pattern would always begin at the same place as for the ;~ 15 preceding line, so that in each elemental area the same :. .1 . .
-~ fraction of the clock pattern would always be travers-~ ed. A similar condition applies when the number k of ~"~
I the elemental areas and the number of lines 2m of each ;` elementa:L area have a comrnon denorrlinator, for in this ; 20 case given parts only of the clock pattern would re-~; peatedly be traversed. If this is to he prevented, be-fore a new printing line is begun the clock pattern in the clock pattern generator must be suitably shift-~; ed.
Thus at -the beglnning of a new row of elemen-~; tal areas the clock pattern would start at the same place at which it began for the preceding row of ele-.',,~, ' .
.-.,~: .

; _ 9 `

PHD 7/~12 11.7.75 S~l clock signal CP2 is also supplied to a counter Z2, which delivers an output signal U2 resetting the fiip-flop F2, Because the capacity 2 of the counter Z2 is equal to the number of dot pairs per line of an elemental area, at the beginning of a new line the clock pattern is thus shifted by the fractional part traversed during a line of an elemen-tal area. Furthermore the reset of the flip-flop F2 causes the flip-flop F1 to be set again so that the output Q1 again applies the main clock signa:L CP1 to thc clook pattern generator TMG. This occurs aftor each comp:Lete lino of dots printed.
The capacity 2 of the counter Z1 is equal to the number of lines per elemental area. Hence when an elemental area or a series of elemental areas has been printed, at the end of the last line the counter 21 on reception of the signal LL produces an output signal U1 which sets the flip-flop F3. The outout sig-~! nal Q3 o~` this flipflop then via the OR gate G12 and th~ AND gate G11 enables the auxiliary clock signal CP2 to be applied to the clock pattern generator TMG, until the signal NL appears and resets the flip-flop F3 again.
Because the spacing between the signals EL and NL
fluctuates statistically, at the beginning of a new series of elemen-tal areas the clock pattern generator
2 25 TMG receives a statistically de-termined number of ad-ditional clock pulses. It i9 assumed that in the interval ,~,. . .
~ between the two signals EL and NL the auxiliary clock ;J
... .

.
,,:
`,' - 11 -,, : ` ~

11.7.75 .~ , 5~1 mental areas. If two elemental areas which succeed one another on the axis t have the sarne binary value, i.e the same density, a certain troublesome periodicity , ................................ .
of the dot pattern would occur. To prevent such perio-dicity, at the beginnlng of a new row of elemental areas ; a statistically determined number of additional clock ,~ pulses is supplied to -the clockpattern generator TMG
of Fig. 2. -~' This i.9 ef~ectod by the circuit arrangement :l 10 shown in Fig. 2. Initially it is assumed that a flip-~s, flop F1 is in a stato such that tho output signal Ql I with a logic I enahlos the AND gate G10 so that the `l main olock signal CP1 is supplied to the clock pattern generator TMG via the AND gate G10 and the OR gate G13.
At the end of a complete line of dots a signal EL ap-.,; .~; . .
:, pears which resets the flip-flop Fl and advances a i!
counter Z1 one posltlon. As a result, supply of the main clock signal CP1 to the clock pattern generator TMG is interrupted.
At the beglnning of a new line of dots a signal NL appears which resets a flip-flop F3, is not ~ already in the reset state. ~urthermore a flip-flop F2 '~ is set so that via an OR gate 12 ~d an AND gate G11 .,,:, , ' a signal Q2 with a logic 1 enables an auxiliary clock signal CP2to be supplied to the clock pattern generator ....
;;" TMG via the OR gate 13. At the same time the signal Q2 also enables an AND gate G1l~ so that the auxiliary . .
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., ~ , 11.7.75 ~46~S4 lL
signal CP2 contains a large number a~ clock pulses.
~his auxiliary clock signal CP2 may have a materially higher frequency than the main clock signal CP1.
Thus it is ensured -that binary values are linearly converted into densi-ty values without the pbssibility of inconvenient periodicities occurring.
In the description AND and OR ga-tes are used as logical ga-tes. Also NAND and NOR gates could have ', been described, I-t is known that in dependancy of ,' 10 a positiva or negative logic AND and NOR gates have the same logical function. The sarne applies for OX
and NAND gates~ ~
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Claims (2)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A logic circuit for a grey-tone image printer comprising a clock pattern generator having a plurality of outputs, each of said outputs producing a distinct clock pulse pattern with a different predetermined number of clock pulses within a predetermined time interval, input means for supplying a digital representation of the density value of an image to be printed; a first and second group of AND-gates, each of said groups comprising at least one AND-gate, each of said AND-gates having a first input to a corresponding bit of said digital representation, a second in-put connected to a corresponding output of said clock pattern generator, and an output; and OR-gate, having a plurality of inputs connected to said outputs of said first group of said AND-gates, and an output; first and second driving circuits for printing a dot pair, having first and second inputs respectively for activation of the corresponding driving circuits, said first driving circuit for printing the first dot, and said second driving circuit for printing the second dot of said dot pair; a change-over switch, connecting said first and second inputs of said driving cir-cuits with said output of said OR-gate, and said outputs of said second group of AND-gates; and means for switching said change-over switch com-prising a random signal generator with a synchronized output.
2. The circuit as defined in claim 1, wherein said second group of AND-gates comprises a single AND-gate having a first input connected to the most-significant-bit of said digital representation.
CA231,750A 1974-07-22 1975-07-18 Method of, and apparatus for, printing grey-tone images Expired CA1040541A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2435090A DE2435090C2 (en) 1974-07-22 1974-07-22 Method and arrangement for printing gray-tone images

Publications (1)

Publication Number Publication Date
CA1040541A true CA1040541A (en) 1978-10-17

Family

ID=5921141

Family Applications (1)

Application Number Title Priority Date Filing Date
CA231,750A Expired CA1040541A (en) 1974-07-22 1975-07-18 Method of, and apparatus for, printing grey-tone images

Country Status (7)

Country Link
US (1) US4033443A (en)
JP (1) JPS5653794B2 (en)
BE (1) BE831553A (en)
CA (1) CA1040541A (en)
DE (1) DE2435090C2 (en)
FR (1) FR2279555A1 (en)
GB (1) GB1510849A (en)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5481013A (en) * 1977-12-12 1979-06-28 Hitachi Ltd Intermediate tone recording sysem
JPS54107119U (en) * 1978-01-13 1979-07-27
US4242003A (en) * 1978-10-16 1980-12-30 Xerox Corporation Multi-pass matrix printing
US4189754A (en) * 1978-11-24 1980-02-19 The Mead Corporation Gray tone reproduction apparatus
DE2931098C2 (en) * 1979-07-31 1983-01-05 Dr.-Ing. Rudolf Hell Gmbh, 2300 Kiel Process for the production of printing plates
DE2943018C3 (en) * 1979-10-24 1982-05-13 Siemens AG, 1000 Berlin und 8000 München Method and arrangement for displaying a halftone image
JPS57193173A (en) * 1981-05-22 1982-11-27 Fuji Photo Film Co Ltd Picture scanning and recording method
US4413269A (en) * 1981-11-23 1983-11-01 International Business Machines Corporation Method of and apparatus for controlling gray scale while printing on charge sensitive recording mediums
JPS58167108U (en) * 1982-04-30 1983-11-08 東芝住宅工業株式会社 Drainage structure
JPH0666872B2 (en) * 1983-07-28 1994-08-24 富士ゼロックス株式会社 Thermal halftone recording device
US4680596A (en) * 1984-08-02 1987-07-14 Metromedia Company Method and apparatus for controlling ink-jet color printing heads
JPH0635019Y2 (en) * 1988-11-15 1994-09-14 松下電工株式会社 A structure for housing the rising part of the outer wall
JPH02162871A (en) * 1988-12-15 1990-06-22 Dainippon Screen Mfg Co Ltd Dot forming method
JPH07578Y2 (en) * 1990-04-26 1995-01-11 ナショナル住宅産業株式会社 Draining structure between the roof of the partial flat and the second floor wall

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3604846A (en) * 1969-03-03 1971-09-14 Mead Corp Method and system for reconstruction of half-tone images
NL7316557A (en) * 1972-12-07 1974-06-11
JPS5222494B2 (en) * 1972-12-15 1977-06-17
DE2262824C3 (en) * 1972-12-22 1975-07-10 Dr.-Ing. Rudolf Hell Gmbh, 2300 Kiel Process for the rasterized reproduction of colored halftone images in single or multi-color printing
US3863023A (en) * 1973-02-28 1975-01-28 Owens Illinois Inc Method and apparatus for generation of gray scale in gaseous discharge panel using multiple memory planes

Also Published As

Publication number Publication date
GB1510849A (en) 1978-05-17
DE2435090A1 (en) 1976-02-12
FR2279555B1 (en) 1979-06-15
DE2435090C2 (en) 1982-06-03
JPS5136930A (en) 1976-03-29
JPS5653794B2 (en) 1981-12-21
BE831553A (en) 1976-01-19
FR2279555A1 (en) 1976-02-20
US4033443A (en) 1977-07-05

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