CA1049151A - Method and apparatus for synchronizing master and local time base systems - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE

A plurality of widely separated local time base systems are synchronized with a master time base system by means of digitally encoded radio signals. All of the time base systems comprise oscillator driven digital clocks which produce a cyclically recurring series of sequential time slots which are individually assigned to the master and local systems to provide time division multiple access to the master system from each local system. Coarse time synchronization is obtained by the transmission of a coarse synchronization signal from the master to each local system at the beginning of the series of slots in the master's time base which resets all local time bases to the beginning of the series of slots.
Fine synchronization is mate during the individual time slot assigned to each local system by the transmission of fine synchronization request and fine synchronization reply signals which are utilized to produce a synchronization error signal in each local system. The error signal is employed to generate frequency and phase corrections for the local oscillator and time corrections for the local clock in accordance with a programmed control state sequence in which the oscillator and clock correction gains used for a particular correction are determined by the number of system cycles between fine corrections and the magnitude of the error. A digital filter technique is utilizcd which approximates the operation of a simple Kalman filter.

Description

1~49~5~L

¦ BACKGROUND OF THE ~NVENTION
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l 1. Field of the Invention l . '~ ' This invention relates to time base system synchron-ization and more particularly to a method and apparatus for synchronizing one or more remotely located local clocks and oscillator frequencies with a master clock and master oscillator ¦ frequency.
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2. Descri~ of the Prior Art . .

Community navigatlon and control systems have been developed which permit a plurality of user aircraft, ships or ~other vehicles forming an operating community to navigate and be controlled by navigation and guidance signals received from a master or control aircraft, shipl vehicle or ground .
l station. The user members of the commilnity are linked to each ¦ other and to the master unit by radio linkages which employ ¦ digitally encoded signals for identification, event timing and data transmission. The radio ranging signals permit ¦ navigation by trilateration computations and transmit master I ¦ naviga~ional data from the control unit to each of the user vehicles. Time division multiple access techniques are u~ilized witl~ tl~ it~lly coded r~lio translnissiorl slgn~lls .
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to permi-t ~wo-way communication between the user members of the community and the controller and also to facilitate ¦~
identification of the community members. The time base for the system is "real time" and consists of successively 1 repeating systcm cycles or "epochs". l~ach system epoch or ', l cycle is of a -~inite time duration and is divided up into a ¦ number of equal time "slots". Each of the user units and the control unit is assigned to a separate and different time , slot in the system cycle, so that two-way radio communication ,between the control unit and each of the user units may be had once during each system cycle during ,the user's time slot. When the time base of each of the user units is synchronized with the time base of the control unit, the digitally encoded radio ., signals may be employed to time and sequence events and deter-lS mine slant range measurements between units. Obviously the accuracy and reliability of systems of this type depend to a large extent upon the degree of,synchroniza,tion between the clock systems of the user units and the clock system of the control unit. Since the members of the community may include aircraft, ships and other movable vehicles, a common power supply may not be employed and synchronization of the c'ock systems of the units must be accomplished by radio signals.
The synchronization technique employed must not only be hi~hly accurate and reliable but must also lend itself to mechanically-ru~ged ochrnization which i5 suitablc for use in land, se~ ~;

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l and air environments. ;
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.Apart from use in community navigation systems, time ba.se synchronization systems are often employed to syn.chronize the clock systems of a plurality of widely-separated computers and/or industrial control systems to permit joint compu~ationàl use and/or joint industrial control applications Further- . .
more, time base synchronization is used in purely horological :.
applications to permit one or more remotely-located visual display clocks to be synchronized with a master clock to provide accurate and uniform visual time display at all :
locations.
. . :`, ' ' : ~ ~ Prior art time base synchronization systems generally make the time base correction by resetting or slaving the local time base to maké the measured time error zero within . .
~ the quantization level of the measurement. This technique .:~ :
makes the accuracy of such systems directly dependent on the ::
accuracy of the discrete time error measurement which is, of course, corrupted by noise and degraded by system errors. ~:
;: Since the time synchronization error is measured instantaneously, it is subject to large deviations in steady state condition .
; because of the inherently short time constant involved and because the past history of deviations and time error .. ~ :
corrections aro not re~lected in the correction signal resulting ... :
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I ~L049151 from the instantaneous time error measurement. Such a system does not have the advantage o~ averaging multiple time error measurements to produce a time error signal which is dependent upon the rate-of-change of time synchronization errors over a 1 ¦ short term his~ory. Additionally, in the prior art systems, ¦ frequency corrections are generally not made to the local oscillators which produce the basic clock rate, with the result that the quality and accuracy of the generated loca]. ~.
, ¦ time base is very dependent upon the quali.ty of the local ¦ oscillators employed, so that th~ use of relatively inexpensive, .¦ commercially-available oscillators of poor quality is precluded.
Some of the known time base synchronization systems utilize ¦ frequency and time standard radio signals which are broadcast ¦ from National Bureau of Standards radio stations. Comparison I receivers are used to compare the received frequency and ¦ time signals with the frequency ald time of local time basa ¦ systems to produce an error signal which is then employed to .
Ibring the local systems into synchronization with the ¦ transmitted frequency and time standarcls. These systen~s are I dependent for their accuracy on a long time integration which ¦ requires very large averaging times. The eqllipment required ¦ is complex and expensive and is usually suitable for use only j in a controlled laboratory environment.
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l SUMMARY OF THE INVENTION

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It is an object of this invention to provide a method and apparatus for time base synchronization wherein the synchronization error signal reflects the rate-of-change of S time errors over a short term history, so that the resulting time base correction reflects the recent history of prior time corrections required.
. ' It is a further object of this invention to provide a method and apparatus for tlme base synchronization which may be employed to not only slave remotely-located local clocks to a master clock but also to make local oscillato~ frequency and phase corrections.
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It is a sti]l further object of this invention to provide a method and apparatus for time base synchronization ~15~ wherein relatively inexpensive and commercially-available local oscillators of poor quality may be employed in the local -time base systems without sacrificing the accuracy and stability of the systems.

It is another object of this invention to~provide a method and apparatus for time base synchronization wherein the 94uellcy an~l t:ime correc~ions ure ~rive{l rrom ~i~itlll filter - 8 - i ., . ' ' .
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¦ techniques which simulate the operation of a simple Kalman filter. - 5 It is an additional object of this invention to , provide a method and apparatus for time base synchronization ¦ which provides rapid, accurate slaving of remotely-located local clocks and oscillators to a master clock and oscillator thTough the use of coded or uncoded radio signals. ' ~' , It is another object of this invention to provide a j ' method and apparatus for time base synchronization which permits'the use of mechanically-rugged equipment ~hich is ~, suitable for use in aircrat, ship and other operating '''~
environments.
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Briefly, the time base synchronization system of ;~
l the invention permits one or more local time base systems, .
¦ each having an oscillator driven clock, to be synchronized "`' ¦ to a master time base system having an oscillator dri~en clock.
The time synchronization error between the systems is measured at predetermined sampling times and frequency and phase correction signals or the local oscillators and time 20 ¦ correction signals for the local clocks are derived from the measured error a~ each of the ,sampling timcs. The oscillator ¦ COrreCtiOIl Sil'llalS ~Te ~pl)lied to tl~6 locnl oscillator alld the il I

time corrcction signals are applied to the local clock at gains which are a function of the magnitude of the error and the number of sampling times between corrections, so that corrections are made which are based upon the rate-of-change of error over the recent history of prior error corrections and ~ -not merely upon the instantaneous value of the measured error ;
at each sampling time. The specific oscillator and clock ¦
gains employed for a particular correction are determined by the control state of the local synchronization system which -~
has a programmed control state sequence in which transfer between control states for large initial errors is, made automatlcally for a predetermined number of sequentially ~
occurring corrections and is dependent upon the magnitude of ~ -the error for smaller subsequent corrections. The oscillator and clock correction gains for a particular control state ¦
may be constant or variable or may depend upon the su~mation of a constant with a variable. The variable employed is the .
number of sampling times bctween corrections which, for a constant sampling rate, is actually a measure of the elapsed , time between corrections. A digital filter which approximates l -~
the operation of a simple Kalman filter is utilized to generate the local oscillator frequency and phase correction signals and the time correction for the local clock.
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The na~ure o the invention ~nd otll6r o~jects ~nd l . .~',,,'',..

104915~L , ¦~ additional advantages thcrcof will bc morc readily understood by those skilled in thc art after consideration of the following detailed description taken in conjunction with the accompanying drawins. `
. . ~, S BRIEF D~SCRIPTION OF THE DRAWINGS
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In the drawings: ~
., . ' ,`"' Fig. l is a schematic diagram illustrating the controller time base in relation to a user time base and showing the transmission sequence of the coarse synchronization, I0 fine synchronization request and fine synchronization reply signals in the time base synchronization system of the invention; - -Fig. 2 is a functional block diagram of a time base synchronization system constructed in accordance with the teachings of the present invention;
: , . ' Fig. 3 is a control state sequcncing diagram showing ¦ the clock and oscillator correction gains utilized in each ¦ control state and the sequence of control states during synchronization or the community navigation system described;
I . . ,., ~ Figs. 4A and 4B respectively illustrate the output l . , .' l . , . .

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~ 049~L~ii1 of the secondary counter of the controller time base system as a function of time for the situation where the I synchronization error is zero and the situation where the i`
l synchronization error is not zero;
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Figs. 5A and 5B respectively illustrate the output of the secondary counter of a user time base system as a function of time for the situation where the synchronization ;
error is zero and the situation where a synchronizatlon error exists;
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Figs. 6A and 6B respectively illustrate the output of the slot timer section of the main counter of the user unit for the situation where there is no synchronization error and the situation where a synchronization error exists;

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Fig. 7 is a functional block dlagram showing the arithmetic section processor which ~enerates the oscillator 1`
frequency and phase corrections and the clock corrections; lnd ,~ . .
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Fig. 8 is a functional block dlagram of a timc base synchronization system constituting an alternative embodiment of the invention.

''.. : '' , ' '' `'. '. . ,', ' ' .: ~ ' ' . ' ~ . , . ', '. ' ` . ' . . . `' ' .', ' . . ` .~' . `: ` , ~0~9~51 I)~SCRIPTI()N 01~ T}IE PRE~ERRED F.MBOnl~ NT OF TIIF. INVENTION
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Referring now to Fig. l of the drawings, there is shown the master time base 20 of the controller in a community navigation system in relation to the time base 21 of a user vehicle "N" of the system. In the illustrated system, the controller ~enerates a master time base which consis~s of successively recurring system cycles or "epochs".
Each system cycle or epoch generated by the controller consists ~ of a series of 1,024 separate time slots of which one time slot is assigned to the controller and the remaining time slots are individually assigned to the user members of the operating community, so that provision is made in the example given for 1,023 system users. In the example chosen, the time duration of a single cycle or epoch is 2.68 seconds, so that each of the time slots within the epoch is 2.62 milliseconds in duration. The controller time base shown in Fig. 1 has been foresllortened for convenience of illustration and shows slot "0" which is assigned to the controller, slot l "N" which is assigne~ to user N and slot "1,023" which i5 .~.
assigned to user 1,023 of the community. The time base 21 which is individually genera~ed by each user melllber of the community is the same as the controller time base and will also consist of 1,024 slots each having a time duration of .6~ milliseconds and an epoch time o~ 2.68 seconds in the ~5 example given.
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~.049~51 In a community navigation systern of the foregoing type, it is essential that the local time base generated by each system user be in close synchronization with the time base generated by the controller, since two-way radio com munication between each user and the controller is made during the unique time slot assigned to that user. The radio linkages between the controller and the users are utilized to peTmit navigation by trilateration computations which employ radio slant range measurements between the users and the controller ld ¦ at various positions in the navigational grid defining the l operating community. Synchronization is obtained through the ¦ use of coarse synchronization, fine synchronization request and fine synchronization reply radio signals which are l digitally encoded with unique codes to identify them to tile ¦ user and controller members of the operating community. Each ¦ of these synchronizàtion signals may be conveniently generated through the use of biphase modulation ~echniques and Barker encoding may be employed to identify the particular synchronization signal involved. The Barker code may, for ~20 example, consist of a sequentially-transmitted train of 13 bits. If biphase modulation techniques are employed, each bit will be defined as the presence or absence of a phase shift in the transmitted RF signal. The radio receivers which receive the signals may employ dif~erential phase decoding which is asynchronous in operation. l~uring decoding, the recelver sums the amplitude of the received sequential pulse ' ~ ' ' . ',~,,~'','~, .,., . ~, , .. . .. . . . . . . .
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104915~L
train over the in~erval of the train aJld the resulting output pulse has its amplitude multiplied by ~he number of bits in the Barker code. The resulting pulse which is a timing pulse which initiates a particular event in the -foregoing exam~le would have an amplitude gain of 13 since a 13 bit code is . employed. It ~till be understood, however, that any suitable method for the transmission and recept~on of the synchroni-zation signals may be employed with the present invention , depending upon the application to which the invention is pul:.

1 In Pig. 1 of the drawings, the time base 21 of a user N of the operating community is shown as being out o~
¦ synchronization with the time base 20 o the contro]ler.
Accordingly, when the controller time base is generating slot I 10~3, the user time base is generating a slot "X". At the ¦ beginning of slot 0, which is assigned to the controller of the community, the controller transmits a coarse synchronization ¦ signal 22 which is received by all of the user craft i.n the I community including user N. When this signal is received l by the user N it is employed to reset the user's clock or time base to the start o an e~och as illustratcd in Fig. 1. Since : ~ the coarse synchronization signal is received by user N aft(~r a time delay tp equal to the RF propagation time betwcen the controller and user, the user's time base will have a relative synchronization crror E with respect to the controller's time ZS ~ base w ch lS equal to the R~ prol)agati:n time. At this ¦ ~ ;

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~049~51 ¦ point, coarse synchronization has been achieved between the controller and user clocks. As the system cycle or epoch continues, slot N is reached in the user's clock. Since ~-this time slot has been uniquely assigned to user N, the user N transmits a fine synchronization request signal 23 ~-at the start of its slot "N" which is received by the controller at a time T in slot "N" on the controller's time base. When the controller receives this signal, it measures the elapsed time between the start of its slot N to t]le 10' receipt of the fine synchronization ~equest signal at time T.
. The controller then transmits a fine synchronization reply ¦ signal 24 at a time ~10-T) in its slot N which is distant ! from the end of its slot the same distance as time T is distant from the start of the slot. When the fine synchronization reply signal 24 is received by user N, the user measures the elapsed time between the receipt of the fine synchronization reply signal and the end of its slot N.
~The magnitude of the elapsed time so measured is equal to twice the time synchronization error E which exists between the user and controller clocks. Since the user N now has information gi~ing it the magnitude of double the error E, it then adjusts its local time base by one-half of the measured amount to thereby bring its time base into ~-synchronization with the controller time base.
. . 1'''''"''''' ~ or example, in the time bases il~ustrated ln l~ig. 1 ~, - 16 - ;~

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of the drawings, the user N time base 21 is shown as 1)eing out of synchronization with the controller time base ~0 by ¦¦ two units of a ten unit slot. Assuming that the RF propagation ¦¦time tp between the controller and user is also two units of I a slot, the fine synchronization request 23 transmittcd by the user N will be received by the controller at a time T which is distant four units ~rom the beginning slot N. The controller then transmits the ~ine synchronization reply signal 24 at a time which is four units distant from the cnd o~ slot N, so that the fine synchronization reply signal is received by the user N at a time which is distant four units from the end of its slot N. The user N then mcasures the elapsed time of four units from the receipt of the fine synchronization reply signal to the end of its slot N and adjusts its local lS clock by a factor equal to one-half tlis amount or by a factor of two units. Accordingly, the user N adjusts its clock to begin transmitting the next slot when eight units of its slot N have elapsed, so that its corrected time base 25 is then in synchronization with the time base 20 of the controller. The fine synchronization request and ine synchronization reply signals are respectively transmitted by the user and the controller once every complete system cycle or epoch, so tha~ the synchronization error E is measured once cvery system cycle which for the example previously given is once every 2.68 seconds. When the initial fine synchronization of the user time base to the controller time base is achieved, '' ' ' . ' . . ' ' ' , ' .. . . ..

~ the oa~se syl~chronization signal transmltted by the co~troller I at the beginning of slot 0 is no longer util~zed since this would automatically produce a loss of synchronization between ~: ~
l the USeT N time base and the controll~er timè base equal to ..
the RF propagation ti.me or the coarse signal. Accordingly, 1?.:.. '.
the coarse synchronization signal is only utilized by the user N when initi.al synchronization or acquisition is achieved, such as, for example, when the user N first joins the operating community controlled by the controller.
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A functional block diagram of a-synchronization ~ ..
system constructed in accordance with the teachings of the present invention is shown in Fig. 2 of the drawings. The : system shown in Fig. 2 may be employed for bo~h the controller and the user members of the operating community. When the system is employed for the controller member of the operatlng .
community, its time base correction logic would be inhibited because the controller time base is the reference or master ~
for the entire community so that no correction is necessary.
Accordingly, the system illustrated in Fig. 2 will be described mainly with reference to its use in a user member , of the community. A main digital counter or divider 30 and a voltage-controlled relaxation oscillator 31 provide the means for generating the local time base for each user member . ;:~
of the communi.ty. Together, these units orm a clock system for the user which is employed in its navigational equipment :
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and whicll must be kept in synchronization with the corres- I
ponding clock system o the controller. The voltage controlled oscillator 31, wllich may comprise an oscillator of relatively poor quality, has an output frequency which is controlled , by the voltage applied to the oscillator from the output of a digital-to-analog converter 32 whici'h is, in turn, driven by the digital output of an up-down counter 33. The up-down counter 33 is initially set to mid-range and is incremented ; or decremented by a series of pulses proportional to the 10' measured synchronization error. rhe input signals to this counter control the oscillator frequency and phase and the ¦ ,sign or direction o correction. The gain of the oscillator correction is determined by the tap on the up-down counter Il to which the~correction signal is applied as will be ¦
~ I explained hereinafter~. The timing outplLt 34 of the main, , counter 30 generates the user time base which must be kapt in synchronization with the time base of the controller. This output in the user is coupled to tlle transmit logic which ' causes the fine synchronization request signal to be ¦ transmitted at'the beginning of thc user's assigned slot. In I the controller, khe timing output ~4 causes the transmit logic ¦ to generate the coarse synchronization signal at the beginning of the controller slot 0.
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A secondary counter or divider 35 is utilized in I the syn hronizatioll system to perform a llumber of fanctioDs.

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Thi coanter is a working counter whicll mak~3s the synchlon-ization error measurements in the user member of the community, by measuring the elapsed time between ~he receipt of the fine synchronization reply signal and the end of the user's assigned ¦ slot. Accordingly, the secondary counter has an output 36 which expresses the measured synchron~zation error in digital form. In the control member of the community, the secondary counter 35 provides a timing output 37 which is applied to l the radio transmit logic to generate the fine synchronization 10~ reply signal at the required time before the end of the user's assigned slot. This function of the secondary counter is . inhibited when the synchronization system is used in a user vehicle. The third function performed by this counter is 1 that of making slant range measureme~ts to determine distance 1 between operating members of the community by the trilater-¦~ation computations referred to previously. Both the main counter 30 and the secondary counter 35 may comprise known digital frequency dividers. For example, the main counter ;~
30 may comprise a 28 bit digital divider which is driven by a 100 Mhz. frequency output from the oscillator 31. The system cycle or epoch time is then determined by the period of the most significant bit in the main divider and the measurement resolution of approximately 10 nanoseconds is established by the period bf the 100 Mhz. oscillator 31. The lO most significant blts of the main divldor are utilized for the slot counting function and the 18 least significant ' . .

l 3~4g~5~L
¦ bits are reservcd for ~he slot timing function. When a time synchroni~ation error is measured by the user, the user must adiust the phase and frequency of its local clock system l so that the state of its main counter 30 is the same as the 5 ~ state of the controller's main counter at any instant of time. This is accomplished by adjusting the ~otal phase of the frequency source plus the divider and by adjusting the frequency of the source. As shown in Fig. 2, the output frequency 38 from the oscillator 31 is employed to drive both the main counter 30 and the secondary counter 35.
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The balance of t]~e system shown in Fig. 2 o~ the drawings is employed to generate the frequency and phase;~
correction signals for the oscillator and the time correction -signals for the main counter. It programs control states and acts as a digital filter to generate time and frequency corrections as a function o the measured synchronization error and elapsed time since the last correction. As will be explained hereinafter, the algorithm for this filter approximates the operation of a simple Kalman filter which ¦ is essentially a linear filter with time-varying gains. The filter logic accepts a measured time base synchronization error and processes it in accordance with the filter algorithm to generate a time correction for the main counter 30 and fre-quency and phase cerrections for the oscillator 31. The filter algorithm smoothes time, frequency and phase corrections to ¦
¦ produce close synchronization between the user oscillator and ~ main counter and the oscillator and main counter of the :, ' '' ' ' " ' ,.' ' . , ', : .
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1049151.
controller. The developement of this filter will now be descrihed for the foregoing system. `~:
In devcloping the Kalman filter, the errors due to ¦I constant oscillator drift can be represcnted by the equations:

S ~ ) ~u n uun-l + ~ ~t; and !

2) ~n ~ h~n l ~t + l/Z ~Jt ~t)2, ¦ where ~ n is frequency error at time tn due to oscillator drift, n is the phase error at time tn due to oscillator ' ¦ drift, ~ is the oscillator drift rate, and ~t is the s~mpling interval. The random oscillator noise can be represented as a Markov:process with time constant r :;
(autocorrelation time). The errors at each sampling time can be represented by the equations: .

( ) ~v n Kouvn l ~ KlRn; and ~ ~ n = ~n-l + K2C~n-1 ~3Rn~

: ~ where Ko = e t/r , K~ e-2 at/r )1/2 : . . ., K2 = 7~(1-e ~t/~r), and :

K3 = (1-e 2~t/~ )1/2 ~ .

.

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and uu n is the frequency error at time tn ~ue to ranclom oscillator noise, n is the phase error at time tn due to . random oscillator noisie, Rn is a Gaussian random.~rariable with zero mean, and standard deviation equal to oscillator :.
. random noise, r is the autocorrelation time of the noise, and ~t is the sampling interval. The total phase and fre(luency :
err~rs may be represented by the foll~wing equations:

) n ~n + ~n i and ¦ ~ (6) ~Jn = ~Vn + U~n I .
1 With these equations, the error dynamics can be written in .:¦ matrix form as follows: :

O K2 ~t /Z(a ~ ~ 9n ~ ~K~ [~

¦ ~ lUn O O Ko 1 ~ t ~Vn- 1 Kl : ~Jn 1= Ko O O ~n-l Kl :.

1~ ~n~ lo O ~ 1 ~t . .~. l ~oo o 1 . ::
. . ..
~ The measurement of time relative:to the controller ~

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reference cloc~. (neglecting quantization) can be represcnted . I by: -8) ~n = [1 0 ~ ~ ~ + V

¦ where n 15 the phase measurement at time tn, and Vn lS a Gaussian random variable representing measurement random ~:~
error. : ~`
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: The above state and measurement equations comprise a ~
: llnear system of the form: - :

n [F3 Xn~ G] Un ; and , (ln~ Yn = [~1] Xn n . ., For these sets of equations, a Kalman filter may be applied . for obtaining a recursive optimal esti.mate of the state : vector Xn given observations Yn ~ Th~ statc estimate at each ~ updatc time n is given by:
(11) X = LF~ Xn l + LX~ (Yn ~3[~ n } ~:
.~ , : ~ '. . . .' . _ Z4 _ ,: , . . : :
: ., ' ' ~ , . ' ' ' 1o49l5l where Xn is the state estimate at time tn, [Kn~ is a gain matrix, and Yn is thc obscrvation or mcasurcmcnt. IE, aftcr each measurement the system total phase (~) and frequency (~u) errors are,corrected by an amount equal to the associated ~ state estimates, then the estimation equation becomes:
I ..
lZ) Xn = [1''] Xn-l + [~ Yn ' ~ since [H] ~ Xn 1 has been made zero. Thus the objective .. :
,, here is to correct the total phase and frequency errors :
l ~ and w)~ given the phase measurement (~ ). The corrections -are the negative of the state estlmates found based upon the above equations: .

13 T T ~ :
:( ) ~n Kc ~n ~~ Kc ~ ; ' (14) Wn = Ko ~n ~ ~= -Ko ~T , .; ' .
where Kc and Ko are the gains for the clock and oscillator, ¦ respectively. The optimum values of these gains are time-varying, and dependent on the sampling rate as well as : :
'covariance matrix uncertainties associate~ with all five ., states. . ' 1':
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By utiliz.ing the forcgoing linear mo~ol as a design ,:
tool Eor ol)tainill~ a sui.tablc approximati.ol) to tho optimulll gain values, Kalman gain matrix values may be computed and .

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- 25 ~ , ., , , , ,~ .

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evaluated using the followin~ equations:
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(l5) [M~ =[F] [Pn ~ [F~ ~ CG~ [Q] [G~ ;

(16) [K~ =[M~ L}~] T {~3 ~M~ [~ T ~v~ . 1; and ~ ~ 17) ~Pn~= [1] [ ~ ~ ~ ]
¦ where ~P~ is the state covariance matrix at time tn or E(XnXn ) given all observations up to and including Yn, ~ Mn] is the state covariance matrix at time tn or E~XnXnT) given all observations up to and inclucling Yn l~ Q is the constant oscillator random noise matrix given by E~UnUnT) for ]0 I any n, and Cfv is the constant random time measurement error : I given by E(Vn2) for any n.
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In the foregoing covariance and for the synch~onization : . p~oblem outlined, a 1 Hz, l~r, initial frequency error and .
600 ms initial phase error between the user and controller 1~clocks may be assumed together with a random oscillator I noise of O.l Hz RMS, a long term drift value of l Hz per :
: ¦ day maximum, and a correlation time for the random oscillator ¦ noise of 4 hours. With these parameters, thc optimum gains : ~ ¦ for the oscillator and clock corrections may be determined l for the sampli.nr, intervals utilizcd. In ~llc system di.scussccl previously, thc cpoch timc of 2.68 seconds :i.s tho timc be~ween the u~ tes for each user ~eml)er o~ the o1)cr~ :
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_ , . ,, , , , ' community and is therefore the sampling interval. For this sampling interval, the following gain variations have been ¦' found: , I . . i ' ~ .
TABLE I

Update Number ' K K
, o c 1 0 1 :' : '2, 3, 4, 5 high 1 , 6, 7 lowlow plus variable -.~ as a'function of N.
. . ~
In the 'foregoing ~able, N is the number of system cycles :10 between updates. A phase or time correction of ~ ~ from ~
equation (13) is added to the clock and a requency correction , of ~ w from e~uation ~14) is added to the oscillator after ,' '~ each update. The clock correction is rounded off to the , , , digitization ti.me of the clock which, in the example previously ,,, `~15 glven, is 10 nanoseconds. The round off remai~nder may be l~ ! accounted for by making a phase correction to the oscillator.
' l , I Table I illustrates how the oscillator and clock ,i'' ' , gains may be varied as the synchronizing system passes through ,, ¦successive updates. After the'user time b~sc is initialized ~I)y tlle oarse syncllronizr~tion signrl, tl~e ~irst updrte occurs ~ ~

. ~ ':
I . '.: '~''' , - - 27 - ,~
. . ., ., .

, . ., ..... . . .
.. . . . : , . ,, . : .
.. .
. :. , . , . . , ~, ,:, , , . . . . : .

when the slot assigned to that user i~ reachcd in the system cycle. During the first update, which is produced by the fine synchronihation request and fine synchronization repIy I signals in the user's slot of that epoch, the clock gain KC
1 is unity and the oscillator gain Ko is zero. During the next~
four successive updates ~updates 2,3, 4 and 5), the clock l gain remains at unity but the oscillator gain is increased.
I For the sixth update, the clock gain is reduced by a constant plus a variable which depends upon the number of missed ;0 updates N and the oscillator gain is reduced to a low value.
The clock and oscillator gains remain at these values during the seventh and succeeding updates provided, however, that ¦ the measured synchronization error E is equal to or less than a predetermined count. If, on a succeeding update, the error ¦ E exceeds the predetermined count for that update and if, for the next succeeding update, the error still exceeds the ¦ predetermined count, the system is shifted into a state which ¦¦ may have higher clock and oscillator gains. If the error ¦¦ which exceeds the predetermined count is not repeated for the 1 two successive updates previously mentioned, the gains are kept at the values used in tho sixth and sovcnth updatos because it is assumed that the high error value was merely a transient. I~ the error exceeds the predetermined count ~ by a large margin and is repeated for two successive updates, the clock and oscillator gains are returned to the high values employed in updates 2, 3, 4 and 5 and the control state . - . . . ... .. ..

iO49151 sequencc for these and succeeding updates ~ill be repcated again. If thc error is greater than the predetermined count but not by such a wide margin and the error is repeated for the two successive updates, the system may be returned to the control state having intermediate clock and oscillator gains.
.
The specific clock and oscillator gains which are employed for a speci~ic system will, in general, depend upon , the Kalman filter algorithm utilized in the system which, in turn, will depend upon the system para~eters. For example, for the system parameters and component characteristics previously outlined, and for an epoch time of 2.68 seconds with 1,024 slots to an epoch, the specific clock and oscillator gain values shown in the following tabie may be utilized:

lS TABLB II

¦UPdate Number Ko KC
1 , O . 1 , . .
2, 3, 4, 5 1/~ 1 ~
6, 7 1/2561/8 ~ ~/32. ;
. . . `'.
Again, N is the number of epochs or cycles between updates.
The ~oregoing ~ain values are approximations W}liC}I havc bcen established by simulation techniques for the system parameters previously discussed.
. ' , ~ :.

~L04!~151 A control st~te seque~ce dl~grdm for Table Il is shown in Fig. 3 of the drawings wherein the various control states assumed by the user's synchronizing system are illustrated in terms of clock gain, oscillator gain, syn-S chronization error count and the number o-f epochs between ¦ -updates. As seen in Fig. 3, when the user's synchronization system is initially turned on it is placed in an idle state 40 wherein it awaits the receipt of the coarse synchronization signal from the controller. When the coarse synchronization ;~
10, signal is received by the user, the user's time base is reset to start the generation of a new epoch with slot 0 and the user's system is placed in control state 41 for the first fine update. In this state, the clock gain is unity and the oscillator gain is zero to allow for the correction o large 15 ~ initial phase errors. For the second, third, fourth and fifth updates, the user's system shifts through the control states 42, 43, 44 and 45 wherein the clock gain remains at unity but ~he oscillator gain is increased to l/4 unity gain.-The lncrease in the oscillator gain durlng the second through~
the fifth updates permits the correction of large initial frequency errors. For the sixth update, the user's systém shifts to control state 46 wherein the clock gain is reduced to a value equal to l/8 unity gain plus a fraction N/32 which is dependent upon the number of epochs between updates.
The oscillator gain is decreased to a small steady stat.e value of l/25G o~ unity ~ain. I}1e clock an~ oscillator gains of the control statc ~or the sixth upda~e aro main~ainotl , , ~
. ., until the synchronization error count E bccomcs equal or 1PSS
than 2 at which time the user's system shifts to control state 47. The clock and oscillator gains in control state 47 are the same as control state 46 and are maintained at this level and in this control state until the error E becomes greater than 2. When the error E becomes greater than 2, -~
the user's system shifts into control state 48 which again maintains the same steady state,clock and oscillator gains , ~ , as control states 46 and 47. On the next update, if the error E is equal to or less than 2, the user syst-em is returned to control state 47 on the assumption that the higher error ~, value was merely a transient and was consequently not repeated on successi~e updates. If, on the other hand, the error E
¦ is greater than 2 with the system in control state 48, the user system is returned to one of the previous control states depending upon the magnitude of the error. If the'error is ~greater than 2 but less than or equal to 20, the user system is returned to control state 46 which has the steady state l values for the clock and oscillator gains which may handle a small correction. If,the error E is greater than 20 with ~ ;, the system in control state 48, the user system is shifted ¦ back to control state 42 which has the htgher clock and oscillator gains requlred to handle the larger magnitude of ~ error. The sy;tem then follows the programmed sequence of ,, control statcs 42, 43, 44, 45, 46 and 47 until the crror ¦ is reduced to an acceptable level. Accordingly, it is , , , ':.
. . , , . .
, - 31 -,''", ,,', ' . ' . - ' '' , ', ' ' ' ".', ~ ." '' ., ' '" ' . ' . .

~1 ~0491S~
¦ believed apparent that the digital filter functions to generate time and frequency correction data as a function of the measured synchronization error and the elapsed time since ~5 the last correction or update. It is essentially a simple .
linear filter with time-varying gains.
: : ~
Referring again to Fig. 2 of the drawings, the digital filter function will now be described in terms of system components. As shown in Fig. 2, a coarse sync. input , signal 50 and a fine sync. reply input signal 51 are applie~
$o sync. state control logic 52. The coarse sync. input `
signal 50 is a pulse which represents l;he digitally encoded R~ signal which was transmitted by the controller. When the ¦ digitally encoded RF coarse synchronization signal is received I I by the user it is decoded to produce an output p~llse repre-¦ senting the signal. The decoder utilized may, or example, comprise known digital comparator circuits which compare a known digital signal with an unknown signal on a bit-by-bit basis to produce a pulse output when t~lereis complete identity ¦ of digital information. In a similar Eashion, the fine synchronization reply RF signal is decoded to produce a fine I ~sync. reply pulse 51, so that the sync. state control logic 52 receives only the pulses representing the receipt o~ these signals. The sync. state control logic 52 controls the gain ~ of the oscillator and clock corrections and consequentIy l receives inl)u~s rrom sequencing logic 53 ;ln~l an error lin~it l logic 54, since the clock and oscillator gains depend upon the I . , .
1'~

~ - 32 - I
, .. . .

~ ~9 ~ 5 control state the user system is in, the number of epochs between updates and the predetermined counts of the error signal E. The fine sync. reply input signal 51 is not only ' applied to sync. state control logic 52 and sequencing logic 53 but also to an arithme~ic section 55, the secondary counter ~;
35 and the main counter 30. The arithmetic section 55 is also responsive to the measured sync. error from the secondary counter 35 and is also controlled by the sequencing logic 53.
The arithmetic section 55 provides outputs representing the 10, magnitude and sign of the required corrections and applies these to an increment control 56 which produces frequency ¦ and phase ad~ustments for the up-down counter 53 and time ¦ adjustments for the main counter 30.
. ~ ',.... .
During initial synchronization when the user first joins the operating community, the receipt o the coarse sync.
input signal 50 by the user serves to reset the main counter 30 and the sync. state control logic 52 to cause the user : ,, - .
to begin the generation of a complete epoch at the start of the !l epoch. This correction is made in a high gain mode by making I j . ... .... .
~20 a direct correction to the main counter 30. l~hen the user"
main counter 30 reaches the beginning of the individual time slot assigned to that user, the tirling output 34 from the main counter causes the user to transmit the fine sync.
request signal to thc controller. The controller then transmits the fine sync. reply signal. When the fine sync. reply sigral . . '."
. . :

1049151 ~ I ~
is received by the user, the sync. error counter which is secondary counter 35 is stopped and the measured sync. error E is applied to the arithmetic section 55. The sequencing logic 53 and arithmetic section 55 combine with the increment S control 56 to generate ~requency, time and phase correction signals through the implementation of the filter algorithm which is modified as a function of number of epochs between ~ ~;
j updates. First, the'oscil]ator 31 is adjusted in frequency l by the digital-to-analog converter 32 and the up-down counter 33 under the control of the increment-control 56. Then the increment control 56 increments or decrements the main counter 30 to adjust the time. Finally, fractional time corrections or phase corrections are made by adjustlng the i' phase of the oscillator 31 by making a frequency o~fset ~or a known period of time. l;
. , ., , In Fig. 4A of the drawings, the operation of the secondary divider of the controller is illustrated ~or the situation wherein the 'synchronization error E between the I controller and user is zero and where radio propagation time 20 1 delay is neglected. The count or output of the secondary t ¦ divider is shown as a function of timc. The secondary ¦ counter period of the controller'is adjusted to cycle as shown ¦¦ by the'dotted line 60, so that the secondary counter has two full cycles during each user slot gencrated by the main 25 ¦ counter in the controller. The secondary counter wilI count .. ..

ll ~

ll ~

1049151 ' I ~ ~
from zero at the beginning of the slot at time To and will ll reach a maximum at the midpoint l~ of the slot, when it ¦I will discharge to zero and cdmmence counting again during l the second half of the same slot. At the end TS of the slot, ; 5 the secondary counter will overflow and again commence counting on the new cycle. When the fine synchronization request signal is received by the controller at time TRo of .
the fine synchronization request signal does not occur at the beglnning To of the slot as would be expected with a 10, situation involving a zero sync. error and a zero propagation time. The nominal receipt time TRo is offset a distance from r.. . ~ .
the beginning of the slot to cover the situation wherein the user transmits prior to the beginning of the slot because its oscillator frequency exceeds the nominal value. Upon i receipt of the fine synchronization request signal by the controller, the secondary divider count is s~opped as 1~ illustrated at 61 and held until the midpoint TM of the slot is reached at which time the count resumes as shown by the - curve 62. When the counter reaches its capacity, it will overflow at time Txo and the count will be returned zero.
Since the secondary counter is arranged to cycle twice ¦ during each usor slot, if its counting is stopped at the I I time TRo and is permitted to resume at the midpoint TM o I the slot, the overflow time Txo will be spaced a distance from the end o the slot which is equal to the distanco between TRo alld the beginning o~ ~he slot. If the fine . ' .
~:
. , . . , . , ., , ' .
' ' . ' , . ..

~ ~ 5~ 1 synchronization reply signal is transmitted by the controller at time Txo~ then it will be transmitted a distance from the end of the slot which is equal to the distance between the beginning of the slot and the receipt of the fine 1 synchronization request signal.
l ' : - : .
Fig. 4B of the drawings shows the ,operation of the -,, secondary counter of the controller for the situation where the synchronization error E is other than zero. In this ~ figure, 61, 62 and 63 again show the counter output for a ¦ zero synchronization error, while cur~e 64 represents the .1 ¦ counter output for the receipt of an e.lrly fine synchronization I request signal at time TRE and curve'65 shows the CounteT
¦ output for the receipt of a late fine synchronization request l signal at time TRL. These curves illustrate that the elapsed ¦ time between the beginning of the slot To and the early ¦ request signal TRE is equal to the elapsed time between the i' transmission time TXE for the fine sync. reply signal and ,the end TS of the slot and that the same situation obtains ~ for the receipt af the late fine sync. request at time TRL
I and the transmission of the late fine sync. reply at time TXL.
; l : '.' The secondary counter operation of the user member of thc community is sllown in Fig. SA of the drawings for the situation whor¢ thoro is a zcro synchrollization error and the l~' proyagatioll time is neglected. 'l'he user secondary countcr may be s¢t to begin counting It tho bcgillning of a . . .
, 1049t 51 typical user slot at time To and to continue counting until the end TS of the slot, when the counter will overflow and commence counting again. When the fine synchronization ¦ reply signal is received by the user this counter would :
S ¦ be stopped and the count would represent the time Txo at which this signal is received. Since the elapsed time between the receipt of the fine synchronization reply signal at time Txo and the end TS of the slot is equal to double the synchronization error E, if the user secondary counter 10, was to be omployed in this manner, the time Txo would dccur at the end of the slot at ti~me Ts, so that only ¦ negative synchronization errors could be measured in the user slot. Accordingly, in order to measure both positive and negative synchroniza~ion errors, the user secondary counter is preloa~ed as shown in Fig. 5A o~ the drawings so that the counter will have reached a predetermined count at the beginning To of the user slot and will over~low at a time Txo which is a predetermined time from the end TS o the slot as shown by the sawtooth curves 70 and 71 in Fig. SA. ~ -In Fig. 5A, the user transmits its fine synchronization request signal at time TRo IIld, for a zero synchronization error and neglecting RF propagation ~ime, the fine synchronization reply signal transmit~ed by the controller will be receivod at time Txo when the secondary counter of 2,5 the user l~ould llormally overflow, so that thc count reached by the uscr secvn~ary counter would be zero.

': ' , ~ .
!~ .

lOq9151 Fig. 5B of the drawings illustrates the receipt of fine synchronization reply signals at times before and after the nominal receipt time of Txo which respectively indicate negative and positive synch:ronization errors. It S may be noted that the fine synchronization request signal will always be transmitted by the user at the time TRo in its own individually-assigned slot. As seen in Fig. 5B, when the fine synchronization reply signal is received by the user at a time TXL which is earlier than the nominal lp receivc timc TXo~ thc uscr countcr will bc stoppcd at some pOillt on the curve 70 as illust,rated by the solid line 72 which will indicate that a negative synchronization error exists having a magnitude indicated by the stored count in the counter. I~ the ~ine synchronization reply signal is received by the user at a time TXE which is later than the nominal receive time Txo~ the counter will be stopped at some point on the curve 71 as shown by the solid line 73 which will indicate a positive synchronization error having ¦ a magnitude indicated by the stored count. Neglecting RF
1 propagation time, a zero synchronization error will be indicated by a count o~ zero in the counter, since the counter will normally ovér~low at time TXo~ I~ the count is in the range-between zero and a count of PC which represents the preload count, a positive synchronization error will be indicated. A negative synchronization error will be indicated , by a count lying in the range between the preload count PC
and the maximum count MC at which the countcr overflows. By .

04~1 5 virtue ~f this arrangement, both the magnitude and sign of the synchronization error may be determined by the secondary counter of the user. Positive errors may be represented in binary notation and negative errors may be represented in 2's complement notation. Ihe resulting synchronization error E may then be processed by the digital filter.
! .
During initial synchronization adjustments when the synchronization error E may be large, the unity gain , 1 time adjustments may be handled directly by ~he main counte~
30 of the user members o the community. As seen in Fig. 6A
lof the drawings, the slot timer section of the main counter 30 of the user commences counting at the beginning To of the user slot and reaches a predetermined end count at the end Ts of the slot as shown by the sawtooth curve 75 if a I zero synchronization error is assumed and RF propagation ¦ time is neglected. The user s].ot timer section is arrangec ¦to count by 2's to a higher end count upon the receipt of:~
la fine synchronization reply signal at time TXo~ The . ;
Icounting by 2's of the slot timer is shown by the dashed curve 76 in Fig. 6A. If the slope of curve 75 is M, then ;~
the slope of the curve 76 will be 2M because of the counting by 2's. Since a zero synchronization error has been assumed in Fig. 6A, no adjustment will be made in the end time TS
of thc slot and thc countcr will ovcrflow .~t this tim~.
1 ~ig. 6B of the drawings illu~trates the slot timer operation ~ of the user main counter when negative and positlve , l . ' ~ 39 synchroniza~ion errors exist. When a fine synchronization reply signal is received by the user at time. TXL for a negative synchronization e~ror, the elapsed time between TXL
and TxO.is equal to tWiCI the synchronization error E as S explained previously. Upon receipt of this signal, the slot timer section of the user main counter commences counting by 2's as shown by the dashed line 77 until it reaches the higher end count for the slope 2M when the counter will over-¦ flow at the time TSL. Because the slope of the liné 77 is 1 twice the slope of line 75, it may be demonstrated mathemat-ically that the elapsed time between TSL and TS is exactly ~ .
equal to the synchronization error E. In a similar fashion, when a fine synchronization reply signal is received by the user at a time TXE indicating a positive synchronization error,: the elapsed time between Txo and TXE is equal to :
twice the synchronization error E. Upon receipt of this signal, the slot timer section of the user main counter commences counting by 2's as shown by the dot-dash curve 78 until the higher end count is reached and the counter overflows ¦¦ at time TSE which is separated from the nominal end T5 of ¦¦ the user slot by an elapsed time equal to the synch~onization error E. By virtue o~ this arrangemcnt, the sensed synchron-ization error 2E may be employed directly to provide a slot :
correction exactly equal to the error E when the end count 2, is reached, which greatly simpli~ies tlle basic digital ~ filter Ll lemelitatio~

Il ' ' ~o ' ' I ~

I
1.

l A functional block diagram for the arithmetic section processor of the digital filter which generates the frequency, phase and clock corrections for the user member l of the community is shown in Fig. 7 of the drawings. The I processor provides the filter algorithms described previously ~ -and functions essentially as a serial processor which generates the frequency, clock and phase corrections in a single pass.
As seen in Fig. 7, the magnitude and sign of the synchron-ization error E are applied to the processor and the error 10 shifts through gating 80 which receives the output of an ~-. 8-bit parallel entry shift register 81 and a sign bit stor~
82. The shifting continues through a full adder 83 which supplies its outpu~ to a 5-bit shift register 84. Gating 80, ¦ full adder 83 and an associated carry flip-flop 85 which is responsive to a sign bit controlled gate 86 enable the ¦ magnitude of the synchronization error to be obtained when the error is negative. After the first five shifts, the magnitude of the error is stored in the shi~t register 81 and is employed for making the frequency adjustment to the ~20 oscillator 31 of Fig. 2 of the drawings. The magnitude and sign of the error are applied to increment control 56 which provides thc frequency corrections for the oscillator through the up-down counter 33 and the digital-to-analog converter 32. ~or a given synchronization crror, magnitude 2~5 and sign, the increment control and corrcction logic adjusts the up-down countcr 33 by one pulse for each count in the error. The gain of Ithe frequency correction may be determined . .
. . .,' - ~1- .

, ~ 0491~
by electin~ the bit in the up-down counter where the correction ¦
pulses are inserted. With the oscillator gain values set forth in Table II, the two insertion points utilized in the ¦ up-down counter would correspond to oscillator gains of ¦ 1/4 and 1/256. -After thc oscillator frequency has been corrected, the shi~ing o the error continues through a multiplier comprising gating 87, full adder 88 with associated carry . flip-flop 89, and full adder 90 with associated carry flip-flop 91. Tlle inputs to the multiplier are controlled by a 5-blt missed update counter 92 which is coupled to the gating 87 and which receives its input from the fine synchronization request and fine synchronization reply pulse l signals. This arrangement provides an efective approximation ¦ of a gain which varies as a function of time between fine synchronization updates. The output of the oregoing ¦
multiplier is applied to the shift register 81 where the least significant bits represent fractional control of the ~ least significant bit of the main counter in the user ¦ synchronization system. The least significant bits which I I are shifted into the shif~ register 81 are also shifted into shift register 84 and associated 3-bit shit register 93 where they are stored for subsequent use for controlling the phase o tllc osclllator. The aforcmelltionc~ shifting continues until the integer value of the filter output is . ' , :

,, I .
,j , 1. .
. . .. .
., .. ~ . . . . .
.

1049~51 aligned in shi.ft register 84 where it is supplied to the -¦I correction logic and increment control 56 to adjust the cou].t Il in the main counter 30 to provide the clock or time correction.
. . .'.
. The phase corrections to the oscillator 31 .~re made by integrating oscillator frequency over a known tlme inter~al and may be accomplished by introducing a frequency - :
change of ~f for a known period of time T and then removing :
the frequency increment. The effect of this adjustment is , ¦ to shift the phase ~ by an amount ~ ~ which is equal to the product of the frequency increment ~ f in Hertz and the integration time T in seconds. The ~f frequency insertions are made at the appropriate gain taps on the up-down counter . . :~
33 and the timing of the insertion-removal of the frequency :~ .
; increments is controlled by the sequencing logic 53. ~ ~ .
.' . ...
From the foregoing description of the preferred embodiment of the invention, it is believed apparent that :
: the synchronization system of the invention provides.a ,.
simple and effective arrangement for synchronizing one or . : .
: : more local clock systems or time bases with a master clock ~ZO :~ system or time base. The corrections which are made not only include correction of the local clock, but also . .
I frequency and phase corrections of the local oscillator which is useed to drive the local clock. This permits the local clock systems to ut~ilize loc~l oscillators o~ a :~

. . ''.~ ~' -- 43 ~ : ~
.' I

.
:, . ' , ', ' , .' :' . ~ ~

relatively inexpensivc, commcrcial ~rade ~hich have only nominal frcquency stability characteristics. The synchronization technique utilized by the present invention provides for a number of control states having variable clock and oscillator correction gains. The gains which are employed in making the corrections depend upon the missed updates or the number of epochs between updates, so that the past history of error corrections is utilized in making the corrections at each update and the corrections are not based solely on the instantaneous synchronization error present at a ~iven sampling time. The corrections are, in effect, based on a mean or average value of time base error rather than the instantaneous synchronization error. Although the time base synchronization technique of the invention has been described wlth reference to a community navigation system wherein a plurality of user or local clock systems are slaved to a controller or master clock system, it will be understood that the invention may be utilized in other and different systems. For example, a plurality of widely separated local computer clock systems could be slaved to the clock system of a master computer to provide for joint computational applications. In this situation, the digitally encodcd, radio-transmitted coarse, fine request and fine reply synchroni~ation signals could be replaced by simple pulses transmitted by telephone lines linking the master and local compu~cr clock systcms. In horological applicationsj remotely located time display clocks could be linked to a ., .. : ,.,, ., , , . . , . ' . ,, .. ,, ~ , ~L049151 ¦ master clock by wire or radio signals and kept~in synchronization by the aforementioned techniques. ~, . ' ~' ' Fig. 8 of th~ drawing; ill,ustrates an alternative embodiment of the invention wherein a sultable, commercially-available computer may be utili;;ed to provide the error ~ `' ¦I processing and c,ontrol sequence functions. In this :
embodiment of the invention, thc main counter 30', the l voltage controlled oscillator 31', the digital-to-analog ¦ converter 32', the up-down counter 33', the secondary counter 35' and the increment control 56' are the sam~ as the correspondingly numbered components In the em~odiment I of Fig. 2 of the drawings. In this arrangement, a computer 100 performs the functions of the sync. state control logic , I 52, the sequencing lbgic 53, the error limit logic 54 and 1~5 1 the arithmetic section logic 55 which are utilized in the ~` embodiment of Fig. 2. The software for the computer 100 ¦ would utilize the Kalman filter techniques previously described ~ ., and would provide the control state sequencing logic for ' ~ ;the sy lcm ln accordance with known programmlng techniques.

Z0 It is believed apparent thal many changes could be 1 made in the construction and describe~ uses of the foregoing "~
time base synchronization system and many seemingly ' different embo~iments of the invention could be constructed without departnng rom the scope thereo. For example, it . , . ''':
' ' .
. .
- 45,- ' ' . ..
. ' "'-... . . .
- : , . . . .
- . .
.
, . .

104915~
is belicved obvious that the previously described gain scttings and control states could be varied to suit a particular application and the characteristics of other and different clock syst~ms utilized. Accordingly, it is intended that all matter cont~ined in the above description or shown in the accompanying drawings shall be interpreted as illustrative and not in a limiting sense.

,."..",......

. . ~ ~
,~ . . . .',.. .' ~' .

" : , ,

Claims (20)

What is claimed is:

1. The method of synchronizing a local time base system having an oscillator driven clock with a master time base system having an oscillator driven clock comprising the steps of measuring the time synchronization error between the said systems at predetermined sampling times;
deriving correction signals for the local oscillator and correction signals for the local clock from the measured time synchronization error at each of said sampling times; and applying said oscillator correction signals to the local oscillator and said clock correction signals to the local clock at gains which are a function of the magnitude of the error and the number of sampling times between corrections.

2. The synchronizing method claimed in claim 1 wherein said oscillator correction signals are frequency and phase correction signals, and said clock correction signals are time correction signals.

3. The synchronizing method claimed in claim 2 wherein the oscillator and clock correction gains employed for a particular correction are determined by the control state in a programmed control state sequence in which transfer between control states for large initial errors is made automatically for a predetermined number of sequentially occurring corrections and is dependent upon the magnitude of the error for subsequent corrections

4. The synchronizing method claimed in claim 3 wherein the control states for correction of said large initial errors have high oscillator and clock correction gains and the control states for said subsequent corrections have lower oscillator and clock correction gains for steady state corrections.

5. The synchronizing method claimed in claim 4 wherein transfer from the control states having said lower oscillator and clock correction gains is made to the control states having said high oscillator and clock correction gains when said error exceeds a predetermined amount for two successive corrections during said subsequent corrections, to thereby avoid spurious corrections for transient large magnitude errors.

6. A time base synchronization system for synchronizing a local time base system having an oscillator and clock with a master time base system having an oscillator and clock comprising means for periodically measuring the time synchronization error between the local and master time bases at predetermined sampling times;
means coupled to the local oscillator for adjusting the frequency and phase thereof;
means coupled to the local clock for adjusting the time thereof;
first logic means coupled to said oscillator and clock adjusting means and said error measuring means for causing the synchronization system to assume a predetermined number of control states having different oscillator and clock correction gains and wherein at least some of said correction gains are a function of the number of said sampling times between error corrections, and second logic means coupled to said first logic means and said error measuring means for causing the synchronization system to follow a programmed sequence of said control states in correcting local oscillator and clock errors, said programmed sequence of control states simulating the operation of a linear filter with time varying gains in accordance with a Kalman transfer function.

7. A time base synchronization system as claimed in claim 6 wherein said programmed sequence of control states provides for the use of control states having high oscillator and clock correction gains for the reduction of large initial synchronization errors and the use of control states having low oscillator and clock correction gains for the reduction of smaller steady state synchronization errors.

8. A time base synchronization system as claimed in claim 7 wherein said programmed sequence of control states provides for automatic transfer between said high correction gain control states for a predetermined number of sequentially occurring error corrections for said reduction of large initial errors and for transfer between said low correction gain control states in accordance with the magnitude of the synchronization error for said reduction of smaller steady state errors.

9. A time base synchronization system as claimed in claim 8 wherein said programmed sequence of control states provides for transfer from said low correction gain control states to said high correction gain control states when said synchronization error exceeds a predetermined amount for a predetermined number of successive error corrections during said reduction of smaller steady state errors, to thereby avoid spurious corrections for transient large magnitude errors.

10. A time base synchronization system as claimed n claim 9 wherein the local oscillator is a voltage controlled oscillator and said local and master clocks are digital counters, said synchronization error measuring means is a digital counter, said first and second logic means produce digital correction pulses for the local oscillator and clock, said local oscillator adjusting means comprises an up-down digital counter having its output coupled to the local oscillator control voltage input through a digital-to-analog converter, the magnitude of the local oscillator output frequency is adjusted by incrementing or decrementing said up-down counter, and the local oscillator frequency correction gain is controlled by controlling the bit in said up-down counter where the digital correction pulses are inserted.

11. A time base synchronization system as claimed in claim 10 wherein phase adjustment of the local oscillator output is made by changing the local oscillator output frequency by a predetermined increment of frequency for a redetermined period of time and then eliminating the incremental frequency change, to thereby adjust the phase of the oscillator output by an amount which is equal to the product of the incremental frequency change and the said time period.

12. A time base synchronization system for synchronizing a local time base consisting of a cyclically recurring series of sequential time slots generated by a voltage controlled local oscillator and local digital main counter with a master time base consisting of a cyclically recurring series of sequential time slots generated by a master oscillator and master main digital counter comprising coarse synchronizing means for bringing said time bases into coarse synchronization, said coarse synchronizing means comprising means coupled to the master main counter for generating a coarse synchronization signal at the beginning of the first time slot in said series of time slots in the master time base, and means coupled to the local main counter and responsive to said coarse synchronization signal for adjusting the local main counter to begin generating the said first time slot in the series of slots in the local time base upon receipt of said coarse signal; and fine synchronizing means for bringing said time bases into fine synchronization, said fine synchronizing means comprising means coupled to the local main counter for generating a fine synchronization request signal at the start of a predetermined one of the remaining time slots in the local time base, means including a master secondary counter coupled to the master main counter for measuring the elapsed time between the receipt of said fine synchronization request signal by the master and the beginning of said predetermined one time slot in the master time base and for generating a fine synchronization reply signal at the beginning of a time period before the end of said predetermined one slot in the master time base which is equal to said elapsed time, means including a local secondary counter coupled to the local main counter for measuring the elapsed time between the receipt of said fine synchronization reply signal by the local and the end of said predetermined one time slot in the local time base to produce a digital synchron-ization error signal, means coupled to the local oscillator for adjusting the frequency and phase thereof in response to local oscillator correction signals, means coupled to the local main counter for adjusting the time thereof in response to local main counter correction signals, control state logic means coupled to said synchronization error measuring means and said local main counter and oscillator adjusting means for establishing a plurality of control states in response to sequencing signals, each of said control states having said local oscillator and local main counter correction signals derived from said synchronization error signal in accordance with a Kalman filter algorithm providing for time varying correction gains which depend upon the number of cycles of said time slots between error corrections, error limit logic means coupled to said synchronization error measuring means for producing error limit signals when said error exceeds a predetermined range of values, and sequencing logic means coupled to said control state logic means and said error limit logic means and responsive to said fine synchronization and error limit signals for producing said sequencing signals to cause said synchronization system to follow a programmed control state sequence in which transfer between control states for large initial errors is made automatically for a predetermined number of sequentially occurring corrections and is dependent upon the magnitude of the synchronization error for subsequent corrections.

13. A time base synchronization system as claimed in claim 12 wherein the local time base system is remotely located from the master time base system, and said coarse and fine synchronization signals are transmitted between said local and master systems by means of wire.

14. A time base synchronization system as claimed in claim 12 wherein the local time base system is remotely located from the master time base system, and said coarse and fine synchronization signals are transmitted between said local and master systems by means of radio transmissions.

15. A time base synchronization system as claimed in claim 14 wherein said coarse synchronization, fine synchronization request and fine synchronization reply signals are digitally encoded radio signals.

16. A time base synchronization system as claimed in claim 12 wherein said local oscillator adjusting means comprises an up-down digital counter having the output thereof coupled to the control voltage input of said local oscillator through a digital-to-analog converter, said local oscillator correction signals comprise digital input signals to said up-down counter representing the magnitude and sign of the frequency correction, and the local oscillator frequency correction gain is controlled by controlling the bit in said up-down counter where the digital input signals representing the magnitude of the frequency change are applied.

17. A time base synchronization system as claimed in claim 16 wherein phase adjustment of the local oscillator output is obtained by introducing a predetermined increment of frequency into the osicllator output for a predetermined time period and then removing the frequency increment at the end of said time period, to thereby adjust the phase of the oscillator output by an amount equal to the product of the frequency increment and said period of time.

18. A time base synchronization system as claimed in claim 12 wherein the control state for the first cyclic correction has a unity main counter correction gain and a zero oscillator correction gain to allow for the correction of large initial phase errors, the control states for the second through the fifth cyclic corrections have a unity main counter correction gain and a high oscillator correction gain to allow far the correction of large initial frequency errors, and the steady state control states for the sixth and subsequent cyclic corrections have a low oscillator correction gain and a main counter correction gain which is equal to a low gain plus a variable gain which is a function of the number of time base cycles between corrections.

19. A time base synchronization system as claimed in claim 18 wherein the synchronization system remains in the control state for the sixth cyclic correction for so long as the measured synchronization error does not exceed a predetermined amount for a predetermined number of subsequent successive cyclic corrections and is returned to a control state having higher oscillator and counter correction gains if the error exceeds said predetermined amount for said predetermined number of subsequent cyclic corrections.

20. A time base synchronization system as claimed in claim 12 wherein the local main counter is corrected in time by causing it to count at double its normal rate upon receipt of said fine synchronization reply signal for control states having large main counter correction gains.