CA1068570A - Method and apparatus for fluid flow control in the parenteral administration of fluids - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE
This invention relates to improvements in fluid flow control systems for parenteral administration of medical fluids.
Prior art control systems are generally adaptable for only a single type of output device and are often deficient in their regulating accurately over a wide range of flow rates. The present invention overcomes these deficiencies by providing a digital system for parenteral administration of medical fluids, wherein a wide variety of different electromechanical output control devices, e.g. a ste ing motor pump or a solenoid actuated I.V. tube pincher, is driven by electrical output pulses of variable frequency and pulse width from a digital pulse generation and control system, the frequency and pulse width of the output pulses being selected and controlled by the system to establish drop flow rates with digital precision over an extremely wide dynamic range. In the preferred embodiment, desired flow rate is achieved, under control of the varying output pulses, by the repetitive unclamping and clamping of the I.V. tubes. Duty cycle limitation, appropriate to the particular operating characteristics of the electromechanical output device utilized, Is implemented to avoid inducing run-way free flow conditions. Appropriate alarms respond to system malfunctions to alert medical personnel.

Description

` 106~S'~ -This invention relates generally to improvements in fluld ~low control systems and more particularly, to a ~-new and improved automatic, sel~-regulating, highly accur-ate drop ~low control system ~or parenteral adminlstration of medlcal ~luids over a wlde range of fluid ~low rates and capable of utllizing a variety of different electromechan- -lcal outpùt devlces, ~uch as posltive pressure lnfuslon pumps u~lng stepping motors or the like, as well a~ con- --trollers uslng electrlcally actuated I.V tube plnchers.
The usual medlcal procedure for the gradual par- -enteral admlnistration of llquids into the human body, such as llquid nutrlents, blood or plasma, makes use of appara-tus whlch ls oommonly referred to ln the medical art as an intravenous adminl~tratlon ~et. The intravenous set usual~
1~ comprlses a bottle of liquld, normally supported in an lnverted posltlon, an lntravenou~ feedlng tube, typl¢ally o~ clear plastic, and a sultable valve mechanism, such a~
a roll clamp, which allow~ the liquld to drlp out of the bottle at a selectively ad~ustable rate into a transparent 20 drlp chamber below the bottle. The drlp chamber serves the dual ~unction of allowing a nurse or other attendant to observe the rate at whlch the liquid drips out of the bottle and also creates a reservoir ~or the llquid at the ; lower end of the drlp chamber to in~ure that no air enters the main feeding tube leading to the patient.
While observatlon o~ the rate of drop flow vla the drlp chamber is a ~imple way o~ controlling the ~mount of llquld fed to a patlent over a period of tlme, lts ultl-mate e~fectlveness requlres that a relatively constant 30 vigil be maintalned on the drop flow, lest lt cease entire-ly due to exhau~tion o~ the llquid supply or become a contlnuous stream and perhap~ lncrease the rate of llquld introduction to the pat~ent to dangerous levels.

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By way of example, lt has been the general prac-tice ln hospltals to have nurses periodlcally monitor drop flow rate at each intravenous feedlng or parenteral in- -fu~ion statlon. Such monitoring of drop flow ls a tedious and time ¢on~uming process, prone to error and associated, po3slble serious consequences5 and resulting in a substan-tial reductlon of the avallable time of quall~led medical personnel for other important dutles. Typlcally, the nurse monitorlng drop flow rate wlll u~e a watch to tlme the number of drops flowing ln an interval of one or more `~ mlnutes, and she wlll then mentally perform the mathematlcs neces~ary to convert the observed data to an appropriate fluid flow rate, e.g., ln cublc centlmeters per hour or drops per minute. If the calculated flow rate 18 SUbBtan-tially dlfferent than the pre~cribed rate, the nurse must manually ad~u~t the roll alamp for a new rate, count drops agaln, and re~alaulate to measure the new rate. -Obvlously, each of the aforedescrlbed measurements ; and calculatlons and flow rate ad~ustments usually take several mlnutes time whlch, when multiplled by the number of stations being monitored and the number of times each statlon should be monltored per day, can result ln a sub-stantial percentage of total personnel tlme avallable. In addltion, under the pres~ure of a heavy ~chedule, the ob-servations and calculatlons performed by a harried nurse - in measurlng and ad~usting ~low rate may not always pro~e ; to be reliable and, hence, errors to occur resultlng in undesired, possibly dangerous infusion flow rates.
In addition to the aforedescribed difficultieR, the parenteral admlnistratlon of medical llquids by gravity ,~,, indu¢td hydrostatic pressure lnfusion of the liguid from a bottle or other container suspended above a patlent, ls very susceptible to fluid flow rate variation due to changes in the llquid level in the bottle, changes in temperature, - -changes in the venous or arterial pressure of the patient, patient movement, and drift in the effective setting of the roll clamp or other valve mechanism pinchlng the feed-ing tube. Moreover, there are a number of situations, such a~ ln lntenslve care, cardlac and pedlatric patlent~, or where rather p~tent drugs are being admlnisted, where the desired drop flow rate must be capable of preclse selection and mu~t not drift beyond certain prescrlbed llmits. In addltlon, lt ls extremely important ln such situatlons for medlcal personnel to be lnformed of undeslred fluc-tuations ln flow rate, fallure of the fluld dellvery ~y~tem, or exhauatlon of llquld supply when the bottle ls emptled.
It will be apparent, therefore, that some o~ the mo~t crltl¢al problams con~ronting hospital personnel fa¢ed wlth an overwhelmlng duty schedule and limlted time avall-ablllty are the problems of qul¢kly, easlly, relia~ly and accurately monltoring and regulating drop flow rate ln the parenteral admlnlstration of medical liquld~.
In recent years, a number o~ electrlcal monitor-lng systems, drop flow co~trollers and in~uslon pumps have been developed to accompli~h the various taaks of sensing and regulating drop ~low rates. Some of the~e device~
have al~o been capable of activating alarms when a poten-; tlally dangerous conditlon exlsts, thus freelng medlcal personnel to some extent for other dutles. However, whlle such monltorlng and drop rate control devices have gener-ally served thelr purpose, they have not always proven 30 entlrely satisfactory from the standpolnt of cost, com-plexity, stability, reliability, accuracy, adaptability to dlfferent types of electromechanlcal ~utput devlce~, or preclsion o~ adjustment over a wide range of selected '' ..

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10685~70 flow rate~. In addition, such systems have sometlmes been subJect to drift and substantial flow rate varlatlons due to changes in temperature feeding tube crlmps, varlatlons in venous or arterlal pressure of the patient, or varlations in the height of the bottle or solution level wlthin the bottle. Substantial difficultles have been experienced particularly ln connectlon with establishing and malntalning ~uch ac¢urate drop flow at very low flow rate~.
Hence, those concerned with the development and 10 use o~ parenteral ~luld adminlstration sy~tems, and partlcu-larly tho~e concerned with the design of automatlo fluid flow control systems, have long recognized the need for improved, relatlvely ~imple, economlcal~ adaptable, relia-able, ~table and accurate devlces for ~luid flow aontrol whlch obviates the aforedescrlbed dif~icultles. The present lnvention alearly fulflll~ this need.
Brlefly, and in general terms, the present inven-tion provldes a new and improved method and apparatus for controlllng drop flow ln the parenteral adminlstration of 20 medlcal liquid~, whereln the frequency and pulse width of electrical output control pulses which operate an electro-mechanical output control device regulatlng liquid flow in a feeding tube are controlled by a unique digltal sy~tem cap-able of sen3ing and regulating drop ~low rate very accurate-. ly over a wlde range o~ ~low rates and with a varlety Or dif~erent electromechanical output devices.
The system for e3tabllshing the frequency o¢ theoutput pul~e~ to the electromechanical control device regu-latlng fluld flow is an open loop digital command system 30 embodying an all digital pulse generation and rate selection subsy~tem wherein the output pulse frequency repre~entlng desired drop ~low rate i~ a relatlvely hlgh, preferably non-integral multlple o~ the actual drop flow rate frequency.

;8570 In the case of some electromechanlcal output control de- ;
vices, as reciprocating I.V. tube plnchers, such a relation-ship between the commanded output pulse frequency and the de~ired drop rate frequency tends to produce less drop dis-tortion and more consl~tently repeatable drop slze from one drop to another.
Addltional control over drop flow rate ls accom-plished by varying the pulse width of the output electrlcal pulses to the electromechanical control devlce, i.e., the tlme duratlon of the period of energlzatlon of the output control devlce provlded by the output pulse. Thls output pulse width i9 preclsely controlled by a closed loop dlgl-tal ~ystem whlch varles the pulse wldth ln digltal servo fashlon to establlsh the desired drop flow rate while maln-talning the a~oredescribed relationship between the aom-manded output pulse ~requency and the desired drop flow rate frequency.
I'he width of the electrical output pulse~ to the electromeahanical control devlce i5 unlquely determined by . . .
a digital memory subsystem whiah includes a palr of - counters, one counter embodylng a ~cannlng control regls-ter, the other counter embodylng a pulse width register.
The scannlng control register determines the duration of each counting cy¢le for itself and the pulse width regls-ter, by initlating and terminatlng the counting cycle for both regl~ter~, the normal rest state for the scanning reg-lster bekween counting cycles (i.e., the lnitlal and final ~tate ~or each countlng cycle) being lts "zero" ~tate.
;Inltiation of each counting cycle, and each out-put electrlcal pulse from the overall control system, ocaurs with each pulse generated by the open loop pulse generatlon and rate selection subsystem. Each output pulse i~ term-lnated whenever the pulse wldth register ls counted to its :

"zero" state. The count in the pulse width reglster at the terminatlon of each countlng cycle is a measure of the pulse width for the electrical output pulse to be gener-ated by the dlgltal system on the next succeedlng counting ~
cycle. In this regard, the pulse width of the output -pulse~ expreseed as a functlon of the content of the pulse wldth reglster 1~ determined by the number of counts re-quired to count up the pul~e width register from its inl-tlal ¢ount state (which ls the last count ~tate in the 10 lmmedlately precedlng countlng cycle) to lts "zero 3tate, the output pulse belng terminated a~ the pulse wldth reg-l~ter ls counted through "zero".
The pulse wldth regi3ter comes to rest in each counting cycle at a count whlch determlne~ the pulse width for the next output pulse to be generated, each countlng cycle being termlnated when the scannlng control register ha~ aounted to "zero". Hence, a unlque pul8e wldth dlgi-tal memory ls provided by the present inventlon.
In accordance wlth the lnvention, the pul~e wldth r~ 20 reglster i8 uniformly decremented by a predetermined num-ber of counts relatlve to the scannlng control register durlng each countlng cycle, to provide output electrical pulses of gradually increaslng pul~e wldth. The pul~e width register i~ also incremented a pre~¢ribed number of ¢ounts relative to the scanning control register, ea¢h time a drop is detected by the system, thereby narrowing the pulse width whenever a drop is detected. The ratlo of the number of counts by whlch the pulse wldth reglster is ; lncremented each time a drop ls detected, to the number of counts the pulse width register is decremented durlng each counting cycle, 19 the same as the aforede~crlbed ratio of output pulse frequency to desired drop flow rate frequency.
Hence, the desired frequency relatlonshlp 1~ preclsely . . ~ .

1~)685~7~

established wlth dlgital precision.
A duty cycle limitation subsystem overrides the pulse width determlnation by the dig~tal memory subsystem in the event the pulse width prescribed by the memory sub-8ystem would exceed an appropriate maximum duty cycle suited to the particular electromechanical output control device being utilized, in order to avoid the possibllity of lnducing runaway free flow condltlons, due to mechanlcal limltatlons in the output control devlce, and consequent 0 10s8 Or control.
The duty cycle llmitation subsystem monltors the commanded period between ~uccessive inltiations of electri- -¢al output pulses and, at the desired duty cycle llmlta-tlon polnt selected for the partlcular electromechanlcal output aontrol device belng ut81ized, terminates the out-put pul~e, provldlng an instantaneous llmitatlon on the electrloal output to the mechanical subsystem, while simul-taneou~ly ~peedlng up the counting rate to the dlgltal memorg 80 that the countlng cycle ls completed more rapld-ly. This latter feature also insures that t~.e dlgltal memory wlll always have completed the la~t countlng cycle prior to inltlatlon of the next counting cycle, in the event a hlgh pulse frequency ls commanded with a perlod between initiatlon of output pulses shorter than the count-lng cycle of the memory at the normal counting rate. How-ever, the accelerated countlng rate to the dlgltal memory provlded by the duty cycle llmltation subsystem lnsures completion of each countlng cycle even at the highest sele~
ted output pulse rates.
A start-up sub~ystem, effective only durlng lnl-t~al operation of the sy~tem or after coming out of an alarm state, temporarily controls the rate selectlon and memory ~ubsystems and accelerate~ inltlal pulse wldth ' -~068570 regulation to more rapidly ach~eve normal operating con-ditions. In this connectionJ the pulse width reglster is decremented by a greater number of counts per counting cycle during the start-up phase to increase the width of th~ electrical output pulses more rapidly. In addition, and only durlng the start-up phase, the rate selectlon subsystem iB preset internally to a prescribed rate, to lnsure that the output pulses are not comlng too slowly or too rapidly during lnitial ad~ustment of the overall lO system. The start-up phase contlnues until a prescrlbed number of initial drops have been detectedl at which time the start-up subsystem relinquiæhes control, and normal pulse rate control and output pulse width ad~ustment occurs for subsequent drop flow beyond the initial few drops de-tected.
For certain types of electrome¢hanlcal output control devl¢es, particularly those capable o~ functioning properly with very narrow pulse width input, the system of the present invention is capable of functioning normally on an expanded low level operational ba~ls, without going into alarm, by storlng and processing the equlvalent of negative pulse wldth in the dlgital memory. This condltlon may occur with normal low level operation in whi¢h ex-tremely narrow pulse wldths are generated, so that further incrementing of the pulse width register upon detection of drops causes the pulse wldth register to overflow.
Overflow of the pulse wldth reglster countwise ls equlvalent to underflow of pulse width, i.e., negative pulse width, which is manlfested by the sudden transition from a very narrow output pulse (a high count in the pulse width reglster) to a very wide output pulse (a very low count in the pulse width register). Assuming the system ls operating to provide normal fluid flow, i.e., there are .

~ 168570 no flow conditions warrantlng generation of an alarm state, the negatlve pulse width condltion will be only transl-tory, and successive decrementing of the pulse wldth regis-ter in ~ucceeding counting cycles should bring the digital memory out of the negative pulse width region and restore normal narrow output pulse generation. ~ence, the cap- ~ -ability o~ operatlon in the negative pulse width reglon by the system of the present lnvention enables an expanded dynamic range o~ operatlon without the need for expanding the count capacity o~ the digltal memory.
The electromechanical output control devlces which may be utllized wlth the system o~ the pre~ent invention -~-generally fall lnto one of two categorle~, po~itive pres-sure infusion devlces such as pumps, or devices whlch sim-ply open and close a feeding tube and are dependent upon gravlt~ induced h~dro~tatic pressure for producing drop ~low The latter category includes I.V. tube plncher de-vlce~ whereln a feeding tu~e clamplng member, normally in the tube ~hut-o~ position, ls repeatedly moved to the tube 20 open po~ition by a sultable electromechanlcal drlver which is, in turn, energized by the electrical output pulse~
~rom the prevlously deacribed dlgital system.
Since gravity induced hydrostatic pressure is a function of ~uch parameter~ as the height o~ the bottle, - the liquld level in the bottle, and the size and flexi-bility o~ the feeding tube, and each of these parameters can be altered, lt is desirable to visually observe an indl ation o~ the output pulse wldth operating range so that, ln the event pulse width ls not in the optimum range, guitable ad~ustoent~ can be made~ such as raising or lower-ing the height of the bottle~ to establish hydro~tatlc pres~ure levels in the feeding tube appropriate to pulse width generatlon in the optlmum region o~ operatlon. The _g _ :., . , ~, . ' . ~

present system provides ~uch a visual lndlcatlon by moni-torlng the status of the pulse wldth reglster and indica-ting, by means o~ a pair o~ lights, whether the electrlcal output pulses being generated by the system fall wlthin the hlKh, low or optimum pulse wldth ranges.
The dlgltal memory 3tatus ls also monitored so that out-of-llmlt condltion~ calllng for flow rate3 ln excess of system dellvery capabllity, or lndlcatlng a , leakage flow rate which cannot be terminated by the output control devlce, trlgger approprlate alarm ~ubsystem~. The 3ystem provides the flexlblllty of a high level alarm whlch indicates a demand for too wlde an output pulse, a varlety Or low level alarms re~ponsive to speclfled non-tolerated sequences of pulse wldths, including excesslve negative pulse wldths for certain type3 of output control devices.
In addition, in order to warn appropriate medical personnel of an exhausted llquid aupply or any other condl-tion ln the adminlstration set preventing ~luid delivery, the alarm ~ubsystem sy~tem is re~ponslve to a lack of drop ; 20 flow detected in a predetermined period of time and as a function of a predetermlned number o~ electrical events ln the control system. In thls regardJ the system alarms if no drops are detected after a prescribed number of output pulses have been ¢ommanded by the open loop pulse genera-tion sub~ystem, and the system wlll also alarm if no drop~
or output electrical pulses have occurred ln a prescribed tlme lnterval.
The new and improved ~luid flow control system of the present lnvention ls extremely accurate, rellable and 30 easy to use. The sy~tem provide~ enhanced digltal pre-cision in ~electing and malntainlng drop flow rates through-out a wide range, and the sy~tem i9 quick to inform med-ical personnel of any conditions which mlght po~e a hazard :

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^` ~068570 to the patlent. Hence, the system of the present lnventlon minlmlzes the tlme consuming and error prone aspects of human m~nltorlng and flow rate adjustment and provides 8ub~tantlal improvement ln economy, adaptablllty to a var- - -lety of dlfferent mechanical output control devlces, rell-a~lllty, stabllity and accuracy over prevlous automatlc control 8y8te~
In one aspect of this invention there is provided apparatus for use in a system for parenteral administration of liquids at desired drop flow rates through a feeding tube from a liquid source to a patient. The apparatus comprises:
electro-mechanical output control means for manipulating the feeding tube to vary the flo~ of liquid in the feeding tube;
electrical pulsing means for providing output pulses to ope-rate said output control means; and digital memory and timing means for automatically predetermining and varying the pulse width of said output pulses operating said control means, to achieve the desired drop flow rate. The output control means is inactive during the periods between said output pulses in a pulse train. The output pulses are at a substantially high-er frequency than the desired drop flow rate frequency.
In another aspect of this invention there is provided apparatus for use in a system for automatic parenteral ad-ministration of liquids at a desired drop flow rate through a feeding tube from a liquid source to a patient. The appa-ratus comprises: output control means for determining the rate of drop flow of liquid in the feeding tube; electrical pulsing means for providing successive output pulses to said output control means; and timing means for varying the pulse width of each of said output pulses to vary the time that said output control means permits liquid to flow in said feeding tube, thereby achieving the desired drop flow rate. The output ' ~
/)~ - 11 -control means is operable to permit liquid flow in a feeding tube during said output pulses and operable to prevent liquid 10w during the periods between said output pulses in a pulse train. The output pulses are at a substantially higher frequency than the desired drop flow rate frequency.
In a further aspect of this invention there is provided a method for use in the parenteral administration of medical fluids by an intravenous set including drop forming means in a flexible tube coupled to said drop forming means for carrying drop flow. The method includes controlling the rate of drop flow through the flexible tube. The mRthod comprises:
clamping said tube to a substantially shut-off state; produ-cing digital control pulses in a pulse train at a selected frequency proportional to the desired rate of drop flow;
monitoring the actual drop flow occurring through said tube;
selectively varying the pulse width of each of said control pulses in a digital memory in accordance with the desired drop flow rate detected; and repetitively opening and closing said tube to fluid flow in response to said digital control pulses to regulate the actual drop flow rate so that it conforms to said desired drop flow rate. The tube is closed during the periods between said control pulses and said pulse train.
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These and other objects, advantages and aspects of the lnventlon will become apparent from the follo~lng more de-- talled description, when taken in conJunction wlth the accompanying drawings Or lllustrative embodiments.
FIGURE 1 ls a block dlagram of an overall system ln whlch some of the baslc concepts of the fluld ~low con-trol ~ystem of the present invention are embodled;
FIGURE 2 ls a graphical representatlon lllustra-~ tlng typical drop size as a function o~ output pulse fre-; quency;
~ .
~r~ a~ -~` ~0685'70 ~:

FIG~RE 3 19 a graphlcal representation of output pulse wldth as a ~unctlon of time;
FIUVRES 4a, 4b and 4c are comblned block dlagrams -.
and electrical schematics of one embodiment of an overall fluld ~low ¢ontrol system ln aocordance with the present invention, FIGURE 4a belng prlmarily directed to the lnput and timlng aubsystem and the output subsystem, FIG~RE 4b being prlmarlly dlrected to the memory and control sub-systems, FIG~RE 4c belng primarlly directed to the vlsual pulse wldth monltorlng subsystem and alarm subsystem;
FIG~RES 5a-5h are graphical representatlons illus-trating varlous electrl¢al state~ in the overall control system o~ FI~RES 4a, 4b and 4c for a varlety Or condltlons :.
of operatlon which demonstrate the functionlng of the duty cycle limltatlon subsystem;
FIG~RES 6a-6g are tables lllustratlng reglster and ' .

:
, ;

,'' :

.

, ;
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:., -- 11 Lb~ --,-~,f~, 106~357(~

flip-flop states in the overall system of FIG~RES 4a-4c for a variety of dlfferent conditions under which drops may be detected;
FIG~RES 7a and 7b and FIGURES 8a-8d are waveforms ~or various portions of the overall system o~ FIGURES 4a-4c when the system 18 being operated in the pump mode; and FIG~RES 9a, 9b, lOa and lOb are waveforms for various portions of the overall system of FIG~RES 4a-4c when the system is being operated ln the controller mode.
Referrlng now to FIGYRE 1 of the drawlngs, there i8 shown a new and improved system for fluld flow control embodylng features of the present lnventlon. In the en-~ulng de~criptlon, whlle reference will be made to the term "I.V." normally connotlng intravenous adminlstratlon, lt is to be understood that this i~ by wag of example only, and the flow control ~ystem of the pre~ent invention 1~ suit_ able for other forms of parenteral admlnl~tratlon as well a~ lntravenou~ admlni~tratlon ' In order to control drop flow rate, lt ls neces-ary to contlnuously monltor the actual drop flow as it occurs ln an I.V. admlnlstration set. Thls is accom-- pllshed ln the system of FIGYRE 1 by a drop detectlon ~ub-~ystem ll which includes a drop sensor lla and a pulse -~ generator llb, both well known ln the art, adapted to detect each drop as lt falls and generate electrlcal pulses at a frequency equal to the drop flow rate.
The drop sensor lla monitors drop flow in a drip chamber ~not shown) of the I.V adminlstratlon set and typlcally may ln~lude a sensor hou~ing (not shown) con-talning a reference llght source located a fixed dlstancefrom a photocell to define an optical sensing gap there-between, with a reference light beam normally implnging upon the photoce~. Th~e houslng ls approprlately clamped 1068570upon the drip chamber o~ the I.V set, with the transparent drip chamber positioned within the sensing gap to inter-cept the re~erence beam A falling drop of llquld within ~- -the drip chamber lnterrupts the reference beam, and the variation in electrical response of the photocell is directed to appropriate circuitry indicating the presence o~ a drop. One example o~ a suitable drop sensor lla is ~:.
set forth in ~. S Patent No. 3~596,515, inventor, Richard A. Cramer While a photocell monitoring device is ideally suited for the drop sensor lla, it will be appreciated that any drop sensing device capable of providing an elec-; trlcal lndlcation of the detectlon of a drop may be used ; without departlng from thæ spirit and scope of the inven-tlon.
The pul~e generator llb i8 typically a conven-tional mono3table flip-~lop (one-3hot) whlch provldes an output pulse each tlme a drop ls detected by the drop sen~or lla, the output pul3es having a prescrlbed pulse width and amplltude compatlble with the input clrcuit re-quirements of the particular monltoring and control sy~tem utilized. The pulse output from the pulse generator llb, representing the detected drop ~low rate, is dlrected as one input to a memory control subsystem 13, and ls also d irected as lnput to an alarm subsystem 14.
Fluid ~low in the feeding tube of the I.V. admin-istratlon set is regulated by the system of the present : invention v~a an electromechanlcal output control device - 15 which, in turn, is periodically energized by receivlng as electrical input the pulsed output over line 17 from an output pulse control subsystem 16.
A variety o~ different electromechanical output control devices 15 can be used with the system of the present invention, such as positive pressure infusion .. . . -1~68S70 pumps~ driven by a d.c stepping motor, or other types of a c or d.c. motors, or devices which simply open and close a feedlng tube and are dependent upon gravity in-duced hydrostatic pressure for drop flow, i.e., a drop ~low oontroller rather than a pump. By way of example, ~he sy~tem of the present lnvention ls described in con-nection with the operatlon of two different types of out-put control devices, one from each of the aforedescrlbed categorles .
10In the lnfuslon pump category, a d.c. stepping motor is employed as a drive for the infusion pump to provide a stepped incremental mechanical output to a ~lurality of cam followers or the like (not shown) whlch ma~sage the I.V feedlng tube and generate a peristaltic pumping actlon capable of developing a substantial posi-tive pre~3ure in the ~eeding ~ube.
In the ~low controller category, the controller ' lncludea an I.V tube pincher devlce wherein a ~eeding tube clamping member, normally apring biased to the tube shut-off posltlon, ls repetltively moved kothe tube-open poaltlon by a ~ultable electromagnetic drlver which is, in turn, energized by the electrical output pulses over llne 17 from the pulse control subsystem 16. Each output pulse directed to the output control device ~, in the case ~ the controller, causes the clamping member to be retracted and thereby opens the feeding tube ~or the duration of the output energizing pulse width. ~y way of -example, the I.V. controlJar output control device 15 may be of the type set forth in U.S Patent No. 3,756,556, inventor, Heinz W. Georgi.
In the case of the stepping motor infus~on pump, each electrical output pulse over line 17 from the pulse control subsystem 16 gakes on a burst of stepping motor ~068570 driver pulses, the duratlon o~ the driver pul3e burst ~ -substantially matching the duration of the output ener-gizing pulse width. Each driver pulse steps the motor a precisely defined rotational increment and thereby peris- ~ -taltically induces fluid flow in the feeding tube by ad-vancing a body of fluid trapped between the cam followers.
While the invention is described in detall, by way of lllustration, in connection wlth the aforementioned stepping motor infusion pump and I.V. controller as typlcal output control devices 15, lt wlll be appreciated that other output control devlces can be readily utilized within the framework of the system described, without departing f;rom the splrit and scope of the lnventlon.
A pulse generatlon and rate ~electlon subsystem 18, which i3 an open loop digital command subsystem, e~tabli~hes the frequency o~ the output pulses produced by the system over line 17 to the output control device 15.
The subsystem 18 is an all dlgital pul~e generatlon ~ub-system which generates a pulse frequency output over line l9 to the output pulse control subsystem 16 and directs the same output over llne 20 to a dlgltal memory subsy~tem 21.
The desired drop flow rate is selected by the operator through ad~ustment of the pulse generation and rate selection subsystem 18. The output pulse frequency from the subsystem 18 ls, in accordance with the invention, not the actual drop flow rate desired, but rather a rela-tively hlgh, preferably non-lntegral multiple of the actual drop flow rate frequency, e.g., typically a ratio of lO-1/2.
In the case of some electromechanlcal output control de-vices 15, such as reciprocating I.V. tube pinchers, such a relationship between the commanded output pulse fre-quency and the desired drop rate frequency tends to produce less drop distortion and more consistently repeatable drop size from one drop to another. This is apparent from FIG~RE 2 of the drawings which illustrates typical drop size as a function of output pulse frequency using an I.V.
controller. The baslc concept of using such a high, non-integral ratlo of output pulse frequency to desired drop flow rate frequency with I.V. controllers has been pre-viously set forth in ~.S Patent NQ. 3,800,794, issued April 2, 1974, to the same inventor as the present appli-lO cation. However, an analog memory and dlfferent type ofcontrol subsystem is taught ln the aforementioned ~. S.
Patent No. 3~8OOS794 than ln the present appllcatlon.
The command pulses generated over line l9 to the output pulse control subsystem 16 determine the inltiation of each output pulse over llne 17 to the output control devlce 15, whereas the termination of each output pulse ls determined by the dlgital memory subsystem 21 whi¢h dlrects an lnput over line 22 to the pulse control sub-system 16. ~enc, ln addltlon to the output pulse fre-20 ~uency control provided by the pulse generatlon and rateselectlon subsy~tem 18, addltlonal control over drop flow rate ls accompllshed by varying the pulse width of the output electrical pulses to the control device 15, i.e., the tlme duratlon of the per~od of energization of the output control devlce provlded by each electrlcal output pulse on line 17. The output pulse wldth is precisely controlled by a closed loop dlgital subsystem, which ln-cludes the digi~al memory subsystem 21, and which varles the pulse width ~n dlgital servo fashion to establish the - 30 desired drop flow rate whlle always maintaining the afore-~scribed relatlonshlp between the commanded output pulse frequency and the desired drop flow rate.
The wldth of the electrical output pulses to the output control devlce 15 is uniquely determined in the system of the present invention by the digiral memory sub-sy3tem 21 in con~unction with the memory control subsystem 13, whlch, in turn, recelves information not only from the dlgital memory subsystem but also ~rom the drop de-tectlon subsystem 11 whlch lncludes the drop sensor lla and pulse generator llb.
The digital memory subsystem 21 includes a pair of dlgibal countersg one counter embodying a scanning control reglster, the other counter embodylng a pulse wldth register. The~e reglsters undergo a counting cycle whlch is lnltiated each time a pulae ls generated over llne 20 by the pulse generatlon and rate selection sub-~y~tem 18, and each counting cycle must be completed be-~ore the next pulse is produ¢ed on llne 20. The ~¢annin~control regl~ter determines the duration o~ each countlng cycle, for itself and ~or the pulse width register, by inltiating and terminating the counting cycle for both reglsters, the normal rest state ~or the scannlng register between countlng cycles (i.e., the lnltial and final state ~or each counting cycle) being its "zero" state.
As previously indlcated, not only i9 lnitlation of each counting cycle determinedS but each output elec-trical pulse ~rom the system over line 17 is al~o ini-tiated, with each pulse generated by the open loop pulse generation and rate selectlon subsystem 18. Each output pulse over line 17 to the control device 15 i9 termlnated whenever the pulse width register of the memory subsystem 21 ls counted to its "zero" state.
The final count ln the pulse width reglster at the termlnation of each counting cycle is a measure of the `; pulse width ~or the very next electrical output pulse to be generated by the system over line 17 on the next succeeding countlng cycle. In this regard, the pulse width of the output pulse over line 17 to the control device 15, expressed as a function of the pulse wldth register count, iB determlned by the number of counts required to count up the pulse width register from lts initlal count state (which is the final count state in the immediately preceding counting cycle) to its "zero"
state, the output energizing pulse to the control device 15 being terminated as the pulse width register is counted through zero. The latter state if communicated over line 22 to the output pulse control subsystem 16.
The pulse width register comes to rest in each ;~
counting cycle at afinal count which determines the pulse width for the next output pulse to be generated over line 17, each counting cycle being terminated when the scanning control register has ¢ounted to its "zero" state.
In accordance with the lnvention, the pulse width register in the dlgital memory subsystem 21 is uniformly de¢remented by a predetermined number of counts relative to the scanning control register during each counting cycle, to provide output electrical pulses of gradually increasing pulse width. The pulse width register is also incremented a prescribed number of counts relative to the scanning control register each time a drop is detected by the drop sensor 11, thereby narrowing the pulse width - whenever a drop is detected. This ls ac¢omplished vla the memory control subsystem 13.
The ratio of the number of counts by whlch the pulse width register is incremented each time a drop is detectedg to the number of counts the pulse width re~ister is decremented during each counting cycle, is the same as ; the aforedescribed ratio of commanded output pulse fre-quency to desired drop flow rate frequency. By way of o68570 example, in a presently pre~erred embodiment of the system of the present invention, the pulse width register is de-cremented by 2 counts during each counting cycle and in-cremented by 21 counts each time a drop is detected by the drop ~ensor lla. Hence, the desired input to output fre-quency ratio of 10~ is precisely established in the digltal memory subsystem 21.
~ he manner in which the output pulse width over llne 17, lndicated in terms of the counts stored in the pulse width reglster of the memory subsystem 21, varies as a function of time is illustrated in FIG~RE 3 of the draw-lngs. It will be apparent from FIG~RE 3 that the output pulse width varies as a staircase function, with each in-; crea~e in pulse width belng 2 count~ decremented from the pulse width reglster and each decrease ln pulse wldth belng 21 counts incremented lnto the pulse width reglster at the polnt of drop detectlon, The wldth of each step in the staircase waveformls a tlme period whlch ls the reclprocal of the output pulse frequency on llne 17, or 1 _ x drop rate. It , 10~
~ wlll be noted that each stalrcase pattern between succes-- sive drop detection events varles ln the number o~ pulse periods or steps included, the patterns alternatlng in 10 and 11 pulse period grouplngs to provide an avera~e lnter-val between successlve drop detectlons of 10'~ pulse periods, the desired ratio.
A start-up subsystem 12 ls e~fective during ini-tlal start-up of the overall system, as well as each tlme the system is brought out of an alarm state. Tn this re-gard, the system starts out with both of the registers ofthe digital memory subsystem 21 reset to their "zero"
; states, so that normal operation of the system would pro-duce extremely narrow initial output pulses over llne 17.

., -19-,'lj~i~
. ...

The start-up subsystem alters the normal operatlon of the memory control subsystem 13 by acceleratlng initial pulse width regulation by the digltal memory subsystem 21 to more rapldly achieve optimum performance conditions by qui¢kly brlnging the output pulse width over llne 17 closer to it~ ultimate range of preferred operation. In order to accomplish this, the pulse width register ls caused to be decremented by a greater number of counts per counting cycle durlng the start-up phase, to increase the width of the electrlcal output pulses more rapldly. Typlcally, instead of increasing pulse width by only 2 counts in the pulse width register each counting cycle, as ls done during normal operation, the pulse width ls lncreased by 9 counts ;
during ea¢h counting cycle. Thls increases the width of -~
electrical output pul~es much more rapidly than would occur ; if the optlmum pulse width operatlng range were approached by the much slower 2 count per countlng cycle lncrease in pul~e wldth.
In addition, and onlg while a start-up phase o~
operation is in ef~ect, the pulse generatlon and rate selection subsystem 18 is temporarily set internally by the start-up system 12 to a predetermlned output pulse rate most suitable for initial ad~ustment o~ pulse width.
: The start-up phase continues until a prescrlbed ; number of lnitial drops~ typ~cally two drops, have been detected by the drop sensor lla, at which time the start-up subsystem 12 relinquishes control, and normal putput pulse width ad~u~tment, l.e., 2 counts of the p~lse wldth register per counting cycle, occurs for all subsequent drop 30 flow beyond the lnitlal two drop~ detected.
A duty cycle llmitation sub~ystem 23 overrldes the pulse width determination by the dlgital memory sub-system 21 in the event the pulse width prescribed by the , . , memory subsystem would exceed an appropriate maximum duty cycle for the particular output control device 15 being utilized by the system, in order to avoid the possibillty of induclng runaway free flow conditions. Such runaway conditlons may occur due to mechanical limitations, e.g., inertia, o~ the output control device 15, and consequent loss of control over fluid flow in the feeding tube may result. The duty cycle of the output control device 15 ls defined as the ratio of the time that the output control device is energlzed, to the total perlod o~ time between lnltiations o~ ~uccessive outputpulses over line 17 driving the output control devlce. `
The duty cycle limitation subsy~tem 23 receives lnput over line 24 ~rom the pul~e generation and rate ~ele~
tlon subsyatem 18 to enable the duty cy¢le subsystem to monl~or the commanded period between initiation of suc-oessive ele¢trical output pulses, as specified by the pulse generation and rate selectlon sub~ystem. At the desired duty cycle limitation point for the particular ele¢tro-20 mechanical output control devi¢e 15 being utilized, the -d~ty ¢y¢le subsystem 23 terminates the output pulse on llne 17 (if it has not otherwlse been termlnated by the memory sub~ystem 21), by directlng a termlnatlon lnput over line 25 to the output pulse control subsystem 16, thus providing an in~tantaneous limitation on the electrical output to the mechanlcal subsystem. Slmultaneously, the duty cy¢le limltation subsystem 23 æpeeds up the counting rate to the dLgital memory subsystem 21 so that the counting cycle is ~ompleted more rapidly. The latter feature is indicated 30 schematically by an input over line 26 to the memory sub-3ystem 21 ~rom the duty cycle subsystem 23, to alter the counting rate normally provided by a clocking ~ubsystem 27 ~ providlng an input over line 28 to the memory subsystem.

1068570 ~
The clocking subsystem 27 ls also illustrated as .
drlving the pulse generatlon and rate selection subsystem ~:
. .
18. In this regard, the clocking sub~ystem 27, while shown for purposes o~ simplicity as providlng inputs only to the pulse generation and rate selection subsystem 18 and digi-tal memory subsy~tem 21, actually provides clocking inputs :
to all of the subsystems to maintain synchronous operation wherever requlred. .
The manner in which the duty cycle llmitation sub~
10 sy~tem 23 increases the countlng rate to the digltal memory ~:
subsystem 21 is by swltching, at the duty cycle llmlta-., .
tion point, from a counting rate which is normally at one- .
tenth of the full clock rate, to counting at the full clock rate, whereby completlon o~ the countlng cycle ls : a¢celerated The latter ~eature also insures that the digltal memory subsystem 21 wlll always have ¢ompleted its last counting cycle prior to initiation of the next count-ing cycle by a pulse received over line 20 from the pulse generatlon and rate selection subsystem 18. In the event 20 a high pulse frequency ls commanded by the pulse generation and rate selection subsystem 18, the perlod between ini-tiatlon of pul~es over line 20 may be considerably shorter - than the perlod required for the counting cycle o~ the digltal memory subsystem 21 at the normal counting rate.
However, the accelerated countlng rate lntroduced by the duty cycle limltation ~ubsystem 23 in~ures completion of each counting cycle by the digital memory ~ubsystem 21 even at the highest selected output pulse rates which the over-all system is designed to produce.
It has been determined~ by experience, that the maximum duty cycle suitable for a typical I.V. controller using an electromagnetically reciprocated I.V. tube pincher, is considerably less than the maximum duty cycle .

1068570 `

permissible with a stepplng motor in~uslon pump. The reason for this ls that the mechanical inertia of the spring-biased I.V tube pincher is typlcally o~ suf~icient magnltude that, lf the duty cycle is made too large, the plncher cannot close off the ~eeding tube completely be-fore being required by the next output pulse on llne 17 to re-open the feedlng tube. This can result in a floatlng action which ~ails to completely pinch o~ the feeding tube and consequently may produce a ~ree flow state~ Once such contlnuous flow occurs, the fluid flow may no longer be divided into incremented drop flow. When no drops are dete¢ted by the system, the pulse width will normally be made even wider, making condltions still worse.
It hss been emplrlcally determined that, ~or I.V.
controller appllcations using an electromagnetically re¢ipro¢ated tube pincher, a duty cycle limltatlon o~ 40 percent is preferable, whereas a duty cycle limitatlon of 75 percent is typically suitable for a positive pressure infuslon pump using a d.c. stepping motor drive. Where other types o~ electromechanlcal output control devices 15 are utillzed, it will be appreciated, of course, that other duty cycle llmltatlons suitable to the partlcular control device selected, may be prescribed in accordance with the teachings of the present invention.
In the case of the I.V con~roller, whlch is de-pendent upon gravlty induced hydrostatlc pressure for in-ducing drop flow, it is deslrable to vlsually observe an lndlcation o~ the output pulse wldth to the control devlce 15 so that, ln the event pul~e width is not in the optlmum operatin~ range, sultable adjustments can be made ln the external I.V. adminlstratlon system, such as raislng or lowering the helght of the bottle, to establlsh proper hydrostatic pressure levels in the feedlng tube appropriate 1068570 : ~

to pulse width generation in the desired region of opera-tion. In thi~ connection~ a visual pulse width indication subsy~tem 29 receives information over llne 30 ~rom the pulse width register of the digital memory subsystem 21 -ana deoodes the pulse width into pulse width operation ~-ranges.
,, .
By means of a pair of lights, the pul~e width ~-indication subsystem 29 lndicates whether the electrical output pulses being generated by the overall system on lO line 17 to the output control device 15 fall within de-flned high low or optimum pulse width ranges. In a presently preferred embodlment of a visual pulse width lndl¢atlon subsystem suitable for use with an I.V. con-troller a green light indlcate~ the low pulse width range, ; a red light lndicates the hlgh pulse width range, while energizatlon of both a red and a green light indicates that operatlon le in an optlmum pulse width range.
An alarms subsystem 14 receives input~ from a tlmer 31~ and from portions o~ the pulse ~neration and rate selection subsystem 18, the digital mem"ry subsystem 215 the output pulse control subs~Jstem 16~ the memory con-trol subsystem 13 the start-up subsystem 12 and the pulse generator llb o~ the drop detectlon sub~ystem. These ln- -puts are used, in a manner to be speclflcally descrlbed hereina~ter~ to monitor system performance so that out-of-limit conditions calling for ~low rates in excess o~ sy~tem delivery capabillty~ or indicating a leakage flow rate which cannot be terminated by the output control device, trigger an alarm st ate which resets the entire system and 30 prevents further system operation until the alarm condi-tions have been corrected and another start-up phase has - been initlated.
The alarms subsystem 14 provides a hlgh level .

alarm responsive to a demand for an excessive output pulse width over line 17. The subsystem 14 also provides a pair of low level alarms, each one suitable to a different type of output control device 15, and each responsive to ; ~pecified non-tolerated sequences o~ pulse width. As will become apparent in connection with the descriptian of the preferred embodiment the stepplng motor in~usion pump may operate properly in the negative pulse width region of the pulse width register andg in this regard, the low level alarm provlded b~ the system o~ the present lnvention wlll only be responslve to a requlrement for excessive negatlve :
pulse wldth which indicates the possibllity of a runaway . ~ree flow conditlon wlth the pump. However, whlle the system may continue to operate electrically in the negative pulse region, ele¢tri¢al output to the output ¢ontrol devlce 15 i~ gated o~ during this perlod o~ operation and this ls indi¢ated schematically by an input over line 33 to the output pulse control subsystem 16 from the alarms ~ubsystem 14 In addition to the hlgh level and low level alarms the alarms ~ubsystem 14 ls responsive to a lack of dete¢tlon o~ any drop ~low within a predetermined period o~ tlme and as a functlon of various electrlcal events o¢currlng in ~he pulse generation and rate selection sub-~- system 18, the memory control subsystem 13 the start-up , . ~ .
~ubsystem 12 and the output pulse control subsystem 16.
In this connectionS the alarms subsystem 14 generates an alarm state lf no drops are detected after a prescrlbed number of pul~es has been generated by the pulse generation and rate selection subsystem~
In additiong the system will also alarm in a "no action" mode if~ ln any prescribed tlme perlod during normal operatlong there are no drops detected by the drop ':.

106~3S70 --sensor lla nor electrical output pulses occurring on line 17. The pre~cribed time period for the "no action" alarm, is typically approxlmately six minutes a time interval compatible with the lowest drop rate frequencies which the sy~tem might be utilized to generate in normal operation.
Referring now to FIG~XES 4a, 4b and 4c of the drawings each o~ these figures are combined block diagrams and electrical schematics of portions of a ~luid flow control sy8tem ln accordance with the present invention, and the figures are arranged with their respective input and output connections allgned so that the three flgures can be used as a single drawing for the entire fluid flow control system. In this regard, the various subsystem ; electrlcal connectlons overlap wlth each other to such a degree that the system is best described wlth regard to the ¢ombined figures, and the balance ofthe description will a¢aordingly be made with reference to suah a composlte drawlng.
; Prlor to a detailed descrlption of the operation of the overall ~ystem depicted ln FIGURES 4a, 4b and 4c, the main elements of each ma~or subsystem area, and their functlons, will ~lrst be summarized.
~ FIG~RE 4a primarily is dire¢ted to the lnput~ ~-timing and output sectlons of the overall ~ystem which would include, referring to FIGYRE 1 previously discussed, the pulse generation and rate selection subsystem 13, the duty cycle limitation subsystem 23, the clocklng subsystem 27, the output pul~e control subsystem 16 and the output control device 15.
; 30 FIGURE 4b relates prlmarily to the memory and control sections of the overall system and~ referring again to FIGURE 1, primarlly includes the digital memory subsystem 21, the drop detection subsystem 11, the memory :`

control subsystem 13 and the start-up subsystem 12.
FIG~RE 4c ls directed prlmarily to the details of the alarms subsystem 14J the visual pulse width indication subsystem 29 and the timer 31.
Referring now to FIGURES 4a, 4b and 4c as a composite system dlagram~ a conventlonal clock generator 40 dlrects pulses over line 41 to a conventlonal dlgital rate multlpller 42 which embodies a plurallty of digltal rate selector swltches 42a.
The rate mùltipller 42 multlplies the input fre-quency by a maximum factor of unlty. The output of the rate multlplier 42 over line 43 ls a pulse rate propor-tlonal to the setting of the rate selector switches 42a and, therefore; proportional to the desired drop flow rate to whlch the system is intended to stabillze. The output of rate multlpller 42 over line 43 is not a ¢ontlnuous pulse train, but rather an lrregular burst of pulsesJ due to the nature of the fractlonal multiplicatlon which can oc¢ur in the rate multiplier. The typically non-uniform pulse train on line 43 is directed to a conventional divider 44 whlch smooths out the ~itter ln the pulse traln.
The electrical output of the divlder 44 ls dlrec-ted to a decoder 45 which decodes out different states o~
the divider 44 for duty cycle llmitation purposes and to generate the reference pulse traln for the system which controls the initiation of each counting cycle and the inltiation of outputpulse~ from the overall sy~tem., The latter is the pulse generated each time the dlvider 44 is counted to its "zero" state (hereinafter referred to a~
the "DRZ" signal) and corresponds to the output of the pulse generation and rate selectlon subsystem 18 o~ FIG-URE 1.
The clock frequency generated by the clock 40 is i~68S70 in a preæently preferred embodiment of the invention, - selected to be 71.68 kilohertz. The rate multiplier 42 multiples the clock frequency by l/lOOth o~ the drop rate selected and dialed in on the rate selector switches 42a.
For example, assuming a selected drop rate o~ 30 drops per minute, the output frequency on line 43 would be:
lnput frequency to divlder 44 = 71- 6l80X 3 = 21.504 kilohertz The divider 44 is 3elected as a register havlng a count capacity of 212 or 4096. Therefore, the output frequency o~ the DRZ pulse traln is:
DRZ frequency = 21-4046x 103 = 5.25 hertz = 315 pulses ' .:.. .
It will be noted that the latter result is exactly lo-1/2 time~ the selected drop rate of 30 drops per minute.
Hence, the clock 40, rate multiplier 42 and divider 44 are seleated to provide the de~ired frequency ratio relation-ship between the output pulse train and the drop flow rate deslred The DRZ signal output from the decoder 45 i~ an open loop command slgnal directed over line ~6 to other portions of the s~tem.
Two other output lines 47, 48 from the decoder - 45 decode out those states which represent certaln count-ing ranges of the divider 44. The output llne 47 ~rom the decoder 45 represent~ a count of 3072-4095 of the divider 44 whlch is the last 25 percent of the count capacity of the divider The llne 48 represent~ a count range o~ 1664-4095 and represent~ the last 60 percent of the count capacity of the divider 44 Therefore, for the time period between successive DRZ pulses generated by the decoder 45 over line 46, the decoder output line 48 will be "false" for the first 40 percent of the perlod and will be "ture" for the la~t 60 .: , . . ~

percent of the per~od up to the next DRZ pulse. The other output line 47 from the decoder will be "false" for the ~lrst 75 percent of the perlod between DRZ pulses and "true" for the last 25 percent. These signals on output lines 47, 48 from the decoder 45 control the duty cycle limltation subsystem The signal9 on lines 47 and 48 are fed to a pair of AND gates 49, 50, respectively, which, in turn; direct their outputs to an OR gate 51. The output from gate 51 over line 52 ls the duty cycle limitation lO control Signal Since the overall system of FIGURES 4a, 4b and 4c~ i8 lntended for use with elther a pump or a controller, the gates 49 and 50 are used to select the particular duty cycle limltation desired, either a 40 percent or a 75 percent output llmitation depending upon the particular output control device intended to be utilized wlth the ~ystem. Thls ls a¢¢omplished by a ~umper connection 53 whi¢h ls sele¢tively in~talled either in the "controller"
positlon or the "pump" position.
Depending upon whlch operatlonal m(,de ls selec-ted, elther an electrlcal "zero" or an electrical "l"
slgnal ls ~ed over line 54 as input to the duty cycle sub-system. When the "controller' mode of operation is selec-, . .
ted~ the "zero" input passes over line 55 as a false"
input to the AND gate 49, thus disablin~ the gate 49. In contrast, the "zero" input is lnverted, by an inverter 56; to provide a "true" input over llne 57 to the AND
gate 50 whlch will thereby have an output dependent upon the status of line 48 from the decoder 45. Thus, the 30 output of the gate 50, which also passes through the OR
gate 51, will be "true" durlng the last 60 percent of the period between each pair of DRZ pulses.
SimilarlyJ if the "pump" mode is selected, a ... .

1()68570 "1" slgnal input will be directed over line 54 to the duty cycle limltation subsystem and, hence J gate 49 will be enabled and gate 50 will be disabled 7 whereby the status ::
of the output line 47 from the decoder 45 will be passed as "true" input to the OR gate 51 whose output over line 52 will be "true" only during the la~t 25 percent of the period between each pair of DRZ pulses.
Hence, it wil]. be apparent that, depending upon -~ :
which mode of operation i8 selected, "controller" or lO "pump", a duty cycle limitation of either 40 percent or ~:
75 percent, respectlvelyJ will be imposed on the system as repre~ented by the ~lgnal on line 52.
~ he output of the clock generator 40 is also dlrected over line 58 to a divlde by ten counter 59 which divides the clock frequancy by a factor of 10 and feeds the reduaed clo¢k frequency over line 60 to an 0~ gate 61. The OR gate 61 also recelves an lnput over line 62 from an AND gate 63 whlch ha3 as lts lnputs the duty cycle control signal on line 64 and the full rate clock slgnal on llne 65. Hence, the output of th~ OR gate 61 .
over llne 75 is the clocking ~ignal (hereinafter referred to as the "CLK" signal) for the entire ~ystem.
The CLK signal will, however, change its fre-;quency from the full clock rate produced by the clock generator 40 to l/lOth of the maximum clock rate depending upon whether or not the duty cycle llmitation ~ignal is "true". merefore, depending upon whether the "controller"
or "pump" mode has been selected, the CLK signal will ~tart out~ after a DRZ pulse, at l/lOth of the maximum clock rate and, when the duty cycle control ~i~nal on llne 52 is "true", the CLK signal will increase its fre-quency to the full clock rate for either the last 60 percent (controller mode) or the la~t 25 percent (pump .~ _3o_ ' mode) of the perlod prior to the next DRZ pulse. As wlll aubsequently be apparent, ~ince the CLK slgnal counts up the memory ~ub3ystem, the portion o~ a count~ng cycle whlch ~ollowa after a "true" duty cycle llmltatlon slgnal ; on llne 52 is counted up at an accelerated rate.
The output of the dlvlder 59 i~ also ~ed over llne 66 to another dlvlder 67 whlch dlvldes the pul~e ~re-quency by two to provlde an output frequency over llne 68 whlch 18 the pulse drive source used to run the stepplng 10 motor o~ a pump. In thls regard, the pulse traln over l~ne 68 18 passed through an AND gate 69 over llne 70 to the ~tepplng motor drlver 71 only when an enabllng lnput over llne 72 from the output pulse control ~ubsystem 18 also dlrected to the gate 69. The partlcular dlvlders 59 and 67 conveniently provlde a drlver pulse sour¢e for the stepplng motor drlver 71 at a aelected stepplng ~requenay o~ 360 hertz, Thi5 steppln~ motor ~requency 18 ¢omputed by dlvldlng the ¢lock ~requency o~ 71.68 kllohertz by 10 and then by 20 to obtaln a pulse ~requency o~ approxlmate-20 ly 360 hertz. Thls arrangement avolde the necesslty Orprovidlng a separate drlver pulse source for the ~tepplng motor drlver.
The output control pulae provlded on llne 72 as lnput to the gate 69 is al~o directed over line 73 to a pincher driver 74 when the system i8 belng uaed in the "controller" mode of operatlon. In the case o~ the con-troller, the output control pulse 18 actually the ener-gizlng pulse ltself for the output ¢ontrol devlae, whereas ln the case of a atepping motor pump, the output pulse 30 simply controla the duratlon or gatlng of a bur~t of pulses ~rom the stepping motor driver pulse source.
Rsferr~ng now mors partlcularly to F~mE 4b, the digltal memory subsystem includea a palr o~ countera, the `:

.
.

scannlng control reglster 83 and the pulse wldth reglster 85. A decoder 84 is associated with the scanning control regl~ter 83, while a decoder 86 ls associated w~th the pulse width reglster 85. The scannlng control register 83 i~ ¢ontrolled by an input AND gate 87 and the pul~e width reglster 85 i3 controlled by an lnput AND gate 88. The gates 87, 88 gate the counting signal CLK into thelr re-~pectlve reglsters at the approprlate tlmes. As wlll be recalled from the previous des¢rlptlon o~ the duty cycle sub~ystem, the ChK slgnal may be elther the ~ull rate alock slgnal o~ 71.68 kllohertz or lt can be only l/lOth o~ that frequency, l.e., 7.168 kilohertz. The higher rate clock -~lgnal 18 ln effect whenever the duty cycle llmitation 19 ~mposed .
Each of the reglsters 83 and 85 has a count aapac- -lty o~ 21 ar 1024. Ea~l¢ally, what occurs in the digital memory and ¢ontrol ~ubsystems 18 that the scanning control register 83 and the pulse width register 85 undergo a counting cycle whlch 18 lnltlated each tlme a DRZ pul~e 19 --generated at the output of the decoder 45 on llne 46, and each counting cycle must be completed before the next DRZ
- pulse 19 produced.
The control reglster 83 determlnes the duration o~ each counting cycle ~or it~elf and the pulse width reglster 85, by inltlatlng the countlng cycle ~rom it~
; "zero" atate upon recelpt of a DRZ pulse, and termlnatlng the counting cycle when it counts to 1024 (the return to -~ its "zero" state). The control register 83 then remains in its "zero" state untll the next DRZ pul3e is produced at the output of the decoder 45.
Normally, the pulse width reglster 85 19 caused to lag the control register 83 by two counts during each counting cycle, thereby increaslng the pulse wldth of the ':

output pulses controlled by the register 85, as measured by the difference between the count in the register 85 and lt~ "1024" t"zero") overflow ~tate.
Each time a drop 1~ detected, the pul~e wldth reelster 85 is incremented by 21 counts relative to the control regi~ter 83 to narrow the e~fective output pulse width as measured by the count ln the register 85. This establi~hes the deslred _~ or lO-l/2 ratlo deslred ~or the output pulse ~requency to the drop ~low rate frequency. In e8sence, the pulse width 18 servoed ln a closed digltal loop to preserve the desired lO-l/2 ratlo which is ~orced on the sy~tem by the DRZ pulse rate produced by the pulse gsneratlon and rate selection subsystem.
The decrementing of the regi~ter 85 relatlve to the ¢ontrol regl8ter 83 18 accompll~hed ln each countlng ¢ycle by holding of~ CLK pulses ~rom the reglster 85 ~or the ~lrst 2 counts recelved by the control register 83 during each countlng cycle. The incrementlng of the pulse wldth reglster 85 relatlve to the control register 83, eaah 20 time a drop 1~ detected, 18 accompl~shed by holdlng o~
CLE pulsee from the control register 83 when the pulse width regi~ter 85 reaches it~ "zero" ~tate after drop detectlon, and resuming countlng of the control register 83 only after the pulse wldth regi3ter has reached a count of "21". Hence, pulse wldth is e~ectively increased and decreased by alterlng the relatlve countlng states or phase exi~ting between the ~canning control reglster 83 and the pulse w~dth reg~ter 85 in the digltal memory subsystem.
; As prevlously lndi¢ated, during the start-up pha~e o~ operation, defined a~ the time to recelve the first two drop~ a~ter initially turnlng on the sy~tem or comlng out o~ an alarm state, the control relatlonship between the control reglster 83 and the pulse wldth register 85 .; -33-':

106~570 ' `
ls altered so that pulse width is increased by 9 counts during each counting cycle, rather than by only two counts, to more rapidly bring the system up to lts normal pul~e width operatlng region. -The size~ i.e., count capaclty, of the reglsters 83 and 85, and the number of counts by which pulse wldth is lncrea~ed and decreased, i9 determined ln accordance with ; -the deslred resolution oP the overall system and the loop galn desired. It has been determlned empirically, for the type of output control devices utilized and the degree of stabllity deslred that, for a system capable of generating (ln the "ump" mode) a drop rate of 99 drops per mlnute, a full range count capaclty of 50 drops for the registers, with a loop gain of approximately 2 percent 18 desirable.
For a full range Or 50 drops, at an lncrement of 21 counts for ea¢h drop detected, a register count capaclty Of 1024 appear~ to be optlmum. This is also desirable aince the maximum increment of 21 counts per drop detected is approxlmately 2 percent of the count capacity, which 20 satis~ies the loop galn requirements. Too high a loop gain~ l.e.~ the percent of change generated ln the ~ystem for each drop detected, would cause the system to react ; too rapidly with possible overshoot and osclllation. A
lower loop gain approaches proportlonal servo control m~re ¢lo~ely and i~ much more reliable than the large on-of~
type ~wings in the system which tend to occur w~th ex-cessively high loop gain.
The count capaclty of 1024 for the registers 83 -~
and 85 is al~o compatible with th~ maximum pulse width 30 re~uirement~ for the system. In thls regard, the output control mechanism utilized may require a maximum pulse - width of approximately 140 mllllseconds and, therefore, the reglsters 83 and 85 must be capable of a complete count~ng cycle ~rom "zero" to "1024" o~ at lea~t 140 mllllseconds at the countlng rate o~ the CLK slgnal. In th ~ regard, using the normal (no duty cycle llmltatlon lmpo~ed) CLK
~requenay of 7.168 kilohertz, the maxlmum pulse width PM
¢apable o~ generation wlth the count capaclty of 1024 ls:

- M 7 168 x 103 - 0.1428 ~econds = 142.8 mllllseconds 5uch a maximum pulse wldth 19 normally required only at very low drop flow rates.
In addltlon, lt wlll be noted that, at the high-e~t sele¢table drop rate oP 99 drops per mlnute typlcally intended ~or the system of the present lnventlon, th~ tlme between DRZ pulses 19 considerably shorter than the maxlmum ¢ounting ¢y¢le period of 143 mlllise¢onds. In thls ¢onne¢-tion, at a selected drop rate of 99 drops per mlnute, the perlod Pp between DRZ pulses ls:

p = 60 seconds 99 drops/min. x 10.5 = .058 se¢onds - 58 milllse¢onds How~ver, lt ¢an be shown that, at such hlgh drop rates, the duty cycle llmltation subsystem will tat 40 percent oP the - period between DRZ pulses ~or the controller mode and at 75 percent of the period between DRZ pul3es ~or the pump - mode~ swltah the CLK signal ~rom 7.168 kllohertz to the maximum clock rate o~ 71.68 kllohertz. Thls enable~ the eountlng ¢ycle to be completed at a very ~a~t rate, termin-atlng the output pulse prematurely and thereby limitlng lt to the designated duty ¢y¢le. Inevltably, thls also shor-tens the counting cycle su~flclently to assure completlon 3~ o~ the countlng cycle prlor to appearance o~ the next DRZ
pulse.
The aforementionèd operation o~ the digital memory 9ubsy~tem and the duty ¢y¢le limltatlon subsystem 18 1(~6~570 lllustrated in FIG~RES 5a through 5h of the drawings.
FIGyRE 5a represents the regular occurrence o~ DRZ pulses which initiate each counting cycle o~ the memory subsystem.
FIGUmE 5b represents the variation of CLK frequency durlng the perlod between successive DRZ pulses and shows the change in frequency from 7.168 kilohertz to a full clock rate ten times greater, or 71.68 kilohertz, after the duty cycle perlod of 40 percent has been reached.
FIGURES 5c, 5d and 5e lllustrate the states of 10 the control reglster 83 and pulse width reglster 85 and the nature of the output pulse cn llne 72, where normal opera-tlon 1~ ~uch that the duty cycle has no effect upon the output pulse width as where narrow output pul~es are called ; ~or. In contrast, FIGURES 5~, 5g and 5h illustrate the various ~tates o~ the control reglster 83 and pul~e wldth reglster 85 and the nature of the output pulses on line 72 where the duty cycle does impose a limltatlon upon output - pulse width.
Referring to FIGURES 5c and 5d, the control regls-ter 83 starts the counting cycle ~rom lts "zer" ~tate, with the pulse wldth register 85 at an lnltial starting state o~
"924" which i8 a relatlvely narrow pulse wldth. The pulse width reglster 85 counts up to lts "zero" state prlor to the duty cycle limitatlon being lmpo~ed and then contlnues to be counted up until it reaches lts ~inal ~tate o~ "922"
(2 counts less than lts orlginal starting state) whlch occurs at the same polnt that the control register 83 passes through lts "zero"state. It wlll also be noted that the memory csuntlng cycles are completed considerably more rapldly due to the higher frequency of the CLK ~ignal a~ter impositlon of the duty cycle limitation than would have been required i~ the duty cycle limltation had not been impo~ed$ as indicated by the fictltlous counting . -~ -36-states denoted in parentheses ln FIGURES 5c and 5d.
The output pulse width on line 72, as illustrated ln FIGURE 5e, is determlned by the pulse wldth register 85 in counting from the "924" state to the "zero" state, and de~ines a relatlvely narrow pulse wldth well within the duty cycle limitation.
Re~erring now to FIG~RES 5~, 5g and 5h, the con-trol register 83 starts out again in its "zero" ~tate, the second "zero" position representing the speeded up com-pletlon o~ the counting cycle, with the thlrd "zero"positlon indicatlng the ~tarting point for the next count-lng ¢ycle as trlggered by the next DRZ pulse. The "zero"
posltion ~hown in parentheses corresponds tothe ~ame posl-tion in FIGURE 5c which indicates how long it would have taken to complete the countlng c~cle if there had been no swltching to a higher CLK ~requency because of ~e duty cycle llmitation FIGYRE 5g shows the pul~e wldth reglster 85 start-lng out with a relatively low count of 124 which would norm-20 ally produce, in the absence o~ the duty cycle llmitatlon,a very wide output pulse on line 72. The flrst "122"
- state shown for the pulse regl~ter 85 represent~ lts state at the end o~ the countlng cycle completed on an acceler-ated basls. The pulse regi~ter 85 remains in the "122"
state untll the next DRZ pulse. The states lndlcated ln parentheses indicate whe~e the pulse register would have been had there been ~u~lcient time for the reglster to count up without a duty cycle llmltation. In thls regard, the figures shown ln parentheses on FIGYRES 5c, 5d, 5f and 5g are sltuations whlch assume that the DRZ pulse ~requency was surPiciently low, substantially lower than that illus-trated in FIG~RE 5a, that the counting cycle could be com-pleted prior to any duty cycle llmltatlon being lmposed, - `- 1068570 l.e , there wa~ adequate tim~ le~t for the counting cycle -to be completed at the normal CLK frequency o~ l/lOth o~
the maximum clock rate.
FIGURE 5h illustrates that the output pulse on l~ne 72 is terminated by imposing the duty cycle limita-tion, even though the electronlcs of the memory subs~tem continue to count up both the control reglster 83 and the pulse width register 8~. In this regard, note that the output pul~e i~ termlnated by the duty cycle limitation rather than the "zero" state of the pulse width register 85. The dotted curve ln FIG~RE 5h illustrates what the pulse width of the outputpulse on line 72 would have been lf no duty ¢ycle limltatlon had been lmposed.
Wlth the aforedescrlbed background in mlnd, the followlng more detalled descrlption of the digital loglc employed ln the overall system will be more readily under-stood.
When the scannlng control register 83 reaches a count of "1024" durlng a countlng cycle~ l.e., lts "zero"
state5 the zero output line from the decoder 84 provldes a "true" output on llne 90 which i8 lnverted by an inverter 91 to disable an AND gate 92. Henc~, the output of the AND gate 92 on llne 93 i~ "false" which produces a "false"
output from the OR gate 94 over line 95 to dlsable the input AND gate 87 to the control register 83. This pre--vent~ the CLK signal from counting up the control reglster 83 any ~urther and effectlvely termlnates the counting cycle at the "zero" state of the control register.
The other lnp~t to the OR gate 94, over line 96, is the DRZ signal which passes through the gate 94 and enables AND gate 87 to again pass the CLK signals to the control register 83J thereby inltlatlng a new countlng cycle. Hence~ the DRZ signal override~ the lnhiblting 10~;8S70 effect o~ the "zero" state of the control register 83 at the beglnning of each new countlng cycle.
After the first counting pulse (DRZ and CLK) is received by the control regi~ter 83~ the "zero" output llne 90 from the decoder 84 goes "~alse" whlch, in turn, makes the output of the inverter 91 go "true" and thereby enables gate 92. The other lnput to the AND gate 92, over llne 97, ls also normally "true", ~o that the output line of gate 92, over line 93, pas~e~ through OR gate 94 to maintaln the 10 AND gate 87 enabled ~or further passage of the C~K pulses to the control register 83 even though the DRZ pulse ls no longer available. Hence, the DRZ pul~e merely inltiates the ¢ountlng cycle whlch then continues until completion.
The input AND gate 88 to the pul~e width regi~ter 85 ls likewlse disabled by the "zero" state o~ the control reglster 83 ~lnce it receives the ~ame lnverted output a~
the gate 92. Thus, the pulse width regl3ter 85 doe3 not yet begin to ¢ount when the DRZ pul~e causes the control i reglster 83 to count ~rom the "zero" state to the "1"
~tate.
Another input to the AND gate 88 of the pulse width register, over line 99, ls the ~ output of a flip- ~;
flop 98. Hence, the flip-flop 98 must be "false" (~ would then be "true") ~or the AND gate 88 to be enabled after the ¢ounting cycle has been lnltiated. In this regard, the J
input o~ the flip-flop 98 is ~et by the same DRZ pulse that enables the control register 83 to be counted from zero to "1". Therefore, on the very next CLK pul~e, whlch count~ the control register 83 from "zero" to "1", the 30 flip-~lop 98 is set "true" which, of cour~e, make~ the ~
output over line 99 to gate 88 "~alse". However, the lnput gate 88 to the pulse wldth regl~ter 85 remaln~ di~abled~
even though the input to the gate 88 over llne 100 from ~ 068570 the lnverter 91 ls now true". Hence, the control reg~-ter 83 has been counted to its "2" state, with no counts havlng yet been passed to the pulse width register 85 ~uring the countlng cycle.
From the foregoing analysis, it will be apparent ; that the pul~e width reglster 85 wlll not count untll the ~lip-flop 98 is reset so that lts ~ output is "true".
- This requlres that the K lnput of the flip-flop 98 be set.
The K input o~ flip-rlop 98 i9 under the control of three 10 gates~ an OR gate 102 and a pair of AND gates 105, 106 whose outputs are directed over lines 107, 108, respec-tively~ as inputs to the OR gate 102.
The AND gate 106 receives as lnput, over line 109, the "1" state o~ the control register 83 decoded out by the decoder 84~ and receives a~ a second lnput, over llne 11OJ the ~ output of a flip-flop 114 which is the start-up control fllp-~lop indlcatlng whether or not the 3ystem is in the start-up phase of operation. The other AND gate 105 recelves a~ one input5 over the line 111, 20 the "8" state of the control register 83 from the decoder 84, and receives as a second input, over line 112, the Q
output from the start-up ~lip-flop 114.
When the system is in the start-up phase of oper-ation, the ~lip-flop 114 will be "true" (it~ Q output wlll be i'true") whereas, when the ~ystem is out of the start-up phase, as will typically be the case for the bulk Or normal operation, the flip-flop 114 will-be fa~se (its output will be true").
Assuming for purposes o~ the present analy~is that the system is out of the start-up phase, then the Q
output of the start-up flip-flop 114 wlll be "true".
Therefore, when the control register 83 has been counted to its "1" state, the AND gate 106 will be enabled, and - ~068S70 lts "true" output will be passed by the OR gate 102 to set the K input of the flip-flop 98. On the very next CLK
pulse, the control register 83 wlll be counted from lts "1"
~tate to its "2" state, t~e pulse width register 85 will remain unchanged, and the flip-flop 98 wlll be reset 80 that lts ~ output will be '!true" prior to receipt of the next CLK pulse.
At thi~ point, both of the inputs over lines 99 and 100 to the pulse width reglster lnput gate 88 are "true", so that the very next CLK pulse ls passed both to the control register 83 and the pul~e width regi~ter 85.
Hence, the pulse width reglster 85 recelves lts first count as the control reglster 83 ls counted to lts "3"
state, thereby resulting in the pulse width register having been deoremented by a ¢ount o~ two relative to the count ln the control register. The gates 87 and 88 continue to be enabled f'or the pas~age of additional CLK countlng pulses ~or the balance o~ the countlng cycle, ln the absence of drop detectlon, until the control reglster 83 agaln counts to its "zero" state, at which tlme both of the gates 87 and 88 are di~abled by the "zero" state output ~rom the decoder 84 which ls lnverted by the inverter 91 in the manner prevlously described. Hence, during each countlng cycle, the pulse width register is decremented by two count~ to produce an lncrea~e in pulse width ~or the output pul3es generated by the system.
As previously lndlcated, when a drop occurs, it is deslred to lncrement the pulse width reglster by 21 counts relative tothe control reglster 83 ln order to narrow the output pulse width ~rom the sy~tem. The pulse width then lncreases ln steps o~ two counts each, as prevlously described in connectlon with FIG~RE 3 of the dra~ing~.
The addltlon of 21 pulse~ to the pulse width '' register 85 during a counting cycle will, o~ course, also include a decrement o~ two pulses during that same counting cycle, in the manner previously set forth, thus resulting in a net lncrease during the counting cycle followlng drop detection o~ 19 pulses incremented lnto the pulse width register 85 relative to the control register 83.
When a drop occur~, it ls detected by a drop detector 115 of the drop detection subsystem, to produce a pulse over line 122 to the "S" or "set" input o~ a drop 10 detection ~lip-flop 118. The drop detection pulse lmmedl-ately sets the fllp-flop 118 non-synchronously (lndepen-dent of the recelpt of a CLE pul~e) in conventlonal set-reset flip-flop manner. Hence, upon drop detection, the ~llp-flop 118 is immedlately forced lnto its "true" ~tate which makes its Q output on llne 1~3 go "true" a~ one input to an AND gate 120. The other lnput to the AND gate 120, over llne 124, is the hlgh order flip-flop of the pulæ
wldth register 8~ indicated as the 512-1023 output line ~; from the decoder 86 of the pulse width register.
Assumlng for the moment that the pulse width register 85 is in its hlgh count state, which provides a "true" output over llne 124, the output o~ the AND gate 120 - will be "true" and will set the J input of a fllp-flop . On the very next CLK pulse, the flip-flop 119 will be "set" so that it~ Q output will go "true". The "true"
state o~ the flip-~lop 119 ls ~ed over llne 125 to the K
input of the drop detection flip-flop 118 so that, on the next CLK pulse, the drop detectlon flip-flop is "reset"
and the gate 120 is thu~ disabled.
3 Hence, the flip-flop 119 is always set "true"
a~ter the flip-~lop 118 has been set "true" and the pul~e width register 85 has count~d up to the state where its hlgh order flip-flop is "true". When the Q output of the flip-flop 119 is i`true", its ~ output over line 127 is ~alse which disables one of the input~ to an OR gate - 121. The other input to the OR gate 121 is the high order ~tate of the pulse width register 85g over line 125, from the decoder 86. When the latter line is "true IIJ the output o~ the OR gate 121 ls "true" and its input over line 97 to the AMD gate 92, previously discussed, contin- ~
ues to enable gate 92 and permit the control register 83 ~-to be counted at times other than when the control regis-ter is in its "zero" state.
On the other hand, when the flip-flop 119 is "true" and the pulse width reglster 83 ls not in its high order counting state, e.g., when the pulse width register has ~ust gone from lts '11023" state to its "zero" state~
the output on llne 124 wlll be "fal~e and the ~ output on line 127 will also be "~alse", resultlng in the gate 92 being di~abled so that ~urther counting of the control regi~ter 83 is arrestçd. Henc, a~ter a drop has been detected, the control register 83 is gated off when the pulse wldth re~lster 85 counts to "zero".
Once the control register 83 i3 thus gated off, further countlng o~ the control reglster will not re~ume again until elther the pulse wldth register 85 counts to ts high order range 512-1023 or the flip-flop 119 is set "false" so that its ~ output over line 127 is "true".
It wlll be observed that the K input of the flip-flop 119 ls set by the "20" output ~rom the pulse width register decoder 86 over line 129. Hence, when the pulse width register 85 has counted to "20"g the K lnput of the fllp-flop 119 is i'setil and, on the next CLK pulse, the pulsewidth register counts to lts "21; state whlle the flip~
flop 119 ls reset" to make its ~ output "true" over line 127. Therefore, on the next CLK pulse which counts the , .

pulse wldth register 85 to its "22" state, the control register 83, again enabled by a "true" output from the OR
gate 121, also receives the CLK pulse and is counted.
Ihi~ results in a suppresslon of 21 counts in the control register 83 relative to the pulse width reglster 85, whlch is equivalent to lncrementing the pulse width register relatlve to the control regi~ter by 21 counts.
At thi~ point, both registers 83 and 85 contlnue to run until the control reglster 83 agaln goes to "zero", at which tlme both reglsters stop. Upon recelpt of the next DRZ pulse, the control register 83 will again ~tart count-ing, followed by the pulse width reglster 85 two count~
later in the manner prevlously described.
Having thus described the manner in which the scannl~g aon~rol register 83 and the pulse width regis-ter 85 are incremented and dearemented relative to eaah other, and the ef~ects o~ counting cycle lnitlation by the DRZ pulse and o~ drop detectlon, several typlcal ~itua-tlons will next be lllustrated. In thls regard~ illus-trative cases will be considered where a drop has beendetected between counting cycles, i.e., a~ter both regls-ters 83 and 85 have come to rest and are awalting a DRZ
pulse to inltiate the next counting cycle. Thls category o~ investigation will be extended to those situation~
lnvolvlng a variety of different starting states ~or the pulse width register 85. In addltion, cases will be consldered for various relatlvP states o~ the control register 83 and pulse width register 85, where a drop is detected whlle a counting cycle is actually in process.
FIG~RES ~a-6c cover those sltuations where a drop is detected between countlng cycle~, whereas FIGURES 6d-6g cover those situatlons where a drop is detected durlng a counting cycle.
' `' ~06~570 FIG~RE 6a is a table of the relative states of the control register 83 and the pulse register 85J and also ~ -~hows the ~tate~ of the flip-flop~ 118 and 119, where the re~isters came to re~t at "zero" in the control reglster and a count of "18" ln the pulse width regi~ter 85 ln the precedlng cycle. A drop was then detected which set the ~;
flip-flop 118 "true" immedlately. Ultimately, a DRZ pulse occurred whlch inltiated the counting cycle. The states shown in the ~irst line of the table are, therefore, the starting states at the beginning of the next countlng cycle after the drop occurred.
The pulse wldth register 85 is lnhibited by two ~-pul~es as the control reglster 83 ls counted, 50 that the reglster 85 i~ counted from "18" to "19" only a~ the con-trol regi~ter ls counted from "2" to "3 . The flip-flop 119 which i~ normally "false" remalns "fal~e", because of the "fal~e" output on line 124 ~rom the high order 512-1023 output of the pulse width regi~ter decoder 86 which disable~ the gate 120 input to the ~lip-flop 119.
Both ~lip-flops 118 and 119 remain unchanged as the register~ 83 and 85 are counted up, until the pulse width register 83 1~ counted to "512". At the latter count of the pulse ~idth regl~ter 85, llne 124 goes "true", enabllng the gate 120 and setting the J input of the fllp-flop 119, 50 that on the very next CLK pul~e, which counts the pulse width register 85 to "513", the flip-flop 119 1~ ~et "true" Thl~ dl~ables the Q output of the flip-flop 119 over line 127, which is replaced by the "true' output on line 124 from the decoder 86, ~o that the control register 83 can continue countlng On the next CLK pul~e, wh~ch counts the pul~e width register 85 to lt~ "514" ~tate, the drop detectlon flip-flop 118 18 "re~et", it~ K lnput having been prevlou~ly "~et" by the Q output on llne 125 from the ~lip-~lop 119. :
Both registers 83 and 85 are then counted con- .
tinuously untll the pulse wldth register is lnlts "zero"
state, at which time the 512-1023 output line 124 from the -~
decoder 86 goe~ "~alse". Slnce the Q output from the flip-flop 119 over line 127 is also "~alse" (the flip-flop 119 having previously been set "true"), both inputs to the OR ~.
gate 121 are "~alse" and the control reglster 83 is thus gated o~f at its count of "1008".
When the pulse width reglster 85 ls counted to lts "20" state, the K input of the ~lip-~lop 119 ls "set" and, when the register 85 i~ counted to "21", the CLK pulse also -. resets the ~llp-~lop 119 so that the ~ output on line 127 is "true", This again enables the control register 83, so that the CLK pulse whlch lncrements the pulse wldth regl~ter 85 to its "22" state ls al~o passed to the ¢ontrol register 83 to count the latter register to "1009".
~oth register~ contlnue to count, with both flip-~lops 118 and 119 "false", untll the control register 83 counts to "zero"~ at which tlme the counting cycle termlnates wlth a count o~ "37" in the pulse width register 85. Since the pulse width register 85 ~tarted out with a count of "18"~
- thls represents a relative increment of 19 counts, which includes both the 21 count increment due to drop detectlon and the normal two count decrement experienced during each . counting cycle.
FIGYRE 6b illustrates the situat~on where the state of the pulse width regi3ter 85 was "512" upon com-pletlon of the previous counting cycle and at the beglnning o~ the counting cycle lllustrated. Ynder those circum-stances, since the fllp-~lop 118 was set "true" immedl-ately upon detectlon of the drop, and the 512-1023 output line from the decoder 86 provicles a "true" output over .

1~68S70 line 124 to the AND gate 120, the very next CLK pulse sets the flip-flop 119 "true" and the next CLX pulse after that resets the flip-flop 118, all prior to the DRZ pulse which lnitiates the next counting cycle. Hence, the counting ;~
cycle starts out with the control register 83 in the "zero"
~tate, the pulse width register 85 in the "512" state, the flip-flop 119 "true" and the flip-flop 118 "~alse".
When the pulse width register 85 is ultimately counted to "zero", the output of the OR gate 121 again goe~ "fal~e" to gate off the control register 83 (as in the ca~e illustrated in FIG~RE 6a) until the pulse width regi~ter counts to "20". In going from count "20" to count "21" ln the pul~e width register 85, the flip-~lop 119 ls "reset", making its ~ output go "true" on line 127, thus enabling the control register 83. Both counters are con-tinuously counted for the remalnder o~ the ¢ountlng cycle as pulse width register 85 is counted by the next CLK pulse to lts "22'l state and the control register 1~ counted to ~tate "515". Counting of both registers proceeds untll the control register 83 ls counted to "zero", at whlch time the count in the pulse width register 85 is "531", again 19 counts more than the starting count o~ 512.
FIG~RE 6c illustrate3 the case where the state o~
the pulse width register at the termlnation o~ the last i counting cycle and at the beginning of the present count-ing cycle ls "1023". For the ~ame reason~ a~ in the case illustrated in FI~RE 6b, flip-~lop 119 has been set "true"
and flip-~lop 118 has been reset to its "false" state. The pul~e wldth register 85 is agaln inhiblted for two counts 30 and then~ as the control register 83 counts to lts "3"
state, the pulse width reglster overflows to "zero" which gakes o~ the control register ~or 21 counts.
As the pulse width register 85 is counted to "22", .

.
the control register 83, having been again enabled ln the manner previously descrlbed for these condltions, is counted to its "4" state. Counting again contlnues until the con-trol register 83 ls counted to "zero 11~ thus terminating the counting cycle.
It will be noted in ~IGYRE 6c that the pul~e width register 85 passes through its "zero" state a second time dùring the countlng cycle, but wlthout gating off the con-trol register 83, since the flip-flop 119 is "~alse" during thls second overflow of the pulse width regi3ter and, therefore, a Q "true" output over llne 127 to the OR gate 121 continue~ to enable the control register 83. At the conclusion of the counting cycle, the count in the pulse width register 85 is "18" which, again, is 19 counts more than its starting state o~ "1023".
FIGYRE 6d illustrates the situation where a drop occur~ during a counting cycle when the control register 83 is in it~ "1" state and the pulse width regi~ter 85 i8 at count "18" The flip-flop 118 ls set to its "true" state immediately upon drop detection, but since the 512-1023 output line from the decoder 86 o~ the pulse width reglster ls "~alse", the flip-flop 119 mu~t remaln "false" until the pulse wldth regi~ter is counted up to 512. It will ~e apparent, upon comparison, that the ~ituation of FIGYRE 6d es~entially duplicates that previously described in connec-tion with FIGYRE 6a.
FIGURE 6e illustrates the case where a drop is detected when the control register is in the "1" state and the pulse width register 85 1~ already in its high order decade of operation at a count of "512". Ynder these circumstances, flip-flop 118 is set "true" immediately on detection of the drop and the latter state over line 123 is immediately passed by the A~ gate 120 to ~et the J

1~68S70 . .

input o~ the flip-~lop ll9. On the next C~K pulse which counts the control register 83 from "l" to "2", the flip-~lop 119 ls set "true". On the next CLK pulse after that, the drop detection flip-flop 118 is re~et. Again, the control register 83 has been counted up while the pulse width register 85 has been inhlbited for two counts. At this polnt, the counting cycle proceeds exactly as for the case lllustrated and described in connection with FIGURE 6b.
FIG~RE 6f illustrates the case where a drop is- `
detected at that point ln the counting cycle when the con-trol register 83 is at a much hlgher count of "500" and the pul3e width reg~ ter i9 at a count of "15". Again, the ~llp-~lop 38 19 immediately set "true" while the ~lip-flop 119 remains "false' until the pulse wldth register counts up to 512, at which time the flip-flop 39 i8 set "true"
a~ the pulse width regi~ter i~ counted to "513" On the very next CLK pulse, the "true output of the ~lip-flop 39 resets the flip-~lop 118 to its "~alse" state.
At this polnt, both reglsters are counted up untll 20 the control register reaches "zero", at which time both -; regi~ters stop and must wait until the next DRZ pulse to ~tart another counting cycle. It will be apparent, ~rom `~ the counting states deplcted in FIG~RE 6~, that, for the condition~ stated, the lncrementing of the pulse wldth reglster in response to drop detection is not accompllshed ln the ~ame counting cycle ln which the drop is actually detected, but ls delayed untll the next countlng cycle.
In this regard, the next DRZ pulse lnltlates the next count-lng cycle, which then inhiblt~ the pulse wldth register 85 by two counts and increments the pulse width register by 21 counts ln the ~ame manner as previously described in connection with the case illustrated in FIG~RE 6b. Note ln FIG~RE 6~ that the pulse width register 85 comes to rest -~-" 1068S70 at a count of "558" which is l9 counts more ~an the "539"
state at the beginning of the counting cycle.
FIGURE 6g illustrates the case where a drop is recelved with a relatively high count o~ "600" in the con-trol reglster 83 and with a relatlvely low count o~ "15" -ln the pulse width reglster 85. The prlmary distlnction between FIGYRE 6g and FIGURE 6f prevlously descrlbed~ is that the control reglster 83 overflows to lts "zero" state prlor to the pulse width register 85 arriving at its high 10 order count of 512.
In FIGURE 6g, the counting cycle in whlch the drop wa~ actually detected is aga1n completed without any incrementing of the pulse wldth reglster 85. As in the case of FI~RE 6f, the 21 count lncrement i8 deferred until the next counting cycle.
~ he next counting cgcle begins with a DRZ pulse, the control register 83 ln the "zero state and the pulse wldth register at "439" The flip-flop 118 has been set "true" by the drop detection, but the fllp-flop ll9 re-

2~ main~ "false" until the pulse width register 83 counts upto "512". The pulse width register 83 ls agaln inhibited by two count~ as the control reglster 83 is counted up and, when the pulse width register overflows to its "zero"
statel the control register ls inhiblted for 21 counts, all essentlally as indicated for the case previou31y de-scribed ln connection with FIGURE 6a. In this regard, note that the final count ln the pulse width regi~ter 85 ls "458" whereas its initlal count state at the beglnning o~
- the last complete counting cycle was "439", representing 30 the desired net increment of 19 counts.
Normally, ln the "controller" mode, drops come at regular periodic lntervals. However, ln the "pump" mode o~ operation, it is possible to receive a burst of drops in -5o-view of the larger body of liquid typically trapped between the cam followers o~ the pump. In the event a second drop occurs before a previous drop has been completely accounted for~ it can be shown that the second drop is ignored by the system. For example, if the flip-flop 118 has been set "true" and the flip-flop 119 is stlll 'Ifalse''~ the second drop ha~ abæolutely no effect on the drop detection flip-flop 118 slnce the latter flip-flop is already "set". In the situation where the drop detection flip-flop is "false"
10 and the flip-flop 119 18 already "true", the drop detec-tlon fllp-flop 118 will lmmediately be "set" again by the ~econd drop but will also be "reset" to itæ "false" state agaln on the next CLK pulse, because of the "true" state of the ~lip-~lop 119 communicated to the K input o~ the drop detection flip-flop.
For certain types of electromechanical output control devices, particularly those capable of reapondlng properly to very narrow pulse width input, the system of the preæent invention is capable of functionlng normally 20 on an expanded low level operatlonal basls, wlthout golng into alarm, by storing and proces~ing the equivalent of negative pulse width in the pulæe width register 85. In the embodlment of the invention illustrated, thi~ type of ~ operation is possible with the system operating in the ; "pump" mode.
; The negative pulse width condition may occur wlth normal low level operation in whlch extremely narrow pulse - width~ are generated~ so that further incrementing of the pul~e width register 85 upon detection of drops cau~es the 30 pulse width register to overflow and start countlng up again. Overflow of the pulse wldth reglæter countwlse 1 equivalent to underflow o~ pul~e wldth, i.e., negative pulæe wldth, whlch is nanlfested by the æudden transitlon )68570 from a very narrow output pulse (a hlgh count ln the pulse wldth register) to a very wlde output pulse (a ver~ low count in the pulse width register)~
As~uming the system is operating to provide normal ~luid flow, i.e., there are no flow conditions warranting generation of an alarm state, the negative pulse wldth condltion ln the pul~e width register 85 will ke only transltory and succe~lve decrementing by two counts per counting cycle will cause the pulse width register to 10 under~low and come out of the negative pulse width region, to thereby restore normal narrow output pulse generation manlfested by a hlgh count state in the pul~e width regis-ter.
Durlng operation o~ the system wlth apparent negative pulse width, the alarms ~ubsystem generate~ an output (without going into an alarm state), in a manner to be subsequently described7 to gate o~f the sy~tem output pulses which would otherwise normally appear on line 72 (FI~RE 4a) while allowlng the memory 3ubsystem to continue 20 to ~un¢tion normally. Thi3 capability of operation in the negatlve pulse width reglon of the pulse width register enables an expanded dynamic range of operatlon without the need for expanding the count ¢apacity of the registers in the digital memory.
FIG~RES 7 and 8 of the drawing~ are next described to further clari~y sy~tem operation under negative pulse wldth conditlons.
FIGURE 7a illustrates a typical output pul~e on llne 70 to the stepplng motor driver 71. FIG~RE 7b show~
30 the corresponding drive pulses whlch are passed to energize the ~tepping motor o~ the puup and it will be observed that the response of the motor to the output pulse o~ FIGURE 7a is es~entially very nearly ~nstantaneou~, with very llttle 1068570apparent mechanical inertia.
FIGYRE 8a shows a rather narrow memory pul~e, which is the solid curve in thls ~igure, while ~IG~RE 8b ~hows a slngle motor drive pulse generated within the memory pulse period, again lndicatlng essentially no delay in re-sponse of the motor.
FIG. 8a also shows a dotted curve whlch lndicates a further reductlon in pulse width by an incrementing of 21 counts and decrementlng of two counts ln the pulse wldth memory 85 during the next countlng oycle after a drop has occurred. Slnce the inltlal pulse wldth in FI~YRE 8a 13 assumed to be extremely narrow, the net increment of l9 count~ ln the next countlng cycle wlll yleld a negative pulse wldth whlch 1~ shown in FIGYRE 8c as an extremely wide mem-ory pul~e due to overflow of the pulse width reglster 85.
FIGYRE 8d illustrates that there is no motor pulse output sln¢e, ln a manner which wlll be subsequently herein-a~ter descrlbed, the output pulse on llne 70 ls gated off -- whenever the pulse wldth register is operatlng ln the nega-20 tlve reglon. -FIGYRE 9a lllustrate9 an output pulse on llne 73 ~or the controller case. FIGYRE 9b indlcates the corres-ponding controller mechanism response and illustrates the t~plcal ef~ects o~ mechanical inertla encountered with such devices.
FIG~RE lOa lllustrates a very narrow memory pulse produced while operating ln the "controller" mode. FIGY Æ
lOb illustrates that~ even though the ~ystem ls not operat-ing in the negatlve pulse width region, th~re ls no mechan-lcal output from the controller because of the mechanlcal~nertia whlch lntroduces a delay greater than the memory pulse wldth.
; The next portion of the description is directed to , . . .

1~68570 the ~tart-up phase o~ operation of the overall system. As previously indicated~ the major difference in the start-up mode of operation is that, instead of altering the pulse width in the pulse width reglster 83 by only two counts in each counting cycleg the pulse width reglster 1~ decre-mented by nlne counts in each countlng cycle untll the first two drops have been received. Then the system switches back to normal operatlon by continuing to decrement the pulse width register 83 two counts per counting cycle. In addition, and only while a start-up phase is in process, the output pulse rate ls temporarily set internally to a prescribed rate most suitable for initial ad~ustment.
When the system fir~t starts out, either during "power on" initialization, or during alarm, all of the ~lip-flops and registers are forced into certain specified states. In this regard~ both of the reglsters 83 and 85 are reset to "zero" over lines 133 and 135, respectively.
The ~lip-flops 118 and 119 are "reset" over line 136, fllp-flop 98 i8 "reset" over line 137, and the start-up flip-20 flop 114 is set to it~ "true" state on line 138. In addl-tion, a flip-flop 140, whlch iæ part of the start-up sub-system, i~ "reset" over line 141. The p~rpo~e of the flip-flop 140 is to keep track of receipt of the first drop in the ~tart-up phase of operation.
Re~erring briefly to FIG~RE 4c, when the system is first turned on, a power-on initializing ¢ircuit 144 ~ets the input of an alarm flip-flop 145 immediately so that the Q output of the flip-flop 145 is "true' on line 146 and all of the syætem flip-flops and registers can be ~ 3 set and reset approprlately for start-up conditions. A
; start~up switch 147 i~ then closed which "sets" the K input of the flip-flop 145 so that on the next CLK pulse over llne 148, the flip-flop 145 will go "false".

-- 1068570 `
The first DRZ pulse will start the control regis-ter 83 counting in the normal fashion, witll the initial counts being inhiblted ~rom the pulse width register 85.
However, since the start-up flip-~lop 114 has been set "true", gate 106 ls disabled and gate 105 is now enabled.
As a result$ the "8" state of the control register 83, rather than the "1" state, from the decoder 84 is utllized to set the K input of the flip-flop 98 so that, lnstead of being decremented by two counts relative to the control 10 re~iBter during each counting cycle, the pulse wldth regls-ter 85 is now decremented by nine counts during each count-ing cycle. This start-up phase can only be terminated by re~ettlng the start-up fllp-flop 114 and, as will subse-quently become apparent this wlll only occur after two drops have been detected.
When a drop is dete~ted, ~lip-flop 118 is set "true" immediate~y and lt wlll then set the fllp-~lop 119 "true", ln the manner prevlously described for normal oper-ation The Q output of the fllp-flop 119 is directed not 20 only over line 125 to "reset" the flip-flop 118, but ls also directed over line 151 as an lnput to each of a pair ~- of AND gates 1~3 and 154. The other inputs to the AND
gate 153 are the "zero" state of the pul~e width reglster ; from the decoder 86, over line 155, and the Q output of the ~tart-up fllp-flop 114, over line 156. Hence, the gate 153 will only be enabled when the sy~tem 1~ in the start-up phase, a drop has been received, and the pulae width regi~ter 85 ha~ been counted to "zero". Therefore, when the Mrst drop is detected, and the pulse width register 30 goes through "zero"~ the output of the gate 153 ~ets the J
lnput of the flip-flop 140 BO that, on the next CLK pulse the ~lip-~lop 140 will be ~et "true .
The fllp-flop 119 will be "reset" as the pulse 106~ 0 width register 85 counts past "20", to remove the "true"
output over line 151 and thereby dlsable the gate 153.
Nothing further happens in the start-up subsystem until a second drop is detected and the flip-~lop 119 i~ agaln set "true" At this time, the output of the AND gate 154 will go "true" on line 161 when the pulse width reglster 85 counts through "zero", since both of the lnputs to gate 154 over lines 151 and 158 will then be "true", and the Q out-put of the flip-flop 140~ over line 159, wlll also be "true" (from the countlng cycle when the first drop was detected), thus providlng the third enabling lnput to the AND gate 154. When the AND gate 154 ~ enabled, lts "truel output resets flip_Plop 140 and the start-up flip-~lop 114 on the next CLK pulse. This results ln a "true"
output ~rom the flip~flop 114, thus disabling the gate 105 and enabling the gate 106, so that the sy~tem exlts from the start-up phase and resumes normal operation in de-crementing the pulse width register 83 by two counts during ea¢h counting cycle.
During the start-up phase, the "true" state of the Q output from the start-up fllp-flop 114 i8 dlrected, over line 157, to the rate multiplier 42 (FIG. 4a) to tempor-arily override the rate selector switches 42a, and inter-nally force the pulse generation subsystem to a predeter-; mined pulse rate most suitable for inltial ad~u~tment of pulse width. This arrangement in~ures pulse width ad~ust-ment at an initial pul~e rate which i~ neither too slow nor too fast, con~idering the loop gain of the overall system. When the start-up phase ls termlnated, the Q out-30 put of the ~lip-~lop 114 will go "~alse", and the rate selector ~wltches 42a will resume normal rate determination control over the rate multiplier 42a.
It wlll be apparent to tho~e of ordinary skill ln :`- 1068570 the art that, during the start-up pha~e, the input over line 157 obviou~ly gates "o~" the normal rate selector switch inputs and gates "in" the prescribed start-up pha3e rate setting. For purposes of slmplicity, the speciflc gate conflguration, which may a3sume a wide variety o~ conven- `
tional loglc con~igurations, has been omitted.
The output pulse control subsystem will be next ~scribed. The output pul~e~ are generated over line 72 by the "true" output o~ an output pulse control flip-flop 162 which ls normally "reset" when the system is flr~t lni-tialized, over llne 163.
m e J input o~ the flip-flop 162 is under the control of an AND gate 165 which, in turn3 has three input~. -One input to the gate 165, over line 166, is the DRZ signal.
The other two inputs to the AND gate 165, over line~ 167 and 168, are line8 whlch are normally "true" but potentially di5abling, the input~ over line~ 167 and 168 being ~rom the alarms ~ub~ystem whlch will be subsequently de~¢rlbed.
Hence, under normal condition~, each time a DRZ pul~e ap-20 pear~ on line 166, the J input of the flip-~lop 162 will be "~et" and, on the next CLK pulse, the flip-flop 162 will go "true". This lnitlate~ the output pul~e from the ~ystem over line 70 (in the "pump" mode) or over line 73 (in the "controller" mode).
- The output pulse to the output control device can only be terminated by re~ettlng the flip-~lop 162. In this regard, the K lnput o~ the fllp-flop 162 i~ controlled by an OR gate 170 havlng two lnputs3 one lnput over line 171 representing the "zero" state o~ the pul e wldth regi~ter 85 ~ro~ the decoder 86~ the other lnput over line 172 being the duty cycle limltation signal at the output o~ the OR gate 51.
Hence, each output pul~e over line 72 1~ inltiated : by a DRZ pul~e, and the pulse ~ termlnated whenever the '' . . : '' ' .
, . .

pulse width register 85 overflows to its "zero state", thus determining the pulse width of the output pulse. If, on the other hand,a pulse width is called for beyond the duty cycle llmitation~ then, before the pulse width register 85 over-~lows, the line 172 wlll go "true", settlng the K input of the ~lip-~lop 162. On the next CLK pulse, the ~lip-flop 162 wlll be reset" to termlnate the output pulse on llne 72 and provlde an lnstantaneous llmltation on the mechanlcal output from the overall system.
While the output pulse lines 70 and 73 are shown as directly drlvlng the partlcular electromechanical output control devlce utilized, it will be appreciated that, depending upon the characteristics of the particular mechan-lcal output, it may be necessary to introduce appropriate delays prior to actual energizatlon by the output pulses.
For example, in the "pump" mode, the pump motor ls normally shut o~ between output pulses. There~ore, rather than enabling the stepping motor driver 71 lmmedlately by the output control signal, a delay of a few clock pulses is introduced to allow the power slgnal to the motor to come up to full level be~ore actually allowing stepping motor ~lses to be applied. Hence, a delay o~ a rew milliseconds, while not actually shown in the drawing o~ the overall system, may be conveniently introduced in any appropriate manner, as by a suitable one-shot, where needed.
The alarms subsystem i8 next described. An AND
gate 175 controls the high level alarm, that is, the alarm respon~e to a requirement for too wide an output pulse. One input to the AND gate 175 is the DRZ pulse on line 176 30 which also start~ every counting cycle and every output pulse to the output control device. Hence,the AND gate 175 can only be enabled during the one clock period duration o~
the DRZ pul~e, so that each time the DRZ pulse appears at the ~068570 -input of the gate 175, the system is being tested ~or the status of the other input lines to that gate. I~ all three other input llnes to the gate 175 are "true", then an ~tput from gate 175 18 provided which i~ passed by the OR
gate 180 to set the alarm fllp-flop 145 whlch, on the next CLK pulseJ goes "true" to energize the alarm dlsplay 181.
A second input to the gate 175, over line 177, -comes from the ~ output Or a flip-flop 182, 80 that ~lip-flop 182 must be in the "reset" condltion for the gate 10 lnput line 177 to be "true". A third input to the gate -175, over llne 178, is from the 768-1023 output of the pul~e width register decoder 86, whlch is "true" only when the pulse width register 85 is ln the last 25 percent of its upper countlng range (indlcating a very narrow pulse width). The ~ourth input to the gate 175, over llne 179, is the ~ output of a flip-flop 183, so that flip-flop 183 must also be false", as ln the case of the fllp-flop 182, ;ln order to enable the gate 175.
The only time that the flip-flop 183 can be "~alse"
20 when a DRZ pulse o¢curs, is if flip-flop 183 has been "reset" on the previous countlng cycle. In this regard, the flip-~lop 183 gets either "set" or "reset" after every DRZ
pulse, so that the flip-flop 183 ls tested at the start of every counting cycle. The J lnput of the ~lip-flop 183 is controlled by an lnput AND gate 185, and the K input o~ the :~llp-~lop 183 ls controlled by an lnput AMD gate 186. Each ..o~ these gates receives the DRZ pulse as an input over line 187.
;The second input to the gate 185, over llne 190, ;30 is the 512-1023 high order ~lip-fl~p output of the pulse : wldth register 85 from the decoder 86. This same output on line 190 ls inverted and then dlrected as the second input to the gate 186. mere~Ore, lf the pul~e width ; ' regi~ter 85 has come to rest in a high count state during the last counting cycle, then the gate 185 will be enabled on the next DRZ pulse to ~et the flip-flop 183 to its "true" state on the very next CLK pulse. If, on the other hand~ the pulse width reglster 85 ends the precedlng count-ing cycle with a count below "tl2", then the gate 186 will go "true" on the next DRZ pulse to "reset" the M ip-flop 183.
Hence, lf a very wide pulse output is produced on the precedlng counting cycle (represented by a low count ln the pulse width register 85) the fllp-flop 183 wlll be "re~et" on the next countlng cycle and its ~ output will go "true". In contrast, a narrower pulse (pul~e width register count of "512" or more)ln the prece~ng countlng cycle will set the fllp-flop 183 80 that its Q output ls "true". ~hu~J the fllp-flop 183 essentially remembers whether the system had a wide pulse or a narrow pulse on the lmmedlately precedlng counting ¢ycle and is used throughout the alarms subsystem for thls purpose.
Assumlng the output pul~es are gettlng longer and longer wlth each countlng cycle, the fllp-~lop 183 will likewise be reset on each countlng cycle to malntain lts ~ output "true". When a countlng cycle i9 flnally reached where the pul~e w~dth register 85 ~ust barely underflow~, the output llne 768-1023 from the decoder 86 will provide a '~true" output, over llne 178, to the AND gate 175. This repre~ents a condition where a very wide output pulse in one countlng cycle i8 lmmediately followed by an extremely narrow output pul~e on the very next countlng cycle, in-dicating that the pulse width register 8~ has underflowed.
Since the flip-Plop 183 had been "reset" every time a long output pul~e occurred~ it i~ stlll "resqt"
from the previous counting cycle andJ with the 768-1023 :

llne "true", the AND gate 175 will be enabled i~ the output from the ~lip-~lop 182 is also "true". The latter flip-~lop 182 is "reset" when the system ls turned on and ls, there~ore, normally "false" so that its ~ output on -line 177 will also normally be "true". It will be appar- ~ -ent, therefore, that whenever a wide pulse i8 followed by an extremely narrow pulse, the AMD gate 175 will be enabled and the ~ystem wlll go into high level alarm.
As wlll subsequently become apparent, the ~lip-10 flop 182 has as its ~unction to remember (in the "pump"
mode o~ operation) that a very wide pulse width has been produced after a very narrow pulse width, and that it is ; not yet desired to go into low level alarm be¢ause o~ the capability o~ the pump for normal operation ln the nega-tive pulse width region o~ the pulse width register 85.
An AN~ gate 195 sets the controller low level alarm One lnput to the gate 195, over l~ne 196, is the DRZ signal at the geginning of each countlng cycle. A
second input, over line 197, is the Q output of the flip-flop 183 (repreBentlng a relatively short output pul~e onthe preceding counting cycle). A thlrd input, over line 198, i8 the 0-255 state from the pul~e width reglster de-coder 86, lndicating that the present pulse being called ~or has a very 1Qng pulse period. A ~ourth input to the gate 195, over line 199, indicates khat the system has been set by the ~umper 53 (FIG. 4a3 to operate in the "controller"
m ode. The ~ifth input to the gate 195, over line 201, ls the ~ output of the start-up flip-flop 114 which indlcates, when the line 201 is "true", that the system i8 out of the start-up phase. This prevents the controller from going into alarm during the start-up phase, since the system normally starts out with extremely narrow pulses (both registers havlng been reset to "zero" initially).

106~3S70 Hence, the input lines 199 and 201 to the AND
gate 195 will always be "true " in normal operation tout-~ide o~ the start-up phase). T;lere~ore, whenever a very narrow pulse on the immediately preceding counting cycle is being ~ollowed by an extremely wide pulse (a pulse width register count of 255 or less), the AND gate 195 will be enabled to pa3s the very next DRZ pulse and thereby trig-ger ~he controller low level alarm through the OR gate 180, to "set" the alarm ~lip-flop 145.
;- 10 The transltion ~rom a narrow pulse to an extremely wide pulse indicates that the pulse width regiater has underrlowed whlch meansJ in the "controller" mode, that the system is lncapable of producing pulses sufficlently narrow to arre~t further fluid flow, e.g., elther the controller 18 incapable o~ clamping of~ the ~eeding tube or a leak exlsts, 80 lt 1~ de~irable to go into the alarm ~tate The pump low level alarm 13 controlled by an AND
gate 204. The pump low level alarm will not be trlggered ' -merely by underflow of the pulse wldth register 83 (neg-ative pulse width), sinae this may ~till be normal opera-tlon ln the "pump" mode. Rather, lt i5 intended that the ~`
- pump low level alarm wlll be trlggered when the pulse wldth . called for in the "pump" mode o~ operation has exceeded a negatlve pul~e wldth requlrement of 25 percent, i.e., the virtual pul~e width ha~ gone from ~omething more than 75 percent on the previous counting cycle to less than 75 percent o~ the maximum pulse width on the present counting cycle. The term "virtual pulse width" is utilized becau~e, 30 a~ will become apparent, the actual output pulse to the output control devlce (the stepping motor driver 71~ is actually gated o~f when the pul~e width reglster 85 i~ in the negative region.

-~2-The sequence of alarm conditions for the pump low level alarm is a very narrow pulse, followed by a very wide pulse (under~low of the pulse width register 85 lnto the negative region) ~ollowed immediately by a reductlon in that very wide pulse wldth to a pulse width ~ust below 75 percent o~ the maximum pulse width. Essentially, this ls very much llke the controller low level alarm except that ; the low level boundary i~ at minus 25 percent o~ the pulse wldth reglster rather than at the zero level o~ the pulse 10 wldth regi9ter; thus provlding enhanced dynamlc range for the "pump" mode o~ operation.
The reason for going into pump low level alarm under the a~oredescribed conditlons ls that a burst of drops ~rom the pump may occur whlch temporarlly may drive the pulse wldth register 85 into the negatlve region, all a~ part o~ the normal operation Or the pump. However, ln such normal operation, the pump wlll gradually return to a narrow pulse wldth in the positlve range of the pulse width reglster I~, on the other hand, the pulse wldth reglster 20 85 1~ continually in¢remented by more and more drops call-lng for even larger negative pulse wldth on a virtual basis, this lndicates that, even wlth no mechanlcal output from the pump (the motor is gated o~f when the pulse width register is ln the negative region) addltlonal drop flow is belng produced, and an alarm state should be generated.
The fllp-flop 182 gets "set" by the same conditions ~; that would trigger a low level alarm in the "controller"
mode o~ operatlon. In this regard, the J input of the ~llp-flQp 182 i~ controlled by an AND gate 205 which re-30 celves a~ one lnput, over llne 206, the Q output o~ the flip-flop 183 and, as a second input over line 207, the 0-255 output from the pulse width reglster decoder 86. The thlrd input to the AND gate 205, over line 208J is the DRZ
:

signal.
Hence, lf there was a very narrow pulse width on precedlng counting cycleJ the Q output o~ the flip-flop 1,83 wlll be "true'. If, in addition, a vexy wide pulse width 1~, being called for on the next countlng ¢ycle, the 0,~"255 decoder output line from the pulse width register 85 will also be "true" so that, on the next DRZ pulse, the gate 205 will be enabled, the J input of the fllp-flop 182 will be "set and, on the very next CLK pulse, the Q out-put from the flip-flop 182 will go "true" on line 209 to the gate 204.
Ihe "~rue output of the gate 205 ls also directed, over line 21O J through an inverter 212 (FIG~RE 4a) to pro-duce a "~alse" output on line 168 and disable the lnput AND gate 165 which control~ the J input of the output pulse control ~lip-flop 162. Thls prevents any output pul~ea from being dlre¢ted to the output control device whenever the pulse width register ls starting to operate in the negative pul~e width region.
The AND gate 214 controls the K in~ut o~ the flip-flop 182. One input to the gate 214 i3 the DRZ slgnal, while the second input to the gate, over line 215, is the 768-1023 output lins from the pulse wldth register decoder 86. Hence, the output of the gate 214 will remain "false"
as long a~ wide pulse widths continue to be generated.
It wiil be apparent, from the foregoing, that the fllp-flop 182 gets "set" whenever a narrow pul~e wldth becomes a very wide pulse width (negative pulse width reglon), and the flip-flop 182 only get~ "reset" agaln ln going from a very wlde pul~e width to a very narrow pulse width. As long as the system remains in the very wlde pulse wldth region, the flip-~lop 182 remalns set "true".
In switching back to narrow pulse wldth operation, the -`' 1(~8570 output of the flip-flop 182 is still "~alse" when the very next DRZ pulse occurs and prevents the hlgh level alarm (the lnput over line 177 to the AND gate 175) from being activated because of the previous operation in the w~de pul~e width region.
Another input to the pump low level alarm gate 204, over line 216, is the 256-511 output llne from the ; de¢oder 86 of the pulse width register 85, which repre~ents a pulse width ~rom 1/2 to 3/4 o~ the maximum pulse width.
The AND gate 204 is only enabled when a short pulse wldth i8 ~ollowed by a very wlde pulse width which ulti-mately drops down to a pulse width of less than 75 percent of the maxlmum pulse width Thls indicates that drop ~low keeps coming, thereby continually reduclng the pulse width more and more, until a negative pulse width beyond 25 per-cent i~ exceeded, which means that the ~y~tem cannot prevent ~low even when the pump is turned off, and thu~ indicating an alarm state.
Again, the sequence for pump low-level alarm must be a short pulse width ~ollowed by a long pul~e width, followed further by an attempt by the ~ystem to reduce the pulse wldth below 75 percent. ~nder these condltlons, flip-flop 182 ls "true", and the pulse width register ls ; lnto the second 25 percent of its count range (256-511) ~o that line 216 is also "true" and, on ~he next DRZ pulse, the gate 204 wlll be enabled to trlgger an alarm state.
The ~ output of the ~lip-~lop 182 ls also directed oYer the line 167 aæ an lnput to the AND gate 165 (FIG 4a) - and, since the ~ output is normally "true", lt typically does not a~ect the generation of the output pul~e by the fllp-flop 162, except when the ~llp-~lop 182 is set "true"
indicat~ng operation in the negatlve region of the pulse wldth register 85.
~65-' , . - , .

Once operation in the "pump" mode has gone into the negative pulse wldtll region of the pulse width regis-ter 85, the system must be capable of coming out of the potentlal alarm state, operating with a narrow pulse width in the posltive region of the pulse wldth register 85, and be prepared to agaln respbnd to an improper pulse width sequen¢e calling ~or excessive negatlve pulse wldth. In thls regard~ upon the ellmination of the transltory con-: dition calllng for negative pulse width, the system should normally begin to produce very narrow pulse widths, and the 768-1023 output line from the pul~e width register ~;~
decoder 86 should go "true", thus enabling the gate 214 on the next DRZ pulse and cau~ing the flip-flop 182 to be "reset" on the next CLK pulse. This output condition will not cause the high level alarm (AND gate 175) to be en-abled slnoe the ~ output of the ~llp-flop 183 whlch 18 also one o~ the inputs to the gate 175, will now be "false".
: During inltial start-up of the overall system, the fllp-flop 182 is "reset" and the flip-flop 183 is set "true". The reason for this is that, in the start-up phase of operation; which starts out with a very ~ide pul~e period, (the pulse wldth reglster 85 is at "O") the fllp-flops 183 and 182 must be inltlally set to lndlcate the appearance of havlng recelved a narrow pulse wldth on a fict~tious preceding counting cycle. Thls will cause fllp-~lop 182 to be set "true" by the very flrst DRZ pulse and also disable gate 165 whi¢h prevent~ the flrst pulse, which is a very wide pulse, from being directed to the output control device. The second output pulse, now a 30 very short pulse, i8 prevented from activating the high level alarm because the fllp-~lop 182 is still "true" and 1~ only "reset" after the second output pulse has been lnitlated by a DRZ pulse. The sequence of a simulated , ' .. . .

- 10685~0 short pulse perlod and an initial wide pulse period would also normally activate the low level alarm in the "con-troller mode". However, this is prevented by the signal -on line 201 which disables the gate 195 during the start-up pha~e.
The ~unction o~ the "no-drop" alarm produced by a "true! output from the OR gate 225 is to count the number o~ DRZ pulse~, i.e., the number of counting cycles ini-tiated ln the digital memory subsystem, and to trlgger an alarm state in the event no drops are detected wlthln a prescribed number of such counting cycles.
The DRZ pulses are dlrected over line 226 a~ lnput -to a counter 227, typically a counter with a range of 27.
The output of the counter 227 is decoded vla a decoder 228 whi¢h has two output llnes, one output line representing a count o~ 64 DRZ pul~es~ the other output llne represent-ing a ¢ount of 96 DRZ pulse~. The counter 227 1~ "reset", ea¢h time a drop is detected, by a "true" output on llne 230 representing the state of the ~llp-flop 119 ln the control ~ubsystem. It will be recalled that the latter flip-flop 119 gets set "true" during the counting cycle following detection of a drop.
The "64" output line from the decoder 228 iB
dlrected as one input to an AND gate 232 whlch has a ; second input, over llne 233, ~rom the ~ output of the start-up ~llp-~lop 114. Hence, durinæ normal operatlon, when the system i9 out of the start-up phase, a count of 64 DRZ
pulses re¢eived, wlthout any drops being detected, will cause the gate 232 to go "true", and thereby trigger an 30 alarm state through the OR gates 225 and 180.
When the system ls still operatlng ln the ~tart-up phase, lt may take more counting cycles to generate the fir~t drop, since the system starts out with a very narrow ' `` 1068570 pulse wldth. There~ore, when the system ls ln the start-up phase, the gate 232 is disabled, and the "96" output -.
line from the decoder 228 ls used to indlcate that 9~ ~ .
countlng cycles have occurred without the detection of a drop, in order to trigger the no-drop alarm state.
A "no action" alarm ls also lncluded ln the alarm sub8ystem and gets actlvated if there are no drops or out- ~ -put pulses from the system occurring ~or any period of ~ix mlnutes.
The "no action" alarm includes a flip-flop 235 --~
whlch resets a counter 236 (typically a 27 counter) each time the fllp-flop ls set "true". The counter 236 ls "reaet" through a pulse gate lndlcated by a capacitor 237a and resistor 237b. The pulse gate 18 actually a differ-entlator which receives the Q output level of the flip-~lop 235 and convert~ it to a pulse capable o~ resettlng the counter 236. The flip-flop 235 ls, ln turn, set to lts : "true" state over the llne 238 whenever the output fllp-flop 162 (FIG. 4a) g oe ~ "true". The output on llne 238 20 i8 also coupled through a pulse gate conslsting of a capa-citor 239a and resistor 239b~ so that the pulse whlch sets the fllp-flop 235 only occurs when the output fllp-f`lop 162 i8 going from lt~ "false" state to lts "true" Rtate.
- The fllp-flop 235 i~ "reset" by an lnput over line 241 ~rom the drop detector 115 (FIG. 4b) each tlme a drop ls detected. Again, the output from the drop detector 115 ls - coupled to the "reset input of the fllp-flop 235 through a pulse gate consisting of a capacltor 242a and a reslstor 242b.
. 30 If output pulse~ are lnitially produced and then `~. ceaRe to be produced by the output flip-flop 162, m ere will be no pulses at the Q output of the fllp-flop 235, . .
since there ls no change in the Q output of the ~lip-.

flop and only a change in output will be passed by the pulse gate. Similarly, if no drops occur, no pulses will occur at the output of the flip-~lop 235, since a drop is required to "reset" the flip-flop 235 before the flip-~lop can be "set" again, and a pulse output will only be produced at the Q output of the flip-flop in going from the "reset" state to the "set" state.
Hence, lf the fllp-flop 235 keeps getting set from the output fllp-flop 162, wlthout any drops being de-tected, the fllp-flop 235 will already have been in the "set state and no transition pulses wlll be generated at the Q output of the flip-flop 235 and, accordingly, the counter 236 will not be "reset". Thus, lt wlll be appar-; ent that the presence o~ both drop~ and output pulses are ne¢essary to generate pulse output from the flip-flop 235 to reset the counter 236. I~ neither drops nor out-put pulses occur for approximately six minutes, the counter 236 will be counted up by an oscillator 245 over line 246.
When a decoder 247 produces an output over line 248 indl-20 catlng that counter 235 ha9 counted up 64 clock periods from the osclllator 245, a six mlnute "no action" alarm will be generated by the output of the OR gate 180.
It wlll be apparent that 64 periods, at 5.6 seconds for eaah perlod, yields a time lnterval of approxlmately 81x minutes. The reason for selecting the six mlnute time interval is that~ at very low pumping rates, it can actually take as long as a period sllghtly less than six minutes between a pair of drops, and it is desired to avoid the alarm state for this condition of operation.
The "no action" alarm will also be trlggered if the operator lnadvertently selects a zero drop rate. ~nder tho~e condltions, no DRZ pulses will be produced, and ther~
- fore, the "no-drop" alarm condition monitored by the OR

gate 225 wlll be ine~fectlve However, the "no-action"
alarm will be triggered after six minutes.
The vlsual pulse width lndicatlon subsystem is next described. T'ne visual pulse width indication sub-sy~tem ls used only ln connectlon wlth those output control devlces whlch depend on gravity induced hydrostatlc pressure levels, such as controllers rather than pumps. :
A red llght driver circuit 251 and a green llght driver clrcult 252 are controlled by their own ~lip-~lops 2~3 and 254, respectlvely The J and K inputs to these fllp-flops 253, 254 are controllPd by four AND gates. An AND gate 255 control~ the J input of the flip-flop 253, the K input of that ~llp-flop belng controlled by an AND gate -256. ~he J lnput of the fllp-~lop 254 18 controlled by an AND gate 258, the K input o~ that ~lip-~lop being controlled by an AND gate 257.
All ~our AND gates 255, 256, 257 and 258 have as one lnput the DRZ slgnal, over line 187. Hence, the vlsual pulse wldth indication subsystem 1~ only "set" or "reset"
at the beginnlng o~ a counting cycle inltiated by a DRZ
pulse. The sub~ystem thus indicates between DRZ pulses where the subsystem had been set on the last DRZ pulse.
When the 3ystem first starts out (power turned on) the red llght fllp-~lop 253 ls "reset" while the green light flip-~lop 254 i3 set "true" over llne 260. Hence, on start-up, the green light will go on immediately. When the fir~t DRZ pulse comes along after such initialization, the ~lse width regiæter 85 has been lnitially set to the "zero"
state, so that the 0-276 output line from the decoder 86 will be "true". ~his produces a "true" input over line 262 to AND gate 255 and is inverted ~y an inve~ter 264 to pro-duce a "true' input over line 266 to the gate Z57. Hence, the green light ~lip-~lop 254 is "reset" by the ~lr~t DRZ

lQ68570 pulse and, as the red light turns on, the green light momen-tarlly turns off.
On the second DRZ pulse, the pulse width register 85 wlll now have nine counts less (start-up phase) than it had before, ~o that the output llne 640-1023 from the de-coder 86 will now go "true", resulting in enabling of the AND gate 258 and dlsabllng of the gate 257, which "~ets"
the flip-flop 254 and turns on the green llght. At the same tlme, the 0-766 output line from the decoder 86 goes "false which dlsables the gate 255 and enables the gate 256, so that the DRZ pulse "resets" the flip-flop 253 and turns of~
- the red llght.
The visual pulse wldth indication subsystem re-main~ in the state with the green light on and the red llght of~ untll the pulse wldth 1~ sufficlently wide so that the 0-766 line out o~ the decoder 86 again goe~ "true" and enables the gate 255 to "set" the red light flip-flop 253 and turn on the red light. Sln¢e the 640-1023 output llne from the de¢oder 86 ls stlll "true", the green llght fllp-20 flop 254 has not yet been "reset". ~nder these ¢ondltlons,both the red light and the green light wlll be turned on.
If the count in the pul~e wldth register 85 ls ~urther reduced below a count of 640, then the output line 640_1023 from the decoder 86 will go "false", gate 258 will be dl~abled, ~ate 257 wlll be ena~led, and the green llght ~llp-flop 254 wlll be "reset" to tu m of~ the green light.
The red llght flip-flop 253 will now remaln ~et to its "true" state, wlth the red llght on, all the way down to a 'zero" count in the pulse width regi~ter 85, indlcatlng very 30 wide pul~es.
Hence, the viæual pulse wldth lndlcatlon system enables ready observance by medical per~onnel of the output pulse wldth range of the fluid flow control sy~tem so that, 85'70 if excessively wide or excessively narrow pulses are being produced, the administration set can be adjusted, as by ralsing or lowering the bottle9 to bring the output pulse wldth into the optimum operating range for the controller.
The new and improved ~luld ~low control system of the present invention is extremely accurate, reliable and ea3y to use. The system provides enhanced digital pre-cl~ion in sele¢ting and maintaining drop ~low rates throughout a wide range, and the syatem is quick to lnform medical personnel of any indi¢ations which might pose a hazard to the patient. System testing and calibration is con~iderably slmplified and is essentially accompllshed merely by ¢he¢king the ¢lo¢k 40. Hen¢e, the system o~ the preaent lnvention minimlzes the time-consuming and error-prone a~pects of human monitoring and flow rate adJustment, provides subs~antlal lmprovement ln e¢onomy, adaptablllty of a single system to a varlety of different me¢hani¢al output ¢ontrol devi¢es~ and enhan¢ed reliability, stabiiity and a¢curacy over previous automati¢ ¢ontrol systems.
It will be apparent from the foregoing that~ while parti¢ular forms of the inventlon have been illustrated and deacribed, various modiflcations ¢an be made without departing from the spirit and s¢ope of the invention.

Claims (47)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. Apparatus for use in a system for parenteral administra-tion of liquids at desired drop flow rates through a feeding tube from a liquid source to a patient, said apparatus comprising: electro-mechanical output control means for manipulating the feeding tube to vary the flow of liquid in the feeding tube; input means for establishing a desired flow rate; electrical pulsing means respon-sive to said input means for providing output pulses to operate said output control means, said output control means being inactive during the periods between said output pulses in a pulse train, said output pulses being at a substantially higher frequency than the desired drop flow rate frequency; and digital memory and timing means for automatically predetermining and varying the pulse width of said output pulses operating said control means, to achieve the desired drop flow rate.

2. A system as set forth in Claim 1, wherein said digital memory and timing means includes at least one counter.

3. A system as set forth in Claim 2, and further including:
drop flow rate detection means; and means for providing a negative pulse width by overflow of said counter through successive incre-menting of said counter when a plurality of drops have been detected in rapid succession.

4. A system as set forth in Claim 1, wherein said digital memory and timing means includes a pair of digital counters.

5. A system as set forth in Claim 1, wherein said digital memory and timing means Includes a digital counter which undergoes successive counting cycles, a single counting cycle for each of said output pulses produced by said pulsing means, the count state of said counter at the beginning of each counting cycle determining the pulse width of the corresponding output pulse produced during that counting cycle.

6. A system as set forth in Claim 5, and further including:

drop flow rate detection means; and means for decrementing said counter by a first prescribed number of counts during each of said counting cycles and for incrementing said counter by a second prescribed number of counts only during a counting cycle after a drop of liquid flow has been detected.

7. A system as set forth in Claim 6, wherein the ratio of said second proscribed number of counts to said first prescribed number of counts Is a predetermined value.

8. A system as set forth in Claim 7, wherein said ratio is the same as the ratio of the frequency of said output pulses pro-duced by said pulsing means to the desired drop flow rate frequency.

9. A system as set forth in Claim 7, wherein the frequency of said output pulses is a high non-integral multiple of the desired drop flow rate.

10. A system as set forth in Claim 9, wherein said ratio is 10-1/2.

11. Apparatus as set forth in Claim 1, and further compris-ing: means responsive to a predetermined sequence of states of said digital memory means for generating an alarm state.

12. Apparatus as set forth in Claim 1, and further compris-ing: means responsive to a predetermined sequence of pulse widths of said output pulses for generating an alarm state.

13. Apparatus as set forth in Claim 1, and further compris-ing: drop flow rate detection means; and means responsive to a lack of detection of flow of liquid in said feeding tube within a prescribed period of time for generating an alarm state.

14. A system as set forth in Claim 1, wherein said digital memory means further comprises: a first digital counter; and a second digital counter having a counting cycle under the control of said first counter.

15. Apparatus as set forth in Claim 14, including means responsive to a prescribed sequence of states of said second counter for generating an alarm state.

16. A system as set forth in Claim 1, and further compris-ing: means for selectively overriding said digital memory and timing means for Imposing a duty cycle limitation upon said pulse width.

17. A system as set forth in Claim 1, and further compris-ing: visual display means for indicating the range of magnitudes of the pulse widths of said output pulses.

18. Apparatus as set forth in Claim 17, wherein said visual display means includes a pair of lights which are energized in pre-determined combinations to indicate a plurality of pulse width ranges of operation.

19. A system as set forth in Claim 1, and further compris-ing: means for temporarily overriding normal control of said pulsing means and setting said pulsing means to a prescribed pulse rate during predetermined periods of operation.

20. The system as claimed in Claim 6, including; means for increasing prescribed number of counts by which said counter is normally decremented during each counting cycle to a larger prescribed number for each counting cycle during an initial start-up period of operation of said system.

21. The system as claimed in Claim 16, and further com-prising: clocking means for generating two different clock rates, a normal clock rate and a higher clock rate.

22. The system as claimed in Claim 21, wherein said duty cycle signal, if imposed during a counting cycle, switches the counting rate of said counter from said normal clock rate to said higher clock rate.

23. The system as claimed in Claim 13, wherein said time is a function of the number of pulses generated by said electrical pulsing means.

24. The system as claimed in Claim 13, wherein said time is a function of the lack of occurrence of drops or output pulses for a prescribed period of time.

25. The system as claimed in Claim 12, wherein said pre-determined sequence of pulse widths is a narrow pulse width of prescribed magnitude followed by a wide pulse width of prescribed magnitude.

26. The system as claimed in Claim 12, wherein said pre-determined sequence of pulse widths is a wide pulse width of prescribed magnitude followed by a narrow pulse width of prescribed magnitude.

27. The system as claimed in Claim 25, wherein said wide pulse width of prescribed magnitude is followed by a narrow pulse width of prescribed magnitude induced by further and successive incrementing rather than further successive decrementing of said second counter.

28. The system as claimed in Claim 6, and further compris-ing: start-up means for preventing normal system response to a predetermined number of initial drops of liquid flow in the feeding tube.

29. The system as claimed in Claim 6, further including:
means for increasing said first prescribed number of counts by which said counter is decremented during each of said counting cycles to a larger number for each counting cycle which occurs during pre-determined periods of operation.

30. The system as claimed in Claim 1, wherein said elec-trical pulsing means includes digital pulse generation and rate determination means for generating command pulses to selectively control the frequency of said output pulses and the time of initia-tion of each of said output pulses.

31. The system as claimed in Claim 30 and including drop flow rate detection means, wherein said pulse width is in-creased with each command pulse produced by said pulse generation and rate determination means and said pulse width to decreased with each drop of flow of liquid in said feeding tube that is detected.

32. The system as claimed in Claim 30, and further compris-ing: means responsive to excessive pulse width for generating an alarm state.

33. The system as claimed in Claim 30, and further compris-ing: means responsive to a predetermined reduced pulse width for generating an alarm state.

34. The system as claimed in Claim 12, and further com-prising: means responsive to a predetermined sequence of pulse widths in prescribed ranges of magnitude for generating an alarm state.

35. The system as claimed in Claim 6, wherein said pulse width is increased during each period between initiation of successive ones of said output pulses and decreased with each drop detected.

36. The system as claimed in Claim 1, including an open loop digital control means for digitally establishing the frequency of output pulses electrically energizing said driving means; and a closed loop digital memory control means, including drop flow rate detection means, for digitally predetermining and varying the pulse width of said output pulses to said driver means.

37. The system as claimed in Claim 1, including an electri-cal stepping motor for driving said output control means, and wherein said electromechanical output control means is a pump.

38. The system as claimed in Claim 1, wherein said electro-mechanical output control means is a feeding tube pincher, and further comprising an electromagnetic actuator for said pincher.

39. The system as claimed in Claim 37, wherein said pump is a positive pressure infusion pump means.

40. The system as claimed in Claim 12, including: flow monitoring means for monitoring liquid flow in the administration system; and digital means responsive to said electrical pulsing means and said flow monitoring means for indicating a lack of flow within a time period determined by a specified number of said pulses.

41. The system as claimed in Claim 12, including: flow monitoring means for monitoring liquid flow in the administration system; and digital means responsive to said pulsing means and said flow monitoring means for indicating a lack of either flow or output pulses within a prescribed time period.

42. The system as claimed in Claim 12, including: flow monitoring means for monitoring liquid flow in the administration system: pulse width monitoring means; and means responsive to said pulse width monitoring means for indicating the occurrence of a pre-scribed non-tolerated sequence of pulse widths.

43. The system as claimed in Claim 1, and further comprising:
means for selectively overriding said digital memory and timing means for imposing a duty cycle limitation upon said pulse width.

44. Apparatus for use in a system for automatic parenteral administration of liquids at a desired drop flow rate through a feeding tube from a liquid source to a patient, said apparatus comprising:
output control means for determining the rate of drop flow of liquid in the feeding tube; input means for establishing a desired flow rate;
electrical pulsing means responsive to said input means for providing successive output pulses to said output control means, said output control means being operable to permit liquid flow in a feeding tube during said output pulses and operable to prevent liquid flow during the periods between said output pulses in a pulse train, said output pulses being at a substantially higher frequency than the desired drop flow rate frequency, and timing means for varying the pulse width of each of said output pulses to vary the time that said output control means permits liquid to flow in said feeding tube, thereby achieving the desired drop flow rate.

45. A method for use in the parenteral administration of medical fluids by an intravenous set including drop forming means in a flexible tube coupled to said drop forming means for carrying drop flow, said method including controlling the rate of drop flow through the flexible tube and comprising the steps of: clamping said tube to a substantially shut-off state; producing digital control pulses in a pulse train at a selected frequency proportional to the desired rate of drop flow; monitoring the actual drop flow occurring through said tube; selectively varying the pulse width of each of said control pulses in a digital memory in accordance with the desired drop flow rate detected and repetitively opening and closing said tube to fluid flow in response to said digital control pulses to regulate the actual drop flow rate so that it conforms to said desired drop flow rate said tube being closed during the periods between said control pulses and said pulse train.

46. The method as claimed in Claim 45, wherein the frequency of opening said tube Is a relatively high multiple of the desired drop flow rate.

47. The method as claimed in Claim 46, wherein said multiple is approximately 10-1/2 times the desired drop flow rate.