CA1074450A - Digital monitor - Google Patents
Digital monitorInfo
- Publication number
- CA1074450A CA1074450A CA276,578A CA276578A CA1074450A CA 1074450 A CA1074450 A CA 1074450A CA 276578 A CA276578 A CA 276578A CA 1074450 A CA1074450 A CA 1074450A
- Authority
- CA
- Canada
- Prior art keywords
- digital
- memory
- monitoring
- numbers
- counter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/28—Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
- G06F11/0763—Error or fault detection not based on redundancy by bit configuration check, e.g. of formats or tags
Abstract
DIGITAL MONITOR
ABSTRACT OF THE DISCLOSURE
A digital monitor for monitoring the operation of a synchronous digital system. Proper operation of the monitored digital system is determined by storing a predetermined sequence of digital numbers in a memory. The bit patterns generated by the system being monitored are utilized as addresses to read the stored digital numbers.
After each read cycle the digital number read from the memory is examined to determine if it has the proper value.
If the value is not proper, a memory is set indicating that the system being monitored has malfunctioned, Additionally, the number of bit patterns checked during each cycle of the system is determined. If the correct number of patterns are not checked, the memory is also set indicating that a malfunc-tion has occurred. Apparatus for monitoring a selected number of analog signals such as power supply voltages is also provided. Either of these tests may be inhibited by signals from the system being monitored or by signals from an external source.
ABSTRACT OF THE DISCLOSURE
A digital monitor for monitoring the operation of a synchronous digital system. Proper operation of the monitored digital system is determined by storing a predetermined sequence of digital numbers in a memory. The bit patterns generated by the system being monitored are utilized as addresses to read the stored digital numbers.
After each read cycle the digital number read from the memory is examined to determine if it has the proper value.
If the value is not proper, a memory is set indicating that the system being monitored has malfunctioned, Additionally, the number of bit patterns checked during each cycle of the system is determined. If the correct number of patterns are not checked, the memory is also set indicating that a malfunc-tion has occurred. Apparatus for monitoring a selected number of analog signals such as power supply voltages is also provided. Either of these tests may be inhibited by signals from the system being monitored or by signals from an external source.
Description
2~
--BACKGROUND OF THE INVENTION
Field of the Invention:
he inventlon rel~tes to methods an~ apparatus for monitoring;digital systems and more particularly to digital monitors which detect mal~unctlons ~y comparing a selected number of digital bit patterns generated by the system being .~ mo~ltored to a sequence o~ stored digital numbers to determlne at the correct bit patterns ~re being generated and that these bit patterns are in the correct sëquence.
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45,939 .
Description of the Pri~r Art:
Prior art monitors for synchronous digital systems have typically utilized a memory of some type to store the bit patterns generated by the system being monitored. The monitor was synchronized with the system to be monitored such that the digital bit patterns stored in the memory were ~-sequentially read an~ compared to the bit patterns generated by the rnonitored system. These bit patterns are ldentical lf and only if the system being monitored is operating properlyO One disadvantage of these SySterQS from a stand-point of circuik complexity was the fact that each memory location required the storage of a number o~ bits equal to -the number of bits in the pattern to be monitored even `~
though the number o~ patterns to be rnonitored was relatively small, SUMMARY OF THE INVENTION
The disadvantages o~ prior art synchronous digital system monitors are substantially reduced by the monitor ~-which is the subject o~ this application. The flrst step in utilizing the disclosed monitor is to establish the bit patterns generated by the system being monitored during normal operation and the order in which these patterns occur. Each bit pattern is identi~ie~ by a number to estab-lish a sequence or numbers ranging from 1 to m. Numbers 1 through m are then store~ in a memory utilizlng the sequentiaI
blt patterns generated by the system being monltored during normal operation as addres~ses~ The process o~ determining the sequence o~ numbers 1 through m and storing these numbers in bhe memory is referred to as the initialization cycle.
As the system being monitored sequentially cycles ,.. , .. ,...... , , .,. ~. ., . , ,, , - . . . .
45,939 through its normal operating cycle the bit patterns gene-rated by the system are coupled to the memory as addresses causing the corresponding memory locations to be read. Each dlgital number read from the memory is checked to determine if it contains any logic "1" bits. Each time a memory location containing at least one logic "1" bit is read a counter is incremented one count, This causes the counter to sequentially cycle through numbers 1 to m as these num-bers are sequentially read from the memoryO
Each tlme the counter is incremented, the output of a counter is compared to the value ~ust read from the memor~O If they are identical the associated bit pattern is then known to be correct. If they are different, an error signal is generated indicating that the system being moni-tored has malfunctionedO Additionally, at the end o~ the - ~
synchronous cycle of the system being monitored the contents ~-o~ the counter are compared to a digital number to determine i~ the proper number o~ correct comparisons have been made.
. .
This provides a two level check wlth each of the bit pat- - -~
terns generate~ by the system ~eing monitored checked to determine if each pattern ls correct and that the correct number of bit patterns was generated. This provides a very ~-~
reliable check on the proper operation of the associated synchronous systems. Either o~ these comparisons can be inhibited by an external signal. Additionally, circuitry is provided ~or monitoring a specified number of analog slgnals.
The monitor also includes circuitry permitting the error signals generat~d by the m~nltor to be interrogated by a digital computer. This feature permits the monitor to be utilized to check lndividual synchronous digital systems
--BACKGROUND OF THE INVENTION
Field of the Invention:
he inventlon rel~tes to methods an~ apparatus for monitoring;digital systems and more particularly to digital monitors which detect mal~unctlons ~y comparing a selected number of digital bit patterns generated by the system being .~ mo~ltored to a sequence o~ stored digital numbers to determlne at the correct bit patterns ~re being generated and that these bit patterns are in the correct sëquence.
~ ~ , .. .: .
~, . . . ..
:: . ~,d~
, , ... .
,., .. , ,, : , .. ~ . . , . , . ~ .~ . : , .
: .' ' ', . . ~: ' ' : ;. .
:,: - . '. , . ',, , ~ ~, ; :
- . : : , , . . . ,., . - : . - :: . : :
.. . ..
, .. .. : .. . ` : ~ ' ' ' ' ' .
45,939 .
Description of the Pri~r Art:
Prior art monitors for synchronous digital systems have typically utilized a memory of some type to store the bit patterns generated by the system being monitored. The monitor was synchronized with the system to be monitored such that the digital bit patterns stored in the memory were ~-sequentially read an~ compared to the bit patterns generated by the rnonitored system. These bit patterns are ldentical lf and only if the system being monitored is operating properlyO One disadvantage of these SySterQS from a stand-point of circuik complexity was the fact that each memory location required the storage of a number o~ bits equal to -the number of bits in the pattern to be monitored even `~
though the number o~ patterns to be rnonitored was relatively small, SUMMARY OF THE INVENTION
The disadvantages o~ prior art synchronous digital system monitors are substantially reduced by the monitor ~-which is the subject o~ this application. The flrst step in utilizing the disclosed monitor is to establish the bit patterns generated by the system being monitored during normal operation and the order in which these patterns occur. Each bit pattern is identi~ie~ by a number to estab-lish a sequence or numbers ranging from 1 to m. Numbers 1 through m are then store~ in a memory utilizlng the sequentiaI
blt patterns generated by the system being monltored during normal operation as addres~ses~ The process o~ determining the sequence o~ numbers 1 through m and storing these numbers in bhe memory is referred to as the initialization cycle.
As the system being monitored sequentially cycles ,.. , .. ,...... , , .,. ~. ., . , ,, , - . . . .
45,939 through its normal operating cycle the bit patterns gene-rated by the system are coupled to the memory as addresses causing the corresponding memory locations to be read. Each dlgital number read from the memory is checked to determine if it contains any logic "1" bits. Each time a memory location containing at least one logic "1" bit is read a counter is incremented one count, This causes the counter to sequentially cycle through numbers 1 to m as these num-bers are sequentially read from the memoryO
Each tlme the counter is incremented, the output of a counter is compared to the value ~ust read from the memor~O If they are identical the associated bit pattern is then known to be correct. If they are different, an error signal is generated indicating that the system being moni-tored has malfunctionedO Additionally, at the end o~ the - ~
synchronous cycle of the system being monitored the contents ~-o~ the counter are compared to a digital number to determine i~ the proper number o~ correct comparisons have been made.
. .
This provides a two level check wlth each of the bit pat- - -~
terns generate~ by the system ~eing monitored checked to determine if each pattern ls correct and that the correct number of bit patterns was generated. This provides a very ~-~
reliable check on the proper operation of the associated synchronous systems. Either o~ these comparisons can be inhibited by an external signal. Additionally, circuitry is provided ~or monitoring a specified number of analog slgnals.
The monitor also includes circuitry permitting the error signals generat~d by the m~nltor to be interrogated by a digital computer. This feature permits the monitor to be utilized to check lndividual synchronous digital systems
-3-~ . . . . . . . . . ..
45,939 . .
with a digital compuker interro~ating a plurality of monitors to determine the operational status o~ the associated sys- -tems~ This permits the operational status ~ a large number of digital systems to be conveniently determined at a central location.
If the application indicates thak some of the bit patterns generated by the system do not require monitoring, -these pakterns can be deleted from the monitoring sequence by storin~ a bit pattern consisting of all zeros in the memory location corresponding to this pattern and deletlng this pattern from the sequence of numbers 1 through m. -~
DESCRIPTION OF THE DRAWINGS ~ ~1 Figure 1 is a flow chart illustrating the initial-ization cycle of the monitor;
~ igure 2 is a ~low chart illustrating the test oycle o~ the monitor.
- ~ .
Figure 3 is a functional block diagram of the monitor. ; ~;
j DETAILED DESCRIPTION
Figure 1 is a ~low chart illustrating the initial- -ization cycle of the m~nltor. In initializing the monitor it is nece~sary to determine the number of bit patterns ~;
generated by the system to be monitored, the sequence in which the bit patterns are generated and select the patterns to be monitore~. It is not necessary, in general, to moni~
tor each and every bit pattern generated ~y a synchronous system in order to predlct the operational status o~ the systems because an error associated with one pattern will probably be re~lected in a later pattern.
The bit patterns to be monitored are utlllzed in .. : .
..
45,93g ~ ~7 ~
the sequence in which they are generated as addresses t-o store digital numbers l through m in a memory wikh m being a number equal to the number o~ bit pakterns to be monitoredO
Digital numbers consisting of all zero bits are stored in all other memory locatlons. ~it patterns can be added to or deleked from the list of patterns being monitored by reprogram-ming the memory. The above described steps for initializing the digital portion of the monitor ~ ~efined by the steps illustrated at reference numbers 9-13 of Figure l.-~
lQ The initialization o~ the analog portions of the monitor conslsts o~ determining the number of analog signals ~ ~ -to be monitored an~ setting the threshol~ levels of khe analog comparator~ This step is illustrated at reference ;
numeral 14, -After the monikor has been inltiallze~, lt is switche~ to the test cycle illustrated in Figure 20 The synchronous dlgltal system associated with the monitor is tested by sequentially reading khe store~ data words from the memory using the blt patterns generated by the synch-? ronous system as ad~resses. F-ollowing each r=ad cycle~ the dlgital word read ~rom the memory is checked to determine i~
the word contains at least one logic "one" bit, If the w~rd includes at least one loglc "one" blt, a counter is incre-mented one coun~O These steps are illustrat~d functionally at re~erence numerals 15 and 16~ The output of the counter is compared to the dlgltal word read from the memory. If the system being monltored ls operating properly the counter will sequentially cycle through numbers l through m as the -numbers l through m are sequentially read from the memory.
Thus there wlll always be a one to one correspondence _5,, 45,939 between the output o~ the counter and khe output of the memory. This correspondence indicates that the bit ~atterns being utilized as addresses are correct. On the other hand3 if the contents of the counter and the output of the memory are not identically equal, at least one bit pattern utilized as an address is wrong indicating that the system has mal-functioned~ Detection of a malfunction causes an error flip-flop to be set. The output signal of the error flip-flop is combined with an "inhiblt sequential test signal" to ~ -... . .
generate a "sequential error signal". The steps ~or sequen-tially performing the a~ove discussed steps are illustrated at re~erence numerals 15, 16, 173 18 and 19 of Flgure 1. ; ~ ;
The output of this counter is also continuously compared to an external number (digital signal) which speci-~ies the number of words containing at least one logic one bit to be read from the memory during each cycle o:~ the monitored system. The result of this comparison is combined :.
with an "inhiblt number o~ patterns test signal" to generate a "number of patterns error signal'1 which enables the setting o~ the system malfunction flip~flop if an error is ~etecte~.
These steps are illustrated functionally at reference nu-merals 20, 21 and 22 Simultaneously with the above descrlbed digital test, a selected number of analog slgnals are compared to - .
desired values ~or these signals and an "analog error signal"
is generated if either of these analog signals is not within prescribed limits. The functional step for performing the , . , .~, . . ..
analog comparison is illustrated at reference numeral 23.
If either of the above tests in~icates a mal-function at the end o~ the cycle of the monitored system, a . ' 45g939 system malfunction fllp-flop is set. This step ls illus-trate~ at reference numeral 22 o~ ~lgure ~, -A functl~nal block diagram of the system ~or per- ~;~
forming the test described above wlth re~erence to Flgures 1 an~ 2 is illustrated in Figure 3. The syskem includes a memory 30 which contains a number of storage locatlons at - -least equal to the number of individual bit patterns to be teste~. During the initialization cycle, the memory 30 -~
receives addresses and data to be stored in the memory from an external programming system (not shown). The signals coupled to the address inputs are a series of digital ~lt -~
patterns identical to the blt patterns generate~ by the system to be monitored when thls system is runctioning ;-properly. The data stored using the,se addresses is a se~uen-tial series of digital numbers ranging from 1 to m with m bein~ a digital number corresponding to the number of bit patterns to be monitoredO Storing o~ the numbers 1 to m in the memory 30 as descrlbed above and storing zeros in the remainder of the memory locations completes the inltiali-zation of the digital portion of the monltor. Detailed apparatus for prograrnming the memory is not shown because such apparatus ls well known ln the prior art.
During the test cycle the sequential bit patterns generated by the sys~em beinæ monitored are coupled to the memory 30 and utilized as addresses tG read data from the memory, Immediately ~ollowln~ the generativn of each o~ the bit patterns, a-read inltiate signal is coupled to the memory 30, This causes the d~ta stored in the memory locatlon corresp~nding to the address s~ecifie~ hy the bit pattern 3~ coupled to the address input to be read and coupled to a -r-. . ~ .
.
45,939 ~ ~'7 digital comparator circuit 31. The memory 30 has been previously programmed such that the normal or expected bit ~atterns generated by the systems being monitored and utilized as addresses by khe memory 30 will cause num~ers 1 through m to be sequentially read from the memory In addition to ~eing coupled to the input of the digital comparator 31 the data output of the read only memory ~ is coupled to a gate 32~ This gate generates a signal at its output anytime the -digital signal coupled to its input includes at least one logic "one" bit. Each of these stored words (having values ranging from 1 to m) contain at least one bit which is a logic "one" This causes the counter 33 to increment onè ~ ~
count each time one of the numbers, 1 through m, is read - -from ~he memory 30O The output ~f this gate is also couple~
to the dlgit~l comparator 31 to inhibit the comparison except during the tlme when the output of its gate is a logic one. This pre~ent-s the generation of incorrect compare ;
~signals during the transitions of the input signals to the c~mparator 31. The other input to the digital comparator 31 20 is the output of counter 33 Counter 33 is also reset by ~
the end of cycle slgnal ~rom the system being monit~red 'h~,,.~.. '''.,.. ' causing the counter to sequentially cycle through numbers l ~- -through m so long as the correct data is being read from the memory 30. Slnce the data read ~rom memory 30 sequentially cycIes through values l to m ~nly lf the a~dress in~uts are in the correct sequence, any difference between the ~ata read from the memory 30 and the output of the counter 33 indicates a system malfunction.
The output signal of the c~mparator 31 is coupled to an error flip-flop 54 through a gate 55. When the output -8~
' ' ' '"
45~939 ' signal of comparator 31 indlcates that the output of the memory 30 is not equal to the oukput of counter 33 this ~.
flip-flQp is set ko indicate that a mal~unctlon has been detected provided that the sequence comparison is not inhlbited by the "inhibit sequential test signal" coupled tc the second input of gate 55O The output of khis flip-~lop is coupled through gate 41 to enable the setting of the system .-malfunction ~lip--flop 42 on the leading edge of the end of cycle pulse.
A second number specl~ying the number o~ patterns to be ¢hecked is coupled to the input of a second comparator 40. The second input to this comparator is the number store~ in digltal counter 33~ At the end of the cycle o~
the system being monltored, the two lnputs to this comparator 40 will be identicaI i~ and ~nl~ if ~he proper number o~ :
comparisons have been made, I~ the proper number o~ compar-isons have not been made the output of this comparator 40 is .;~
low indicating that the system being monitored has malfunctioned ; based on the ~act that the proper number.of comparisons have 2~ not been ma~eO.
Analog comparator 56 receives as inputs a number of analog signals such as the power supply voltages of the system being monitored. I~ any of these voltages are not withln predetermined tolerances an "analog error signal" is generated indicating a mal~unction Speci~ically, the:;
monitor illustrated ln Figure 3 in¢ludes an analog comparator 56 for monit~rlng a plu8 5, minus 5, plus 12, minus 12, plus 30, minus 30 and minus 60 volt power supplies. I~ the output of any of these power supplies is not within prescribe~ . :
30 limits the output signal o~ analog comparator 56 is low . .:
_9_ . .
'' ~' ,', . ' . "" , " , , , , ,,, ,., , , . , . :
45g939 ~.~7~
indicating that one of the power supplies has malfunctioned~
The output of this comparator is combined in a gate 41 with the output signals of comparator 40, and the output signal of error ~lip-flop 54 to generate a composite malfunction signal. If this signal is high the mal~unctiQn flip~flop~
is set by ~he end of cycle pulse to a value indicating that an error has ~een detectedO If an error has not been detected the flip-flop will remain in a normal state, Additional flexibility is provided by circuitry 10 which permits the malfunction flip-~lop 42 to be interro- ~ -gated by an external system such as a digital computer. The clrcuitry permitting the computer to interrogate the monitor includes a serial to parallel converter 45. This clrcuit accepts a~serial address i~enti~ylng the individual monitors .~, . . .
via a ser'ial data bus ~rom the com~uter. Serial addressing 1s conkemplated as being the mosk useful because the lnter~
oonnection be~ween the computer and the monitor is simpler~ ~
- It is obvious that parallel addressin~ could also be utilized ~ ;
wlth a slight m~dification of the system. ~ -The serial to parallel converter 45 provides a ~-parallel address identlfying the associated monitor to a comparator circuit 47~ The other input to this comparator is a digital number identi~ying the associated monitor.
When these two inputs are identical a signal is gener ked `
whioh enables gate 50~ The output~o~ gate 50 and the outpuk of the malfunctlon flip-flop 42 are coupled as lnputs to gate 52~ If the monitor is not to be interrogated by the computer a logic one is coupled to a second input of gate 50 provlding a continuous enabIe ko gates 50 and 52 such thak ~ . .
the oukput of the mal~unction fllp-flop ~ ls always couple~
., .: " , ' ..',.. . .
... -. .. .. ...... . . .. . .. . . .
45, 939 ~6J7~S~I
to the outputO
The above apparatus can be constructed uslng well known digital and analog clrcuits and no aetalled circuit description of the system/believed to be requiredO
,.
~ "-~".
,.'' ~'' -.
': :'" -,.~,';. :' .: .'',' ':~ "
. . ,: . ,
45,939 . .
with a digital compuker interro~ating a plurality of monitors to determine the operational status o~ the associated sys- -tems~ This permits the operational status ~ a large number of digital systems to be conveniently determined at a central location.
If the application indicates thak some of the bit patterns generated by the system do not require monitoring, -these pakterns can be deleted from the monitoring sequence by storin~ a bit pattern consisting of all zeros in the memory location corresponding to this pattern and deletlng this pattern from the sequence of numbers 1 through m. -~
DESCRIPTION OF THE DRAWINGS ~ ~1 Figure 1 is a flow chart illustrating the initial-ization cycle of the monitor;
~ igure 2 is a ~low chart illustrating the test oycle o~ the monitor.
- ~ .
Figure 3 is a functional block diagram of the monitor. ; ~;
j DETAILED DESCRIPTION
Figure 1 is a ~low chart illustrating the initial- -ization cycle of the m~nltor. In initializing the monitor it is nece~sary to determine the number of bit patterns ~;
generated by the system to be monitored, the sequence in which the bit patterns are generated and select the patterns to be monitore~. It is not necessary, in general, to moni~
tor each and every bit pattern generated ~y a synchronous system in order to predlct the operational status o~ the systems because an error associated with one pattern will probably be re~lected in a later pattern.
The bit patterns to be monitored are utlllzed in .. : .
..
45,93g ~ ~7 ~
the sequence in which they are generated as addresses t-o store digital numbers l through m in a memory wikh m being a number equal to the number o~ bit pakterns to be monitoredO
Digital numbers consisting of all zero bits are stored in all other memory locatlons. ~it patterns can be added to or deleked from the list of patterns being monitored by reprogram-ming the memory. The above described steps for initializing the digital portion of the monitor ~ ~efined by the steps illustrated at reference numbers 9-13 of Figure l.-~
lQ The initialization o~ the analog portions of the monitor conslsts o~ determining the number of analog signals ~ ~ -to be monitored an~ setting the threshol~ levels of khe analog comparator~ This step is illustrated at reference ;
numeral 14, -After the monikor has been inltiallze~, lt is switche~ to the test cycle illustrated in Figure 20 The synchronous dlgltal system associated with the monitor is tested by sequentially reading khe store~ data words from the memory using the blt patterns generated by the synch-? ronous system as ad~resses. F-ollowing each r=ad cycle~ the dlgital word read ~rom the memory is checked to determine i~
the word contains at least one logic "one" bit, If the w~rd includes at least one loglc "one" blt, a counter is incre-mented one coun~O These steps are illustrat~d functionally at re~erence numerals 15 and 16~ The output of the counter is compared to the dlgltal word read from the memory. If the system being monltored ls operating properly the counter will sequentially cycle through numbers l through m as the -numbers l through m are sequentially read from the memory.
Thus there wlll always be a one to one correspondence _5,, 45,939 between the output o~ the counter and khe output of the memory. This correspondence indicates that the bit ~atterns being utilized as addresses are correct. On the other hand3 if the contents of the counter and the output of the memory are not identically equal, at least one bit pattern utilized as an address is wrong indicating that the system has mal-functioned~ Detection of a malfunction causes an error flip-flop to be set. The output signal of the error flip-flop is combined with an "inhiblt sequential test signal" to ~ -... . .
generate a "sequential error signal". The steps ~or sequen-tially performing the a~ove discussed steps are illustrated at re~erence numerals 15, 16, 173 18 and 19 of Flgure 1. ; ~ ;
The output of this counter is also continuously compared to an external number (digital signal) which speci-~ies the number of words containing at least one logic one bit to be read from the memory during each cycle o:~ the monitored system. The result of this comparison is combined :.
with an "inhiblt number o~ patterns test signal" to generate a "number of patterns error signal'1 which enables the setting o~ the system malfunction flip~flop if an error is ~etecte~.
These steps are illustrated functionally at reference nu-merals 20, 21 and 22 Simultaneously with the above descrlbed digital test, a selected number of analog slgnals are compared to - .
desired values ~or these signals and an "analog error signal"
is generated if either of these analog signals is not within prescribed limits. The functional step for performing the , . , .~, . . ..
analog comparison is illustrated at reference numeral 23.
If either of the above tests in~icates a mal-function at the end o~ the cycle of the monitored system, a . ' 45g939 system malfunction fllp-flop is set. This step ls illus-trate~ at reference numeral 22 o~ ~lgure ~, -A functl~nal block diagram of the system ~or per- ~;~
forming the test described above wlth re~erence to Flgures 1 an~ 2 is illustrated in Figure 3. The syskem includes a memory 30 which contains a number of storage locatlons at - -least equal to the number of individual bit patterns to be teste~. During the initialization cycle, the memory 30 -~
receives addresses and data to be stored in the memory from an external programming system (not shown). The signals coupled to the address inputs are a series of digital ~lt -~
patterns identical to the blt patterns generate~ by the system to be monitored when thls system is runctioning ;-properly. The data stored using the,se addresses is a se~uen-tial series of digital numbers ranging from 1 to m with m bein~ a digital number corresponding to the number of bit patterns to be monitoredO Storing o~ the numbers 1 to m in the memory 30 as descrlbed above and storing zeros in the remainder of the memory locations completes the inltiali-zation of the digital portion of the monltor. Detailed apparatus for prograrnming the memory is not shown because such apparatus ls well known ln the prior art.
During the test cycle the sequential bit patterns generated by the sys~em beinæ monitored are coupled to the memory 30 and utilized as addresses tG read data from the memory, Immediately ~ollowln~ the generativn of each o~ the bit patterns, a-read inltiate signal is coupled to the memory 30, This causes the d~ta stored in the memory locatlon corresp~nding to the address s~ecifie~ hy the bit pattern 3~ coupled to the address input to be read and coupled to a -r-. . ~ .
.
45,939 ~ ~'7 digital comparator circuit 31. The memory 30 has been previously programmed such that the normal or expected bit ~atterns generated by the systems being monitored and utilized as addresses by khe memory 30 will cause num~ers 1 through m to be sequentially read from the memory In addition to ~eing coupled to the input of the digital comparator 31 the data output of the read only memory ~ is coupled to a gate 32~ This gate generates a signal at its output anytime the -digital signal coupled to its input includes at least one logic "one" bit. Each of these stored words (having values ranging from 1 to m) contain at least one bit which is a logic "one" This causes the counter 33 to increment onè ~ ~
count each time one of the numbers, 1 through m, is read - -from ~he memory 30O The output ~f this gate is also couple~
to the dlgit~l comparator 31 to inhibit the comparison except during the tlme when the output of its gate is a logic one. This pre~ent-s the generation of incorrect compare ;
~signals during the transitions of the input signals to the c~mparator 31. The other input to the digital comparator 31 20 is the output of counter 33 Counter 33 is also reset by ~
the end of cycle slgnal ~rom the system being monit~red 'h~,,.~.. '''.,.. ' causing the counter to sequentially cycle through numbers l ~- -through m so long as the correct data is being read from the memory 30. Slnce the data read ~rom memory 30 sequentially cycIes through values l to m ~nly lf the a~dress in~uts are in the correct sequence, any difference between the ~ata read from the memory 30 and the output of the counter 33 indicates a system malfunction.
The output signal of the c~mparator 31 is coupled to an error flip-flop 54 through a gate 55. When the output -8~
' ' ' '"
45~939 ' signal of comparator 31 indlcates that the output of the memory 30 is not equal to the oukput of counter 33 this ~.
flip-flQp is set ko indicate that a mal~unctlon has been detected provided that the sequence comparison is not inhlbited by the "inhibit sequential test signal" coupled tc the second input of gate 55O The output of khis flip-~lop is coupled through gate 41 to enable the setting of the system .-malfunction ~lip--flop 42 on the leading edge of the end of cycle pulse.
A second number specl~ying the number o~ patterns to be ¢hecked is coupled to the input of a second comparator 40. The second input to this comparator is the number store~ in digltal counter 33~ At the end of the cycle o~
the system being monltored, the two lnputs to this comparator 40 will be identicaI i~ and ~nl~ if ~he proper number o~ :
comparisons have been made, I~ the proper number o~ compar-isons have not been made the output of this comparator 40 is .;~
low indicating that the system being monitored has malfunctioned ; based on the ~act that the proper number.of comparisons have 2~ not been ma~eO.
Analog comparator 56 receives as inputs a number of analog signals such as the power supply voltages of the system being monitored. I~ any of these voltages are not withln predetermined tolerances an "analog error signal" is generated indicating a mal~unction Speci~ically, the:;
monitor illustrated ln Figure 3 in¢ludes an analog comparator 56 for monit~rlng a plu8 5, minus 5, plus 12, minus 12, plus 30, minus 30 and minus 60 volt power supplies. I~ the output of any of these power supplies is not within prescribe~ . :
30 limits the output signal o~ analog comparator 56 is low . .:
_9_ . .
'' ~' ,', . ' . "" , " , , , , ,,, ,., , , . , . :
45g939 ~.~7~
indicating that one of the power supplies has malfunctioned~
The output of this comparator is combined in a gate 41 with the output signals of comparator 40, and the output signal of error ~lip-flop 54 to generate a composite malfunction signal. If this signal is high the mal~unctiQn flip~flop~
is set by ~he end of cycle pulse to a value indicating that an error has ~een detectedO If an error has not been detected the flip-flop will remain in a normal state, Additional flexibility is provided by circuitry 10 which permits the malfunction flip-~lop 42 to be interro- ~ -gated by an external system such as a digital computer. The clrcuitry permitting the computer to interrogate the monitor includes a serial to parallel converter 45. This clrcuit accepts a~serial address i~enti~ylng the individual monitors .~, . . .
via a ser'ial data bus ~rom the com~uter. Serial addressing 1s conkemplated as being the mosk useful because the lnter~
oonnection be~ween the computer and the monitor is simpler~ ~
- It is obvious that parallel addressin~ could also be utilized ~ ;
wlth a slight m~dification of the system. ~ -The serial to parallel converter 45 provides a ~-parallel address identlfying the associated monitor to a comparator circuit 47~ The other input to this comparator is a digital number identi~ying the associated monitor.
When these two inputs are identical a signal is gener ked `
whioh enables gate 50~ The output~o~ gate 50 and the outpuk of the malfunctlon flip-flop 42 are coupled as lnputs to gate 52~ If the monitor is not to be interrogated by the computer a logic one is coupled to a second input of gate 50 provlding a continuous enabIe ko gates 50 and 52 such thak ~ . .
the oukput of the mal~unction fllp-flop ~ ls always couple~
., .: " , ' ..',.. . .
... -. .. .. ...... . . .. . .. . . .
45, 939 ~6J7~S~I
to the outputO
The above apparatus can be constructed uslng well known digital and analog clrcuits and no aetalled circuit description of the system/believed to be requiredO
,.
~ "-~".
,.'' ~'' -.
': :'" -,.~,';. :' .: .'',' ':~ "
. . ,: . ,
Claims (7)
1. Apparatus for monitoring the operation of a synchronous digital system to detect malfunctions thereof, comprising in combination:
a) memory means having stored therein at first predetermined storage locations a first predetermined group of digital numbers comprising a sequence of numbers comprising a sequence of numbers ranging in value from 1 to m with each storage location being identified by a digital number having a bit pattern corresponding to a bit pattern generated by said synchronous system when said system is operating normally and stored therein at the remaining memory locations a second predetermined group of digital numbers, said first and second predetermined groups of digital numbers being mutually exclusive;
b) read means for sequentially reading digital numbers from said memory means utilizing a series of digital bit patterns generated by the system being monitored as addresses;
c) a digital counter and means for incrementing said digital counter one count each time a digital number containing at least one logic "one" bit is read from said memory means to generate and store in said digital counter a number corresponding to the number of words containing at least one logic "one" bit which are read from said memory means; and d) first compare means for comparing said digital numbers from said memory means to the number stored in said digital counter to generate a first error signal when the data output of said memory means and said number stored in said digital counter are not identical.
a) memory means having stored therein at first predetermined storage locations a first predetermined group of digital numbers comprising a sequence of numbers comprising a sequence of numbers ranging in value from 1 to m with each storage location being identified by a digital number having a bit pattern corresponding to a bit pattern generated by said synchronous system when said system is operating normally and stored therein at the remaining memory locations a second predetermined group of digital numbers, said first and second predetermined groups of digital numbers being mutually exclusive;
b) read means for sequentially reading digital numbers from said memory means utilizing a series of digital bit patterns generated by the system being monitored as addresses;
c) a digital counter and means for incrementing said digital counter one count each time a digital number containing at least one logic "one" bit is read from said memory means to generate and store in said digital counter a number corresponding to the number of words containing at least one logic "one" bit which are read from said memory means; and d) first compare means for comparing said digital numbers from said memory means to the number stored in said digital counter to generate a first error signal when the data output of said memory means and said number stored in said digital counter are not identical.
2. Apparatus for monitoring a synchronous digital system in accordance with Claim 1 further including:
a) a second compare means responsive to an external signal and said number stored in said counter to generate a second error signal if the expected number of digital words containing at least one logic "one" bit are not read from said memory means during each cycle of said synchronous digital system as indicated by said number stored in said counter.
a) a second compare means responsive to an external signal and said number stored in said counter to generate a second error signal if the expected number of digital words containing at least one logic "one" bit are not read from said memory means during each cycle of said synchronous digital system as indicated by said number stored in said counter.
3. Apparatus for monitoring a synchronous digital system in accordance with claim 2 further including means for combining said first and second error signals to produce a composite malfunction signal.
4. Apparatus for monitoring the operation of a synchronous digital system in accordance with claim 2 fur-ther including means for selectively inhibiting said second error signal.
5. Apparatus for monitoring a synchronous digital system in accordance with claim 4 further including means for setting a malfunction flip-flop in response to said composite malfunction signal.
6. Apparatus for monitoring a synchronous digital system in accordance with claim 5 further including decoding means responsive to an external digital signal to produce an output signal indicative of the status of said malfunction flip-flop.
7. Apparatus for monitoring a digital system in accordance with claim 5 further including means for monitoring a selected number of analog signals to generate an analog error signal if any of said analog signals are not within prescribed limits and for combining said first and second error signals with said analog error signal to generate a composite error signal.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US05/691,177 US4084262A (en) | 1976-05-28 | 1976-05-28 | Digital monitor having memory readout by the monitored system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1074450A true CA1074450A (en) | 1980-03-25 |
Family
ID=24775462
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA276,578A Expired CA1074450A (en) | 1976-05-28 | 1977-04-20 | Digital monitor |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US4084262A (en) |
| JP (1) | JPS52146140A (en) |
| BE (1) | BE855151A (en) |
| CA (1) | CA1074450A (en) |
| DE (1) | DE2723714A1 (en) |
| DK (1) | DK234177A (en) |
| GB (1) | GB1527486A (en) |
| NL (1) | NL7705245A (en) |
| NO (1) | NO771586L (en) |
Families Citing this family (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2715983C2 (en) * | 1977-04-09 | 1983-12-29 | Ibm Deutschland Gmbh, 7000 Stuttgart | Circuit arrangement in a digital computer for monitoring and checking the proper operation of the digital computer |
| US4159531A (en) * | 1977-11-21 | 1979-06-26 | Mcgrath Joseph G | Programmable read-only memory system for indicating service maintenance points for motor vehicles |
| USRE31407E (en) * | 1978-05-10 | 1983-10-04 | Tesdata Systems Corporation | Computer monitoring system |
| US4166290A (en) * | 1978-05-10 | 1979-08-28 | Tesdata Systems Corporation | Computer monitoring system |
| DE2833761C3 (en) * | 1978-08-01 | 1981-12-03 | Siemens AG, 1000 Berlin und 8000 München | Circuit arrangement for monitoring the status of signal systems, in particular road traffic light signal systems |
| US4313200A (en) * | 1978-08-28 | 1982-01-26 | Takeda Riken Kogyo Kabushikikaisha | Logic test system permitting test pattern changes without dummy cycles |
| DE2913402A1 (en) * | 1979-04-04 | 1980-10-09 | Tekade Felten & Guilleaume | DEVICE FOR REMOTE MONITORING AND SIGNALING OF STATE CHANGES OF CYCLICALLY INQUIRED CHARACTERISTIC FREQUENCY MONITORING TRANSMITTERS |
| US4320881A (en) * | 1980-10-03 | 1982-03-23 | American Standard Inc. | Fail-safe decoder for digital track circuits |
| JPS5775335A (en) * | 1980-10-27 | 1982-05-11 | Hitachi Ltd | Data processor |
| US4751673A (en) * | 1982-03-22 | 1988-06-14 | The Babcock & Wilcox Company | System for direct comparison and selective transmission of a plurality of discrete incoming data |
| JPS58201154A (en) * | 1982-05-19 | 1983-11-22 | Nissan Motor Co Ltd | Mode monitoring device of microcomputer |
| JPH0619666B2 (en) * | 1983-06-30 | 1994-03-16 | 富士通株式会社 | Failure diagnosis processing method |
| US4728883A (en) * | 1985-03-15 | 1988-03-01 | Tektronix, Inc. | Method of testing electronic circuits |
| USRE33461E (en) * | 1985-10-16 | 1990-11-27 | Unisys Corporation | Generation and diagnostic verification of complex timing cycles |
| US4726025A (en) * | 1985-10-16 | 1988-02-16 | Sperry Corporation | Generation and diagnostic verification of complex timing cycles |
| US5844510A (en) * | 1996-01-26 | 1998-12-01 | Ora Electronics, Inc. | System and method for extracting a data signal encoded onto first and second binary signals |
| US6108637A (en) * | 1996-09-03 | 2000-08-22 | Nielsen Media Research, Inc. | Content display monitor |
| JP2000013414A (en) * | 1998-06-25 | 2000-01-14 | Fujitsu Ltd | Intra-device supervisory and control system |
| US6927682B1 (en) | 2002-12-21 | 2005-08-09 | Jeff Touhey | Digital vehicle service indicator |
| US7246289B2 (en) * | 2003-09-30 | 2007-07-17 | Nortel Networks Limited | Memory integrity self checking in VT/TU cross-connect |
| JP4464454B1 (en) * | 2008-11-27 | 2010-05-19 | Ｎｅｃエレクトロニクス株式会社 | Semiconductor device and verify method in semiconductor device |
| CN111830452B (en) * | 2020-07-22 | 2023-05-23 | 云南电网有限责任公司电力科学研究院 | Method and simulation equipment for verifying reliability of double-end ranging positioning formula |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3286239A (en) * | 1962-11-30 | 1966-11-15 | Burroughs Corp | Automatic interrupt system for a data processor |
| US3518413A (en) * | 1968-03-21 | 1970-06-30 | Honeywell Inc | Apparatus for checking the sequencing of a data processing system |
| US3599146A (en) * | 1968-04-19 | 1971-08-10 | Rca Corp | Memory addressing failure detection |
| US3579199A (en) * | 1969-02-03 | 1971-05-18 | Gen Motors Corp | Method and apparatus for fault testing a digital computer memory |
| US3838264A (en) * | 1970-11-25 | 1974-09-24 | P Maker | Apparatus for, and method of, checking the contents of a computer store |
| US3700870A (en) * | 1971-04-09 | 1972-10-24 | Honeywell Inf Systems | Error control arrangement for associative information storage and retrieval |
| US3745316A (en) * | 1971-12-13 | 1973-07-10 | Elliott Bros | Computer checking system |
| FR2257213A5 (en) * | 1973-12-04 | 1975-08-01 | Cii | |
| US3919533A (en) * | 1974-11-08 | 1975-11-11 | Westinghouse Electric Corp | Electrical fault indicator |
| US3963908A (en) * | 1975-02-24 | 1976-06-15 | North Electric Company | Encoding scheme for failure detection in random access memories |
-
1976
- 1976-05-28 US US05/691,177 patent/US4084262A/en not_active Expired - Lifetime
-
1977
- 1977-04-20 CA CA276,578A patent/CA1074450A/en not_active Expired
- 1977-05-05 NO NO771586A patent/NO771586L/en unknown
- 1977-05-10 GB GB19516/77A patent/GB1527486A/en not_active Expired
- 1977-05-12 NL NL7705245A patent/NL7705245A/en not_active Application Discontinuation
- 1977-05-25 JP JP5998677A patent/JPS52146140A/en active Pending
- 1977-05-26 DE DE19772723714 patent/DE2723714A1/en not_active Withdrawn
- 1977-05-27 BE BE178004A patent/BE855151A/en unknown
- 1977-05-27 DK DK234177A patent/DK234177A/en not_active Application Discontinuation
Also Published As
| Publication number | Publication date |
|---|---|
| NL7705245A (en) | 1977-11-30 |
| BE855151A (en) | 1977-11-28 |
| DE2723714A1 (en) | 1977-12-08 |
| NO771586L (en) | 1977-11-29 |
| US4084262A (en) | 1978-04-11 |
| JPS52146140A (en) | 1977-12-05 |
| GB1527486A (en) | 1978-10-04 |
| DK234177A (en) | 1977-11-29 |
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