CA1085057A

CA1085057A - Method of transmitting digital signals

Info

Publication number: CA1085057A
Application number: CA292,740A
Authority: CA
Inventors: Toshitada Doi; Shinichi Kazami
Original assignee: Sony Corp
Current assignee: Sony Corp
Priority date: 1976-12-24
Filing date: 1977-12-09
Publication date: 1980-09-02
Also published as: GB1579199A; AT381428B; ATA929277A; FR2375769A1; US4206440A; FR2375769B1; NL190133B; DE2757401C2; DE2757401A1; JPS5380105A; NL7714283A; NL190133C; IT1090969B; AU3163077A; AU514602B2

Abstract

ABSTRACT OF THE DISCLOSURE

Digital signals consisting of sets of simultaneous bits have an error-correcting signal encoded into them by adding an error-correcting bit to each set. The sets thus enlarged are referred to as digital words. The digital signals are then converted from simultaneous, or parallel, form to serial, or sequential, form and the digital words from a block of several digital signals at a time are interleaved in such a way that corresponding words from each of the digital signals in the same block are placed in immediate sequence. Prior to adding the error-correcting bits error-detecting bits can be added to the original bits in inter-secting sets that intersect the first-mentioned sets, in row column relationships and parity bits can also be formed simultaneously with the formation of the error-correcting bits as extensions of the intersecting sets. In decoding the resulting signals changes in the bits forming one word of each digital signal can be directly corrected, and additional errors can be detected and minimized by forming mean value signals of digital signals that immediately precede and follow the erroneous digital signal or by retaining the preceding digital signal until the succeeding signals return to correct or correctable form.

Description

L~ présente invention concerne un appareil destiné à
mesurer la circonférence d'un objet de section cylindrique ou sensiblement ou de toute autre section, l'appareil trouvant une application particulière à la mesure de la circonférence des troncs d'arbres, tuyaux ou similaires.
L'objet de l'invention se rattache au secteur technique ' des appareils de mesure.
Il est bien connu que pour déterminer le cubage des troncs d'arbres, on mesure la longueur de ceux-ci et leur circon~érence. ~
Le métreur prend la circon~érence de l'arbre à l'aide d'un mètre -par exemple et rencontre souvent de notables difficultés pour e~fectuer une bonne mesure. Il doit d'autre part se baisser pour les ef~ectuer, ce qui est particulièrement harassant lorsque -`
plusieurs centaines de mesures sont ~aites dans une journee. Le problème était de pouvoir prendre correctement la circon~erence de l'arbre sans ef~ectuer des gestes pénibles.
Selon l'invention, on remédie à ces inconvénients en réalisant un appareil comprenant deux branches articulées formant d'un côté bras de préhension et de serrage, et du côté opposé, deux parties courbées opposées et join-tives.
Selon une autre caractéristique de l'invention, un câble gradué ou similaire est ~ixé sur l'une des branches et est guidé
par coulissement dans la branche opposée. L'ouverture des branche~ autorise de par leur partie courb~e le pasl~age diamètral de la section à mesurer de l'arbre à l'encontre du cable ou similaire qui es-t sollicité en traction et enserre la périphérie dc la ~ection lor~ de la ~ermeture des branches provoquant ainsi de par son brin libre un déplacement linéaire correspondant du câble ou similaire.
Selon une autre caractéristique de l'inven-tion, le câble permet directement ou d'une manière rapportée de lire au travers d'une ouver-ture avec repère établi sur le bras de préhension :
corre~pondan-t, la mesure de la circonférence de l'arbre. ;-D'autres caractéristiques encore, ressortiront de la description qui suit. ~`
Pour bien fixer l'object de l'invention, sans toutefois le limiter dans les dessins annexés:
;

La figure 1 est une vue de face en coupe de l'appareil. ~ ;
- La figure 2 est une vue de coté selon la figure 1 de l'appareil.
La figure 3 est une vue schématique de l'appareil en fonctionnement, la mesure d'un tronc d'arbre de grand diamètre étant e~fectuée.
La figure 1~ est une vue schemétique de l'appareil en ` ~onctionnement, la mesure d'un tronc d'arbre de petit diamètre étant e~fectuée.
I,a figure 5 est une vue en coupe selon la coupe A-A.
La ~igure 6 est une vue en coupe selon B-B.
Afin de rendre plus concret l'object de l'invention, on le décrit maintenant d'une manière non limitative en se réfèrant aux exemples illustrés par les figures du dessin.
On voit ainsi à la ~igure 1 l'appareil de mesure A objet de l'invention. Il comprend deux branches 1 et 2 articulées, ~`
l'une par rapport ~ l'autre, ~ormant d'un coté bras de préhension et de serrage 11 et 21, et du coté opposé deux part.ies courbées 12 et 2Z~ opposées et jointives de par leurs extrémités.
Un cable C gradu~, ou ~imilaire est ~ixé sur l'une des branches 1 à sa partie supérieure 13 et est guidé par coulissement dans la branche opposée 2. L'ouverture des branches autorise de par leurs parties courbées 12 et 22, le passage diametral de la section à mesurer de l'arbre T, à l'encontre du câble C ou similaire qui est sollicité en traction et enserre la périphérie de la section de l'arbre lors de la ~ermeture des branches. Le mouvement d'ouverture des branches provoque un déplacement .

5~i7 linéaire du câble ou similaire correspondant à la circonférence du tronc d'arbre. Lors de la ~ermeture jusqu'en position de , butée des branches le cable enserre la périphérie du tronc d'ar~re. Ce cable C permet directement ou d'une manière rapportée de lire au kravers d'une ou~erture avec repère R
établi sur le bras de préhension correspondant 21. On peut -prévoir selon un mode de réalisation de l'appareil que le câble ou similaire est accouplé en bout à l'extrémité d'un -mètre à ruban 3, dont le bo1tier 31 est rixé sur 17extrémité ~, du bras de préhension 21 correspondant, par tout moyen connu tel ~ue pattes rapportées, etc. Le talon 32 du mètre présente une ou~er-ture 39 de passage du cable ou similaire. Le cable C présente à son extrémité Cl un moyeu d'arret 4 venant en butée contre le talon. Egalement l'extrémité supéreure de la bande d'accrochage 19 présente une patte 5 repliée intérieurement dans laquelle est réalisée une ouverture 51 pour le passage du cable ou sim;laire. L'extrémité C2 du cable est également reliée à un autre moyen d'arret 6 venant en butée contre la `
patte repl;ée. Ces moyens d'arret 4 et 6 sont réalisés de toute fa~on connue et peuvent etre par exemple de simples axes.
L'axe d'articulation 7 des branches 1 et 2 est sensiblement décalé par rapport au point de contact des extrém;tés s'upérieures 13 et 23 des dite9 branches. Les rayons de courbure des parties courb~es sont sen~iblemenk di~ferents. L'une des branche~ 1 ;, possède des moyens d'accrochage, par exemple des griffes 8 rapportées ou profilées direc-tement et ont pour but d'accrocher ek de maintenir en prise le tronc d'arbre pour faciliter le passage de l'autre branche. ~ien entendu les griffes existent sur tout ou partie de la partie recourbée de la branche. La branche de comrnande de l'appareil est de sec-tion creuse et permet le positionnement du cable, ruban, ou similaire. Ce cable peut etre de toute forme, de,toute nature, de toute section .
.

i7 et coopère avec un mètre enrouleur 3. Des axes de guidage 9 sont disposés transversalement dans le bras de commande, le câble étant alors positionn~ entre les dits axes de guidage et la partie intérieure arrière de la branche. Ces dispositions permettent de maintenir en position le mètre dans son logement. ;~
Un ressort à boudin 10 peut être rapporté et positionné dans la branche de commande. Il vient en butée contre d'une part -le talon du mètre ou l'extrémité du câble, tandis que son autre extrémité bute contre un moyen d'arrêt 11 positionné et fixé
de toute ~açon connue par exemple par rivetage dans la branche sensiblement au niveau du début de la partie recourbée. L'action de rappel du ressort se combine avec l'action de rappel provenant du mètre enrouleur lorsque le câble après chaque mesure revient `
dans sa position initiale. La lec-ture de la mesure est obtenue en disposant sur une des faces du bras de commande une ou~erture permettant de voir le positionnement du mètre. Un repère est établi et ~ixé par tout procédé connu, soudure, collage ou similaire. Une gaine transparente ou similaire peut etre ~ixée sur l'ouverture ou sur tout ou partie de la branche de commande, par tout moyen connu tel gue collage.
Un moyen élastique 12, représenté en traits interrompus aux figures 3 et 1~ du dessin peut etre adjoint et etre dispos~
d'une part sur la partie de câble ~ormant boucle et d'autre part, sur l'axe d'articulation. Cette disposition as~ure le guidage en trois points du cable et dans le plan des branches.
Selon une autre forme de réalisation on peut prévoir ~ue le dispositi~ de mesure est con~u en un seul élément, le câble ou similalre pouvant etre gradué et enroulé à son ;
extrémité à la manière d'un mètre enrouleur pres du bras de commande, le ressort 10 assurant toujours le rappel.
Selon une autre forme de réalisation, l'appareil comprend deux branches articulées et profilees à la manière décrite , .,., . ., ~ . . . . . . .

1~ !35~7 précéde~ment. La mesure est e~fectuée en disposan-t sur l'une ;~ ~.
des branches un secteur gradué, fixé de toute fac~on connue sur ::
la branche, tandis que sur l'autre branche on positionne Judicieusemen-t un repère coopèrant avec le secteur suivant ..
l'ouverture donnée aux branches de l'appareil pour encercler le tronc d'arbre. Cette disposition n'est pas illustrée sur le dessin. :`
On peut également prévoir à titre d'accessoire de disposer une petite tablette sur l'un des bras de préhension. Celle-ci pouvant être montée pivotante sur un bras afin que lorsque ~. .
l'appareil est en fonctionnement elle soit placée parallèlement .....
:.... :: .:
à l'axe du bras de préhension, pour ne pas gener le métreur, . .
en position de non fonctionnement le métreur peut la disposer ~ .
; pour lui permettre d'écrire.
Il est bien évident que les bras de préhension peuvent a~oir une forme quelconque et être relevés par exemple. Il est bien évident que la commande de rappel du cable et du mètre peut etre :
manuelle, par tout moyen approprié, tel que manivelle par exemple ou autres.
: 20 Il est bien entendu que cet appareil à mesurer la circonférence d'un objet peut trouver de multiples applications, autres que celles précédemment mentionnées. Il peut par exemple .
permettre de mesurer la circonférence de tou-t objet de tou-te , .
section cylindrique ou sensiblement tel que des tu~aux, des bar.res, des objets d~ sect~ons poly~onales ou autres. I1 suffira d'adapter aux objets à mesurer la forme courbée des branches pour qu'elles puissent bien enserrer l'objet, les dispositions concernant le câble ou similaire restant les memes.
Les advantages ressortent b;en de la description qui précède, et en particulier on souligne la facilité accrue pour mesurer la circon~érence du tronc d'arbre au moyen d'un appareiL simple, coûteux et qui évite une fatigue importante de .
''' ' . ' ~ .' ' . . , ' ' ' ' . ' 5~

celui qui doit prendre les mesures et la simplicité de fonctionnement de l'appareil. ~ :
L'invention ne se limite aucunement à celui de ses modes d'application non plUS qu'à ceux des modes de réalisation de ses diverses parties ayant plus specialement été indiqués; :~
elle en embrasse au contraire toutes les variantes.

' :.' : , . '' :
, .: '' .

our tiers within the encoder 5. The first tier includes exclusive-OR gates 5-49 through 5-68, the second tier includes gates 5-69 through 5-80, the third, tier gates 5-81 through 5-90, and the fourth tier, gates 5-91 and 5-93. The circuit has ten output terminals 5-93 through 5-102.
Input terminals 5-29 through 5-48 are arranged in four ; 2a groups connected to four similar sets of exclusive-OR gates, each set including four exclusive-OR gates connected in the same way. For example, the bit signals r4, r8, rl2, rl6, and ; r20 of the column vector Bl in Fig. 2C are applied to the input terminals 5-29 through 5-33, respectively. The terminals 5-29 and 5-30 are the input terminals for the exclusive-OR gate 5-61 and the terminals 5-31 and 5-32 are the input terminals for the exclusi~e-OR gate 5-62. The outputs of the gates 5-61 and 5-62 are connected to the two input terminals of the exclusive-OR
gate 5-77, the output of which is connected to one input 3a terminal of the exclusive-OR gate 5-86, the other input terminal of which is directly connected to the input terminal 5-33.

-19a~

.

lO~SOS7 The sub~circuit just defined adds, on a modulo 2 basis, th~! "O" or "l" signals r4~ E8- ~12' rl6' and r2Q P
at the output terminal 5-~g the output bit signal b that is the parity checking bit of the vector Bl in Fig. 2C. If the ; number of "l" signals applied to the group of terminals 5-2~
through 5-33 is even, ~ = 0, but if the number is odd, b = 1.
The ORC encoder 5 produces the parity bits c through e ; at the terminals 5-100 through 5-102, respectively, in the same way that the bit signal b is produced at the terminal 5-99. In addition, the ORC encoder 5 produces ORC signals A through E by modulo 2 addition of the bit signals rl through r20 and produces the parity check bit a to correspond to the number of "1" signals in the signals A through E.
In the past, the ORC signals have been recorded so that there are six rows Z0 to Z5 formed in parallel tracks on magnetic tape by six stationary transducers. Here, the following expressions are given for the column vectors Bo to B4-Bo = (A, B, C, D, E)' Bl = ~r4, r8, rl2~ rl6' 20 B2 = ~r3~ r7, rll~ rls~ rlg~ (2) B3 = (r2, r6, rl0, rl4, 18 B4 = (rl, rs, rg, rl3~ 17 where the primes mean the transposed matrix.
The column vectors Bl to B4 are composed of information bits, whereas the column vector Bo is defined as follows:

Bo = TBl + T B2 + T B3 + T B4 (3 where T is defined by the following matrix, 108505~7 Q a a o a o o o a l a o ~4) T = a o 1 a o o o a 1 o With T2, T3 and T4 being previously determined, the respective bits of the column vector Bo can be obtained by the parallel processing of the following expressions in the circuit of Fig.
4:
A = r5 + r10 + rl5 + rl7 20 B = r4 + r9 + rl4 + rlg C = r + r + r8 + r10 + rl3 + rl5 + rl7 18 20

2 r7 + r9 + rl2 + rl4 + rl7 + rlg 5) E = rl + r6 + rll + rl3 + rl6 18 The five bits (a to e) of the sixth row Z5 are even parity bits for column vectors Bo to B4.
That is, a = A + B + C + D + E
b = r4 + r8 + rl2 + rl6 + 20 c = r3 + r7 + rll + rl5 19 ~ (6) d = r2 + r6 + r10 + rl4 + rl8 e = rl + r5 + r9 + rl3 + rl7 The parallel-series converter 6 is supplied simultaneously with all of the information bits (rl to rl61 from A-D converter

3~ the CRC code (rl7 to r2~ from CRC encoder 4 and the ten bits (A to E~ and (a to el from the CRC encoder 5, thereby producing simultaneously a 30-hit series code (hereinafter referred to ; as one blockl in the order of Z0~ Zl~ Z2 ~ Z5 as illustrated in Fig. 2C.

lV850S7 The 30-bit block is con~rerted by the parallel-to--series converter 6 from paralleI form l~nto the serial form shown in Fi~. 2D, one row at a time. Each row consists of Information bits of adjacent order and the ORC code bît associated with that order. Thus, tfie least significant bits are in one row of the array in Fig. 2C, the next four in the next row, and so on to the final row that has the four most significant bits.
The interleaving circuit 7, one embodiment of which is shown in Figs. 6 and 7, and which accomplishes an essential 10 aspect of this invention, will now be described in conjunction with Figs. 5, 8, and 9.
Fig. 5A shows the serial code of 35H length with the rows Z0 to Z5 supplied as a unit from the parallel-series converter 6. This code is composed of 210 blocks Kl, K2...
..K210 in the period of 35H, and hence there exists a code of 1260 rows containing a total of 6300 bits. In the interleave circuit 7, the first rows Z0 of five bits are extracted from each of the respective blocks Kl to K210 and arranged in the block order as indicated by solid lines in Fig. 5B. Next, 20 the second rows Zl are selected from each of the respective blocks Kl to K210 and arranged in the block order as shown by broken lines in Fig. 5B. Similarly, the following third to sixth rows Z2 to Z5 are respectively chosen from each of the blocks Kl to K210 and arranged in the block order. Therefore, the output of the interleave circuit 7, as illustrated in Fig.
5B, includes six groups of tracks Z0 to Z5 in order each group consisting of 210 tracks extracted from each of the blocks Kl to K210. This grouping places bits of like order from 210 successïve samplings in the sample~and-hold circuit 2 in Fig. 1 30 so that they are adjacent in time and will be recorded in adjacent :.............. . .

track increments on the tape in the yTR 9.
S~nce the ;nte~lea~î`ng is completed within a period of 35~[ as described previously, a memory capacity CM required for the interleaving i`s given by-CM - 3 x 6Q x 35 2 6300 bits = 6.3 K bits For reducing the time base of a PCM signal, in addition to effecting interleaving thereof, it is necessary to provide a memory capacity of at least 3 ~. Further, in order to eliminate time base variations due to the jitter, drift or the like upon reproduction, it is desirable to select a memory capacity of 4 CM. That is, four RAMs I, II, III and IV
each having a capacity of CM~ as illustrated in Fig. 6, are employed. The four RAMs are controlled so that when any one of them is carrying out a write operation, another RAM can carry out a read operation. In addition, by making the frequency of a read clock pulse higher than that of a write clock pulse, a predetermined data-lacking period is formed, and by controlling the addresses in which information is written, or stored, and from which it is read, or retrieved, the interleaving is carried out.
Fig. 6 shows one example of the memory device 7.
Each of the RAMs I to IV is a static RAM of 8K bits and has a data input terminal, a data output terminal, a terminal R/W
to which write and read control signals are applied, a terminal ADRS to which an address signal is applied, and a terminal CS
to which is applied a RAM selecting signal for selecting one of RAMs I to IV. Address selectors 31 through 34 are provided for the RAMs I to IV, respectively. Either of the write-address or the read-address signals of 13 bits in parallel is 3Q selected in the address selectors by a write-control and read-' ~ossosq control s,ignal from a ~ite-control and read-control circuit 35, and deli.vere.d to th.e ter,m.;nal ADRS of the respecti`~e RAMs. The write-address s;gnal is the combination of a bit address signal of 5 bi`ts in parallel (since one word is composed of 30 bits and a 5-bit signal is the minïmum required to provide at least 30 addresses~ and a word-addres-s signal of 8 bits in parallel (since the interleaving is completed through 210 words Kl to K210 which. require at least 8 bits~.
A write-bit address counter 36W is provided for generating the bit-address s;gnal, and a write-word address counter 37W is ' -provided for generating the word-address signal. A write clock . . .
pulse generator 38 forms a word clock pulse and a bit clock pulse having a period of 310 of the former repetition period by the application of the clock pulse from a clock generator 39. The bit clock pulse is applied to the write bit address counter 36W, and the word clock pulse to the write word address counter 37W. That is, the write bit address counter 36W to be supplied with the bit clock pulse progresses one step every 30 counts, while the write word address counter 37W to be supplied with the word clock pulse having a frequency of 30 that of the bit clock pulse is adapted to progress one step every 210 counts. A carry from the write word address counter 37W is fed to a RAM selector 40, which then delivers a RAM-selecting signal to the terminal CS of the respective RAMs. Therefore, when the PCM signal of 210 words (each word being composed of 30 bits~ is written in RAM I, for example, the write address counter 37W produces a carry, by which the next PCM signal is written in RAM II. At the same time, the carry- from the write word address counter 37W is fed to the :., ~-. 30 read control circuit 35, which delivers the write-control and read-control signal to the terminal R/W of the respective RAMs .:.
., -24-. ~ .
':' ~0850S~7 -so as to specify the write cycle of the RAMs.
Like the write address- signal, the read address signal consists of 13 bîts ïn paralleI that result from the combination of the bit address signal of 5 bits in parallel supplied from the read bit address counter 36R and the word address signal of 8 bits in parallel supplied from the read word address counter 37R. This address signal of 13 bits is applied to the address selectors 31 to 34. In order to reduce the time base during reading, the period of the read bit clock pulse is selected to ~e somewhat shorter than that of the write bit clock pulse, and to produce interleaving, the read bit address counter 36R
and the read word address counter 37R are controlled by an interleaving control circuit 41.
Fig. 7 shows the read bit address counter 36R of 30-count progress that is supplied with the bit clock pulse. The bit clock pulse is also applied to a quinary counter 42, and the carry of this counter is fed to a clock input terminal CP of the read word address counter 37R and to a load terminal LD
of the read bit address counter 36R. The read word address 2Q counter 37R is of 210-counts progress, and its carry is applied to a clock input terminal CP of a buffer 43 and one input terminal of an AND gate 44. The buffer 43 receives the output of 5 bits in parallel from a full adder 45 when a carry occurs from the read word address counter 37R. The parallel 5-bits output 43 is fed to a preset terminal PS of read bit address counter 36R, which is preset when the aforesaid carry occurs.
One input of the full adder 45 is supplied with a BCD code corresponding to 5, and the other input is supplied with the output of buffer 43, which is cleared at the end of every 35H
period when the interleaving in completed. The other input , lO~S057 terminal of the AND gate 44 is supplied with the carry of the write bit address counter 36R, and thereby produces an output, which is then fed to a RAM selector 40.
The interleavi`ng operati`on in such a construction will be now described with reference to Fig. 5. It is first assumed that a RAM, for example RAM I, contains a PCM signal of 210 words as illustrated in Fig. 5A and the contents of RAM I
are to be read out. Fig. 8 illustrates symbolically the arrangement of six words collected into three groups of two words, each, in one horizontal line interval. Each word in this arrangement is either the left or right channel signal of a stereophonic signal. The corresponding left and right signals are arranged to be recorded side by side as the two words of a group.
The content of buffer 43 is zero at first, and the write word address signal specifies Kl. Then, when the write bit address counter successively specifies five addresses with the application of the bit clock pulse and the first row ZO
(5 bits~ of word Kl is completely read out, the word address counter is incremented to specify the next word K2, and the first row ZO of word K2 is read out. Similarly, when the first rows ZO of the remaining words up to K210 are completely read out, a carry occurs from the read out word address counter 37R. This carry permits buffer 43 to receive the output of the full adder 45 and, as a result, the content of buffer 43 corresponds to 5, thereby presetting the read bit address counter 36R.
Therefore, the content to be read out upon speciEying the word Kl is at the sum address of 5 and the previous address, and hence the next row Zl of word Kl is read out. Similarly, the next rows Zl of K2~ K3...~...K210 are read out, and then 1~85057 the word address 37R produces a carry, by which the content of buf~er 43 is made lQ~5 +~ 5 2 ~ p~esettin~ the read bit adclress counter 36R. Accordi`ngly, the third rows Z2 of the respectïve words are read out in sequence. When the row Z2 of word K210 is read out, the content of buffer 43 becomes 15(5 + 10 = 15~. Thus, the fourth rows Z3 of the respective words are successively read out. Likewise, the content of buffer 43 becomes 20(5 + 15 = 20~, thereby permitting the fifth rows Z4 of the respective words to be read out in sequence, lQ and the content of buffer 43 becomes 25(5 + 20 = 25), which permits the sixth rows Z5 of the words to be sequentially read out. Each time the sixth row Z5 of each word is read out, the read bit address counter 36R produces a carry, so that the output of the AND gate 44 is at a high level at the time point when the row Z5 of word K210 is read out. This high-level output is fed to the RAM selector 40, and hence next read operation is performed on the RAM II, and at the same time buffer 43 is cleared. Thus, by controlling the address signal upon readîng as described above, it is possible to carry out the interleaving as illustrated in Fig. 4.
~' Fig. 9 illustrates the operation of the RAMs. The write - operation of the RAMs is performed in the order of I, II,..... IV, while the read operation thereof is stopped during the data-lacking period of 17.5 H that consists of the vertical blanking period, which includes the vertical synchronizing signal VD.
When RAM I undergoes a write operation, RAM IV is subject to a read operation. To perform the de-interleaving and extend the time base, it is sufficient that the write and read operations as illustrated in Fig. 9 may fie reversed. Because of the fact that the circuit can operate in reverse fashion, the de-inter-10850S~7 leave circuit 12 of the reproducing system can be formed fundamentally in the same manner as that of the interleave circuit 7.
Now, the ORC decoding will be described as carried out in the circuit 14 in Fig. 1. From the above description of encoding, the equations Za + Zl + Z2 + Z3 + Z4 + Z5 = (7) Z'0 + TZ'l + T2Z'2 + T3Z'3 + T Z'4 = (8) are satisfied.
The error pattern will now be assumed as follows:
B4 B3 B2 Bl 0 e04 eO3 eo2 eOl eOO Z
elO 1 (9 e20 Z2 " ~ " " e30 Z3 e40 Z4 e54 e50 Z5 Accordingly, an error ei (i = 0, 1, 2, 3, 4, 5) occurring in the i-th row is expressed by ei = (eio, eil, ei2, ei3, ei4) (10) where i is ~, 1, 2, 3, 4 and 5, and a given row including this error is shown by the expression:

~i = Zi + ei (11) Symptoms that appear when a succession of signals including the above error is received are called a syndrome, and syndromes Sl and ~2 are defined as follows.

108S~7 Sl Z0 + Zl + Z2 + Z3 + Z4 + Z5 (12) = (SlO~ Sll~ S12~ S13, S14) 2 Zo~ + TZl, + T Z2~ + T3Z3, + T4Z4, = Bo + TBl + T B2 + T B3 + T B4 (13) = (S20, 521~ S22~ S24) If no error occurs, both syndromes Sl and S2 are zero.

Thus, when error occurs, the syndromes can be rewritten as follows:
Sl = ~ Z.' + ~ e., = ~ e , (14) : i-o 1 i=o 1 i=o S2 = ~ T ei, (15) i=o The syndrome Sl can be determined by summing all the bits of each dolumn of the received (reproduced) code. That is, .1 , Sll = r4 + r8 + rl2 + rl6 20 S12 r3 + r7 + rll + rl5 + rlg + c (16) S13 = r2 + r6 + r10 + rl4 + rl8 S14 rl + rs + rg + rl3 + rl7 + e The circuit in Fig. 10 corresponds to the block 15 in ` Fig. 1 and is capable of accomplishing the additions required by equations (16~. The circuit in Fig. 10 has thirty input terminals 15-1 through 15-30 to which sixteen reproduced information bits rl through rl6, five ORC code bits A through E, four CRC code bits rl7 through r20, and five vertical parity check bits a through e are applied in the order in which they are labeled on the drawing. The input terminals are connected in pairs to fifteen exclusive-OR input gates 15-31 through 15-45, respectively.

~o8505q The complete circuit 15 is made up of five identical sub-circuits, and the outputs of two of the three input gates of each sub-circuit are connected to the input terminals of one of five exclusive-OR gates 15-46 through 15-50, respectively.
The output terminal of each of the latter gates and the output terminal of the remaining input gate in the same sub-circuit are connected to the input terminals of an output exclusive-OR
gate of that sub-circuit. These output gates 15-51 through 15-55 have output terminals 15-56 through 15-60, respectively, from which the components S10 through S14 of the syndrome S
are made available.
; The uppermost sub-circuit, which is illustrative of all, includes the input terminals 15-1 through 15-6 to which the r4, r8~ rl2' rl6~ r20~ and b of vector Bl are applied. If there is no error due to a dropout or burst, an even number of these coefficients (or none of them) will have the value "1" and the output signal Sll will have the value "0".
For a completely error-free reproduced block, all of the signals S10 through S14 will have the value "0".
2Q The syndrome S2 can be obtained by the following expression similar to the way in which the column vector Bo was obtained at the time of encoding:

S20 = A + r5 + rl0 + rl5 + rl7 20 21 B + r4 + r9 + rl4 + rlg S = C + r3 + r5 + r8 + rl0 + rl3 + rl5 + 17 18 20 S 3 = D + r2+ r7 + r9 + rl2 + rl4 17 19 (17) S 4 = E + r1 + r6 + r11 + rl3 + rl6 18 :

1085~)57 Although the syndrome S2 can also be formed by a feedback shift recJister, the simultaneous availability of all components of the syndrome in parallel makes it possible for the syndrome to be det:ermined as given above. In the case of correcting a burst error that exists within one row, if a burst error occurs in the i-th row, the following relations are satisfied:
Sl = ei, (18) 2 { i' ~ ~ ~ ) (19) Q (i = 5) where S2 = 0 means that the sixth row Z5 has a wrong parity bit, so that the received succession of signals itself is treatecl as the output data. Therefore, after the expression, -1 (20) is established and i (the row in which there is an error) is determined to satisfy the relations, Sl = S3, the operation of Zi' = Zi' + Sl (21) is performed, thus correcting the error ei.
Fig. 11 is a detailed drawing of circuit 16 in Fig. 1 for generating both the syndrome S2 and the expression S3 directly from the 30-bit parallel signal at the output of the series-to-parallel converter 13 in Fig. 1. Because all of the bits are applied simultaneously, the relations required for determining the syndrome S2 and the expression S3 are available at once and do not require a shift register.
Circuit 16 in Fig. 11 has twenty-six input terminals 16-1 through 16-26. All of the reproduced information bits rl through rl6, CRC hits rl7 through r20, and ORC bits A
through E are applied to the input terminals as labeled. The parity checking bits a through e are not applied because they ~085()57 do not enter into the computation of S2 or S3, so that there are actually only 25 of the possible 30 bits of the output signal of the series-to-parallel converter 13 applied to ci:rcuit 16. However, the bit 17 is applied to two terminals 16~5 and 16-20 so that an even number of bits is applied.
A11 of the components shown within the circuit 16 are exclusive-OR gates 16-27 through 16-55 arranged in five tiers.
The gates are grouped together to provide modulo 2 addition according to equations (17~. Gates 16-27 adds bits r5 and rl07 gate 16-28 adds bits rl5 and r20. Gate 16-36 adds the modulo 2 sum of the outputs of gates 16-27 and 16-28 and gate 16-41 adds th~ output of the latter to the bit rl7. Finally, gate 16-46 adds the modulo 2 sum output of gate 16-41 to bit A to ~i complete the modulo 2 sum of all of the coefficients necessary to determine the component S20 of the syndrome S2. This component is available at an output terminal 16-56, one of ten output terminals 16-56 through 16-65.
In a similar manner, gates 16-29, 16-37, 16-42, and 16-47 form the modulo 2 sum necessary to produce the syndrome component S21 at the output terminal 16-60; and the component S22 at the output terminal 16-61 is formed by modulo 2 - addition in the gates 16-27, 16-28, 16-36, 16-41, 16-30, 16-31,16-38, 16-43, and 16-48. The component S23 is formed by modulo 2 addition in the gates 16-29, 16-37, 16-32, 16-33, 16-39, 16-44, and 16-49; and the component S24 is formed by modulo 2 addition in the gates 16-31, 16-34, 16-35, 16-40, 16-45, and 16-50.
Circuit 16 also forms the matrix components Fl through F5 for computation of matrix T in equation (20). Component 3Q Fl is formed ~y modulo 2 addition of components S20 and S22 in the gate 16-51; component F2 is formed by modulo 2 addition of ' 108505`7 components S21 and S23 in the gate 16-56; component F3 is formed by modulo 2 addition of components S20, S22 and S24 in ga1:es 16-51 and 16-52; component F4 is :formed by modulo 2 addition of components S20, S21, and S23 in gates 16-55 and 16--56; and component F5 is formed by modulo 2 addition of p S20, S21, S22, and S24 in gates 16-51, 16-52, and 16-53.
The establishment of S3 can be made in parallel by predetermining T 1, T 2, T 3, T 4 and T 5 and performing the 10 addition of each expression as given below:

S21 S20 + S22 T S2 = S20 + S22 S21 + S23 S23 T S2 =S24 S24 s2o s2o S21 S21 + S23 S20 + S22 (22) S20 ~ S22 + S24 S20 + S21 + S43 T-3S = S20 S21 S21 T S2 =20 + S22 S20 - S22 S21 + S33 S20 + S21 + S23 S20 + S21 + S22 + S24 T S2 = S21 + S22 S20 ~ S22 + S24 The circuit 17 in Fig. 1, in which the syndrome Sl is compared with the expression S3, and the error-correcting circuit 18 are shown in detail in Fig. 12. The comparison . circuit 17 has five input terminals 17-1 through 17-5. Each of the inputs is connected to a set of six exclusive-OR gates in an array of thirty such gates 17-6 through 17-35. For example, the input terminal 17-1 is connected to one input tenminal of each of the gates 17-6 through 17-11. The outputs of the gates 17-6 through 17-35 are connected in intersecting sets to a set of NOR gates 17-36 through 17-41. For example the exclusive-OR gates 17-6, 17-12, 17-18, 17-24, and 17-30 comprise a set that intersects each of the sets connected to the input terminals 17-1 through 17-5, and all of the gates of this intersecting set are connected to input terminals of the NOR gate 17-36.
The components S20 through S24 of syndrome S2 and the components Fl through F4 of the matrix T i in equation (20) are connected to the gates 17-6 through 17-35 as indicated in Fig. 12, and if all of the components S20 through S24 and Fl through F4 are zero, which is the condition for no error, the outputs of all of the NOR gates 17-36 through 17-41 will be "1". Another NOR gate 17-42 to which only the components of the syndrome S2 are connected will also have a "1" output. Two OR gates 17-43 and 17-44 combine the outputs of four NOR gates 17-36 through 17-38 and 17-42 into two input terminals of the NOR gate 17-45.
The circuit 18 as shown in Fig. 12 includes four non-inverting input circuits 18-1 through 18-4 connected respectively, to the input terminals 17-2 through 17-5. The outputs of the circuits 18-1 through 18-4 are connected, respectively, to sets of five AND gates 18-5 through 18-9, 18-15 through 18-19, 18-25 through 18-29, and 18-35 through 18-39. The output of the NOR gate 17-36 is connected to an intersecting set of the AND gates 18-5, 18-15, 18-25, and 18-35, and the outputs of NOR gates 17-37 through 17-40 are connected to similar inter-secting sets of the AND gates.

1~)850~7 ;, - .
The outputs of the AND gates 18-5 through 18-9 are connected, respectively, to one input terminal of a set of exclusive-OR gates 18-10 through 18-14, respectively, and in the same manner, the AND gates 18-15 through 18-19 are connected to exclusive-OR gates 18-20 through 18-24, AND gates 18-25 through 18-29 are connected to exclusive-OR gates 18-30 through 18-34, and AND gates 18-35 through 18-39 are connected to exclusive-OR gates 18-40 through 18-44. The output terminals of the exclusive-OR gates in ascending numerical order 10 are, respectively, 18-45 through 18-64.
The comparison circuit 17 generates, simultaneously, every variation of T iS2, which means that it generates every possible value of S3 and compares each of these values with syndrome Sl. If there are no errors in the reproduced signal, the syndrome Sl will be "0", which means thatits components S10 through S14 will be "0". The components S20 through S24 of the syndrome S2 will also be "0", which means that the ; components Fl through F5 will also be "0". Consequently all of the inputs to the NOR gates 17-36 through 17-42 will be 20 1l0ll, and the outputs of these NOR gates will be "1". Therefore, the output value H of the NOR gate 17-45 will be "0".
: The input terminals 17-2 through 17-5 of the comparison :
- circuit 17 are shared by the error-correction circuit, and when the signal is error-free, the inputs to the circuits 18-1 through 18-4 will b~ "0". This causes all of the AND gates . in the circuit 18 to be disabled. The output of each AND
` gate is combined with a specific one of the bits r1 through r20 of the reproduced signal applied to the other input . terminal of the exclusive-OR gates 18-10 through 18-14 for : 30 the AND gates 18-5 through 18-9.
; ' ' ., , lO~SOS7 secause, under error-free conditions the output of each of the AND gates is "0", the output of each of the exclusive-OR gates at the respective output terminal 18-45 through 18-64 corresponds to the value of the bit ri applied to that exclusive-OR gate. Mathematically this corresponds to adding "0" to each bit ri, which, of course, does not change the value of the latter at all.
However, if there is an error in even a single reproduced bit, the condition of circuits 17 and 18 changes considerably. For example, in the case of the arbitrarily chosen number 00110100100011010101 referred to previously in analyzing the CRC encoder 5, the first sixteen digits are information bits rl through rl6 and the last four are CRC bits rl7 through r20. If, between the encoding circuit 5 and the syndrome Sl generator 15, the value of bit rl6 is changed from "1" to "0", the component Sll of the syndrome Sl will change from "0" to "1" at the output terminal 15-56 in Fig. 10.
The error in bit rl6 also causes the component S24 of the syndrome S2 as generated at the output terminal 16-65 in circuit 20 16 in Fig. 11 to change from "0" to "1", which changes the value of component F3 at the output terminal 16-58 from "0" to "1".
This, in turn, causes the component F5 at the output terminal 16-59 to change from "0" to "1".
When these modified values are applied to the comparison circuit 17 in Fig. 12, the component Sll applied by way of the input terminal 17-2 causes the upper input terminal of each of the exclusive-OR gates 17-12 through 17-17 to have a "1" signal applied to it. The change of value of the component S24, which is applied either by itself or as part of the components F3 and F5, to the lower input terminal of the ~o~sos7 diagonal line of exclusive-OR gates 17-10, 17-15, 17-20, 17-25, and 17-30 and to the exclusive-OR gates 17-17 and 17-35 in the bottom row, causes all of these lower input terminals to take on the value "1". As a result, at least one input to each of the NOR gates 17-36 through 17-42, except the NOR gate 17-39, has a "1" value instead of a "0" value.
The output value of the NOR gate 17-45 remains at "0" due to the fact that at least one of its input terminals has a "1"
value signal on it. This one input terminal is the one lQ connected to the output of the NOR gate 17-39. The output of ; that NOR gate remains at "1" because the "1" value of the components Sll and F5 applied to the two input terminals of the exclusive-OR gate 17-15 cause both of these input terminals to change from "Q" to "1", and the modulo 2 addition in that exclusive-OR gate causes its output terminal to remain at "0".
Because of the "0" value output of each of the NOR
gates 17-36 through 17-38 and 17-40, all of the AND gates in the error-correction circuit 18 connected thereto are disabled.
Only one row of AND gates 18-8, 18-18, 18-28, and 18-38 are 20 enabled by the "1" value output of the NOR gate 17-39. But three of these four enabled AND gates are disabled by "0"
signals from the circuits 18-1 through 18-3. These are AND
gates 18-8, 18-18, and 18-28. Only AND gate 18-38 has a "1"
value applied to both of its input terminals and, therefore, this is the only AND gate that supplies a "1" value signal to the exclusive-OR gate 18-43 to which it is connected.
It is this same exclusive-OR gate 18-43 to which the bit rl6 is connected. That bit has been assumed to have the erroneous value "0" instead of "1". However, the exclusive-` 30 OR gate adds the value "1" from the AND gate 18-38 to produce a corrected "1" value at its output terminal 18-63. If the :

.

108S0~7 bit rl6 had erroneously been a "1", it would have been corrected to "0" by the modulo 2 addition with the "1l' value of the output from the AND gate 18-38. Thus, all of the output terminals 18-45 through 18-64 have correct values of output bit signals rl through r20.
The corrected bits Il through I20 are supplied from the output terminals 18-45 through 18-64 and are applied to input terminals 19-1 through 19-20 of the CRC decoder 19 in Fig. 13 in the order identified in that figure. The bit signals I
through I20 are the same as the bits rl through r20, respectively, but have been identified by the letter "I" to indicate that they have passed through the error-correction i circuit 18.
; Like several of the other circuits, the CRC decoder 19 consists of a set of exclusive-OR gates 19-21 through 19-38 to add the inputs Il through I20 selectively, always on a modulo 2 basis. The gates 19-21 and 19-22 receive and add p s I20, I2, I8 and I14, and the gate 19-29 adds the outputs of the gates 19-21 and 19-22 together. The gate 2Q 19-26 adds the bits I1o and (now-corrected) I16 and the gate 19-32 adds to the sum thereof the bit I14. The outputs of the gates 19-29 and 19-32 are added together in the gate 19-35 to form the output signal P4.
- The gate 19-25 forms a modulo 2 sum of the bits I6 and I12 and the gate 19-31 adds the bit I18 to this sum. The out-puts of the gates 19-31 and 19-32 are combined in the gate 19-37 to form the output signal P2.
The gates 19-23, 19-24, and 19-30 form the sum of the bits I19, I1, I7, and I13 and this sum is applied to one input ; 30 terminal of the gate 19-36. The gates 19-28 and 19-34 form the sum of the bits I3, Ig, and I15 and supply this sum to the 1~8505q other input terminal of the gate 19-36. The output of the latter gate is the output signal P3.
The gates 19-27 and 19-33 add the bits I5, Ill, and I17, and the resulting sum is added to the output of the gate 19-34 in the gate 19-38 to form the output signal Pl.
The output signals Pl through P4 are combined in an OR
gate, which is made up of a NOR gate 19-39 and an inverter 19-40. The output terminal of this OR gate is terminal 19-41.
The signal H from the coincidence circuit 17 is also supplied through an input terminal 19-42 to the NOR gate 19-39.
Signal H has the value "0" if there are no uncorrectable errors in the coincidence circuit but the value "1" if the syndrome Sl does not equal the expression S3, which indicates that there are errors that the ORC circuitry cannot correct.
If only one row of the original array of bits in the order in which they appear in Fig. 26 has errors, they can be corrected in the ORC decoder 18, but if two or more rows have bits with erroneous values, the combined circuits 17 and 18 cannot correct them. In that case, the CRC decoder 19 detects the error. Such a large number of errors is quite rare, but this system is of professional quality, and it is important to correct all errors.
Mathematically, the CRC decoder divides the polynomial having the coefficients of information bits Il to I16 and CRC
code (I17 to I20~ by a generating polynomial. When the remain-der of four bits is represented by Pl to P4, respectively, each of the bits can be derived from the following expressions as in the case of encoding:

1 I3 + I5 + Ig + Ill + I15 + I17 (23) . :

10850Sq P3 = Il + I3 + I7 + Ig + I13 + I15 19 P4 = I2 + I4 + I8 + Ilo + I14 16 20 ';
If the outputs of the four bits Pl to P4 from the CRC
decoder 19 are all "0", it indicates that nor error occurs, but if even one of the four bits becomes "1", the occurrence ;~ of error are recognized and can be detected.
Fig. 14 shows an example of the interpolation circuit 21, which has an input terminal 31 at which a clock pulse CK is applied and a terminal 32 to which the output of the OR gate 20 is supplied. The circuit also includes latch circuits 33 and 34, which are connected so that a parallel 16-bit output signal U1 from the latch circuit 33 can be supplied to the latch circuit 34. A D-type flip-flop circuit 33a associated with the latch circuit 33 has its D-input terminal connected to the terminal 32 and its output terminal connected to the D-input terminal of another D-type flip-flop circuit 34a, which - is associated with the latch 34. The outputs Q1 and Q2 of the flip-flop circuits 33a and 34a, respectively, occur slightly delayed from the time when the clock pulse CK occurs.
; 20 A data selector 35 composed of an input selecting gate ` and a latch circuit is also part of the interpolation circuit 21. The data selector 35 selects either a parallel 16-bit output signal U2 of the latch circuit 34 or a parallel 16-bit output signal U4 supplied from a mean-value forming circuit 36 that consists of full adders and performs in a digital manner.
The selection is made in accordance with an output Nl of a NAND
gate 37 in such a way that the selector 35 chooses the output U2 if Nl = "1" or the output U4 if N1 = "0".

- ~ ~

~08S05~

One of the two input signals to the mean-value forming circuit 36 is the parallel 16-bit output signal Ul of the latch circuit 33 and the other is an output signal U3 of the dat:a selector 35. The circuit 36 produces the output signal U4 as a mean value of its two input signals. The NAND gate 37 is supplied with the output Ql of the D-type flip-flop circuit 34a. The output N2 of a NAND gate 39 to which the outputs Ql and Q2 are applied is supplied to the J-input terminal of a J-K flip-flop circuit 40, and through a NOT
- 10 cïrcuit, or inverter, 41 to the K-input terminal of the J-K
flip-flop circuit 40. An output Q3 of the J-K flip-flop circuit 40 is fed to a NAND gate 42, the output N3 of which is applied to the data selector 35 for the latter to operate at each clock pulse.
The operation of the interpolation circuit 21 constructed as described will now be described in connection with Figs. 15 and 16. The 16-bit information as a PCM signal ffl iS supplied from the error-correcting circuit 18 and includes a sequence of signals ml, m2, m3, ....... ~ Also, it is first assumed that each of the signals ml to m4 does not include an error, that signal m3 is latched onto the latch circuit 33, that signal m2 is latched onto the latch circuit 34, and that signal ml is latched onto the data selector 35 with signal ml appear-ing as the output signal U3 of the data selector 35 before the first pulse CKl illustrated in Fig. 16A occurs. Then, when the first clock pulse CKl does occur, signal m4 is latched onto latch circuit 33, and signal m3 is transferred to the latch circuit 34. Since the output of the OR gate 20 supplied to the terminal 32 together with the signal m4 is "0", the output Ql (shown in Fig. 16B) of the flip-flop circuit 33a is "0".

108505~

In addition, since it has been assumed that the signal m3 does not include an error, the output Q2 (shown in Fig. 16C) of the flip-flop circuit 34a is also "0". Therefore, the output of the NAND gate 37 as shown by Fig. 16D, has a value of "1", as does the output N2 of the NAND gate 39. Hence, the output Q3 of J-K flip-flop circuit 40 is "1"~ as shown by Fig. 16E.
As a result, the data selector 35 is supplied with a clock pulse N3 (shown by Fig. 16J) corresponding to the clock pulse CKl so that the signal m2 is latched onto the data selector 35 to appear as the output signal U3.
If the next information bit signal m5 includes an error, signal m5 is latched onto the latch circuit 33 by the applica-tion of the clock CK2 thereto and signal m4 is latched onto the latch circuit 34. Then, the output Ql becomes "1" at a time somewhat delayed from the time when the clock pulse CK2 occurs. Since the output Q2 is "0", the outputs Nl and N2 f NAND circuits 37 and 39 are both "1", and hence the output Q3 is "1". The clock pulse N3 corresponding to clock pulse CK2 ; is applied to the data selector 35, so that the signal m3 is latched onto the data selector 35 to appear as the output U3.
If the next information bit signal m6 is correct, the clock pulse CK3 is applied to the latch circuit 33, onto which the signal m6 is thus latched as signal m5 is latched onto latch circuit 34. Since the outputs Ql and Q2 equal "1" and llOII, respectively, at the time of occurrence of the clock pulse CK3, the outputs Nl and N2 are both "1" and hence the output Q3 becomes "1". Then, the clock pulse N3 corresponding to clock pulse CK3 is applied to data selector 35, onto which signal m4 is latched to appear as output signal U3.
If the next information bit signal m7 is wrong, clock pulse CK4 is fed to the latch circuit 33, onto which the signal 10850S`7 m7 is thus latched, and the signal m6 is latched onto the latched circuit 34. At this time, the mean value forming circuit 36 produces a mean value of signals m6 and m4, namely, the value (m4 ~ m6)/2. Since the outputs Ql and Q2 are "0"
and "1", respectively, at the time the clock pulse CK4 occurs, the output N1 becomes "0". Thus, the mean value (m4 + m6)/2 is latched onto the data selector 35 instead of the signal m5, which appears as the output signal U3.
If the next information bit signal m8 is also wrong, lQ the signals m8 and m7 are latched onto the latch circuits 33 ; and 34, respectively, by the application of clock pulse CK5, and since the outputs Q1 and Q2 equal "1" and "0", respectively, signal m6 is latched onto the data selector 35 to appear as the output signal U3.
Upon the application of the next information bit signal m9 (assumed to be correct), the clock pulse CK6 is supplied to the latch circuit 33, and the signal m9 is thus latched thereon.
At the same time signal m8 is latched onto latch circuit 34.

,., At this time, since the outputs Q1 and Q2 are both "l", the output N2 becomes "0" to make the output Q3 of J-K flip-flop circuit 40 "0", with the result that the data selector 35 is 'i:
~- not supplied with a clock pulse corresponding to clock pulse CK6, as may be seen in Fig. 16J. Therefore, the signal m6 is kept as the output signal U3, that is, the data selector 35 acts to hold the previous value.
When the next information bit signal ml0 (assumed to be correct) occurs, the clock pulse CK7 is applied to the latch cïrcuit 33 to latch the signal m6 thereon, and the signal m9 is latched onto the latch circuit 34. At the same time, since the outputs Q1 and Q2 equal "0" and "l", respectively, the out-put N1 becomes "0" and hence the data selector 35 produces the . .

~085057 output U3 of (m6 + m8~/2 from the mean value forming circuit 36.
If the next succession of information bit mll, ml2, ... ....are correct, the application of clock pulses CK8, CKg,..... causes the data selector 35 to produce the output signal U3 of signals 9' ml0' mll~ ml2~-----ln sequence As described above, the interpolation circuit 21 permits correct information bit signals to pass therethrough as its outputs, and a wrong information bit signal to be replaced by a mean value of the correct bits adjacent thereto, as its output.
In addition, if a succession of incorrect bits occurs, the interpolation circuit 21 functions to hold the previous correct information bits. Of course, there is a very low probability that correction by the ORC will be impossible.
In accordance with the present invention as stated above, the error-correcting code, which, when arranged in a matrix form, makes it possible to correct a burst error in the row direction, can be converted to a series arrangement in order to be processed as a series signal, for example by being recorded on a single magnetic track. In this case, since the error-correcting code is not only arranged to be Zo~ Zl' Z2' Z5 in series at each clock as shown in Fig. 5A, but also rearranged by the interleave circuit 7 to take the form of Z0 Z' Zl Zl' ~ i.e., the six groups of the corresponding rows in the plurality of clocks are continuous in series as illustrated in Fig. 5B, it is possible to reduce considerably the influence of a drop out, which is inevitable when using magnetic mediums. That is, any burst error due to a drop out or the like which does not exceed the length of 210 words, which r at six words per line interval, cover 35 line intervals, can be made to exist within one row in each block by the ORC arrangement, and thus corrected.

,:
~ ~ , - - ' .' ., - :

1~)850S~
' If the error-correcting code does not undergo the interleave process with only the series conversion made as illustrated in Fig. 5A, only the two wrong bits extending over rows Z0 and Zl~ by way of example, results in the error of two rows. However, by means of the ORC, it is possible to correct the error of two rows as long as the numbers of the incorrect rows can be detected by other means.
In order to avoid the complexity of the construction of the system, it is desirable to arrange that any burst error exist within one row. Even if the system is constructed to be capable of correcting error in two rows, a burst error of at m~st tw~ rows can be corrected. As in the above embodiment, providing the capability of completing the rearrangement within one field would be advantageous for editing recorded signals.
Further, the present invention makes use of the combination of the error detecting code (CRC code) and the ORC, and hence is characterized by a very high probability of error detection. In addition, this invention, as described in the above embodiment, is best suited for converting an audio signal to a PCM signal, such as a 16-bit PCM signal for each of the two channels of a stereo signal, and using as its transmission medium a single track as a VTR of a wide-band magnetic recording and reproducing apparatus.
', , :

Claims

REVENDICATIONS

1. Appareil destiné à mesurer la circonférence d'un objet, caractérisé par le fait qu'il comprend: deux branches articulées, sensiblement en un point médian, formant d'un côté
bras de préhension et de serrage, et du coté opposé, deux parties courbées opposées et jointives de courbure sensiblement différent; la première partie courbe ayant le rayon le plus important, présente des griffes d'accrochage pour autoriser le passage sous l'arbre, son positionnement et son maintien; un câble gradué fixé sur l'une des branches et guidé par coulissement dans la branche opposée; l'ouverture des branches autorisant de par leurs parties courbées, le passage diamétral de la section à mesurer, de l'objet à l'encontre du câble qui est sollicité
en traction et enserre la périphérie de la section lors de la fermeture des branches, provoquant ainsi de par son brin libre, un déplacement linéaire correspondant du câble, ledit câble permetant directement au travers d'une ouverture avec repère établi sur le bras de préhension correspondant, la mesure de la circonférence de l'objet.

2. Appareil pour mesurer, selon la revendication 1, caractérisé en ce que l'axe d'articulation des branches est sensiblement décalé par rapport au point de contact des extrémités supérieures desdites branches.

3. Appareil pour mesurer selon la revendication 2, caractérise en ce que l'extrémité supérieure de la première partie courbe constituant la branche d'accrochage, présente une patte repliée intérieurement dans laquelle est réalisée une ouverture pour le passage du câble; l'extrémité du câble étant reliée à un moyen d'arrêt venant en butée contre la patte repliée; la dite patte étant positionnée sensiblement avant l'extrémité de la branche, afin d'éviter toute détérioration du câble.

4. Appareil de mesure selon la revendication 1, caractérisé en ce qu'un ressort de rappel est positionné dans la seconde partie courbe constituant la branche de commande, ledit ressort venant en butée contre le talon de mètre constituant l'élément de mesure de la circonférence de l'objet, tandis que son autre extrémité bute contre un moyen d'arrêt positionné
dans la branche, sensiblement au niveau du début de sa partie recourbée; l'action de rappel dudit ressort se combinant avec l'action de rappel provenant de l'enroulement automatique du mètre.

5. Appareil de mesure selon la revendication 4, caractérisé
en ce que un moyen élastique est disposé sur la partie du câble susceptible de s'enrouler et l'axe d'articulation de deux bras de préhension empêchant tout détérioration du câble.

6. Appareil de mesure selon la revendication 1, caractérisé en ce qu'un secteur est monté sur l'une des branches articulées dans sa partie formant bras de préhension, près de l'axe d'articulation, un repère étant judicieusement positionné
sur l'autre bras, pour donner la mesure exacte de la circon-férence.

7. Appareil de mesure selon la revendication 6, caractérisé en ce qu'une tablette est disposée près de la partie arrière sur l'un des bras.