CA1092656A

CA1092656A - Receiver for data transmitted by means of the interleaved binary phase shift keyed modulation technique

Info

Publication number: CA1092656A
Application number: CA300,379A
Authority: CA
Inventors: Alex H. Lautier; Jean L. Monrolin
Original assignee: International Business Machines Corp
Current assignee: International Business Machines Corp
Priority date: 1977-06-10
Filing date: 1978-04-04
Publication date: 1980-12-30
Also published as: GB1563385A; FR2394218B1; US4186348A; DE2823213A1; DE2823213C2; FR2394218A1; JPS545369A

Abstract

RECEIVER FOR DATA TRANSMITTED BY
MEANS OF THE INTERLEAVED BINARY PHASE
SHIFT KEYED MODULATION TECHNIQUE
Abstract A receiver in which the received signal is demodulated by means of an in-phase reference carrier and a quadrature reference carrier both of which are supplied by a clock and carrier recovery device, thereby supplying the in-phase and quadrature components of the sig-nal. The sign of the sum of these components and that of the differ-ence between them are selectively gated to the output of the receiver under control of the clock signal supplied by the clock and carrier recovery device. In this device, the frequency of the received sig-nal is doubled and the signal thus obtained is modulated by the clock signal at half the signaling rate extracted from the received signal.
This modulation operation yields a signal at twice the carrier fre-quency from which the in-phase and quadrature reference carriers are extracted.

Description

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1 This invention relates to data transmission systems and, more particularly, to a data receiver ~or a data transmisslon system em-ploying the interleaved binary phase shift keyed modulation tech-nique.
Interleaved binary phase shift keyed modulation is a particular form of the widely used binary phase shift keyed (BPSK) modulation technique, which has been described in many publications. Reference may be made, for instance, to the book entitled "Information Trans-mission, Modulation and Noise", by M. Schwartz, section 4-2, McGraw-Hill, New York, 1970, for a description of BPSK modulation, and tothe books entitled "Data Transmission", by R.W. Bennett and J.R.
Davey, chapter 10, McGraw-Hill, New York, 1965, and "Principles of Data Transmission", by R.W. Lucky, J. Salz and E.J. Weldon, Jr., chapter 3, McGraw-Hill, New York, 1968, for a general description of the phase shift keyed modulation technique. Briefly, BPSK modulation is a technique where the bits to be transmitted are sent one at a time at instants which have a T-second spacing and are called signaling -instants. Each bit value corresponds to one of two possible carrier phase changes relative to the carrier phase at a preceding signaling - 20 instant. At each signaling instant, the absolute carrier phase can assume one of two possible values. By indicating the two possible values of the phase of the carrier in a so-called signal space dia-gram, a couple of points that are 180 apart in phase are obtained which illustrate the modulation scheme employed.
In the interleaved BPSK modulation technique, the bit to be transmitted is made to correspond, at an even signaling instant, to a selected one of a first couple of points that are 180 apart in phase in the diagram, and, at an odd signaling instant, to a selected one of a second couple of points that are 180 apart in phase, with - ~ 30 the first and second couples of points being 90 apart in phase.~ FR9~77-002 - 2 -.. - . . .. .. :. ~ . . ..

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1 An advantage of interleaved BPSK modulation over BPSK modu-lation is that it provides a modulated signal with an envelope that varies little in time. Consequently, most of the energy re-mains concentrated in a well-defined, narrow frequency band in a nonlinear channel. Interleaved BPSK mdoulation has been advan-tageously used in satellite communication systems where signals are received and transmitted over several adjacent frequency bands - through a single nonlinear transponder, so that it is essentialthat the methods of modulation employed minimize interference in these bands. However, there is a disadvantage inherent in this type of modulation. As mentioned above, interleaved BPSK modulation in-volves the use of two different couples of points in the signal space diagram, and if the transmitted data is to be correctly detected the receiver must know at a given signaling instant whether it is to use the first or the second couple of points as a detection reference.
In other words, the receiver must be synchronized with the transmitter.
In the early transmission systems that used interleaved BPSK modu-lation, a synchronization sequence was transmitted before the data message. This is, of course, time-consuming and required the use of additional equipment in both the transmitter and the receiver and of a special resynchronization procedure in the event of phase loss of the signals defining the interleaving rate.
This invention provides a self-synchronized receiver of simple design for use in a data transmission system employing the inter-leaved BPSK modulation technique.
Broadly, this is attained by providing a receiver in which the received signal is demodulated by means of an in-phase reference - carrier and a quadrature reference carrier both of which are supplied by a clock and carrier recovery device to thereby supply the in-phase and quadrature components of the signal. The sign of the sum of -~

-. ~ : ' . . , . : ~ -3~6~6 1 these components and that of the dif~erence between them is selec-tively gated to the output of the receiver under control of a clock signal supplied by the clock and carrier recovery device. In this device, the frequency of the received signal is doubled and the signal thus obtained is modulated by the clock signal at half the signaling rate extracted from the received signal. This modulation operation yields a signal at twice the carrier frequency from which the in-phase and quadrature reference carriers are extracted.
The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of a preferred embodiment of the invention, as illus-trated in the accompanying drawings.
Figure 1 is a block diagram of a transmitter for a transmission system using the interleaved BPSK modulation technique.
Figure 2 shows the signal space diagrams that illustrate the interleaved BPSK modulation technique.
Figure 3 is a block diagram of a data receiver according to the present invention.
To illustrate the context within which the invention finds ap-plication, a simplified block diagram of a transmitter using theinterleaved BPSK modulation techn;que has been shown ;n figure 1.
The data bits to be transmitted are present on line 1 and fed via line 2 to the input of a low-pass filter 3 and via line 4 to an in-put of an Exclusive OR circuit 5, the output from which is applied ~ ~:
via line 6 to the input of a low-pass filter 7 identical to filter 3. The outputs from filters 3 and 7 are respectively fed via lines 8 and 9 to a first input of each of a couple of modulators 10 and 11.
A carrier generator 12 supplies an "in-phase" carrier that is ap-plied to the second input of modulator 11 via line 13. The phase of .-.': ' ' .
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1 this carrier is shifted 90 by a phase shifter 1~ and applied as a "quadrature" carrier to the second input of modulator 10 via line 15. The outputs from modulators 10 and 11 are summed by a summing device 16 the output from which is applied via line 17 to the input of the transmission channel. A clock 18 provides signals at the signaling rate I/T which are applied to a divide by two circuit 19. The clock signals supplied at a rate of 1/2T by circuit 19 are fed to the other input of Exclusive OR cir-cuit 5 via line 20.
Before describing the operation of the device of figure 1, the three signal space diagrams shown in figure 2 which illustrate the interleaved BPSK modulation technique will be discussed. The first or leftmost diagram in figure 2 shows the couple of points, A-B, re-presenting the two phase values that the carrier can assume at sig-naling instant nT, T being the signaling period and the value of n being any integer. The modulation scheme illustrated by the first diagram will be referred to hereafter as "modulation scheme 1".
The second dlagram, in the center oF figure 2, depicts the couple of points, C-D, representing the two phase values that the carrier can assume at signaling instant (n+l)T. The modulation scheme illus-trated by the second diagram will be referred to as "modulation scheme

2". The third diagram, shown at right in the figure, depicts the couple of points representing the two phase values that the carrier can assume at signaling instant (n+2)T, these points being, of course, points A-B. Each of these points can be defined in the respective diagram by its rectangular coordinates, which represent the in-phase and quadrature components of the carrier. In the modu-lation scheme shown in figure 2, the in-phase and quadrature com-ponents of the various points are as follows:
A(+l, +l); B(-l, -1), C(-l, +1), and D(+l, -1).
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~%656 1 Points A, B, C and D represent the respective phase values of the carrier, namely, 45, 225, 135 and 315.
The operation of the device shown in figure 1 will now be des-cribed. The data bits to be transmitted are sent over line 1 as rectangular pulses. Typically, a 1 bit will be represented by a rectangular pulse of amplitude +l and a O bit by a rectangular pulse of amplitude -1. Clock 18 generates clock signals at the signaling rate l/T. In practice, clock 18 supplies at each signaling instant a clock pulse that may be regarded as the equivalent of a 1 bit.
The frequency of the clock signals from clock 18 is divided by two by the divider 19. Thus, divider 19 provides a clock pulse, which may be considered equivalent to a 1 bit, every other signaling instant.
Divider 19 may be regarded as supplying a O bit at each even signal-ing instant and a 1 bit at each odd signaling instant.
; At an even signaling instant, a O bit is applied via line 20 to Exclusive OR circuit 5. As a result, a data pulse present on line 1 is directly inputted via line 2 to filter 3, and passes unchanged through Exclusive OR 5 before being inputted via line 6 to filter 7.
The data bit pulses inputted via lines 6 and 2 to filters 7 and 3 represent the in-phase and quadrature components, respectively, of the carrier to be transmitted. For example, i~ the data bit to be transmitted is a 1 bit, both the in-phase and quadrature components are equal to +1, which defines point A in the first diagram of figure 2.
If the data b;t to be transmitted ;s a 0, both components are equal to -1, which defines point B in the first diagram of figure 2. Points A and B represent carrier phase values of 45 and 225, respectively.
At an odd signaling instant, a 1 bit is applied via line 20 to Exclusive OR circuit 5. Accordingly, a data pulse present on line 1 is directly inputted via line 2 to filter 3 and is inverted by Ex-` 30 clusive OR 5 before being inputted via line 6 to filter 7. In this ~-case, if a 1 bit is to be transmitted, its in-phase and quadrature ~L~ 6~

1 components will be respectively equal to 1 and +1, thereby de-fining point C in the second diagram of figure 2. If a 0 bit is to be transmitted, its in-phase and quadrature components will be respectively equal to +l and -1, thereby defining point D in the second diagram of figure 2. Points C and D represent carrier phase values of 135 and 315, respectively.
The rectangular pulses corresponding to the in-phase and quad-rature components are respectively fed to low-pass filters 7 and 3 which convert them respectively into two pulses called baseband signal elements whose shape is more suitable for transmission. The signal elements thus obtained on lines 9 and 8 are used to modulate the in-phase carrier and the quadrature carrier, respectively, by -means of modulators 11 and 10. The modulated signals are combined in summing device 16 and applied via line 17 to the input of the transmission channel.
The data receiver of the present invention will now be described with reference to figure 3, which illustrates a data receiver in ac-cordance with the invention for a satellite transmission system em-ploying the interleaved BPSK modulation technique. The signal from the transmission channel is applied via line 30 to the input of a matched analog filter 31. The output from filter 31 is applied via line 32 to the input of a couple of demodulators 33 and 34 which, in this example, are balanced ring modulators. Such modulators are well known components that are widely used in data transmission and will not be described in detail hereafter. A carrier and clock recovery device 35, to be described later, supplies a reference carrier which is directly fed via line 36 to demodulator 33 and, through a 90 phase shifter 37 and line 38, to demodulator 34. The outputs of demodulators 33 and 34 are directly connected to low-pass filters 39 and 40, respectively. In the example illustrated, filters 39 and 40 are passive analog filters of a conventional type that serve ''"

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1 to eliminate uncesirable modulation products and thermal noise.
The output from filter 39 is applied via line 41 to a (-) input - of a summing device 42 and to a (+) input of a summing device 43.
The output from filter 40 is applied via line 44 to a (+) input of summing device 42 and to another (+) input of summing device 43.
In this example, devices 42 and 43 are conventional analog devices that use operational amplifiers. The outputs of summing devices ~2 and 43 are respectively connected to the inputs of two limiters 45 and 46 which provide, for example, an up level or a down level in response to a positive signal or to a negative signal, respectively. ~-The outputs of limiters 45 and 46 are respectively connected to an input of each of a couple of two-input AND gates 47 and 48. The -clock signals provided by the clock and carrier recovery device 35 are directly applied via line 49 to the second input of AND gate 47, and, through an inverter 50, to the second input of AND gate 48. The outputs of AND gates ~7 and 48 are connected to the input of an OR
~:~ gate 51 at the output of which signals representative of the received data are available.
Referring in more detail to the clock and carrier recovery device :
- ~ 20 35, the output from filter 31 is inputted via line 52 to a frequency mult;pl;er 53 which multiplies the frequency by two and the output of which is connected via line 54 to the ;nput of a wide-band band-pass filter 55. The output of f;lter 55 is connected v;a l;ne 56 to an input of a modulator 57 the output of which is connected to the input of a narrow-band band-pass filter 58. The output of filter 58 is connected to the input of a frequency divider 59 that serves to divide the frequency by two and provides a reference carrier on line 36.
The output of frequency multiplier 53 is also connected via line 60 to the input of a narrow-band band-pass filter 61 the output of which is connected to the input of a frequency divider 62 that divides the ~ ;
; frequency by two. Circuit 62 provides a reference clock signal that is applied to the other input of modulator 57 via line 63. This . . .

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1 signal is additionally applied to AND gate 47 and to inverter 50 via line 49. In the embodiment illustrated in figure 3, filter 55 is a wide-band passive analog filter~ filters 58 and 61 are narrow-band helical analog filters, modulator 57 is a balanced ring modulator, and frequency multiplier 53 and frequency dividers 59 and 62 are conventional analog components.
The operation of the device illustrated in figure 3 will now be described. The phase-modulated waveform received from the transmission channel via line 30 is first filtered in a convention-al manner by matched filter 31 to eliminate the out of band noiseand to limit the effects of intersymbol interference. The modulated and filtered waveform obtained at the output of filter 31 is a com-plex waveform which is dependent, in particular, on the signal ele-ment being used and the method of modulation itself. However, to simplify the description of the device of the present invention, the modulated and filtered waveform s~t) may be expressed as s(t) = cos (~ct + k~ + a(t)) (1) where:
~c is the angular frequency of the carrier, K~ are the phase changes representative of the data, with k assuming the values 0 and 1, O(t) is a term representing the modulation of +~/2 or - ~/2 that is introduced by the interleaving technique.
The frequency of waveform s(t) is multiplied by two in frequency multiplier 53. This multiplier provides a waveform sl(t) which may be written as sl(t) = 2 cos [2~ ct + 2k~ + 26(t)] + 1/2 (2) In what follows, the DC component +1/2 which appears in relation (2) will be ignored since this component is eliminated by filters 55 and 61. For simplicity, the multiplication coefficient 1/2 will also ; FR9-77-002 - 9 -', , . . . . ....... . . . . . . . .
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1 be ignored and waveform sl(t) will be written as sl(t) = cos [2~ ct + 2k~ + 20(t)] (3) In accordance with relation (3), waveform sl(t) includes the term 2~ c-t, which is representative of twice the carrier fre-quency, the term 2k~ , which may be removed from relation (3) -since it iS a multiple of 2 ~, and the term 20(t). The term 2~(t), introduced by the interleaving technique, represents a modu-lation of + ~ of the carrier. Without yoing into mathematical developments, it may be said that thiS additional modulation of ~
causes two rays at frequencies (2~ c ~ ~/T) and 2 ~c - ~/T), : :
where l/T is the signaling frequency, to appear in the spectrum of waveform sl(t), Which may consequently be written as ..

Sl(t~ = cos [(2~c + ~ ) t] + cos [(2 ~c ~ ~) t~ (4) In the example illustrated in figure 3, frequency multiplier 53 performs two different functions: it is used both to eliminate the data, thereby allowing the unmodulated carrier to be recovered, ' and to detect the envelope of the received waveform to extract timing information thereform. ThiS is due to the fact that, in this example, the carrier frequency (70 MHz) differs considerably from the signaling frequency (24.7 MHZ), SO that there iS no risk of the two functions inter~ering with each other. It will be understood by those skilled in the art that, in other embodiments, provision could be made for -~ an evelope detector separate from frequency multiplier 53.
As has jUSt been stated, frequency multiplier 53 detects, in a manner known per se, the envelope of the received waveform. As iS also known per se, the envelope of the received waveform includes a significant component at the signaling frequency l/T. This Com-ponent is extracted by the narrow-band filter 61, Which iS centered ~` at the si9naling frequency, the signaling frequency proYided by fil- -ter 61 is halved by frequency divider 62, Which provides a clock signal S2(t) writ~en as :
FR9-77-002 - 10 - .

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Z6~6 1 s2(t) = cos ~ t Clock signal s2(t) at half the signaling frequency defines the interleaving rate.
This clock signal is used to modulate the signal sl(t) fil-tered by filter 55, this being done by means of modulator 57.
Modulator 57 provides a signal s3(t):
s3(t) = sl(t) x s2(t) (6) which may also be written, in accordance with relations (~) and [~ c TT) t~ + cos ~ 2 ~ - ~) t~ x c Simplifying, relation (7) may be written s3(t) = cos 2 ~ct ~ cos 1(2 ~c + T ) ]
In relation (8), the term cos 2 ~ ct represents twice the carrier frequency.
The signal s3(t) provided by modulator 57 is fed to narrow-band filter 58 which is centered at twice the carrier frequency and elimin-ates the component representing the term cos l'2~ ct + T ) in relation (~). Accordingly, twice t:he carrier frequency is obtained at the output of f;lter 5~.
The output from filter 58 is fed to frequency divider 59, which provides the carrier frequency on line 36. This carrier frequency is used as in-phase reference carrier. This reference carrier, when its phase is shifted 90 by the 90 phase shifter 37, is used as ; quadrature reference carrier.
Before proceeding with the description of the operation of the device shown in figure 3, the data detection principle used by the receiver will be briefly discussed with respect to the diagrams of figure 2. At a given signaling instant, the received signal may be .:

~2656 1 represented by a point 7 in the diagrams of ~igure 2. (Forsimplicity, point Z has only been shown in the leftmost diagram).
The x and y coordinates of this point are representative of the in-phase and quadrature components, respectively, of the received signal.
Assuming an ideal transmission, point Z, representatiYe of the received signal, would coincide with point A, B, C or D repre-sentative of the transmitted signal. This does not happen in prac-tice and it is necessary to determine from point Z which of points A-D has been transmitted. In the receiver of the present invention, when modulation scheme 1 is used, that is, at even signaling instants, the decision will be made that point A, representative, for example, of a 1 bit, has been transmitted if the sum x~y of the components of the received signal is positive, and that point B, representative, for example, of a 0 bit, has been transmitted if the sum x+y is ; negative. This amounts to using the detection threshold illustrated by the axis designated "Ref.l" in the first diagram of figure 2. If modulation scheme 2 is used, that is, at odd signaling instants, the decision will be made that point C, representative, for example, of ; 20 a 1 bit, has been transmitted if the difference, y-x, between the components of the received signal is positive, and that point D, re-presentative of a 0 bit, has been transmitted if the difference y-x is negative. This amounts to using the detection threshold illus-trated by the "Ref.2" axis in the second diagram of figure 2. It is the clock signal prcvided by the clock and carrier recovery device ~ ;
35 which determines whether the received signal is to be detected in relation to modulation scheme 1 or modulation scheme 2.
Referring again to figure 3, the received waveform filtered by filter 31 is demodulated by the in-phase and quadrature reference carriers using demodulators 33 and 34. The in-phase and quadrature components, x and y, respectively, of the received signal are ob-tained at the output of demodulators 33 and 34, and take the form of - - - - :

Z6~i 1 baseband signal ele~ents which, ideally, would be id?ntical to the baseband signal elements available at the output of filters

3 and 7 in the transmitter of figure 1. Then, the in-phase and quadrature components of the received signal are conventionally applied to filters 39 and 40, respectively. The filtered in-phase component is subtracted from the filtered quadrature com-ponent in summing device 42. The filtered in-phase and quadrature components are summed in summing device 43. Thus, the sum x~y of the in-phase and quadrature components and the difference, y-x, between them are obtained at the output of devices 43 and 42, respectively. Limiters 45 and 46 provide the sign of the differ-ence between the components and that of their sum, respectively.
Referring to the diagrams of figure 2, it will be seen that if the signaling instant is even and if the sum x+y of the components is positive, this will mean that point A has been transmitted. At an even signaling instant, the sign of the sum x+y is representative of the data. Similarly, at an odd signaling instant~ the sign of the diff~rence y-x is representative of the data. The clock sig--; nal supplied by device 35 determines whether the signaling instant is even or odd. When the clock signal present on line 49 is up, the sign of the difference y-x is gated to the output of the receiver through AND gate 47 and OR gate 51, whereas when the clock signa~
on line 49 is down, the sign of the sum x+y is gated to the output ~ - of the receiver through AND 48 and OR 51.
The self-synchronization feature of the receiver of the inven-tion will now be described. It will be assumed that at a given sig- ;
naling instant a 1 bit is sent by transmitting the carrier whose com-\ -ponents are x=+l, y=+l, that is, by transmitting point A. In the absence of synchronization error, the clock signal present on line 49 will be down and the sign of the sum x+y, i.e. a positive sign, will be gated to the output of the receiver as representing a 1 bit. If ;
a synchronization error occurs, the clock signal on line 49 will be up, activating AND gate 48 and gating the sign of the difference y-x FR9-77-002 - 13 - :
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~L~ S 6 1 to the output of the receiver. However, a synchronization error means that an error equal to ~ alters the clock signal on line 63, which error results in the carrier present on line 36 exhibiting an error equal to ~/2. The carrier will rotate by ~/2 and the components of the point received will be x=-l and y=+l. Then, y-x will be equal to +2 and the sign of y-x will be positive. The output of the receiver will see a positive sign and detect a 1 bit.
Thus, a clock signal error will have no effects on data detection.
The receiver is, therefore, self-synchronized.
While the invention has been particularly shown and described with reference to a preferred embodiment thereof, it will be under-stood by those skilled in the art that numerous changes in form and detail may be made therein without departing from the spir;t and scope o~ the invention.

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Claims

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. In a data transmission system employing an interleaved binary phase shift keyed modulation technique wherein each of two values of a bit to be transmitted at an even signaling instant is made to correspond to a selected one of a first couple of points differing in phase by 180° in a space diagram illustrating the state of the carrier being transmitted, and wherein each of the two values of a bit to be transmitted at an odd signaling in-stant is made to correspond to a selected one of a second couple of points differing in phase by 180°, with the first and second couples of points being 90° apart in phase, a receiver including:
input means for receiving a signal from the transmission channel, means for extracting a reference carrier from said received signal, first demodulation means for demodulating said received sig-nal by means of said reference carrier, thereby providing an in-phase component of said signal, second demodulation means for demodulating said received signal by means of said reference carrier the phase of which has been shifted 90°, thereby providing a quadrature component of said signal, first summing means for providing a difference between said in-phase and quadrature components, second summing means for providing a sum of said in-phase and quadrature components, first detection means for providing a sign of said difference between said components, second detection means for providing a sign of said sum of said components means for extracting from said received signal a clock signal at half the signaling rate, and gating means for selectively gating the sign of said difference between said components or the sign of said sum of said components to the output of said receiver under control of said clock signal.

2. Receiver according to claim 1, wherein said means for extract-ing said clock signal includes:
means for detecting an envelope of said received signal, first narrow-band filter means for extracting a signal at the signaling frequency from a signal provided by said means for detecting said envelope of said received signal, and means for halving said signaling frequency, thereby providing a clock signal at half said signaling rate, and said means for extracting said reference carrier including:
means for doubling the frequency of said received signal, modulation means for modulating said signal the frequency of which has been doubled, by means of said clock signal at half said signaling rate, second narrow-band filter means for extracting a signal at twice the carrier frequency from the signal provided by said modulation means, and means for halving the frequency of said signal at twice the carrier frequency and for supplying said reference carrier.

3. Receiver according to claim 1, wherein said means for extract-ing said clock signal includes:
means for doubling the frequency of said received signal, first narrow-band filter means for extracting a signal at the signaling frequency from the signal provided by said means for doubling the frequency of said received signal, means for halving the frequency of said signal at the signaling frequency, thereby providing said clock signal at half the signaling rate, and said means for extracting said reference carrier including:
modulation means for modulating the received signal whose frequency has been doubled by means of said clock signal at half the signaling rate, second narrow-band filter means for extracting a signal at twice the carrier frequency from the signal provided by said modu-lation means, and means for halving the frequency of said signal at twice the carrier frequency, and for providing said reference carrier.