CA1100195A - Clock pulse generator with selective pulse delay and pulse width control - Google Patents
Clock pulse generator with selective pulse delay and pulse width controlInfo
- Publication number
- CA1100195A CA1100195A CA309,373A CA309373A CA1100195A CA 1100195 A CA1100195 A CA 1100195A CA 309373 A CA309373 A CA 309373A CA 1100195 A CA1100195 A CA 1100195A
- Authority
- CA
- Canada
- Prior art keywords
- pulse
- pulses
- delay
- selector
- delayed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/08—Clock generators with changeable or programmable clock frequency
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/04—Shaping pulses by increasing duration; by decreasing duration
- H03K5/06—Shaping pulses by increasing duration; by decreasing duration by the use of delay lines or other analogue delay elements
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/131—Digitally controlled
Abstract
CLOCK PULSE GENERATOR WITH SELECTIVE PULSE DELAY AND PULSE WIDTH CONTROL Clock generating apparatus for a computer system has selective pulse delay and pulse width control. Selection of pulse delay and pulse width is accomplished by loading registers with predetermined data patterns. The registers can be loaded under program control or by data entry units, such as a keyboard, switches, etc. The registers are located in coarse land fine pulse delay and pulse width adjustment units. These units have the same physical structure, but are functionally definable by a settable control element. A dither delay element is included in these coarse and fine adjustment units, and it is selectable to provide a small increment of delay. The coarse pulse delay and pulse width adjustment units also include pulse mode control circuitry to control operation in either normal oscillator mode or in single cycle mode.
Description
B = I =
Field of the Invention ¦ 20 This invention relates to clock pulse generating appara-tus and, more particularly, to clock pulse generating apparatus for computer systems with selective pulse delay (skew) and pulse width control. The requirement for adjusting pulse width and skew is accentuated in computer systems constructed from large scale integrated (LSI) circuitry. This is because LSI circuits have looser tolerances on device parameters than other circuit technologies~ Additionally, because of the mass number of circuits which can ,;
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Backgroulld of the Invention (continuecl) 1 reside on a single chip, an entlre logic path may be contained on
Field of the Invention ¦ 20 This invention relates to clock pulse generating appara-tus and, more particularly, to clock pulse generating apparatus for computer systems with selective pulse delay (skew) and pulse width control. The requirement for adjusting pulse width and skew is accentuated in computer systems constructed from large scale integrated (LSI) circuitry. This is because LSI circuits have looser tolerances on device parameters than other circuit technologies~ Additionally, because of the mass number of circuits which can ,;
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Backgroulld of the Invention (continuecl) 1 reside on a single chip, an entlre logic path may be contained on
2 the single chip. Thus, a given path may be slow on one chip and
3 fast on another chip, or the path may shrink a pulse on one chip
4 and expand the pulse on another. Further, there are pulse propa-gation delays, due to diEferent cable and wire lengths and pu]se 6 width variations, because of circuit delays. ~lence, by incorpor-7 ating the present invention into a computer system, the ease of 8 manufacture of the computer system is greatly enhanced. This is 9 because of the need to tune each computer system as a step in the manufacturing process, and the present invention greatly facili-11 tates this tuning. Also, after the computer system has been in 12 use, it may be necessary to retulle it, and the present invention 13 facilitates this retuning.
14 Description of _he Prior Art Pulse delay and pulse width adjustment is well known in 16 the prior art. Further, the prior art teaches apparatus Eor se-17 lecting the amount of delay; for example, the IBM Technical Dis-18 closure Bulletin, Volume 15, Number 1, dated June, 1972, pages 252-19 254, sets forth an electronically adjustable computer clocking system where the amount of pulse delay is selectable. This prior 21 art, however, does not teach selectable pulse width control whereby 22 skew and pulse width can be automatica~ly adjusted. U.S. Patent 3,440,546, 23 dated ~pril 22, 1969, entitled, "Variable Period and Pulse Width 24 Delay l/ined Pulse (~enerating System", sets forth pulse width con-trol. ~owever, such pulse width contro:l operates in a different 26 manner; i.e., the control is on the input to the delay element.
27 ']'he malmer ~or selectively varying the plllse width is thus dif-28 ferent. In the present invention, pulse width is controlled by use ; ¦ EN977-0~4 2 Background o~ the Invention (continuecl) 1 oE logic elements and a control register, whereas in Patent 3,440,546, 2 pulse width is controlled by the switching of a bistable device 3 from one state to another state. In that arrangement, the reso-4 lution ln pulse width cannot be as accurate as in the present invention, because the switching time o~ the bistable device has an ; 6 affect on the pulse width.
7 In general, there are other clock pulse tuning systems, 8 such as set forth in the ~sM Technical Disclosure sulletin, Volume 18, 9 Number 6, dated November, 1975, pages 1912-1913, entitled, "Computer --Clock Distribution System With Programmable Delay and Automatic 11 Adjustment". However, the systems do not have selective pulse 12 width adjustment. ~n the present invention, diffe~ent pulses from 13 the delay element are selected, and the selected pulses are com~
14 bined by log:ic to provide skew and pulse width adjustment.
SU~ARY OF THE I~IENTION
16 The principal objects oE the invention are to provide 17 improved pulse generating apparatus which: (a) has selective pulse 18 delay and pulse width control; (b~ utilizes a common circuit part 19 selectively settable to be either a coarse or a fine pulse width and pulse delay adjustment unit; (c) includes pulse mode control in 21 the coarse pulse width a~d pulse delay adjustment unit; (d) enables 22 dynmaic adjustment of pulse delay ancl pulse width, without physi-23 cally changing circuit connectic,ns and (e) provides skew ancl pulse -~ 24 w:idth adjustment with a high degree of resolution.
These objectives are achieved by apply-~ng pulses from a 26 free running oscillator to a delay element, such as a delay line.
27 Pulses appearing at various taps on the delay line are applied to ' I
I E~1977-004 3 ^ ~
Summary of the Invention (continued~
logic elements for both pulse delay adjustment and pulse ~idth 2 adjustment. These logic elements are conditioned by the outputs of 3 decoders fed by contents of registers which are set with prede-4 termined values. The outputs of the logic elements for the pulse
14 Description of _he Prior Art Pulse delay and pulse width adjustment is well known in 16 the prior art. Further, the prior art teaches apparatus Eor se-17 lecting the amount of delay; for example, the IBM Technical Dis-18 closure Bulletin, Volume 15, Number 1, dated June, 1972, pages 252-19 254, sets forth an electronically adjustable computer clocking system where the amount of pulse delay is selectable. This prior 21 art, however, does not teach selectable pulse width control whereby 22 skew and pulse width can be automatica~ly adjusted. U.S. Patent 3,440,546, 23 dated ~pril 22, 1969, entitled, "Variable Period and Pulse Width 24 Delay l/ined Pulse (~enerating System", sets forth pulse width con-trol. ~owever, such pulse width contro:l operates in a different 26 manner; i.e., the control is on the input to the delay element.
27 ']'he malmer ~or selectively varying the plllse width is thus dif-28 ferent. In the present invention, pulse width is controlled by use ; ¦ EN977-0~4 2 Background o~ the Invention (continuecl) 1 oE logic elements and a control register, whereas in Patent 3,440,546, 2 pulse width is controlled by the switching of a bistable device 3 from one state to another state. In that arrangement, the reso-4 lution ln pulse width cannot be as accurate as in the present invention, because the switching time o~ the bistable device has an ; 6 affect on the pulse width.
7 In general, there are other clock pulse tuning systems, 8 such as set forth in the ~sM Technical Disclosure sulletin, Volume 18, 9 Number 6, dated November, 1975, pages 1912-1913, entitled, "Computer --Clock Distribution System With Programmable Delay and Automatic 11 Adjustment". However, the systems do not have selective pulse 12 width adjustment. ~n the present invention, diffe~ent pulses from 13 the delay element are selected, and the selected pulses are com~
14 bined by log:ic to provide skew and pulse width adjustment.
SU~ARY OF THE I~IENTION
16 The principal objects oE the invention are to provide 17 improved pulse generating apparatus which: (a) has selective pulse 18 delay and pulse width control; (b~ utilizes a common circuit part 19 selectively settable to be either a coarse or a fine pulse width and pulse delay adjustment unit; (c) includes pulse mode control in 21 the coarse pulse width a~d pulse delay adjustment unit; (d) enables 22 dynmaic adjustment of pulse delay ancl pulse width, without physi-23 cally changing circuit connectic,ns and (e) provides skew ancl pulse -~ 24 w:idth adjustment with a high degree of resolution.
These objectives are achieved by apply-~ng pulses from a 26 free running oscillator to a delay element, such as a delay line.
27 Pulses appearing at various taps on the delay line are applied to ' I
I E~1977-004 3 ^ ~
Summary of the Invention (continued~
logic elements for both pulse delay adjustment and pulse ~idth 2 adjustment. These logic elements are conditioned by the outputs of 3 decoders fed by contents of registers which are set with prede-4 termined values. The outputs of the logic elements for the pulse
5~ delay and pulse ~idth adjustment are logically combined to result
6 in a pulse having -the desired skew and pulse width adjust~lent. The
7 Yalues in the registers can be set therein under program control,
8 or by manual entry devices, such as a keyboard, switches, etc. One
9 computer system may require one set of values in the registers for its skew and pulse width adjustment, while another computer system 11 might require a different set of values for skew and pulse width 12 adjustment during the tuning of the computer system. The registers 13 can be expanded so as to include a position for controlling whether 14 an adjustment unit is to be a coarse adjustment unit or a fine adjustment unit. If the pulse delay and pulse width adjustment 16 unit is controlled as a fine adjustment unit, the pulse mode con-17 trol circuitry is not enabled. Thus, a single unit or part number 18 can be used for a coarse or fine adjustment unit. The basic reason 19 for having coarse and fine adjustment units is that the coarse adjustment unit provides extra drive capability for the oscillator.
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21 DESCRIPTr~ OF TIIE DR~W-NGS
22 FIG. l is a block diagram illustrating the invention 23 embodied to include a s:ingle coarse adjustment unit and a plurality 24 of fine adjustment units having gated outputs;
FIG. 2 is a diagram illustrating details of the coarse 26- adjustment unit of FIG. l;
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i Description of t~le Drawings (continued) 1 FIG 3 is a diagram illustrating the details of the ~ine 2 adjustment Ullit of FTG 1, 3 FIG 4 is a timing diagram showing pulses at different 4 points in FIG l;
FIG 5 is a logic diagram illustrating details of the .. .
6 pulse mode control circuît within the coarse adjustment unit of 7 FIG 2;
8 FIG 6 is a block diagram illustrating the invention for 9 generating in-phase and out-of-phase, or even and odd pulses, to-gether with control circuitry for generating CPU, storage and 11 cl~annel gating signals;
12 FIG 7 is a block diagraln illustra~ing the invention 13 incorporated on a LSI chip, where the oscillator and the delay line 14 are located off-chip; and, FIG 8 is a timing diagram illustrating how a timing 16 pulse can be adjusted by the present invention for different func-17 tional unitS within a computer system 18 DESCRIPTION OF T~IE INVENTION
19 With reference to drawings, and particularly to ~IG. lS
the invention is illustrated by way of example as including an 21 oscillator 10, which provides sequentially occurring pulses at a 22 predetermined frequency. ~n oscillato~ pulse is illustrated ~y 23 wave form ~ in FIG. 4. The oscillator pulses are applied over 24 line 11 to a coarse adjustment unit 15. The function of the coarse adjustment unit 15 i8 to provide gross pulse skew and width adjust-26 ment for the pulses coming from oscillator 10 Coarse adjustment .
¦ EN977-004 5 .,, s Description oE tlle Invention (continued) 1 unit 15 does not change the repetition rate or frequency of the 2 pulses emanating from oscillator 10.
3 ` The timing pulses from coarse adjustment unit 15 are applied over line 37 to fine adjustment units 55 and to clock ga~e generator 80. The present invention does not require both coarse 6 and fine adjustment units, nor does it require a plurality of fine 7 adjustment units. The use of both coarse and fine adjustment 8 units, however, provides extra drive capability for the oscillator.
9 ~lthough a plurality of fine adjustment units may not be required, it is usually desirable to have different fine adjustment units for 11 different functional units within a computer system. ~or example, 12 one fine adjustment unit would provide timing pulses for the cen-13 tral processing un;t, while another fine adjustment unit would 14 provide tlming pulses for storage, and still another fine adjust-ment unit would provLde timing pulses for the channel.
16 Clock gate generator 80 uses the timing pulses from 17 coarse adjustment unit 15 for generating gating pulses, which are 18 applied over bus 81 to the fine adjustment units 55. Generally, in 19 a computer system, it is desirablé to provide gated clock pulses to the various functional units within the computer system. Normally, 21 the running of the computer clock is controlled by a clock run 22 signal. The clock run signal normally comes from control circuitry 23 within the computer system, and is applied to the clock gate generator 80 26 via input termInal 82. The clock gate generator 80 can consist of latches or polarity hold circuits connec-ted as a ring, and where 26 ~the output from the last latch or polarity hold circuit is fed back 27 ~to condition tbe first latch or polarity ho]d circuit in the ring.
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EN977-aO4 6 Description of the Invention (continued) 1 The clock run signal has a time duration to condition the setting 2 oE the first latch or polarity hold circuit, but terminates before 3 the next pulse comes along for setting the next or second latch o 4 the latch ring. The pulses for successively setting the latches or polarity hold circuits of the clock gate generator 80 are shown as 6 coming from the coarse adjustment 15. These pulses, of course, 7 could come from any one of the fine adjustment units 55 if a more 8 precise clock gating signal were desired.
9 The scan-in and shiEt terminals 12 and 13 are used for setting data values into the coarse adjustment and fine adjustment ll units 15 and 55 in a manner to be described shortly. Pulses can 12 also be generated in a single cycle mode. ~s will 'oe seen later 13 herein, in connection with the description of FIG. 5, whenever a 14 minus level voltage is applied to terminal 91, the clock is in-hibited; i.e., clock pulses are blocked from leaving the coarse 16 adjustment unit 15. Single cycle operation is controlled by op-17 erating single cycle switch 92. Single cycle switch operation will 18 be described în detail later herein.
19 The coarse adjustment unit 15, FIG. 2, includes a delay line 16, which, in this example, has ten output taps. The pulses 21 from oscillator 10 are ap?lied to the input of delay line 16 via 22 line ll. The output tapsi~rom delay line 16 provide pulses, spaced 23 from each other a predetermined amount. For example, a 22 nano-24 second delay lille divided into Len taps provides a del~y between pulses of 2.2 nanoseconds per tap. The outputs Erom delay line 16 26 and the pulses rom :Llne 11 are Eecl via bus 17 to pulse delay and EN~77-004 7 l .
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Description of the Invention (continued) l pulse width selectors 20 and 23. Selectors 20 and 23, in t'nis 2 example, include eleven ~ND circuits, which are selective]y con-3 ditioned by outputs from decoders ]9 and 22, respectively. De-4 coders 19 and 22 have inputs from latch rings 18 and 21, respec-tively. Latch rings 18 and 21 can be constructed from conventional 6 latches or from latches set forth in U.S. Patent 3,806,891, dated 7 ~pril 23, 197~, by Eichelberger, et al, for "Logic Circuit for Scan 8 In/Scan Out". Latch rings 18 and 21 are essentially connected as 9 one long shift register, where the output Erom the last latch in ring 18 is connected to the input of the first latch in ring 21.
11 The output of the last latch in ring 21 is connected to the Scan 12 Out line. The data pattern to be entered into latch rings 18 and 13 21 is serially applied to input terminal 12, and shift pulses for 14 shifting the data into the latch rings are applied to terminal 13.
The latches forming latch rings 18 and 21 can operate in both shiEt 16 register and nonshift register modes.
17 Normally, in a computer system, the predetermined value 18 to be entered into the latch rings 18 and 21 would be scanned into 19 these latch rings during initial program load of the computer system. The values to be set therein, o~ course, are obtained by 21 checking different points o the computer circuitry, such as by 22 means of oscilliscope, to determine the amount oE adj~lstment re-23 quired. Once knowing the amount of adjustment required, the values 24 for prod;lcing the required adjustment can be computed.
Pulse delay and pulse widtil selectors 20 and 23 each 26 include, in this particLlar exarnple, eleven ~ND circuits having 27 inputs from the eleven taps of delay line 16, and conditioned by Description oE the Invention (continued) 1 the eleven outputs of decoders 19 and 22, respectively. Tlle values 2 set into latch rings 18 and 21 will determine which of the AND
3 circuits in selectors 20 and 23 are conditioned. The outputs oE
4 the AND circuits in selectors 20 and 23 feed OR circuits which provide outputs on lines 24 and 25, respectively. The output 6 pulses appearing on lines 24 and 25 are represented ~y wave forms B
7 and C, respectively, in ~IG. 4. It should be noted that wave forms B and C are representitive only, and their occurrences in 9 time depend upon the values in latch rings 18 and 21, respectively.
The pulse from pulse delay selector 20 is applied via 11 line 24 to AND circuits 26 and 27. In a similar manner, the output 12 of pulse width selector 23 is applied via line 25 td ~ND circuits 30 13 and 31. AND circuits 26 and 30 feed NOR circuit 34 directly, 14 whereas ~ND circuits 27 and 31 feed NOR circuit 34 via dither-delay elemenets 29 and 33. These dither-delay elements have a delay of 16 one nanosecond. The last latch in latch rings 18 and 21 determine 17 ~hether or not the pulses from selectors 20 and 23 will pass through 18 dither-delay elements 29 and 33, respectively. The output ~rom the 19 last latch in ring 18 is applied directly to AND circuit 27, and is applied to ~ND circuit 26 via inverter 28. Hence, if this latch is 21 set to the zero state, AND circuit 26 is conditioned, and if set to 22 the one state, AND circuit 27 is conditioned. In a similar manner, 23 the output of the last latch in latch ring 21 is applied to ~ND
24 circuit 30 via inverter 32 and directly to ~ND circuit 31.
NOR circuit 34 tunctions to logically com~ine the two 26 input pulses that it receives. In this particular example, the 27 input pulses are negative-going pulses, and thus, the output from ' ¦~ EN977-004 9 .' j , .
s Descr:iptlon of the Invention (continued) 1 NOR circuit 34 is a positive-going pulse on line 35, as indicated 2 by wave form D, in FIG. 4. This positive-going pulse has a pulse ; 3 width CW, which is equal to the time interval during which both of 4 the two input pulses are negative. The coarse delay CD and the coarse pulse width CW for the coarse adjust-output pulses are given 6 by the following expressions:
7 CD = CH x aD (1) 8 C~ = 2 ~ ~D ~CH - CL) (2) 9 Where:
CD = Coarse ~djust Delay 11 CH = Tap Number of Higher Selected Delay Line lap 12 ~D = Time Delay ~etween Adjacent De:Lay Line Taps 13 CW = Coarse Wi.dth 14 P2 = 1/2 of Oscillator Period CL:= Tap Number of Lower Selected Delay Line Tap 16 In FIG. 2, selector 2~ selects the higher numbered tap 17 of delay line 16, and selector 23 selects the lower numbered tap of g 18 that delay line. Hence, selector 20 is termed the pulse delay 19 selector and selector 23 is the pulse width selector. Of course, the functions of selectors 20 and 23 could be reversed without ¦ 21 affecting the output from the coarse adjust unit 15. The coarse ;~
22 adjust unit 15 functions to chop the clock pulses more than neces-23 sary, so as to provide clock pulse separation. ~s :it will be seen 24 shortly, the ~ine adjust units 55 expand the pulses Erom coarse a~just unit 15 ~o provide clock pulses with the desirecl skew and 26 pulse ~Jidth adjustment.
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~ l~M977-004 10 Description of the Invention (colltinued) ~ 1 The pulse from I~OR circuit 34 iS appliecl vi~ line 35 to ; ~ 2 pulse mode control circuit 36, which permits either normal opera-3 tion or pulse mGde operation. For normal operation, pulse mode 4 control circuit 36 passes repeti~ive pulses appearing on line 35 to output line 37. Normal operation-is con~rolled by leaving set 6 pulse mode terminal 38 at a positive level. When terminal 38 is 7 lleld at a negative level, operation takes place in a pulse mode.
8 Pulse mode operation is used for diagnostic purposes. Pulse mode 9 control circuit 36, when operating in the pulse mode, allows a ~
single pulse on line 35 to pass to line 37, although repetitive 11 pulses are applied via line 35 to the pulse mode control circuit 36.
12 Hence, when terminal 38 is shifted to a negative level, pulse mode 13 control 36 blocks pulses from transferring from line 35 to line 37.
14 A single pulse can be transferred from line 35 to line 37 by op-eration of single cycle switch 39. In order Eor a pulse to pass 16 from line 35 to line 37, single cycle switch 39, which is a push-17 button type of switch, must be depressed and then released.
18 The details of the pulse mode control circuit 36 are 19 sho~n in FIG. 5. As previously indicated, the voltage level of terminal 38 is held at a positive value for normal operation.
21 Level control of terminal 38, of course, can be controlled by a 22 switch or a program bit; i.e., when the program bit is in the one 23 state, terminal 38 would be at a positlve level and when in the 24 zero state, terminal 38 would be at a negative level, or vice versa, the program bit states being a matter oE choice. In this 26 partlcular example, pulse mode circult 36 also contains a chip 27 select terminal whlch, as lt will be seen later herein, permits a I
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9~i Description of the InveQtion (continued) 1 common part to be used for both a coarse or fine adjustment unit.
2 The chip select terminal 40 is controlled by an additional scan 3 ring position, w~lich will be descri~ed in FIG. 7. Because the 4 pulse adjust unit 15 o~ FIG. 2 is designated as a coarse adjust unit, the chip select scan ring position is not shown or required.
6 In this instance, chip select 40 would be tied to a negative level.
7 Chip select terminal 40 feeds NOR circuit 41 and OR
8 circuits 42 and 43, as does pulse mode terminal 38. The single 9 cycle switch 39, which is at either a positive or negative le~el, feeds NOR circuit 41 and OR circuit 42. Pulses on line 35 are 11 applied to inverter 44 and NOR circuit 45. The OUtpllt of the 12 inverter 44 changes repetitively with the repetitive pulses on 13 line 35, and is applied to NOR circuit 46 which forms a latch with 14 NOR circuits 47 and 48. The output of NOR circuit 48, in addition to feeding back to NOR circuit 47, feeds NOR circuit 45, which also 16 has an input from NOR circuit 49. NOR circuit 49 receives inputs 17 from OR circuits 42 and 43. NOR circuit 41 feeds NOR circuits 46, 18 47, and NOR circuit 50, which forms a latch with NOR circuit 51.
l9 NOR circuit 50 also has an input from OR circuit 43. NOR circuit 51, in addition to receiving an input from NOR circuit SO, has an input 21 from NOR clrcuit 45, and the output of NOR circuit 51 feeds back to 22 an input of NOR circuit Sp. The output of NOR circuit SO is also 23 applied to inputs of NOR circuits 46 and 47.
24 Wben in the normal or run mode, pulse mode terminal 38 is at a positive voltage level, single cycle swi~ch 39 is at a 26 positive voltage level and chlp select terminal 40 is at a negative 27 vo]tage level. Thus, the OtltpUt of NOR circuit 41 :is at a negative .
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Description of tbe Invention (continucd) 1 level, an~ the outputs of OR circuits 42 and 43 are at positive 2 levels. The output of NOR circuits 49 and 50 are at negative 3 levels. The output of NOR circuit 46 is at a positive level when 4 the input pulse is present, i.e., the output of inverter 44 is at a negative level and the other inputs from NOR circuits 41 and 50 are 6 both at a negative level. The output of NOR circuit 48 will be at 7 a negative level, and will be held at this negative level by the 8 latch back path to NOR circuit 47, because the output of NOR cir-9 cuit 47 is a positive level, in that all of its inputs are at ~
negative levels. Thus, NOP~ circuit 45 will have its inputs from 11 NOR circuits 48 and 49 at negative levels, and the input from 12 line 35 will switch levels in accordance with the pulses appearing 13 thereon. Thus, the output of NOR circuit 45 will be at a negative 14 level when the pulse is present, and at a positive level ~hen the pulse is absent. The output of MOR circuit 51 is i~aterial during 16 normal mode operation.
17 When in the single cycle mode, pulse mode ter~inal 38 and 18 select terminal 40 are at a negati~e level. Further, assuming that 19 single cycle switch 3g is not pressed, the output of NOR circuit 41 is at a negative level. The output of OR circuit 42 is at a posi-21 tive level; ho~ever, the output of OR circuit 43 is at a negative 22 level. Thus, the output of NOR circuit 49 is at a negative level.
23 NOR circuit 50 has a posLtive output, and thus, the outputs of NOR
24 circuits 46 and 47 are at a nega~ive level.
When tlle pulse on Line 35 goes negative, the output of 26 NOR circuit 48 stays positive, and ~he output of NOR circuits 45 27 and 51 stay negative. Therefore, the latch forme(t by NOR circuits 50 ".
¦ EN977-004 13 : .
Description of the In~ention (continuecl~
1 and 51 stays i~l the same state. Then, the output on line 37 re-2 mains at the negative level. ~hen the switch SCS 3~ is operated, 3 the output of NOR 41 switches to a positive level, and tile output 4 lével of OR circuit 42 goes to a negative level. Thus, the output of NOR circuit 49 goes to a positive level, and the output of NOR
6 circuit 50 goes to a negative level. The output of NOR circuit 45 7 remains at the negative level, and hence, although the output oE
8 NOR circuit 51 switches to a positive level, no pulse is passed to 9 line 37 because ~OR circuit 45 remains at the negative level.
The output of NOR circuit 48 is at a positive level.
11 Then, upon release of the switch SCS 39, the output of NOR circuit 41 12 goes to a negative leve], and the output of OR 42 rëturns to the 13 positive level. The output of OR circuit 43 remains at the nega-14 tive level. Tl~e output of NOR circuit 49 goes to a negative level, and the output of NOR circuit 50 remains at the negative level.
16 The output of NOR circuit 46 is dependent upon the level passed by 17 inverter 44. When the pulse on line 35 is at a positive level, the 18 output of NOR circuit 46 goes positive. This causes the output of 19 NOR circuit 48 to go to a negative level. The output of NOR cir-cuit 45 remains at the negative level, but when the pulse on line 35 21 goes to a negative Ievel, the output of NOR circuit 45 goes to a 22 positive level. The output of NOR circuit 51 goes to a negative 23 level, and the output of NOR circuit 50 goes to a pos:itive level.
24 Thus, a single clock pulse on line 35 is passe~ to the output l:ine 37 by operation ancl re]ease of the single cycle switch 39 when 26 terminal 38 is at a negative level for pulse mode operation.
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EN977-Oa4 14 ~ 1 , .
, Description oE the Invention (continuecl) The pulses appearing on line 37 are applied to fine ad-2 just units 55. In this particular instance~ the coarse adjust 3 unit 15 has fifteen driver outputs, and thlls, is able to drive fif-4 teen fine adjust units 55. The pulses appearing on line 37 are 5~ applied to delay line 56 in each fine adjust unit 55 having de-: 6 tailed logic circuitr~, as illustrated in FIG. 3. Delay line 56 is 7 similar to delay line 16 of the coarse adjust unit 15, and has ten 8 taps which, together with a tap taken from line 37, form bus 57, 9 which feeds pulse delay selector 60 and pulse width selector 64.
Pulse delay and pulse width selectors 60 and 64 have eleven AND
11 circuits each, which have inputs from taps on delay line 56, and 12 are conditioned by outputs oE decoders 59 and 63, respectively.
13 Decoders 59 and 63 are fed by outputs of scan rings 58 and 62.
14 Scan rings 58 and 62 are similar to sc~n rings 18 and 21, and can ; 15 be set with values in the same manner as previously described in 16 connection wi.th scan rings 18 and 21.
17 The last position of scan ring 58 feeds inverter 66 and 18 AND circuit 68. The output of pulse delay selector 61 feeds AND
19 circuits 67 and 68. The output of AND circuit 67 feeds NOR cir-cuit 74 directly, whereas the output of AND circuit 68 feeds NOR
¦ 21 circuit 74 via dither-~elay 69. The pulse appearing at the output 22 of selector 60 on line 61 is represented by wave form E in FIG. 4.
23 Pul.se width selector 64 nas eleven AND circuits, which.
24 are fed by bus 57, and these hND circuits are conditioned by the outputs of decoder 63. Decoder 63 is Eed 'oy outputs of scan rin~ 62.
26 Pulse width selector 64 passes a pulse on line 65, which is repre-. ~
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Description of the Inve~tion (continued) 1 sented by wave form F in FIG. 4. The pulses passed by pulse width 2 selector 64 over line 65 are applied to ~ND circuits 71 and 72, 3 which are condi.tioned by the last positiorl oE scan ring 62. ~ND
4 circuit 71- is conditioned via inverter 70, and AND circuit 72 is conditioned directly from the last position of scan ring 62. The 6 output of AND circuit 71 feeds NOR circuit 74, and the output of 7 AND circuit 72 feeds NOR cîrcuit 74 via ditller-delay 73.
8 It should be noted that the pulses represented by wave 9 forms E and F are positive-going pulses, and thus, the NOR circu:it 74 passes a negative-going pulse, as represented by wave form G in 11 FIG. 4; The output of NOR circuit 74 is at a negative level during 12 the time that either of the pulses on lines 61 or 65 are at a 13 positive level. It is thus seen that the pulse represented by wave 14 form G has a greater width than the pulse which is fed over line 37 to the fine adjust unit 55. ~xcluding the effect of the dither-16 delay circuits 69 and 73, the amount o:E fine delay FD and fi.ne 17 width FW adjustment provided by the fine adjust unit 55 are given 18 by the following expressions:
19 FD = FL ~ ~D ~3) FW - CW + ~D (FH - FL) ~4) 21 Where:
22 FD = Fine ~djust Delay 23 FL = Tap Nu~lber o I.o~ler Se:Lected ~e:lay l.ine Tap 24 ~D = Time ~)elay Between ~djacent De:lay Line Taps FW = Eille ~lid th 26 Fll = Tap Number of lligher Se:Lect Delay l.ine Tap E.977-004 16 . .
s Description o.E the Illvention (continue~l) 1 Thus, any difference in the delay line taps selected by 2 selectors 60 and 64 functions to increase the width of the pulse 3 appearing at the output of NOR circuit 74. The additional delay, 4 which can be provided by each of the dither-delay circuits 69 and 73, is equal to one-half of ~D. In this particular example, the 6 additional dither-delay is equal to one nanosecond. Thus, the fine 7 delay or fine width c~n be additionally adjusted by one nanosecond.
8 The output of NOR circuit 74 feeds negative ~ND circuits 75, 9 76, 77 and 78. These negative AND circuits are conditioned by clock gates GO, Gl, G2 and G3, respectively. The clock gates GO, 11 Gl, G2 and G3 are provided by the clock gate generator 80 in FIG. 1.
12 Negative ~ND circuits 75, 76, 77 and 78 provide tilning pulses TO, 13 Tl T2 and T3, respectively, where timing pulse TO is illustrated by 14 wave form I, and is present when negative AND circuit 75 is con-lS ditioned by clock gate GO, represented by wave form H in FIG. 4.
16 The width of clock gate GO is selected so that it conditions as-17 sociated Degative AND circuit 75 for the range of different possible 18 delayed positions of the pulses passed by NOR circuit 74. The 19 clock gates GO-G3, inclusive, occur sequentially, and thus, the timing pulses TO-T3, occur sequentially.
21 In some computer systems, it is desirable to have a two-22 phase clock pulse generator, as set forth in FIG. 6. Oscillator 10, 23 in FIC. 6, feeds delays lOOa and lOab. Delays lOOa and lOOb function 24 to adjust time delays due to wi;ring distance differences. Delays lOOa and lOOb feed the coarse even and coarse ocld adjustment units 15a 26 and 15b, respectively. Coa-rse even and coarse odd ad~usLment 27 units 15a and 15b have two sets of outputs. One set of outputs '' .
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~ N977-aO4 17 '.', j .
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Descr:iption of the Invention (contin~led) includes two drivers which Eeed bus 110. The other set of outputs 2 includes fourteen drivers which feed bus 111. Bus 110 feeds two 3 delay elements represented by delay 1.12, and these two delay elements 4 feed two fine adjust units 55a and 55b. The coarse adjust units 15a and 15b and t.ile fine adjust units 55a and 55b have the structures 6 of the coarse adjust unit 15 and the fine adjust unit 55 illus-7 trated in FIG.'s 2 and 3, respectively. The two drivers in coarse 8 adjust units 15a and 15b which feed b~s 110, ho~ever, provide 9 adjusted pulses only in the normal and not in the pulse mode, because the pulses from fine adjust units 55a and 55b provide 11 storage refresh timing pulses. The storage refresh tirning pulses 12 must occur continuously. The fine even and fine odd adjust units 55a 13 and 55b are gated by clock gates from storage refresh clock ring 116, 14 which is controlled by storage refresh controls 115.
The fourteen drivers feeding bus 111, which feeds twelve 16 delay elements represented by delay 113, can pass coarse adjusted 17 pulses in either normal or pulse mode. Delay elements 112 and 113 18 function to adjust out wiring distance differences and delays due 19 to fine adjust chip differences. Delays 113 feed fine even and fine odd adjust units 55c. These fine even and fine odd adjust 21 units are gated by gates from gate unit 120. Gate unit 120 has 22 three types of gate inputs. Clock gate generator 124 provides CPU
23 gates T0, Tl, etc., via CPU gate control 121 and storage gates S0 24 Sl, ctc., via storage gate control 122. Clock gate gen~rator 125 provides channel gates C0, Cl, etc., via chamlel gate control 123.
26 CPU clock rlng counter 124 receives odd and even (pulse mode) 27 pulses from tlle outputs of fine even and fine odd ad,just unit 55c.
EN977-004 , 18 Description of the Invention (continued) 1 CPU clock ring counter 124 also has an input from clock controls 130.
2 It should be n~ted that clock controls 130 provide the pulse mode 3 signal whicLI is applied to the coarse even and coarse odd adjust 4 units 15a and 15b, which feed bus ]11. These particular coarse even and coarse odd adjust units can operate in the pulse mode.
6 ~lock controls 130 also provide a control signal to channel clock 7 ring counter 125. Clock controls 130 have additional control 8 inputs which are not pertinent to the present invention. '~hese 9 addltional inputs are labeled 'IOther CTRLS". Clock controls 130 also receive storage refresh timing pulses on line 131 for syn-11 chronization purposes.
12 The present invention can be implemented ln large scale 13 integration (LSI~ technology. A pulse width and pulse delay adjust 14 unit is shown in FIG. 7 as being incorporated in a single LSI chip.
This pulse delay and pulse width adjust chip has pulse width and 16 pulse delay scan rings 150 and 151. These scan rings have the same 17 function dS the scan rings described in connection with the coarse 18 adjust unit 15 of FIG. 2 and the fine adjust unit 55 of FIG. 3.
19 The oscillator and delay lines are located off-chip, and thus, are not shown in FIG. 7. The eleven signals from the oscillator and 21 delay line, not shown, are transmîtted via bus 152 to pulse delay 22 decoder and selector circuit 153, and to pulse widti~ decoder and 23 selector circuit 154. Tile pulse dela~ and pulse width decoder and 24 selector circuits 153 and 154 contain A~ clrcuits having inputs from bus 152, and inputs rom scan rings 150 and 151. In other 26 words, pulse delay decoder and selector clrc~lit 153 performs the -.i ,~ S
Description of the Invention (continued) 1 sarne function as decoder 19, and pulse delay selector 20 of FIG. 2 2 and decoder 59 and pulse delay selector 60 of FIG. 3. Similarly, 3 pulse width decoder and .selector circuit 154 performs the same ~ ~I function as decoder 22, and pu]se width selector 23 of FIG. 2 and 5 decoder 63 and pulse width selector 64 of ~IG. 3. The output of ' ` 6 pulse delay decoder and selector 153 is applied to OR invert cir-7 cuits 155 and 157. OR invert circuit 155 is conditioned by the . 8 ~ero bit position of scan ring 151~ and OR invert circuit 157 is 9 conditioned ~y this bit position via inverter 156. OR invert circuit 157 feeds dither-delay 158, and the output of dither-11 delay 158 is applied, together with the output of OR invert cir-12 cuit 155, to a DOT OR connection 159.
13 The output of pulse width decoder and selector circuit 154 14 is applied to OR invert circuits 160 and 161. OR invert circuit 160 is conditioned by the zero bit position of scan ring 150, and OR
16 invert circuit 161 is conditioned ~y this ~it position of scan 17 ring 150 via inverter 162. The output of OR invert circuit 161 s 18 feeds dither-delay 163. The output of dither-delay 163 is applied, 19 together with the output of OR invert circuit 160, to the DOT OR
.` 20 connection 159. The DOT OR connection 159 feeds pulse delay 165 . 1 21 and pulse mode control circu:it 170.
- 22 Pulse mode control circuit 170 functions in the same 23 manner as the pulse mode control circuit 36 of FIG. 2~ Pulse mode 24 control circuit 170 is rendered inoperative, however, i.f Lhe adjust 25 unit is to be a fine adjust unit. Latch 171 is conrlected to the 26 last position of scan ring 151, and its output determines tlle op-27 eration of pulse mode control circuit 170. The output of latch 171 .
~ ~ I EN977--004 20 , I ' , .
Description o~ tlle Inventiotl (continuecl) 1 is connected to a terminal, not snown, in pulse mode control cir~uit 70, 2 which has the same function as terminal 40 in ~IG. 5. ~[ence, if 3 latch 171 is set to the one state, pulse mode control circuit 170 4 could operate in the pulse mode, and the pulse delay and pulse width adjust chip becomes a fine adjust unit. On the other hand, 6 if latch 171 is set to the zero state, pulse mode control circuit 170 7 can operate in the pulse mode, and the pulse delay and pulse width 8 adjust unit ~ecomes a coarse adjust unit. The state oE latch 171, 9 of course, is program settableJ as are the states o~ latch rings 150 and 151. A scan-in operation, as previously described, is used to 11 set the states oE latcll rings 150 and 151 and the state of latch 171.
12 Pulse de]ay circuit 165 functions in a manner similar to the delay 13 circuits 112 in FIG. 6.
14 The output of pulse delay circuit 165 is applied to AND
circuits 175 and 177. These AND circuits are conditioned by the -16 output of latch 171. Hence, there will be an output from ~ND-17 circuits 175 and 177 only when latch 171 is set to the one state.
18 It should also be noted that latches 175 and 177 are conditioned by 19 gat;ng pulses applied over bus 166. The output of pulse mode 2Q control circuit 170 is applied to AND circuits 176 and 178, and to ¦ 21 groups of AND circu;ts 180, 185, l9O and 195. ~ND circuits 176 and 22 178 are conditioned ~y the output of latcn 171 via inverter 172.
23 llence, ~ND circuits 176 ancl 178 pass pulses Erom pulse mode control 24 circuit 17U when latch 171 is set to the zero state. AND circuits 176 and 178, as well as the ~roups of AND circuits 180, 185, l9O alld 26 195, are conditioned by the gating si~llals transmittecl over bus 166.
27 In this particular example, AND circults 175, 176, 177 and 178 are i ~P~ 3L9S;
Description of the Invention ~cont:iuued) 1 conditioned by a gate G5 signal. The groups oE AND circuits 180, 2 185, 190 and 195 are conditioned by gate G4, gate G3, ga~e G2 and 3 gate G0 signals, resp~ctively.
4 FIG. 8 illustrates the formation of a timing pulse which has been coarse adjusted by a pulse delay o~ zero and a pulse width 6 of 53 and flne adjusted with a pulse delay of 9 and a pulse width 7 of 7, plus a dither-delay. This timing pulse is illustrated as % being adjusted for the central processing unit, as contrasted to a 9 timing pulse adjusted for storage. The timing pulse adjusted for storage has the same coarse adjustment as the pulse for the CPU, 11 but has a fine adjustmènt with a delay of 3.
12 From the foregoing, it is seen that the invention pro-13 vides an improved pulse generating apparatus which has selective 14 pulse delay and pulse width control. Further, it is seen that the inventîon enables dynamic adjustment of pulse delay and pulse width 16 without physically changing circuit connections. It is also seen 17 that the invention provides skew and pulse width adjustment with a 18 high degree of resolution. The invention includes pulse mode 19 control in the coarse pulse width and pulse delay adjustment unit.
; 20 It is also seen that the invention can utilize a common circuit 21 part 5electively settable to be either a coarse or a fine pulse 22 width all~ pulse delay adjustment unit.
I EN977-0~4 22 ,
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21 DESCRIPTr~ OF TIIE DR~W-NGS
22 FIG. l is a block diagram illustrating the invention 23 embodied to include a s:ingle coarse adjustment unit and a plurality 24 of fine adjustment units having gated outputs;
FIG. 2 is a diagram illustrating details of the coarse 26- adjustment unit of FIG. l;
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i Description of t~le Drawings (continued) 1 FIG 3 is a diagram illustrating the details of the ~ine 2 adjustment Ullit of FTG 1, 3 FIG 4 is a timing diagram showing pulses at different 4 points in FIG l;
FIG 5 is a logic diagram illustrating details of the .. .
6 pulse mode control circuît within the coarse adjustment unit of 7 FIG 2;
8 FIG 6 is a block diagram illustrating the invention for 9 generating in-phase and out-of-phase, or even and odd pulses, to-gether with control circuitry for generating CPU, storage and 11 cl~annel gating signals;
12 FIG 7 is a block diagraln illustra~ing the invention 13 incorporated on a LSI chip, where the oscillator and the delay line 14 are located off-chip; and, FIG 8 is a timing diagram illustrating how a timing 16 pulse can be adjusted by the present invention for different func-17 tional unitS within a computer system 18 DESCRIPTION OF T~IE INVENTION
19 With reference to drawings, and particularly to ~IG. lS
the invention is illustrated by way of example as including an 21 oscillator 10, which provides sequentially occurring pulses at a 22 predetermined frequency. ~n oscillato~ pulse is illustrated ~y 23 wave form ~ in FIG. 4. The oscillator pulses are applied over 24 line 11 to a coarse adjustment unit 15. The function of the coarse adjustment unit 15 i8 to provide gross pulse skew and width adjust-26 ment for the pulses coming from oscillator 10 Coarse adjustment .
¦ EN977-004 5 .,, s Description oE tlle Invention (continued) 1 unit 15 does not change the repetition rate or frequency of the 2 pulses emanating from oscillator 10.
3 ` The timing pulses from coarse adjustment unit 15 are applied over line 37 to fine adjustment units 55 and to clock ga~e generator 80. The present invention does not require both coarse 6 and fine adjustment units, nor does it require a plurality of fine 7 adjustment units. The use of both coarse and fine adjustment 8 units, however, provides extra drive capability for the oscillator.
9 ~lthough a plurality of fine adjustment units may not be required, it is usually desirable to have different fine adjustment units for 11 different functional units within a computer system. ~or example, 12 one fine adjustment unit would provide timing pulses for the cen-13 tral processing un;t, while another fine adjustment unit would 14 provide tlming pulses for storage, and still another fine adjust-ment unit would provLde timing pulses for the channel.
16 Clock gate generator 80 uses the timing pulses from 17 coarse adjustment unit 15 for generating gating pulses, which are 18 applied over bus 81 to the fine adjustment units 55. Generally, in 19 a computer system, it is desirablé to provide gated clock pulses to the various functional units within the computer system. Normally, 21 the running of the computer clock is controlled by a clock run 22 signal. The clock run signal normally comes from control circuitry 23 within the computer system, and is applied to the clock gate generator 80 26 via input termInal 82. The clock gate generator 80 can consist of latches or polarity hold circuits connec-ted as a ring, and where 26 ~the output from the last latch or polarity hold circuit is fed back 27 ~to condition tbe first latch or polarity ho]d circuit in the ring.
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EN977-aO4 6 Description of the Invention (continued) 1 The clock run signal has a time duration to condition the setting 2 oE the first latch or polarity hold circuit, but terminates before 3 the next pulse comes along for setting the next or second latch o 4 the latch ring. The pulses for successively setting the latches or polarity hold circuits of the clock gate generator 80 are shown as 6 coming from the coarse adjustment 15. These pulses, of course, 7 could come from any one of the fine adjustment units 55 if a more 8 precise clock gating signal were desired.
9 The scan-in and shiEt terminals 12 and 13 are used for setting data values into the coarse adjustment and fine adjustment ll units 15 and 55 in a manner to be described shortly. Pulses can 12 also be generated in a single cycle mode. ~s will 'oe seen later 13 herein, in connection with the description of FIG. 5, whenever a 14 minus level voltage is applied to terminal 91, the clock is in-hibited; i.e., clock pulses are blocked from leaving the coarse 16 adjustment unit 15. Single cycle operation is controlled by op-17 erating single cycle switch 92. Single cycle switch operation will 18 be described în detail later herein.
19 The coarse adjustment unit 15, FIG. 2, includes a delay line 16, which, in this example, has ten output taps. The pulses 21 from oscillator 10 are ap?lied to the input of delay line 16 via 22 line ll. The output tapsi~rom delay line 16 provide pulses, spaced 23 from each other a predetermined amount. For example, a 22 nano-24 second delay lille divided into Len taps provides a del~y between pulses of 2.2 nanoseconds per tap. The outputs Erom delay line 16 26 and the pulses rom :Llne 11 are Eecl via bus 17 to pulse delay and EN~77-004 7 l .
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Description of the Invention (continued) l pulse width selectors 20 and 23. Selectors 20 and 23, in t'nis 2 example, include eleven ~ND circuits, which are selective]y con-3 ditioned by outputs from decoders ]9 and 22, respectively. De-4 coders 19 and 22 have inputs from latch rings 18 and 21, respec-tively. Latch rings 18 and 21 can be constructed from conventional 6 latches or from latches set forth in U.S. Patent 3,806,891, dated 7 ~pril 23, 197~, by Eichelberger, et al, for "Logic Circuit for Scan 8 In/Scan Out". Latch rings 18 and 21 are essentially connected as 9 one long shift register, where the output Erom the last latch in ring 18 is connected to the input of the first latch in ring 21.
11 The output of the last latch in ring 21 is connected to the Scan 12 Out line. The data pattern to be entered into latch rings 18 and 13 21 is serially applied to input terminal 12, and shift pulses for 14 shifting the data into the latch rings are applied to terminal 13.
The latches forming latch rings 18 and 21 can operate in both shiEt 16 register and nonshift register modes.
17 Normally, in a computer system, the predetermined value 18 to be entered into the latch rings 18 and 21 would be scanned into 19 these latch rings during initial program load of the computer system. The values to be set therein, o~ course, are obtained by 21 checking different points o the computer circuitry, such as by 22 means of oscilliscope, to determine the amount oE adj~lstment re-23 quired. Once knowing the amount of adjustment required, the values 24 for prod;lcing the required adjustment can be computed.
Pulse delay and pulse widtil selectors 20 and 23 each 26 include, in this particLlar exarnple, eleven ~ND circuits having 27 inputs from the eleven taps of delay line 16, and conditioned by Description oE the Invention (continued) 1 the eleven outputs of decoders 19 and 22, respectively. Tlle values 2 set into latch rings 18 and 21 will determine which of the AND
3 circuits in selectors 20 and 23 are conditioned. The outputs oE
4 the AND circuits in selectors 20 and 23 feed OR circuits which provide outputs on lines 24 and 25, respectively. The output 6 pulses appearing on lines 24 and 25 are represented ~y wave forms B
7 and C, respectively, in ~IG. 4. It should be noted that wave forms B and C are representitive only, and their occurrences in 9 time depend upon the values in latch rings 18 and 21, respectively.
The pulse from pulse delay selector 20 is applied via 11 line 24 to AND circuits 26 and 27. In a similar manner, the output 12 of pulse width selector 23 is applied via line 25 td ~ND circuits 30 13 and 31. AND circuits 26 and 30 feed NOR circuit 34 directly, 14 whereas ~ND circuits 27 and 31 feed NOR circuit 34 via dither-delay elemenets 29 and 33. These dither-delay elements have a delay of 16 one nanosecond. The last latch in latch rings 18 and 21 determine 17 ~hether or not the pulses from selectors 20 and 23 will pass through 18 dither-delay elements 29 and 33, respectively. The output ~rom the 19 last latch in ring 18 is applied directly to AND circuit 27, and is applied to ~ND circuit 26 via inverter 28. Hence, if this latch is 21 set to the zero state, AND circuit 26 is conditioned, and if set to 22 the one state, AND circuit 27 is conditioned. In a similar manner, 23 the output of the last latch in latch ring 21 is applied to ~ND
24 circuit 30 via inverter 32 and directly to ~ND circuit 31.
NOR circuit 34 tunctions to logically com~ine the two 26 input pulses that it receives. In this particular example, the 27 input pulses are negative-going pulses, and thus, the output from ' ¦~ EN977-004 9 .' j , .
s Descr:iptlon of the Invention (continued) 1 NOR circuit 34 is a positive-going pulse on line 35, as indicated 2 by wave form D, in FIG. 4. This positive-going pulse has a pulse ; 3 width CW, which is equal to the time interval during which both of 4 the two input pulses are negative. The coarse delay CD and the coarse pulse width CW for the coarse adjust-output pulses are given 6 by the following expressions:
7 CD = CH x aD (1) 8 C~ = 2 ~ ~D ~CH - CL) (2) 9 Where:
CD = Coarse ~djust Delay 11 CH = Tap Number of Higher Selected Delay Line lap 12 ~D = Time Delay ~etween Adjacent De:Lay Line Taps 13 CW = Coarse Wi.dth 14 P2 = 1/2 of Oscillator Period CL:= Tap Number of Lower Selected Delay Line Tap 16 In FIG. 2, selector 2~ selects the higher numbered tap 17 of delay line 16, and selector 23 selects the lower numbered tap of g 18 that delay line. Hence, selector 20 is termed the pulse delay 19 selector and selector 23 is the pulse width selector. Of course, the functions of selectors 20 and 23 could be reversed without ¦ 21 affecting the output from the coarse adjust unit 15. The coarse ;~
22 adjust unit 15 functions to chop the clock pulses more than neces-23 sary, so as to provide clock pulse separation. ~s :it will be seen 24 shortly, the ~ine adjust units 55 expand the pulses Erom coarse a~just unit 15 ~o provide clock pulses with the desirecl skew and 26 pulse ~Jidth adjustment.
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~ l~M977-004 10 Description of the Invention (colltinued) ~ 1 The pulse from I~OR circuit 34 iS appliecl vi~ line 35 to ; ~ 2 pulse mode control circuit 36, which permits either normal opera-3 tion or pulse mGde operation. For normal operation, pulse mode 4 control circuit 36 passes repeti~ive pulses appearing on line 35 to output line 37. Normal operation-is con~rolled by leaving set 6 pulse mode terminal 38 at a positive level. When terminal 38 is 7 lleld at a negative level, operation takes place in a pulse mode.
8 Pulse mode operation is used for diagnostic purposes. Pulse mode 9 control circuit 36, when operating in the pulse mode, allows a ~
single pulse on line 35 to pass to line 37, although repetitive 11 pulses are applied via line 35 to the pulse mode control circuit 36.
12 Hence, when terminal 38 is shifted to a negative level, pulse mode 13 control 36 blocks pulses from transferring from line 35 to line 37.
14 A single pulse can be transferred from line 35 to line 37 by op-eration of single cycle switch 39. In order Eor a pulse to pass 16 from line 35 to line 37, single cycle switch 39, which is a push-17 button type of switch, must be depressed and then released.
18 The details of the pulse mode control circuit 36 are 19 sho~n in FIG. 5. As previously indicated, the voltage level of terminal 38 is held at a positive value for normal operation.
21 Level control of terminal 38, of course, can be controlled by a 22 switch or a program bit; i.e., when the program bit is in the one 23 state, terminal 38 would be at a positlve level and when in the 24 zero state, terminal 38 would be at a negative level, or vice versa, the program bit states being a matter oE choice. In this 26 partlcular example, pulse mode circult 36 also contains a chip 27 select terminal whlch, as lt will be seen later herein, permits a I
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9~i Description of the InveQtion (continued) 1 common part to be used for both a coarse or fine adjustment unit.
2 The chip select terminal 40 is controlled by an additional scan 3 ring position, w~lich will be descri~ed in FIG. 7. Because the 4 pulse adjust unit 15 o~ FIG. 2 is designated as a coarse adjust unit, the chip select scan ring position is not shown or required.
6 In this instance, chip select 40 would be tied to a negative level.
7 Chip select terminal 40 feeds NOR circuit 41 and OR
8 circuits 42 and 43, as does pulse mode terminal 38. The single 9 cycle switch 39, which is at either a positive or negative le~el, feeds NOR circuit 41 and OR circuit 42. Pulses on line 35 are 11 applied to inverter 44 and NOR circuit 45. The OUtpllt of the 12 inverter 44 changes repetitively with the repetitive pulses on 13 line 35, and is applied to NOR circuit 46 which forms a latch with 14 NOR circuits 47 and 48. The output of NOR circuit 48, in addition to feeding back to NOR circuit 47, feeds NOR circuit 45, which also 16 has an input from NOR circuit 49. NOR circuit 49 receives inputs 17 from OR circuits 42 and 43. NOR circuit 41 feeds NOR circuits 46, 18 47, and NOR circuit 50, which forms a latch with NOR circuit 51.
l9 NOR circuit 50 also has an input from OR circuit 43. NOR circuit 51, in addition to receiving an input from NOR circuit SO, has an input 21 from NOR clrcuit 45, and the output of NOR circuit 51 feeds back to 22 an input of NOR circuit Sp. The output of NOR circuit SO is also 23 applied to inputs of NOR circuits 46 and 47.
24 Wben in the normal or run mode, pulse mode terminal 38 is at a positive voltage level, single cycle swi~ch 39 is at a 26 positive voltage level and chlp select terminal 40 is at a negative 27 vo]tage level. Thus, the OtltpUt of NOR circuit 41 :is at a negative .
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Description of tbe Invention (continucd) 1 level, an~ the outputs of OR circuits 42 and 43 are at positive 2 levels. The output of NOR circuits 49 and 50 are at negative 3 levels. The output of NOR circuit 46 is at a positive level when 4 the input pulse is present, i.e., the output of inverter 44 is at a negative level and the other inputs from NOR circuits 41 and 50 are 6 both at a negative level. The output of NOR circuit 48 will be at 7 a negative level, and will be held at this negative level by the 8 latch back path to NOR circuit 47, because the output of NOR cir-9 cuit 47 is a positive level, in that all of its inputs are at ~
negative levels. Thus, NOP~ circuit 45 will have its inputs from 11 NOR circuits 48 and 49 at negative levels, and the input from 12 line 35 will switch levels in accordance with the pulses appearing 13 thereon. Thus, the output of NOR circuit 45 will be at a negative 14 level when the pulse is present, and at a positive level ~hen the pulse is absent. The output of MOR circuit 51 is i~aterial during 16 normal mode operation.
17 When in the single cycle mode, pulse mode ter~inal 38 and 18 select terminal 40 are at a negati~e level. Further, assuming that 19 single cycle switch 3g is not pressed, the output of NOR circuit 41 is at a negative level. The output of OR circuit 42 is at a posi-21 tive level; ho~ever, the output of OR circuit 43 is at a negative 22 level. Thus, the output of NOR circuit 49 is at a negative level.
23 NOR circuit 50 has a posLtive output, and thus, the outputs of NOR
24 circuits 46 and 47 are at a nega~ive level.
When tlle pulse on Line 35 goes negative, the output of 26 NOR circuit 48 stays positive, and ~he output of NOR circuits 45 27 and 51 stay negative. Therefore, the latch forme(t by NOR circuits 50 ".
¦ EN977-004 13 : .
Description of the In~ention (continuecl~
1 and 51 stays i~l the same state. Then, the output on line 37 re-2 mains at the negative level. ~hen the switch SCS 3~ is operated, 3 the output of NOR 41 switches to a positive level, and tile output 4 lével of OR circuit 42 goes to a negative level. Thus, the output of NOR circuit 49 goes to a positive level, and the output of NOR
6 circuit 50 goes to a negative level. The output of NOR circuit 45 7 remains at the negative level, and hence, although the output oE
8 NOR circuit 51 switches to a positive level, no pulse is passed to 9 line 37 because ~OR circuit 45 remains at the negative level.
The output of NOR circuit 48 is at a positive level.
11 Then, upon release of the switch SCS 39, the output of NOR circuit 41 12 goes to a negative leve], and the output of OR 42 rëturns to the 13 positive level. The output of OR circuit 43 remains at the nega-14 tive level. Tl~e output of NOR circuit 49 goes to a negative level, and the output of NOR circuit 50 remains at the negative level.
16 The output of NOR circuit 46 is dependent upon the level passed by 17 inverter 44. When the pulse on line 35 is at a positive level, the 18 output of NOR circuit 46 goes positive. This causes the output of 19 NOR circuit 48 to go to a negative level. The output of NOR cir-cuit 45 remains at the negative level, but when the pulse on line 35 21 goes to a negative Ievel, the output of NOR circuit 45 goes to a 22 positive level. The output of NOR circuit 51 goes to a negative 23 level, and the output of NOR circuit 50 goes to a pos:itive level.
24 Thus, a single clock pulse on line 35 is passe~ to the output l:ine 37 by operation ancl re]ease of the single cycle switch 39 when 26 terminal 38 is at a negative level for pulse mode operation.
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EN977-Oa4 14 ~ 1 , .
, Description oE the Invention (continuecl) The pulses appearing on line 37 are applied to fine ad-2 just units 55. In this particular instance~ the coarse adjust 3 unit 15 has fifteen driver outputs, and thlls, is able to drive fif-4 teen fine adjust units 55. The pulses appearing on line 37 are 5~ applied to delay line 56 in each fine adjust unit 55 having de-: 6 tailed logic circuitr~, as illustrated in FIG. 3. Delay line 56 is 7 similar to delay line 16 of the coarse adjust unit 15, and has ten 8 taps which, together with a tap taken from line 37, form bus 57, 9 which feeds pulse delay selector 60 and pulse width selector 64.
Pulse delay and pulse width selectors 60 and 64 have eleven AND
11 circuits each, which have inputs from taps on delay line 56, and 12 are conditioned by outputs oE decoders 59 and 63, respectively.
13 Decoders 59 and 63 are fed by outputs of scan rings 58 and 62.
14 Scan rings 58 and 62 are similar to sc~n rings 18 and 21, and can ; 15 be set with values in the same manner as previously described in 16 connection wi.th scan rings 18 and 21.
17 The last position of scan ring 58 feeds inverter 66 and 18 AND circuit 68. The output of pulse delay selector 61 feeds AND
19 circuits 67 and 68. The output of AND circuit 67 feeds NOR cir-cuit 74 directly, whereas the output of AND circuit 68 feeds NOR
¦ 21 circuit 74 via dither-~elay 69. The pulse appearing at the output 22 of selector 60 on line 61 is represented by wave form E in FIG. 4.
23 Pul.se width selector 64 nas eleven AND circuits, which.
24 are fed by bus 57, and these hND circuits are conditioned by the outputs of decoder 63. Decoder 63 is Eed 'oy outputs of scan rin~ 62.
26 Pulse width selector 64 passes a pulse on line 65, which is repre-. ~
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Description of the Inve~tion (continued) 1 sented by wave form F in FIG. 4. The pulses passed by pulse width 2 selector 64 over line 65 are applied to ~ND circuits 71 and 72, 3 which are condi.tioned by the last positiorl oE scan ring 62. ~ND
4 circuit 71- is conditioned via inverter 70, and AND circuit 72 is conditioned directly from the last position of scan ring 62. The 6 output of AND circuit 71 feeds NOR circuit 74, and the output of 7 AND circuit 72 feeds NOR cîrcuit 74 via ditller-delay 73.
8 It should be noted that the pulses represented by wave 9 forms E and F are positive-going pulses, and thus, the NOR circu:it 74 passes a negative-going pulse, as represented by wave form G in 11 FIG. 4; The output of NOR circuit 74 is at a negative level during 12 the time that either of the pulses on lines 61 or 65 are at a 13 positive level. It is thus seen that the pulse represented by wave 14 form G has a greater width than the pulse which is fed over line 37 to the fine adjust unit 55. ~xcluding the effect of the dither-16 delay circuits 69 and 73, the amount o:E fine delay FD and fi.ne 17 width FW adjustment provided by the fine adjust unit 55 are given 18 by the following expressions:
19 FD = FL ~ ~D ~3) FW - CW + ~D (FH - FL) ~4) 21 Where:
22 FD = Fine ~djust Delay 23 FL = Tap Nu~lber o I.o~ler Se:Lected ~e:lay l.ine Tap 24 ~D = Time ~)elay Between ~djacent De:lay Line Taps FW = Eille ~lid th 26 Fll = Tap Number of lligher Se:Lect Delay l.ine Tap E.977-004 16 . .
s Description o.E the Illvention (continue~l) 1 Thus, any difference in the delay line taps selected by 2 selectors 60 and 64 functions to increase the width of the pulse 3 appearing at the output of NOR circuit 74. The additional delay, 4 which can be provided by each of the dither-delay circuits 69 and 73, is equal to one-half of ~D. In this particular example, the 6 additional dither-delay is equal to one nanosecond. Thus, the fine 7 delay or fine width c~n be additionally adjusted by one nanosecond.
8 The output of NOR circuit 74 feeds negative ~ND circuits 75, 9 76, 77 and 78. These negative AND circuits are conditioned by clock gates GO, Gl, G2 and G3, respectively. The clock gates GO, 11 Gl, G2 and G3 are provided by the clock gate generator 80 in FIG. 1.
12 Negative ~ND circuits 75, 76, 77 and 78 provide tilning pulses TO, 13 Tl T2 and T3, respectively, where timing pulse TO is illustrated by 14 wave form I, and is present when negative AND circuit 75 is con-lS ditioned by clock gate GO, represented by wave form H in FIG. 4.
16 The width of clock gate GO is selected so that it conditions as-17 sociated Degative AND circuit 75 for the range of different possible 18 delayed positions of the pulses passed by NOR circuit 74. The 19 clock gates GO-G3, inclusive, occur sequentially, and thus, the timing pulses TO-T3, occur sequentially.
21 In some computer systems, it is desirable to have a two-22 phase clock pulse generator, as set forth in FIG. 6. Oscillator 10, 23 in FIC. 6, feeds delays lOOa and lOab. Delays lOOa and lOOb function 24 to adjust time delays due to wi;ring distance differences. Delays lOOa and lOOb feed the coarse even and coarse ocld adjustment units 15a 26 and 15b, respectively. Coa-rse even and coarse odd ad~usLment 27 units 15a and 15b have two sets of outputs. One set of outputs '' .
~, , .
~ N977-aO4 17 '.', j .
- . .
Descr:iption of the Invention (contin~led) includes two drivers which Eeed bus 110. The other set of outputs 2 includes fourteen drivers which feed bus 111. Bus 110 feeds two 3 delay elements represented by delay 1.12, and these two delay elements 4 feed two fine adjust units 55a and 55b. The coarse adjust units 15a and 15b and t.ile fine adjust units 55a and 55b have the structures 6 of the coarse adjust unit 15 and the fine adjust unit 55 illus-7 trated in FIG.'s 2 and 3, respectively. The two drivers in coarse 8 adjust units 15a and 15b which feed b~s 110, ho~ever, provide 9 adjusted pulses only in the normal and not in the pulse mode, because the pulses from fine adjust units 55a and 55b provide 11 storage refresh timing pulses. The storage refresh tirning pulses 12 must occur continuously. The fine even and fine odd adjust units 55a 13 and 55b are gated by clock gates from storage refresh clock ring 116, 14 which is controlled by storage refresh controls 115.
The fourteen drivers feeding bus 111, which feeds twelve 16 delay elements represented by delay 113, can pass coarse adjusted 17 pulses in either normal or pulse mode. Delay elements 112 and 113 18 function to adjust out wiring distance differences and delays due 19 to fine adjust chip differences. Delays 113 feed fine even and fine odd adjust units 55c. These fine even and fine odd adjust 21 units are gated by gates from gate unit 120. Gate unit 120 has 22 three types of gate inputs. Clock gate generator 124 provides CPU
23 gates T0, Tl, etc., via CPU gate control 121 and storage gates S0 24 Sl, ctc., via storage gate control 122. Clock gate gen~rator 125 provides channel gates C0, Cl, etc., via chamlel gate control 123.
26 CPU clock rlng counter 124 receives odd and even (pulse mode) 27 pulses from tlle outputs of fine even and fine odd ad,just unit 55c.
EN977-004 , 18 Description of the Invention (continued) 1 CPU clock ring counter 124 also has an input from clock controls 130.
2 It should be n~ted that clock controls 130 provide the pulse mode 3 signal whicLI is applied to the coarse even and coarse odd adjust 4 units 15a and 15b, which feed bus ]11. These particular coarse even and coarse odd adjust units can operate in the pulse mode.
6 ~lock controls 130 also provide a control signal to channel clock 7 ring counter 125. Clock controls 130 have additional control 8 inputs which are not pertinent to the present invention. '~hese 9 addltional inputs are labeled 'IOther CTRLS". Clock controls 130 also receive storage refresh timing pulses on line 131 for syn-11 chronization purposes.
12 The present invention can be implemented ln large scale 13 integration (LSI~ technology. A pulse width and pulse delay adjust 14 unit is shown in FIG. 7 as being incorporated in a single LSI chip.
This pulse delay and pulse width adjust chip has pulse width and 16 pulse delay scan rings 150 and 151. These scan rings have the same 17 function dS the scan rings described in connection with the coarse 18 adjust unit 15 of FIG. 2 and the fine adjust unit 55 of FIG. 3.
19 The oscillator and delay lines are located off-chip, and thus, are not shown in FIG. 7. The eleven signals from the oscillator and 21 delay line, not shown, are transmîtted via bus 152 to pulse delay 22 decoder and selector circuit 153, and to pulse widti~ decoder and 23 selector circuit 154. Tile pulse dela~ and pulse width decoder and 24 selector circuits 153 and 154 contain A~ clrcuits having inputs from bus 152, and inputs rom scan rings 150 and 151. In other 26 words, pulse delay decoder and selector clrc~lit 153 performs the -.i ,~ S
Description of the Invention (continued) 1 sarne function as decoder 19, and pulse delay selector 20 of FIG. 2 2 and decoder 59 and pulse delay selector 60 of FIG. 3. Similarly, 3 pulse width decoder and .selector circuit 154 performs the same ~ ~I function as decoder 22, and pu]se width selector 23 of FIG. 2 and 5 decoder 63 and pulse width selector 64 of ~IG. 3. The output of ' ` 6 pulse delay decoder and selector 153 is applied to OR invert cir-7 cuits 155 and 157. OR invert circuit 155 is conditioned by the . 8 ~ero bit position of scan ring 151~ and OR invert circuit 157 is 9 conditioned ~y this bit position via inverter 156. OR invert circuit 157 feeds dither-delay 158, and the output of dither-11 delay 158 is applied, together with the output of OR invert cir-12 cuit 155, to a DOT OR connection 159.
13 The output of pulse width decoder and selector circuit 154 14 is applied to OR invert circuits 160 and 161. OR invert circuit 160 is conditioned by the zero bit position of scan ring 150, and OR
16 invert circuit 161 is conditioned ~y this ~it position of scan 17 ring 150 via inverter 162. The output of OR invert circuit 161 s 18 feeds dither-delay 163. The output of dither-delay 163 is applied, 19 together with the output of OR invert circuit 160, to the DOT OR
.` 20 connection 159. The DOT OR connection 159 feeds pulse delay 165 . 1 21 and pulse mode control circu:it 170.
- 22 Pulse mode control circuit 170 functions in the same 23 manner as the pulse mode control circuit 36 of FIG. 2~ Pulse mode 24 control circuit 170 is rendered inoperative, however, i.f Lhe adjust 25 unit is to be a fine adjust unit. Latch 171 is conrlected to the 26 last position of scan ring 151, and its output determines tlle op-27 eration of pulse mode control circuit 170. The output of latch 171 .
~ ~ I EN977--004 20 , I ' , .
Description o~ tlle Inventiotl (continuecl) 1 is connected to a terminal, not snown, in pulse mode control cir~uit 70, 2 which has the same function as terminal 40 in ~IG. 5. ~[ence, if 3 latch 171 is set to the one state, pulse mode control circuit 170 4 could operate in the pulse mode, and the pulse delay and pulse width adjust chip becomes a fine adjust unit. On the other hand, 6 if latch 171 is set to the zero state, pulse mode control circuit 170 7 can operate in the pulse mode, and the pulse delay and pulse width 8 adjust unit ~ecomes a coarse adjust unit. The state oE latch 171, 9 of course, is program settableJ as are the states o~ latch rings 150 and 151. A scan-in operation, as previously described, is used to 11 set the states oE latcll rings 150 and 151 and the state of latch 171.
12 Pulse de]ay circuit 165 functions in a manner similar to the delay 13 circuits 112 in FIG. 6.
14 The output of pulse delay circuit 165 is applied to AND
circuits 175 and 177. These AND circuits are conditioned by the -16 output of latch 171. Hence, there will be an output from ~ND-17 circuits 175 and 177 only when latch 171 is set to the one state.
18 It should also be noted that latches 175 and 177 are conditioned by 19 gat;ng pulses applied over bus 166. The output of pulse mode 2Q control circuit 170 is applied to AND circuits 176 and 178, and to ¦ 21 groups of AND circu;ts 180, 185, l9O and 195. ~ND circuits 176 and 22 178 are conditioned ~y the output of latcn 171 via inverter 172.
23 llence, ~ND circuits 176 ancl 178 pass pulses Erom pulse mode control 24 circuit 17U when latch 171 is set to the zero state. AND circuits 176 and 178, as well as the ~roups of AND circuits 180, 185, l9O alld 26 195, are conditioned by the gating si~llals transmittecl over bus 166.
27 In this particular example, AND circults 175, 176, 177 and 178 are i ~P~ 3L9S;
Description of the Invention ~cont:iuued) 1 conditioned by a gate G5 signal. The groups oE AND circuits 180, 2 185, 190 and 195 are conditioned by gate G4, gate G3, ga~e G2 and 3 gate G0 signals, resp~ctively.
4 FIG. 8 illustrates the formation of a timing pulse which has been coarse adjusted by a pulse delay o~ zero and a pulse width 6 of 53 and flne adjusted with a pulse delay of 9 and a pulse width 7 of 7, plus a dither-delay. This timing pulse is illustrated as % being adjusted for the central processing unit, as contrasted to a 9 timing pulse adjusted for storage. The timing pulse adjusted for storage has the same coarse adjustment as the pulse for the CPU, 11 but has a fine adjustmènt with a delay of 3.
12 From the foregoing, it is seen that the invention pro-13 vides an improved pulse generating apparatus which has selective 14 pulse delay and pulse width control. Further, it is seen that the inventîon enables dynamic adjustment of pulse delay and pulse width 16 without physically changing circuit connections. It is also seen 17 that the invention provides skew and pulse width adjustment with a 18 high degree of resolution. The invention includes pulse mode 19 control in the coarse pulse width and pulse delay adjustment unit.
; 20 It is also seen that the invention can utilize a common circuit 21 part 5electively settable to be either a coarse or a fine pulse 22 width all~ pulse delay adjustment unit.
I EN977-0~4 22 ,
Claims (9)
- Claim 1 (continued) one control element of said second selector means, whereby the pulses generated by said logic circuit means depends upon which control elements of said first and second selector means are energized.
- 2. Tile clock pulse generating apparatus of Claim 1, wherein the pulse generated by said logic circuit means has a pulse width less than the pulse width of pulses from said first and second selector means.
- 3. The clock pulse generating apparatus of Claim 1, wherein the pulse generated by said logic circuit means has a pulse width greater than the pulse width of pulses from said first and second selector means.
- 4. The clock pulse generating apparatus of Claim 1, further comprising:
pulse mode control means connected to said logic circuit means and selectively operable in one mode to pass repetitive pulses generated by said logic circuit means and selectively operable in another mode to pass only a single pulse of said re-petitive pulses generated by said logic circuit means, and means for controlling selective operation of said mode control means in said one and another. modes.
5. The clock pulse generating apparatus of Claim 4, wherein said means for controlling selective operation of said mode - Claim 5 (continued) control means is a selectively settable binary element.
- 6. The clock pulse generating apparatus of Claim 1, further comprising:
first dither-delay circuit means for delaying pulses from said first selector means less than the amount of delay be-tween pulses of said set of delayed pulses before said pulses from said first selector means are applied to said logic circuit means, and selectively operable means for selectively applying delayed pulses from said first selector means to said first dither-delay means and for blocking pulses from passing directly from said first selector means to said logic circuit means. - 7. The clock pulse generating apparatus of Claim 6, further comprising:
second dither-delay circuit means for delaying pulses from said second selector means less than the amount of delay be-tween pulses of said set of delayed pulses before said pulses from said second selector means are applied to said logic means, and selectively operable means for selectively applying delayed pulses from said second selector means to said second dither-delay means and for blocking pulses from passing directly from said first selector means to said logic circuit means.
8. Clock pulse delay and pulse width adjusting apparatus for adjusting pulse delay and pulse width of a series of repetitive Claim 8 (continued) clock pulses emanating from a source of clock pulses in a pro-grammed computer system, the improvement comprising:
a delay line connected to receive said series of repeti-tive clock-pulses, and having a set of outputs for providing a set of delayed clock pulses for each received clock pulse, pulse delay selector means connected to said delay line to receive said set of delayed clock pulses and selectively op-erable to pass only one delayed pulse of said set of delayed pulses, pulse width selector means connected to said delay line to receive said set of delayed clock pulses and selectively op-erable to pass only one delayed pulse of said set of delayed pulses, pulse delay scan ring means settable under program con-trol for controlling selective operation of said pulse delay se-lector means, pulse width scan ring means settable under program con-trol, for controlling selective operation of said pulse width se-lector means, first dither-delay circuit means for delaying pulses from said pulse delay selector means less than the amount of delay between pulses of said set of delayed pulses, second dither-delay circuit means for delaying pulses from said pulse width selector means less than the amount of delay between pulses of said set of delayed pulses, logic circuit means for forming adjusted pulses from pulses passed by said pulse delay and said pulse width selector - Claim 8 (continued) means and said first and second dither-delay circuit means, first switch means connected to receive pulses from said pulse delay selector means and from said first dither-delay circuit means and selectively operable under control of said pulse delay scan ring means to pass either the pulse from said pulse delay selector means or the pulse from said first dither-delay circuit means to said logic circuit means, and second switch means connected to receive pulses from said pulse width selector means and from said second dither-delay cir-cuit means and selectively operable under control of said pulse width scarring means to pass either the pulse from said pulse width selector means or the pulse from said second dither-delay circuit means to said logic circuit means.
- 9. The clock pulse delay and pulse width adjusting apparatus of Claim 8, further comprising:
pulse mode control means connected to said logic circuit means and selectively operable in one mode to pass repetitive pulses from said logic circuit means and selectively operable in another mode to pass only a single pulse of repetitive pulses from said logic circuit means, and means for controlling selective operation of said mode control means in said one and another modes.
1. Clock pulse generating apparatus for a computer system, including means for providing a series of repetitive clock pulses, the improvement comprising:
delay circuit means for providing a set of delayed pulses from each pulse of said series of repetitive pulses, first selector means connected to said delay circuit means to receive said set of delayed pulses, and having a number of selectively operable control elements equal to the number of de-layed pulses in said set, each control element having an input connected to receive one delayed pulse of said set of delayed pulses, an output and a control input which upon being energized passes said one delayed pulse to said output, said output of each control element being commonly connected to an output of said first selector means, second selector means connected to said delay circuit means to receive said set of delayed pulses, and having a number of selectively operable control elements equal to the number of de-layed pulses in said set, each control element having an input connected to receive one delayed pulse of said set of delayed pulses, an output and a control input which upon being energized passes said one delayed pulse to said output, said output of each control element being commonly connected to an output of said second selector means, logic circuit means for generating pulses formed from pulses from said first and second selector means, and selectively settable means for energizing the input of one control element of said first selector means and the input of
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US05/861,755 US4165490A (en) | 1977-12-19 | 1977-12-19 | Clock pulse generator with selective pulse delay and pulse width control |
| US861,755 | 1977-12-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1100195A true CA1100195A (en) | 1981-04-28 |
Family
ID=25336669
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA309,373A Expired CA1100195A (en) | 1977-12-19 | 1978-08-15 | Clock pulse generator with selective pulse delay and pulse width control |
Country Status (13)
| Country | Link |
|---|---|
| US (1) | US4165490A (en) |
| JP (1) | JPS5857769B2 (en) |
| AT (1) | AT375203B (en) |
| AU (1) | AU518871B2 (en) |
| BR (1) | BR7808271A (en) |
| CA (1) | CA1100195A (en) |
| CH (1) | CH637491A5 (en) |
| DE (1) | DE2851519C3 (en) |
| ES (1) | ES475912A1 (en) |
| FR (1) | FR2412205A1 (en) |
| GB (1) | GB2010552B (en) |
| IT (1) | IT1160023B (en) |
| SE (1) | SE7812553L (en) |
Families Citing this family (57)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SE408985B (en) * | 1977-12-27 | 1979-07-16 | Philips Svenska Ab | PULSE GENERATOR |
| DE2812242A1 (en) * | 1978-03-21 | 1979-10-04 | Bosch Gmbh Robert | PROGRAMMABLE SEQUENCE CONTROL |
| US4249119A (en) * | 1978-12-18 | 1981-02-03 | Rca Corporation | Digital drive circuit for electric motor or the like |
| JPS5921045B2 (en) * | 1978-12-20 | 1984-05-17 | 富士通株式会社 | Adjustment method of clock signal distribution circuit |
| US4254327A (en) * | 1979-05-17 | 1981-03-03 | The United States Of America As Represented By The Secretary Of The Navy | Pulse generator having selectable pulse width and pulse repetition interval |
| US4316148A (en) * | 1979-09-04 | 1982-02-16 | Sperry Corporation | Variable frequency logic clock |
| FR2468256A1 (en) * | 1979-10-22 | 1981-04-30 | Thomson Csf Mat Tel | Synchronised digital clock signal generator - uses model frequency signal and produces synchronising signal from harmonics of model signal to produce desired output |
| US4359689A (en) * | 1980-01-11 | 1982-11-16 | Honeywell Information Systems Inc. | Clock pulse driver |
| US4468624A (en) * | 1980-07-23 | 1984-08-28 | The United States Of America As Represented By The Secretary Of The Air Force | Programmable synchronous digital delay line |
| US4414637A (en) * | 1981-01-13 | 1983-11-08 | Honeywell Information Systems Inc. | Adjustable clock system having a dynamically selectable clock period |
| US4488297A (en) * | 1982-04-05 | 1984-12-11 | Fairchild Camera And Instrument Corp. | Programmable deskewing of automatic test equipment |
| US4511846A (en) * | 1982-05-24 | 1985-04-16 | Fairchild Camera And Instrument Corporation | Deskewing time-critical signals in automatic test equipment |
| ZA836998B (en) * | 1982-10-12 | 1984-05-30 | Int Computers Ltd | Data storage unit |
| DE3375266D1 (en) * | 1983-06-08 | 1988-02-11 | Ibm Deutschland | Method and circuit arrangement for the generation of pulses of arbitrary time relation within directly successive pulse intervals with very high precision and temporal resolution |
| US4789835A (en) * | 1983-08-01 | 1988-12-06 | Fairchild Camera & Instrument Corporation | Control of signal timing apparatus in automatic test systems using minimal memory |
| US4820944A (en) * | 1983-08-01 | 1989-04-11 | Schlumberger Systems & Services, Inc. | Method and apparatus for dynamically controlling the timing of signals in automatic test systems |
| US4675562A (en) * | 1983-08-01 | 1987-06-23 | Fairchild Semiconductor Corporation | Method and apparatus for dynamically controlling the timing of signals in automatic test systems |
| JPS6089773A (en) * | 1983-08-01 | 1985-05-20 | フエアチアイルド カメラ アンド インストルメント コ−ポレ−シヨン | Method and device for dynamically controlling timing of signal in automatic test system |
| US4546269A (en) * | 1983-12-01 | 1985-10-08 | Control Data Corporation | Method and apparatus for optimally tuning clock signals for digital computers |
| US4805195A (en) * | 1984-06-08 | 1989-02-14 | Amdahl Corporation | Selectable timing delay circuit |
| JP2539600B2 (en) * | 1985-07-10 | 1996-10-02 | 株式会社アドバンテスト | Timing generator |
| JPS6270922A (en) * | 1985-09-04 | 1987-04-01 | Fujitsu Ltd | Clock phase control system |
| GB2187005B (en) * | 1986-02-21 | 1990-07-18 | Cirrus Designs Limited | Timing system for a circuit tester |
| US5184027A (en) * | 1987-03-20 | 1993-02-02 | Hitachi, Ltd. | Clock signal supply system |
| DE3870680D1 (en) * | 1987-03-20 | 1992-06-11 | Hitachi Ltd | CLOCK SIGNAL SUPPLY SYSTEM. |
| US4833695A (en) * | 1987-09-08 | 1989-05-23 | Tektronix, Inc. | Apparatus for skew compensating signals |
| US4868514A (en) * | 1987-11-17 | 1989-09-19 | International Business Machines Corporation | Apparatus and method for digital compensation of oscillator drift |
| EP0319761A3 (en) * | 1987-12-11 | 1990-10-24 | COMPUTER CONSOLES INCORPORATED (a Delaware corporation) | Multi-phase clock circuitry |
| US4931986A (en) * | 1989-03-03 | 1990-06-05 | Ncr Corporation | Computer system clock generator for generating tuned multiple clock signals |
| US5258660A (en) * | 1990-01-16 | 1993-11-02 | Cray Research, Inc. | Skew-compensated clock distribution system |
| US5036528A (en) * | 1990-01-29 | 1991-07-30 | Tandem Computers Incorporated | Self-calibrating clock synchronization system |
| JP2567163B2 (en) * | 1991-08-29 | 1996-12-25 | 株式会社東芝 | Semiconductor integrated circuit |
| CH682608A5 (en) * | 1991-10-28 | 1993-10-15 | Landis & Gyr Business Support | Arrangement for monitoring of AC switches. |
| DE4244696C2 (en) * | 1991-11-01 | 1995-05-18 | Hewlett Packard Co | Variable width current mirror DAC for IC testing in computer test system |
| DE4235317C2 (en) * | 1991-11-01 | 1994-07-07 | Hewlett Packard Co | Controllable delay circuit |
| US5382850A (en) * | 1992-09-23 | 1995-01-17 | Amdahl Corporation | Selectable timing delay system |
| US5577235A (en) * | 1994-08-31 | 1996-11-19 | Microchip Technologies, Inc. | Microcontroller with multiple timing functions available in a single peripheral module |
| US5594894A (en) * | 1994-10-07 | 1997-01-14 | Microchip Technology Incorporated | Microcontroller with programmable postscaler for pulse width modulation interrupt |
| JP3708168B2 (en) * | 1995-06-13 | 2005-10-19 | 富士通株式会社 | Delay device |
| JP2994272B2 (en) * | 1996-08-23 | 1999-12-27 | 九州日本電気株式会社 | Multi-phase clock generation circuit |
| JP3690899B2 (en) * | 1997-05-30 | 2005-08-31 | 富士通株式会社 | Clock generation circuit and semiconductor device |
| KR100247477B1 (en) * | 1997-06-30 | 2000-03-15 | 김영환 | Clock apparatus for skew control with non-overlapping |
| US6067648A (en) * | 1998-03-02 | 2000-05-23 | Tanisys Technology, Inc. | Programmable pulse generator |
| US6268753B1 (en) * | 1998-04-15 | 2001-07-31 | Texas Instruments Incorporated | Delay element that has a variable wide-range delay capability |
| JP3380206B2 (en) * | 1999-03-31 | 2003-02-24 | 沖電気工業株式会社 | Internal clock generation circuit |
| TW550446B (en) * | 1999-03-31 | 2003-09-01 | Oki Electric Ind Co Ltd | Internal clock generation circuit |
| US6441666B1 (en) | 2000-07-20 | 2002-08-27 | Silicon Graphics, Inc. | System and method for generating clock signals |
| US6868504B1 (en) * | 2000-08-31 | 2005-03-15 | Micron Technology, Inc. | Interleaved delay line for phase locked and delay locked loops |
| US6865425B2 (en) * | 2002-01-07 | 2005-03-08 | Siemens Energy & Automation, Inc. | State machine for a pulse output function |
| JP4231230B2 (en) * | 2002-02-05 | 2009-02-25 | セイコーエプソン株式会社 | Pulse waveform shaping apparatus, laser printer, pulse waveform shaping method and laser printer serial video data generation method |
| DE10249886B4 (en) * | 2002-10-25 | 2005-02-10 | Sp3D Chip Design Gmbh | Method and apparatus for generating a clock signal having predetermined clocking characteristics |
| US6836166B2 (en) * | 2003-01-08 | 2004-12-28 | Micron Technology, Inc. | Method and system for delay control in synchronization circuits |
| US7253671B2 (en) * | 2004-06-28 | 2007-08-07 | Intelliserv, Inc. | Apparatus and method for compensating for clock drift in downhole drilling components |
| US7489176B2 (en) | 2006-04-28 | 2009-02-10 | Rambus Inc. | Clock distribution circuit |
| US8102720B2 (en) * | 2009-02-02 | 2012-01-24 | Qualcomm Incorporated | System and method of pulse generation |
| US9419630B2 (en) * | 2014-12-29 | 2016-08-16 | Texas Instruments Incorporated | Phase shifted coarse/fine clock dithering responsive to controller select signals |
| US10367480B1 (en) * | 2018-03-12 | 2019-07-30 | Honeywell International Inc. | Systems and methods for generating high performance pulse width modulation (PWM) signals |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3440546A (en) * | 1965-11-15 | 1969-04-22 | Ibm | Variable period and pulse width delay line pulse generating system |
| US3383525A (en) * | 1966-01-21 | 1968-05-14 | Chemcell Ltd Chemcell Limitee | Selectable cycle timer with plural outputs of different time intervals and automaticreset |
| US3633113A (en) * | 1969-12-22 | 1972-01-04 | Ibm | Timed pulse train generating system |
| US3697879A (en) * | 1971-08-31 | 1972-10-10 | Eltee Pulsitron | On-off pulse time control |
| JPS536817B2 (en) * | 1972-04-04 | 1978-03-11 | ||
| US3805167A (en) * | 1972-06-27 | 1974-04-16 | Telex Corp | Digital pulse generator with automatic duty cycle control |
| US3959730A (en) * | 1974-09-16 | 1976-05-25 | Rockwell International Corporation | Digital hysteresis circuit |
| US4011517A (en) * | 1975-01-22 | 1977-03-08 | Stromberg-Carlson Corporation | Timer apparatus for incrementing timing code at variable clock rates |
| US3986126A (en) * | 1975-05-15 | 1976-10-12 | International Business Machines Corporation | Serial pulse-code-modulated retiming system |
| US4101761A (en) * | 1976-11-26 | 1978-07-18 | Pacific Western Systems | Timing pulse generator |
-
1977
- 1977-12-19 US US05/861,755 patent/US4165490A/en not_active Expired - Lifetime
-
1978
- 1978-08-15 CA CA309,373A patent/CA1100195A/en not_active Expired
- 1978-08-30 AU AU39388/78A patent/AU518871B2/en not_active Expired
- 1978-10-19 JP JP53127908A patent/JPS5857769B2/en not_active Expired
- 1978-10-31 IT IT29275/78A patent/IT1160023B/en active
- 1978-11-10 CH CH1157978A patent/CH637491A5/en not_active IP Right Cessation
- 1978-11-16 FR FR7832878A patent/FR2412205A1/en active Granted
- 1978-11-22 GB GB7845543A patent/GB2010552B/en not_active Expired
- 1978-11-29 DE DE2851519A patent/DE2851519C3/en not_active Expired
- 1978-11-30 AT AT0856978A patent/AT375203B/en not_active IP Right Cessation
- 1978-12-06 SE SE7812553A patent/SE7812553L/en unknown
- 1978-12-12 ES ES475912A patent/ES475912A1/en not_active Expired
- 1978-12-15 BR BR7808271A patent/BR7808271A/en unknown
Also Published As
| Publication number | Publication date |
|---|---|
| AU518871B2 (en) | 1981-10-22 |
| US4165490A (en) | 1979-08-21 |
| JPS5857769B2 (en) | 1983-12-21 |
| BR7808271A (en) | 1979-08-14 |
| DE2851519A1 (en) | 1979-06-21 |
| FR2412205A1 (en) | 1979-07-13 |
| JPS5487447A (en) | 1979-07-11 |
| AU3938878A (en) | 1980-03-06 |
| SE7812553L (en) | 1979-06-20 |
| GB2010552A (en) | 1979-06-27 |
| DE2851519C3 (en) | 1981-06-11 |
| AT375203B (en) | 1984-07-10 |
| ATA856978A (en) | 1983-11-15 |
| CH637491A5 (en) | 1983-07-29 |
| IT1160023B (en) | 1987-03-04 |
| ES475912A1 (en) | 1979-04-16 |
| IT7829275A0 (en) | 1978-10-31 |
| FR2412205B1 (en) | 1983-01-28 |
| GB2010552B (en) | 1982-04-21 |
| DE2851519B2 (en) | 1980-09-04 |
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