CA1104226A

CA1104226A - Computer useful as a data network communications processor unit

Info

Publication number: CA1104226A
Application number: CA286,217A
Authority: CA
Inventors: James E. Vander Mey
Original assignee: Codex Corp
Current assignee: Motorola Solutions Inc
Priority date: 1976-09-08
Filing date: 1977-09-07
Publication date: 1981-06-30
Also published as: SE429270B; US4096571A; SE7710048L; GB1593404A

Abstract

ABSTRACT OF THE DISCLOSURE
A computer useful as a data network communications processor unit is shown having multiple processors and a common set of independent memory resources accessed by all of the processors over a common bus, and controlled by a common clock. Logic circuitry for allocating the pro-cessors to the individual memory resources is formed by a set of individual contention logic circuits, one associated with each processor, all capable of operating in parallel time, being combinatoric in nature and requiring no sequential states of operation, or logic signals sequentially propagated through the set of logic circuits, and together enabling one allocation per clock interval. The individual contention circuit for each processor features input from each independent memory resource denoting its availa-bility, interconnection with the other contention circuits to provide the longest length of time any other processor of the set has waited for access, priority interconnection with the other contention circuits ranking the circuits according to a pre-determined priority rule to break ties between the circuits in case of equality of all other criteria, and connection with its respective processor indicating need of the processor for access over the bus and the identity of the memory resource required by the processor.
Each contention circuit compares its length of time of waiting for the address/data bus to that of the other circuits and connects its own pro-cessor automatically to the bus when its inputs and connections establish for it that: (a) it requires access to a memory resource, (b) and the memory resource it requires is available, (c) and it has waited as long or longer than any other processor, (d) and there is no processor with higher rank meeting conditions (a) through (c).

Description

11~4~Z~;

This invention relates to a bus allocation system for a computer that has multiple processors and a common set of independent memory resources accessed by all of the processors over a common bus, to a data network processor unit which utilizes such a system to meet various needs of a data network, and to a modularized unit which enables ready expansion of the processor and memory capabilities~ eOgO~ to tailor the unit to the level of traffic encountered at a particular data network node to which the unit is assigned.
The invention employs the eombination of distributed contention logic, enabling use of identical logic on each contending module; parallel eontention for fast priority resolution and bus alloeation; eontention based on availability of requested system resources; and contention based on priority that is a function of waiting time. The invention also employs memory modules which resolve among themselves the nature of the interleaving to be employed and the assignment of memory busy lines whieh communieate with the eontention logie, all in a manner whieh requires no ehange to the eontention logieO
Among the benefits aehievable by use of the invention are no wasted bus eyeles if any module is requesting any available resouree, equal servieing with no loek-outs possible (FIF0), very fast eontention resolution due to parallelism that does not require "daisy" ehain seleetion; and use of simplified hardware meehanisms that are distributed on eaeh proeessor and memory module~ with no straps~ eteO or centralized eontrol requiredO
Aeeording to the invention, for use in a eomputer or data : :
eommunieations processor unit comprising multiple processors and a eommon set of independent memory resourees aeeessed by all of the processors over a eommon bus~ and eontrolled by a common clock~ a logic circuitry is provided for allocating the proeessors to the individual memory resourees whieh eomprises a set of individual eontention logie eircuits, one associated with each proeessor~ enabling all to operate in parallel time, to be ' ' 11~4~

combinatoric in nature and to require no sequential states of operation, or logic signals sequentially propagated through the set of logic circuits~
and~ in their joint functioning enabling one allocation per clock intervalO
The individual contention circuit for each processor featuresO input from each independent memory resource denoting its availability, inter-connection with the other contention circuits to provide the longest length of time any other processor of the set has waited for access, priority interconnection with the other contention circuits, ranking these circuits according to a pre-determined priority rule to break -ties between the circuits in case of equality of all other criteria~ and connection with its own respective processor indicating need of the processor for access over the bus and the identity of the memory resource required by the processorO
Each contention circuit is constructed to compare independently its length of time of waiting for the bus to that of the other circuits and is adapted to connect its own respective processor automatically to the bus when signals over the respective inputs and connections establish~ that~
for the respective processor: (a) it requires access to a memory resource~
(b) and the memory resource it requires is available~ (c) and it has waited as long or longer than any other processor, (d) and there is no processor with higher rank meeting conditions (a) through (c) (iOe.~ no processor with higher rank is "tied~)0 In preferred embodiments disabling inputs are provided for the set of contention circuits~ the contention circuit of highest rank having no such effective input~ and the circuits of decreasing rank having corres-pondingly increasing numbers of effective inputs, corresponding to the contention circuits of higher rank, each contention circuit being constructed to generate a discrete signal based upon satisfaction to the contention circuit of all of the criteria (a)~ (b) and (c) which is connected to a respective input of each contention circuit of lower rankO Preferably each contention logic circuit has a set of identical input lines corres-1~4~Z~

ponding to one less than the number of contention logic circuits in the set,those not needed being provided a constant dummy or false logic value, the contention circuit of highest rank having such value on all of its inputs and the contention logic circuits of descending rank having descend-ingly fewer of such inputs, the last circuit having noneO Each contention logic circuit except that of lowest rank has an effective output which signals a true priority value when its logic circuit satisfies all criteria (a)~ (b) and (c)O Each such output is connected to a respective input of each circuit of lower rank to disable the circuit.
Also~ in preferred embodiments~ the system includes means to provide a composite indication of the longest waiting time of all contention logic circuits on a wait bus to which all contention circuits are connected.
Preferably each contention logic circuit places upon the wait bus its waiting time value. Each contention circuit has a comparator for comparing its waiting time value with the time value on the bus and means to disable the respective contention logic circuit when the comparison shows that the wait bus value is greater. Preferably too~ each contention logic circuit includes a shift register started by a bus request signal from the pro-cessor, and means are provided: to maintain the shift register clear during intervals when the corresponding processor and contention circuit are not waiting, to accumulate in the shift register a set of consecutive ones corresponding to the number of intervals the processor and contention circuit have been waiting~ and~ during each cycle when it is contending, to apply the set of ones to corresponding inputs of the wait bus~ whereby the highest order "one" applied to the wait bus represents the longest waiting time of any contention logic circuit in the systemO
In preferred embodiments each stage of a waiting time shift register is connected to the respective wait bus line through a logic device implementing the wired OR function~ whereby a logical true is forced on the respective line regardless of the value of any other input ZZ~

to the line~ preferably each device being an open collector ~AND gate having as inputs a stage of the shift register, and a signal indicating availability of the memory sought by the corresponding processor.
Preferred embodiments also employ a comparator comparing the stages of the shift register with corresponding lines of the wait bus~
adapted to emit a true signal when and only when there is identity in the two sets of inputs. Preferably a logic device has as inputs the comparison signal, a signal indicative of availability of the memory sought by the corresponding processor and a set of signals from higher ranked contention circuits~ representing no higher ranked circuit is tied~ this logic device being adapted to emit a bus grant signal when all of the inputs are of true value, the bus grant signal preferably also being emitted to disable lower ranked contention circuitsO
Also in preferred embodiments a memory busy bus is provided having one line associated with each memory resource~ carrying a busy or not busy signal~ means defining the address of the computer on an inter-leaved basis modulo n where n is a number equal to (or in some instances greater) than the number of independent memory resources~ each of the contention circuits having a data selector whose inputs are the lines of the memory busy bus and the lowest significant lines of the address request of the respective processor~ the data selector adapted to produce a positive indication when the modulo n value corresponds to a memory busy line having a "not busy" signalO Preferably the output of the selector is connected as an enable signal to a bus grant output deviceO In preferred embodiments a data network processor unit is provided incorporating the before-described contention logic circuitry and having an input/output bus connected to a multiplicity of real time data ports~ and connectable via a selected processor to the address/data bus, the contention logic circuitry adapted to speed the processing of the data to enable real time operation without interruptionO

1~4~26 In preferred embodiments the data communications processor unit includes blank spaces and appropriate connectors for receiving additional processor modules. Insertion of a processor establishes disabling inputs from any processor of higher rank and disabling outputs to any processor of lower rank, preferably accomplished by an identical set of connectors at each position with disabling inputs and dummy (constant false) inputs distributed as described above. The modules also provide a constant false signal to all of its priority inputs that would receive inputs from the absent processor. By these various connections, insertion or removal of a processor automatically enters or removes it from the bus contention system.
(Insertion of the processor also automatically connects its contention logic to the memory busy bus and the wait bus.) In the modularized data communications processor the memory busy bus preferably has a plurality of lines and interconnect connectors for engagement by inserted memory modules. Identical logic circuits can be provided on the memory modules themselves~ according to the invention~ by which, by merely sensing the absence or presence and the position of adjoining modules~ each memory module allocates to itself the appropriate interleave format~ address response and memory busy line for the contention logicO In a preferred embodiment~ a single memory module carries two memory sections. If it senses no module present with which it can perform modulo 4 interleave~ it shifts itself to a modulo 2 interleave mode~
assigns even addresses to one and odd addresses to the other memory section, and assigns two of the four memory busy lines to each memory section~ so that both show busy to the contention logic when the respective memory section is busy.
On the other hand if a module senses the presence of another available module~ both modules automatically conform to a modulo 4 inter- -leave mode~ each assigning to its two memory sections two of the four possible interleave addresses depending whether it is left or rightg and ~1~4226 correspondingly assigns its two memory sections respectively to two memory busy lines. In this particular embodiment~ modulo 4 operation may occur for the address ranges of each pair of neighboring modules~ and a modulo

2 may occur for the possibly remaining module, over its address range.
m ese and other features and advantages of the invention will be understood from the following description of a preferred embodiment taken in conjunction with the drawings wherein:
Figure 1 is a block diagram of a multiFrocessor, multimemory computer incorporating logic contention circuitry according to the invention.
Figure 2 is a block diagram of a single processor ~2 of Figure l;
Figure 3 is a schematic diagram of the logic contention circuit of the processor of Figure 2;
Figure 4 traces certain events over time on the circuit of Figure 3;
Figures 5 and 6 are block diagrams similar to Figure 1 of data network processors incorporating the invention~ while Figure 7 is a schematic and table illustrating interaction of the memory modules relative to the address linesO
Figure 8 shows a circuit by which a memory module of Figures 6 and 7 responds to the presence of others~-and allocates to itself an appropriate section of the address range and memory busy bus.
Figure 1 illustrates a computer system embodying the inventionO
m e computer system has four processor modules 20 (a~ b, c~ d) and four memory modules 22 (a~ b~ c~ d)o The processors share the memory modules on a time shared basisO Bidirectional data transfers between memories and processors are accomplished by using a group of common signal lines called the address/data bus I~ which supplies the addresses to the memory and transfers the data. The auxiliary busses II-IV shown are employed in the contention logic 30 (see Fig. 2)o Each processor may independently attempt to access a given memory module. Since these access attempts are indepen-dent, conflicts for use of the time shared address/data bus and the memory modules will occur. It is the function of the contention logic associatedwith each processor to determine when it may use the bus to access a memory module.
The memory modules also operate independently. In this embodiment they are organi~ed to respond to interleaved addresses, the interleaving here corresponds to the modulo 4 value of the address~ chosen because the memory cycle time is typically longer than a memory access time and a memory module recently accessed may not be available when a processor wishes to access ito The contention logic 30 on each processor must know the memory status of each independent section of memoryO For this purpose a unidirec-tional memory busy bus II is provided for each independent memory~ upon which the respective memory module indicates its busy status by asserting a "memory busy" signal when appropriate, for each master clock interval.
There is one "memory busy" signal for each independent section of memory;
hence a total of 4 lines comprise the '!memory busy" bus for the embodiment of Figure 1. This "memory"-bus is routed to each processor, as shownO
To ensure fairness of service in cases of conflicting requests for the address/data bus~ certain criteria are applied by the contention logic associated with each processor. The first criteria is that the memory module it wishes to access must be available before it can be granted bus access. This can be determined from the "memory busy" buso The next criteria is that no other processor has waited for a longer period of time than this processor has. To evaluate this criteria each contention logic maintains a record of how long its processor has been waitingO Each contention logic compares the value on the "wait time" bus (bidirectional bus III~ connecting all processors) with the value it has maintained for its processor.
A final criteria is necessary if more than one processor has met all the previously stated criteria, namely has been waiting for the same ~1~42~;

period of time and the memory modules they seek to address are available.
In case of this kind of tie a strict priority ordering criteria is appliedO
In this embodiment this is achieved by a distributed priority function using the priority bus lines IV as shown in Figure 1 in conjunction with priority circuitry in each contention logicO Simply stated this last criteria is met if all the priority inputs to the contention logic are logical false.
When the contention logic on any processor module has determined that all the criteria for bus access have been met, it will automatically assert a signal on a bus priority line to disable all lower priority processors. As shown in Figure 1 this output line becomes one of the priority inputs to all lower ranked processor module contention logicsO
Figure 2 illustrates a processor module with contention logic 30.
m e processing element 32 of the module determines when the memory access needs to be made. In this embodiment the processing element~ when requiring access to the memory, asserts a "bus request" signal which is connected to the contention logicO me processing element also supplies to the contention logic the address of the memory module being requestedO In this embodiment the address input consists of the two lowest order address lines to specify which of the four possible interleaved memory modules is being accessed~ according to the modulo 4 ~alue of the address appearing in the address/data buso m e contention logic applies the contention algorithm as described above and supplies to the processing element the "bus grant" signal 24 at the appropriate time. m e processor module will then be able to use the system bus on the next clock cycle to carry address and data information to the memory modules by emitting a bus enable signal 26 for enabling its bus drivers 28 and receivers to the respective busses as shown in Figure 2.
Figure 3 illustrates the elements of the contention logic 30O
m e "memory busy" bus from the memory modules is connected to the four-to-. :
'. -one data selector 35. The two low order address lines from the processing element are used as inputs to the data selector to select the appropriate "memory busy" lineO me "bus request" line from the processing element is also connected to the data selector as the output enable condition. The output from the data selector indicating the state o~ the selected "memory busy" line is connected to various elements of the contention logic, as shown.
me entire system illustrated in Figure 1 operates from a master system clockO mis implies that all state changes throughout the system are synchronous with respect to a particular instant in time. Thus all processor requests for memory are synchronized to some particular point in time.
The contention logic circuits associated with each processor operate such that after every state transition each will resolve any outstanding request for the memory and the bus before the next clock transitionO me result will be that one and only one processor will grant itself access to the address/data bus on the next clock cycle, if in fact any processor is requesting a memory unit that is available.
Since all state changes occur on a clock edge, all signals will stabilize after some propagation delay time before the next clock edge.
This applies to all signals being received by the contention logic and of -course therefore all signals output by the contention logicO
A processor requiring a memory access will supply the "bus request" signal to its contention logic circuitO mis signal will enable the data selector outputO me output of this data selector will be one of the ~'memory busy" lines from the memory as shown in Figure 3. me partic_ ular "memory busy" line will be selected by the two low order address lines supplied by the processing element. m e sense of the "memory busy' lines on the system bus is inverted. mus if the memory being selected is not busy~ the output of the data selector will be logical true or higho 11~4Z~6 This output signal will be applied to the four ~AND gates 10, driving the "wait" lines. This will result in the value of the "wait time" shift register being supplied to the wait bus in inverted formO Initially the "wait time" shift register will be clear. This is due to the "clear"
input being asserted when there is no "bus request" signal from the processor element. If, however, the bus request signal has been asserted for some time due to contention delay, the ~'wait time" shift register will be clocked and a value of "one" will be shifted into the least significant bit. If the bus request is still present when the next "wait clock" signal occurs another bit will be shifted into the "wait time" shift register. This process continues with each "wait clock" signal until the bus is granted and the "bus request" signal is removed thereby clearing the "wait time" shift register. Figure 4 illustrates an example of the change in states of the "wait time" shift register, In this example the "bus request" signal was present from the processor for three "wait clock" periods before the bus grant occurred and the "bus request" signal was removed.
Since each processor module's contention logic may be asserting wait signals at the same time, the value of the wait lines on the bus -reflects that of the processor which has been waiting the longest. This is due to the fact that the NAND gates are open collector drivers which result in the "wired OR" function. To determine if this processor has been waiting as long as or longer than any other processor, the contention logic merely has to compare the contents of its "wait time" shift register with the value present on the bus, The values of the "wait time" shift register are entered into the comparator as the A inputsO The value of the wait line on the bus are the B inputs to the comparatorO If the "equal" output of the comparator is high, then no processor has been waiting longer than this processor.
If the processor element is requesting the bus and the selected memory is not busy, the first input to the priority NAND gate will thus be -- 10 _ il~4Z;~i higho Furthermore, if this processor has been waiting at least as long as any other processor the "equal" output of the comparator which is the second input to the priority NAND gate 12 will also be high~ Note that these inputs will a~ become stable sometime after the clock edge but definitely before the next clock edge (of course, taking care to ensure that the propagation delay time through the various components and over the bus lines is small compared to the clock interval). If the three priority input lines are also high~ indicating a logical false condition, then the output of the priority NAND gate 12 will be low indicating a "bus grant"
to the processorO This "bus grant" line will also become one of the priority lines to the other processors as determined by the bus interconnect scheme of the priority lines shown in Figure 1~ in which the dummy values supplied by priority dummy source 19 are of the value corresponding to "no higher rank processor tiedO" It can be seen from Figure 1 and Figure 3 that in case of a contention tie~ the highest rank processor, which in this embodiment is the lowest number processor among those tied, and no other will have a "bus grant" signal present at its processing element on the next clock edgeO
It is important to note that the transition of the "memory busy", "wait"~ and "priority" signals during the interval between clocks is unim-portant. What is important is only that they be stable by the time of the next clock edge. m e only factor affecting this settling time is the propagation delay time to the various components.
The wait time bus has a number of lines for indicating various durations of waiting. Each "wait" line is driven by an open collector NAND gate 10 as shown in Figure 3. One set of inputs to these NAND gates is connected to respective stages of "wait time" shift registerO The other set of inputs is connected in common to the output of the data selectorO
The "wait time" shift register has a "clear" input which is connected to `
the "bus request" line from the processor elementO The "wait clock" for the ~ 2A~

"wait time" shift register is simply the master clock divided by a divide down counter, for instance each wait clock interval may represent 6 inter-vals of the master clock. The outputs of the t'wait time~' shift register are also connected thru inverters to the A inputs of a comparator and the B
inputs of that same comparator are connected to the nwaitn lines on the buso The ~equal~l indication output of the comparator is connected to the input of priority NAND gate~ 12. The other inputs of this gate are the output of the four to one data selector, and the three priority lines from the buso The output of this NAND gate 12 is the inverted state of the "bus grant"
signal which is cormected to the processing element and one of the bus priority lines.
All of the components of this contention logic are readily available components supplied by numerous manufacturers. One such manufac-turer is Texas Instruments and these components may be found in "The TTL
Data Book", Texas Instruments, 1973. Specifically, the following elements may be employed:
4 to 1 data selector 74153 Comparator SN 7485 Wait time shift register SN 74195 NAND G~TE 12 SN 7430 It is easily seen by one skilled in the art that various alterna-tives and extensions to this embodiment are easily possible. For example, for an additional processor one need only add one more "priority" line on the bus and expand the priority NAND gate in each contention logic section by one input. To add more memory modules one needs simply add one more "memory busy" line for each independent section of memory~ or combine the additional memories into groups such that they share busy lines, and make appropriate changes in the address protocol. To change the wait time, for example~ one can simply change the "wait clock" period or add additional - 12 _ stages to the wait time shift register. It should also be obvious that one can skew the actual bus access time with respect to the bus grant timeO For example, the address time may immediately follow the bus grant, but the data transfer may be at some later time, fixed in relation to the bus grantO This in no way changes the basic contention mechanismO m us it is seen that a truly modular architecture has been provided, which requires virtually no change in logic when scaling from a single processor and memory to multiples of either or bothO
Data communications requirements typically vary widelyO Even within the same network, there may be small nodes supporting only a few ports over a single communications link, as well as large backbone nodes passing traffic from many sources over multiple high-speed linksO Trunk -speeds range commonly from 2400 to 9600 bps, but in larger networks 1902 Kbps and even 50/56 Kbps links may be justifiableO A major goal for the embodiment now to be described is to meet these varying requirements within a common~ modular architectureO It is also the object to provide a multinode network that avoids a constricting capacity ceiling through use - ~:
of a selectable number of microprocessorsO
Typical multiprocessor architectures dedicate each processor to a certain subset of the tasks that have to be performed. The present invention enables effective implementation of a parallel, or symmetric multiprocessor architecture in which every processor is equally capable of picking up any taskO me advantage of this approach is that any number ; of processors from 1 to the maximum physical limit can be used~ thus yielding a modular machine whose power can be tailored to nodal requirementsO
With a single processor, the machine to be described is well adapted to typical small-node applications, while an 8-processor machine has approx-imately the processing power (for communications applications) of two mid-size minicomputers and can support of the order of 50/56 Kbps of full duplex throughputO

, ' 1~ 4ZZ6 Another advantage of the symmetric multiprocessor design made possible by the invention is reliability, since removal of a failed processor allows the system to continue to operate, with reduced processing powerO
In the present embodiment of Figure S the high bus transfer rates desired are achieved by use of a high-speed, synchronized mainframe bus (allocated by the contention system already described) to link the processors with each other, with the program and data memories, and with the micro-programmed master controllerO In terms of bus contention the master controller processor is treated identically to any other processorO Communi-cations with the external data communication ports~ on the other hand~ is a naturally asynchronous and lower speed process taking place over greater physical distances~ so a separate I/O bus with its own asynchronous protocol is employedO
Figure 5 shows the resulting relationship between the major functional elements of the processorO The mainframe address/data bus supports, e.g~, up to 8 microprocessor modules and a mixture of up to 8 RAM and ROM memory modules, with any processor able to access any memory.
The I/O (IN/OUT) bus connects the mainframe to the individual external data source/sinks, or ~ports~O A variety of port types may be provided, for instance data terminal ports 82 and data link ports 92, each connected to the I/O bus through a corresponding I/O controller~ 80 and 90~ respectivelyO In ~ .
one specific embodiment up to 32 ports can be accommodated in a port nest~ -which is a physically separate subassembly that contains a nest interface card to interface to and redrive the I/O bus; and up to 8 port nests can be attached to one mainframeO The master controller module controls the I/O
bus, interfaces it to the mainframe address/data bus, and performs numerous other functions common to the communications problemO An optional module~
not shown~ can interface an optional operator~s console to the master controller and can support other optional featuresO
Figure 6 illustrates a modularized data network processor having 4,~

operational characteristics along the lines just describedO Insertion or removal of a processor or memory module automatically enters or removes it from the bus contention processO For this purpose the processor bank is provided with connectors 23 for the various lines, to define four processor positions, 20i iv Three are shown filled, with the blank at position 20iio The hard wiring for bus contention is constructed to accommodate the maximum number, 4, and thus with the position 20ii blank, inhibit output 21i from module 20i terminates at an open connector 23. As can be seen, this has no effect on the contention logic for the installed processors.
The inputs 21ii to the lower ranked processors~ similarly now connected to open connectors 23, are constructed to introduce constant highs to indicate the logical false condition to the respective contention logic circuits (see in Figure 3 the voltage source V and the resistors 25, these of values chosen to be overridden when real signals appear on the priority lines)O
The memory bank is similarly wired with connectors, in this case to define up to eight positions for accepting memory modules. By means of module outputs 36,38 and inputs 40~42 at the left and right sides of each module, any module can detect the presence and position of adjoining modulesO On this basis the module can decide for itself, by predetermined rule, the proper allocation of the memory busy lines, the interleave mode of operation (whether modulo 2 or modulo 4) and address assignments between the memory segments of the module, employing memory address decoder 700 Referring to the schematic and table of Figure 7~ with two modules present in the first two positions~ determined~ eOgO~ by permanent wired module numbers as shown, the modules decide upon a modulo 4 interleave. In this case the last two address lines 14 and 15 locate the module pair, address line 1 selects between the members of the pair~ and address line O selects between the two memory sections~ Ml and M2, of each module. The memory busy lines are assigned in accordance with the modulo 4 value of the assign-ments within the pairO

11~42Z~i With only one module presnet, (or three, with the first twoalready paired for modulo 4 operation) the module decides for itself to interleave modulo 2 with the following busy line assignments:

Ml M2 00 and 11 10 and 11 In the case of three modules being present a complex relationship occursO
The first four memory sections provided by the first and second modules proceed with a modulo 4 interleave as if the third module were not present.
The third module, having detected its position accepts addresses higher than the capacity of the modulo 4 system and allocates these higher order bytes between its two memory sections on a modulo 2 interleave basisO The even and odd memory sections of this modulo are then coupled to the memory busy lines with memory sections in the modulo 4 set~ and operate dependently with them as a single independent memory resource for bus contention purposes O
Thè foregoing assignments are accomplished on each memory module on the basis of the inputs 40 and 42, employing the logic circuit 60 of Figure 8 to produce signals A,B which directly enable the NAND gates to appropriately assign the memory busy lines to the memory sections, and which, by input to the address decoder 70, enable the decoder 70 to shift to implement the appropriate line of the table of Figure 7O
Figure 8 shows the logic diagram to implement the algorithm for determining whether a 2 or 4-way interleave is to be employed and assignment of the memory busy linesO If the value of the memory module number~ modulo 2~ equals 0 and signal 40 is logical true~ gate 50 indicates 4-way interleave and gate 51 enables memory busy lines 0 and lo If instead the value of the memory modulo number~ modulo 2~ equals 1 and signal 42 is logical true~ . :
gate 50 indicates 4-way interleave and gate 52 enables memory busy lines 2 and 3. If neither of the above is true then gate 50 indicates a 2-way interleave and gates 51 and 52 are logical true~ enabling all four busy lines.

11~4Z26 In a more complex embodiment adapted for memory modules of differing capacities, in place of the wired in memory module numbers for determining address, each module is provided with an adder 80, suggested by dotted lines in Figure 7~ to which is input, by the preceding module, the total memory capacity preceding it, and which outputs, to the succeeding module, that total incremented by the capacity of the respective moduleO
This effectively defines for each module the address range to which it is assigned. Provisions are then made, e.gO on the memory modules themselves, to ensure that the modules mate in appropriate characteristics~ eOgO
memory size~ before they jointly enter into the modulo 4 mode of address interleaveO `

Claims

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. For use in a computer comprising multiple processors and a common set of independent memory resources accessed by all of said processors over a common bus, and controlled by a common clock, logic circuitry for allocating individual processors to the individual memory resources, said logic circuitry comprising a set of individual contention logic circuits, one associated with each said processor, all capable of operating in parallel time, being combinatoric in nature and requiring no sequential states of operation, or logic signals sequentially propagated through the set of logic circuits, and together enabling one said allocation per clock interval, the individual contention circuit for each processor having:
input from each independent memory resource denoting its availability, inter-connection with the other contention circuits to provide indication of the longest length of time any other processor of the set has waited for access, priority interconnection with the other contention circuits, ranking the circuits according to a predetermined priority rule to break ties between said circuits in case of equality of all other criteria, and connection with its own respective processor indicating need of said processor for access over the bus and the identity of the memory resource required by said processor, each contention circuit constructed to compare independently its length of time of waiting for said bus to that of the other circuits and adapted to connect its own respective processor automatically to the bus when signals over the respective inputs and connections establish, that, for the respective processor: (a) it requires access to a memory resource, (b) and the memory resource it requires is available, (c) and it has waited as long or longer than any other processor, (d) and there is no processor with higher rank meeting conditions (a) (b) and (c).

2. The system of claim 1 wherein, for said priority interconnection, disabling inputs are provided for said set of contention circuits, the contention circuit of highest rank having no such effective input, and the circuits of decreasing rank having correspondingly increasing numbers of effective inputs, corresponding to the contention circuits of higher rank, each contention circuit constructed to generate a discrete signal connected to a respective said input of each contention circuit of lower rank based upon satisfaction of said contention circuit of all of said criteria (a), (b) and (c).

3. The system of claim 2 wherein for said priority interconnection each contention logic circuit has a set of identical input lines corresponding to one less than the number of contention logic circuits in said set, means providing a constant dummy logic value, the contention circuit of highest rank having all of its said inputs connected to said dummy value, and the contention logic circuits of descending rank having descendingly fewer of its said inputs connected to said dummy value, the last said contention logic circuit having no such connection, each contention logic circuit except that of lowest rank having an effective output for signalling a priority value of opposite sense from that of said dummy logic value that its logic circuit satisfies all criteria (a), (b) and (c), said output of each circuit connected to a respective said input of each contention logic circuit of lower rank and disabling means in each contention logic circuit to disable said circuit upon receipt of a priority value from any contention logic circuit of higher rank.

4. The system of claim 1 including means to provide a composite indication of the longest waiting time of all contention logic circuits on a wait bus to which all contention circuits are connected.

5. The system of claim 4 including means in each contention logic circuit enabling it to place upon said wait bus its respective waiting time value, each of said contention circuits having a comparator adapted to compare its respective time value with the time value on said bus, and means to disable the respective contention logic circuit in response to its said comparator when its comparison shows that the waiting time value on the wait bus exceeds the respective waiting time value.

6. The system of claim 5 wherein each contention logic circuit includes a shift register, means to maintain said shift register clear during intervals when said corresponding processor and contention circuit are not waiting, means to accumulate in said shift register a set of consecutive ones corresponding to the number of intervals said processor and contention circuit have been waiting, and means, during each cycle to apply said set of ones to corresponding inputs to said wait bus, whereby the highest order one on said wait bus represents the longest waiting time of any contention logic circuit in said system.

7. The system of claim 6 wherein each stage of each shift register is connected to the respective wait bus line by means of a logic device implementing the wired OR function, whereby a logical true in any such stage forces the corresponding value regardless of the value of any other input to the line.

8. The system of claim 7 wherein each said logic device is an open collector NAND gate having as one input a stage of said shift register, and the set of NAND gates each having as its other input a signal indicative of availability of the memory sought by the corresponding processor, of 10.

9. The system of claim 6 including a comparator having as inputs the stages of said shift register and the corresponding lines of said wait bus, and adapted to emit a positive comparison signal when and only when there is identity in the two sets of inputs.

10. The system of claim 9 including a logic device having as inputs said comparison signal, a signal indicative of availability of the memory sought by the corresponding processor, and a set of signals from higher ranked contention circuits, representing no higher ranked circuit is tied, said logic element adapted to emit a bus grant signal when all said inputs are of positive value.

11. The system of claim 10 wherein said bus grant signal is emitted to lower ranked contention circuits for use in inhibiting corresponding logic devices in said circuits.

12. The system of claim 1 including a memory busy bus having one line associated with each independent memory resource, carrying a "busy" or "not busy" signal, means defining the address of said computer on an interleaved basis modulo n where n is a number equal to or greater than the number of independent memory resources, each of said contention circuits having a data selector having as inputs the lines of said memory busy bus and the lowest significant lines of the address request of the respective processor to give the modulo n value of the requested address, said data selector adapted to produce a positive indication when said modulo n value corresponds to a memory busy line having a "not busy" signal.

13. The system of claim 12 wherein the output of said selector is connected as an enable signal to a bus grant output device.

14. The system of claim 12 wherein a bus request signal from said processor, when said processor has a data transfer requirement, is connected as a start signal of a waiting time shift register.

15. A data network device incorporating the structure of claim 1, said network device having an input/output bus connected to a multiplicity of real time data ports, and connectable via a selected processor to said access/data bus, said contention logic circuitry adapted to speed the processing of the data to enable real time operation without interruption.

16. The system of claim 1 wherein said computer is a real time data communications processor unit for transferring data between various data ports at a node of a communications network, said multiple processors are connected to communicate with the data ports over a common input-output bus, said independent memory resources are connected to be accessed by the various processors over a common address/data bus, by which each of a succession of characters of data derived from a given data port is placed in a memory resource by an individual processor and thereafter is removed from said memory resource and delivered to another data port by an in-dividual processor, said processor unit is of modular construction including processor modules and memory resource modules and constructed to enable change in the number of processor or memory resource modules to conform the processor unit to the level of data traffic at the point of use, each processor including a contention logic circuit by which it determines for itself the times of access to said common address/data bus for the purposes of transferring a character of data between a port and memory resource and performing functions ancillary thereto, and a wiring system interconnecting the memory resource modules and the processor modules to enable function of said contention logic circuits, said wiring system defining a plurality of busy lines, one for each independent memory resource, over which the respective memory resources inform the set of contention logic circuits of the processors of its busy or not busy state and wait time lines over which each respective processor informs the others of the respective duration each has been waiting for access to said address/data bus, means in each contention logic circuit for determining availability of a memory resource to which its processor element requires access and duration of time of waiting to establish the respective processor as one that is contending and has waited at least as long as any other, and said wiring system defining priority lines connected to disable all but the highest such contending processor in accordance with a predetermined priority rule.

17. The system of claim 16 including at least one blank space for receiving an additional processor module, and wiring automatically connected by insertion of an additional processor module, to provide priority inter-connection from the newly inserted module to each of the pre-existing processor modules, with disabling outputs to any processor of lower rank according to said predetermined priority rule.

18. The system of claim 17 wherein said priority wiring system is arranged to define a plurality of processor positions into which said processors with their respective contention logic circuits may be inserted, each contention logic circuit having a set of identical input terminals corresponding to one less than the maximum number of processor modules that can be inserted into said unit, said wiring system and said contention logic circuits cooperatively constructed to enable a permanent false value to be present on all of said inputs to the contention circuit of highest rank and descendingly fewer of said inputs for contention circuits or correspondingly descending rank, each contention logic circuit constructed to produce a positive value priority output when its processor is a contending processor which has waited at least as long as any other, said wiring system connecting the output position of each contention circuit to a respective input position of each contention logic circuit of lower rank, and disabling means in each contention logic circuit to disable said circuit upon receipt of a said positive priority value from any contention logic circuit of higher rank, said wiring system and said contention logic circuits also coopera-tively constructed so that absence of any processor from the unit causes the inputs of lower rank that are connected to receive the output of the absent processor to show a permanent false value, whereby insertion or removal of a processor automatically enters or removes the processor from the bus contention system.

19. The system of claim 16 including means to provide a composite indication of the longest waiting time of all contention logic circuits on a wait bus to which all contention circuits are connected, and means en-abling any additional processor module inserted in said unit to automatic-ally connect its contention logic circuit to said wait bus.

20. The system of claim 19 including means in each contention logic circuit enabling it to place upon said wait bus as input its respective waiting time value, each of said contention circuits having a comparator adapted to compare its respective time value with the time value on said bus, and means to disable the respective contention logic circuit in response to its said comparator when its comparison shows that the waiting time value on the wait bus exceeds the respective waiting time value, said wait bus constructed to be automatically connected to receive said input from and deliver the bus time value to any additional processor module by insertion of said module into said unit.

21. The system of claim 16 including a memory busy bus having one line associated with each independent memory resource, carrying a busy or not busy signal, means defining the address of said computer on an inter-leaved basis modulo n where n is the number of independent memory resources, each of said contention circuits having a data selector having as inputs the lines of said memory busy bus and the lowest significant lines of the address request of the respective processor to give the modulo n value of the requested address, said data selector adapted to produce a positive indication when said modulo n value corresponds to a memory busy line having a not busy signal, and means enabling any additional processor module insert-ed in said unit to automatically connect its contention logic circuit to said memory busy bus.

22. The system of claim 16 including a memory busy bus having a plur-ality of lines for engagement by inserted memory modules, a single memory module inserted in said unit effective to signal on all of said lines to said contention logic circuits, and said memory modules and said lines cooperatively constructed so that upon insertion of a second said memory module, said modules allocate said lines between themselves.

23. The system of claim 22 including wiring means and means on said modules engageable therewith for causing each module to sense the presence and location of additional memory modules in the unit, and responsive thereto to assign to themselves respective busy lines in accordance with a predeter-mined rule.

24. The system of claim 23 including logic circuitry on each of said memory modules responsive to the presence and location of additional memory modules to automatically assign to themselves a range of addresses in accordance with a predetermined rule.

25. The system of claim 24 wherein each memory module has two data memory resources and there are four memory busy lines communicating to said contention logic circuits, said memory modules constructed so that in the presence of a single module in said unit, two of said busy lines are assigned to each resource, both showing busy to the contention logic circuit when the respective memory resource is busy.

26. The system of claim 25 wherein insertion of a second said memory module is effective to allocate one busy line associated with each resource of the first module to a respective resource of the second module, said modules including means sensing the position of each other and adapted to select the particular busy lines in accordance with a predetermined rule based upon relative position of said modules.

27. The system of claim 26 wherein said modules include means to shift themselves from a modulo 2 interleave address mode of operation when only one module is present to a modulo 4 interleave address mode of oper-ation when two modules are present, said contention circuit being unaffected thereby.

28. The system of claim 26 wherein insertion of an additional module is effective to connect its memory to a busy line to which another memory is assigned, said two memories thereby effectively constituting a single independent memory resource for the function of said contention logic circuits.

29. The system of claim 1 wherein said computer is a real time data communications processor unit for transferring data between various data ports at a node of a communications network, said multiple processors are connected to communicate with the data ports over a common input/output bus, said independent memory resources are connected to be accessed by the various processors over a common address/data bus, by which each of a succession of characters of data derived from a given data port is placed in a memory resource by an individual processor and thereafter is removed from said memory resource and delivered to another data port by an individual processor, said processor unit is of modular construction having processor modules constructed to enable change in number to conform the processor unit to the level of data traffic at the point of use, said processor unit including contention resolution means to determine the times of access to said common address/data bus for the purposes of transferring a character of data between a port and memory and performing functions ancillary thereto, and a wiring system interconnecting the memory resources and the processor modules to enable function of said contention resolution means, said wiring system defining a plurality of busy lines, one for each independent memory resource, over which the respective memory resources inform said contention resolution means of its busy or not busy state and wait time wiring over which each respective processor can inform the contention resolution means concerning the respective duration it has been waiting for access to said address/data bus, means enabling insertion of a processor module to automatically include its input to said contention resolution means, said contention resolution means responsive to said busy lines for determining availability of memory resources to which processor elements require access to establish a processor as one that is contending, and said wiring system defining priority lines connected to enable only a processor selected in accordance with a priority rule which takes waiting time into account.

30. The system of claim 29 wherein each module includes means to shift itself from a first to a second address mode of operation in response to the presence of another module, said second mode being an interleave mode.

31. The system of claim 30 wherein said processor unit has memory modules and each memory module has two data memory resources, said module including means to shift itself from a modulo 2 interleave address mode in which successively addressed data words are allocated to said two memory resources on said module to a modulo 4 interleave mode shared with another such module, in the manner that in the set of four successive addresses, two are directed to each module.