CA1105585A

CA1105585A - Programmable controller with modular firmware for communication control

Info

Publication number: CA1105585A
Application number: CA280,365A
Authority: CA
Inventors: Kenneth N. Larson; Alfred D. Scarbrough; John B. Knueven
Original assignee: Bunker Ramo Corp
Current assignee: Bunker Ramo Corp
Priority date: 1976-06-15
Filing date: 1977-06-13
Publication date: 1981-07-21
Also published as: JPS6058497B2; DE2726811A1; GB1573046A; FR2355332A1; GB1573047A; US4079452A; JPS5316542A

Abstract

ABSTRACT OF THE DISCLOSURE
This invention relates generally to a programmable controller module. In almost all data management systems, a controller is designed to accommodate only peripheral devices having a common communication discipline. An object of this invention is to provide some identification of the discipline of each peripheral device connected to each channel serviced by a programmed controller module in order for the appropriate protocol to be used, and to provide the protocols for the different dis-ciplines in separate selectable modules. A programmable controller module (PCM) for operably coupling a plurality of peripheral devices (PDs) of various communication disciplines to a data processor (DP) or to remote PCMs through a serial interface adapter (SIA) or parallel interface adapter (PIA). The PCM is comprised of a serial purpose computer having implement specific communication protocols (routines) for different com-munication disciplines. Each PD is assigned, and addressed by, a channel code. A discipline identification (DID) line is connected from each adapter channel to one of a predetermined number of terminals in the PCM. There is one terminal for each communication discipline for which there is stored an appropriate protocol. Each channel has its DID line connected to the appropriate terminal according to the communication discipline of the PD
connected to it. When a channel is addressed, its DID is activated. The PCM then scans the terminals to determine which is activated to ascertain the discipline of the device.

Description

1 1~55~5 ~ V~ la~e~,t~;encrall~ ko digital com-put~r (~ta m~nlt~e!n~r~ cms, and mcre ~ar~icularly to im~)rov~ments in a r)ro~rammable controller rno~ule for facil-~t;a1;:Lng comm~lnl(at-Lon ~j~twcen peri~her~l devices employing ~ f~rent c~mmunlca~ion ~isci~lines, and be~ween such devlces and ~l da~a processor.
In almost all data management systems, a con-t~oller is des~gned to accommodate only per~pheral devices having a common communication disclpline. To accommodate a plurality of peripheral devlces of dirferent disciplines, it ls necessary to provide a controller o~ different design for each communication discipline. In typical data manage-ment systems, there may be over six t~Jpes of major network communication disciplines and a multitude of communication disciplines for specialized peripheral devices and term-nals. The term "communication dlscipline" is defined as the set o~ rules or criteria governing the message format uti-lized by a partlcular network, peripheral device or terminal.
Exemplary ~actor~ distingui5hing one di~cipline ~rom another involve~ for example, synchronization, start and end of transfer sequence, message ~egment length, etc. Each type of discipline requires a di~ferent data handling protocol. The term '1protocol" is deflned as the programmed procedure ~or inputing and outputing data to and from a network peri-pheral device or terminal accordLng to the discipline of the data. The f~llowing l-lst comprises only a small por-tion o~ tho~e disciplines which may be of interest in a ~ypical data management system.
O~UNICATION DISCIPLII`rE
30 VIP VISUAL IMAGE PRO~ CTIOM TERIIII~L (~IO~rEYT~ELL) DN355 DATA-~T 355 (HO~Y1~JELL) BAUDOT TTY ITA NG. 2 TELLTYPET~.ITER
ASCII TTY ASCII r~lETYPEl~rRITr~R - ODD OR EV--T~ PARITr ~1 PT-PT BISYNCH POINT-TO-POINT BINARY SYNCHRONOUS
RLP300 REMOTE LINE PRINTER 300 (HONEYWELL) GENSER AUTODIN GENERAL SERVICE PORT

WUPTC WESTERN UNION PROGRAMMABLE TERMINAL
CONTROLLER (AUTODIN) ~N30 DATA-NET 30 (HONEYWELI.
DACOM DACOM FACSIMILE UNIT

A communication control unit Model BR 1569 manufactured by the Bunker Ramo Corporation employs a programmable controller module for interconnecting peripheral devices of different dis-ciplines to each other and to a data processor comprised of a bus organized central processing unit and a main memory. The complete control unit is described in U.S. Patent 4,075,691, titled "Communica,tion Control Unit". As originally conceived, the Model BR 1569 control unit contains firmware in a read-only memory (ROM) of a programmable controller module (PCM) which defines and implements a specific communication protocol for each of 16 channels. A typical system implements three to four pro-tocols with a number of channels assigned to each protocol. A
basic problem with that arrangement was that completely new firmware (software entered into a ROM) had to be assembled, de-livered and installed each time there was a new channel assign-ment or a new protocol added, An ob~ect of this invention is to provide some identi-fication of the discipline of each peripheral device conDected to each channel serviced by a programmed controller module in order for the appropriate protocol to be used, and to provide the protocols for the different ~l~S~S
lisci~)iirlcs i~ c~ara~e modules ~ ic~l ~an bc added or de-let;ed a., t!le requlremenks of ~he sys~em dictate.
~ 3rierly, in accordance with an exemplary embodi-ment of the lnventlorl~ a communication control unit is pro-vided wl~h a program~ble controller module (PCM) contalning a modular read-only memory (ROM) for storing a control program in two levels, a f~rst level stored in a predeter-mined number of ROM modules ~typically one or t,wo ROM
modules) whlch contalns control routines for servicing a number of different channels, and a second level which con-tains discipline dependent routines to be used for the different devices in separate ROM modules with all routines (protocol) for a specific discipline in one module, i.e., with a separate module for each protocol.
Each communication channel to be controlled by the PCM is dedicated to a peripheral device of a particular communication discipline by connecting from it a discl-pline identification (DID) line to one of a predetermined number, N, of input terminals to the PCM. Each input ter-minal thus conn,ected to rece-ive a DID signal is scanned whenever a channel is found request~ng service as the PCM
routinely addresses the channels under programmed control.
The discipline o~ the peripheral device as~igned to a chan-nel is thus determined each tlme it is selected by the PCM
under programmed control. Once the discipline o~ a device is determined under first level programmed control, khe flrst level control program branches to the appropriate one of a plurality of second level control programs in which the necessary protocol is stored for the identified discipline. The protocol is totally contained within a ROM
module which is preprogrammed before the ROM module is in-stalled. A protocol ROM may be lnstalled in any address position of the PCM program memory; its position is _ j_ ll~S5~S

correlated with the terminals connected to the DID lines by the first level program.
Instruction sequencing is effected by a PCM address counter. Each jump instruction in a protocol is restricted to addresses within the ROM module dedicated to the protocol until the last instruction of the protocol is reached. The last in-struction is a direct (full address) jump instruction to a loca-tion in the first level control program. In that manner, up to N protocols may be added and associated with the N terminals of the PCM. All peripheral devices requiring a specific protocol have their DID signal lines connected to the same terminal. The DID signal line for a specific peripheral device is activated when the channel to which it is connected is addressed by the PCM.
The invention is particularly directed toward a com-munication control unit useful in a data processing system in-cluding a data processor, at least one interface adapter and a plurality of peripheral devices for communicating with the data processor through an interface adapter. The adapter has a plur-ality of addressable channels, each channel being dedicated to a separate peripheral device, and each device being capable of hand-ling messages in accordance with one of a number of distinct com-munication disciplines. The control unit comprises a program-mable controller module for addressing the channels and handling messages between the channels and the data processor in accor-dance with the communication discipline of the device connected to the channel addressed. The programmable controller module has a plurality of input terminals, one discipline identification ter-minal for each of the plurality of distinct communication disci-plines. The interface adapter has means responsive to address signals from the programmable controller module for addressing the channels, each channel having a discipline identification line connected to one of the discipline identification terminals , , ,, , i8S

in accordance with the communication discipline of the device con-nected to the channel. Each channel further has means responsive to the addressing means for activating its discipline identifi-cation line. The programmable controller module includes means for responding to an activated line to determine which com-munication discipline to use in handling a message between the addressed channel and the data processor.
The novel features of the invention are set forth with particularity in the appended claims. The invention will best be understood from the following description when read in conjunction with the accompanying drawings.
FIG. 1 is a block diagram of a data processing system incorporating a communication control unit in accordance with the present invention.
FIG. 2 is a block diagram of a programmable control module (PCM) shown in FIG, 1, FIG. 3 is a block diagram of a serial inter~ace adapter module (SIA) shown in FIG, 1.
FIG. 4 is a schematic diagram illustrating the manner in which a discipline identification (DID) line conn~cted to one o~ the DID terminals in a PCM is activated in an SIA when one of its channels is addressed by the PCMo FIG. 5 is a diagram of a relay switch that is equiva-lent to a three-state activating gate in FIG. 4.
FIG. 6 is a schematic diagram illustrating the modular arrangement of a ROM program memory in the PCM

. ,~

l~q~S

Attention is initially directed to FIG. l which deplcts in block form a data processing system incorpora-ting a communication control unit in accordance with the aforesaid copending application. The system is comprised of a data processor lO which ~lcludes a programmed digital computer and a main memory. The computer ls bus oriented and therefore includes a data bus ll for data input and output to peripheral devices. The system further includes at least one, and sometimes two, direct memory access modules (DMA) 12, a programmable controller module (PCM) 13 for each DM~ and typically one to ~our serial and/or parallel interface adaptors (SIA and/or PIA) 14 connected to the PCM through an SIA/PIA DATA bus 15.
The DMA connects to the data bus and can there-fore receive data, addresses and control signals ~rom the data processor and send data, addresses and control sig-nals to the data proce~sor in 16 bit words.
The PCM is a programmable controller that re-ceive~ and sends addresses, data and commands from and tothe DMA in 8-bit bytes or characters. After processing the data or commands, the PCM performs required functions and sends or receives 8-bit data or commands to or from an addressed SIA or PIA via the I/0 bus. The addressed SIA converts the 8-bit data character to ~erial data, with code conversion if requlred, for transmission to an appro-priate one Qf four channels or receives the serial data and converts it to parallel 8-bit data, with code conver-sion if required, on receiving. The addressed PIA conver~s the PCM 8-bit data and control characters into parallel s~gnals compatible wlth the peripheral devlce, and con-verts data and status sigr~ls from the peripheral device into a form compatible with the PCM.

S

~ :ac~l~;LI`~ o~ A ls coupled to fuur separate channels each Or which may corlnect to a peripheral device, sllch as a CRT termînal, line printer, teletypewriter, etc.
~lthough a slllgle communication control unit can interface with up to thirty-two channels, using two DMAs for slm-pliclty in explanation herein, the invention will be de-scribed with reference to a 16 channel unit lncluding one DMA and one PCM.
As depicted in FIG. 1, one of the SIA channels may be connected to a remote terminal 16 via an appropriate data link 17 as a ~Iperipheral unit" which is itself com-prised of ~ PCM 18 and PIAs and SIAs 19 interconnected through SIA/PIA may be identical. In that regard, the PCM 18 may also be connected to a data processor by a DMA and data bus, but since the PCM 18, like the PCM 13, is in fact a microprogrammed computer, the remote terminal 16 may function alone and communicate with the communica-tlon control unit from which it receives data as a peri-pheral device having a predetermined and specified commun-ication discipline.
Each SIA or PIA provides i.ts PCM with up to fourchannels, and each channel may be connected to any one of a plurality of different types of perlpheral devices having any one of eight communication disciplines, such as a per~pheral device (PD) 21. Each channel produces a signal over one wire which identifies its peripheral device. For example, when the device 21 connected to channel 4 is addressed by the PCM 13 via the bus 15, channel 4 transmits a signal over a unl~ue one of four wires in a cable 22. The other end of the wire ls c:onnec-ted to one of eight terminals (ports) of the PCM according to the discipline of the device. For example, assuming termlnal No. 3 of the e-~ght terminals numbered 1 through 8 'S:~S

i~> X'!-''`,erVt`d ~OJ' ~ C~ lcvices, a2ld th.l~ tl~e device 21 is Or such a commullicatiorl discipline, the associated wire within the SI~ is co~lrlected to the ~erminal No. 3. Conse-quently, when channel 4 ~s addressed, a signal is trans-mitted over that; w:Lre to t;he terminal No. 3. The PCM
then scar~s the terminals to determine which has a signal and in that manner ascertains that cha~lel 4 which has ~ust been addressed has connected to it an ASCII-TTY de~
vice. As a coneequence of that, the PCM will branch to a modular ROM in its program memory wherein a suitable pro-gram is stored for recei.ving data from or transmitting data to the peripheral device according to the ASCII-TTY dis-cipline. Thus, in accordance with an exemplary embodiment of the invention, the system may be init-lally assembled with from one to seven protocols (programs) for up to seven different dlsciplines, each assigned addresses correspond-ing to the terminal numbers. For example, the ASCII-TTY
protocol would be assigned the octal address 3. (The eighth terminal is not used.) All ASCII-Tl~ devices connected at the time of initial installation, and all other ASCII-TTY devices thereafter added in any channel, will have its discipline identification signal line connected to the same terminal No. 3.
An advantage of the present invention ls that when a system is installed, only a few (for example 3) modular ROMs may be required, each with a different proto-col for the different PDs. In that e~enf" only terminals 1, 2 and 3 would be used and the modular ROMs would be assigned octal addresses 1, 2 and 3. Thereafter, if it becomes necessary to add peripheral devices of rourth and fifth types of communication disciplines, it would be a simple matter to add fourth and fifth modular ROMs with appropriate protocols preprogrammed, and to assign them t.;;~5 ~ c ~d(3reL,ses .~r tel mli~als ~Os 1~ and 5 b/ virtue of thelr physical location wit.lin the PCM. In addition, termirlal asslgnments could be easlly cllanged. The -Lndividual ROMs preproKrammed with var-Lous protocols could be assembled and placed in inventor~J. This would give the user the opportunity to order on short notice any protocol ROM
which can easily be plugged into unused ROM module loca-tions in the PCM without any change in previously installed protocol ROMs. The only limitation to this concept is that each protocol program must fit into the modular ROMs which must all be of the same size. However, this limita-tion is not restrictive since experience has shown that each of the standard disciplines require protocols that will fit economically into a 25~ word ROM module.
Bef'ore proceeding with a more detailed descrip-tion of the present invention, the organization of the PCM
disclosed in the aforesaid copending application will be brie~ly described with reference to FIG. 2. But flrst it is appropriate to review the requirements of the Dr~ on the bus 11.
First, the in~ormation to he sent or received either resides in or will be stored in the main memory of the data processor 10. Secondly, control Or the bus is at all times malntained by the data processor. Thus, any DMA
on the bus uses either a Data (IN) or Data (OUT) command rollowed by the necessary data and address locations to transf'er data into or out of that memory. For example, when the system is transmitting data to a peripheral de-vice and needs data from memory to do so, t'ne D~ obtains ~he bus ~rom the da~a processor via a non-processor request (NPR~ and issues:
(1) Data (OUT) command

(2) The starting address in memor~J.

_~_ 11~55~5 The -Llr~ then receiv~s a si~teen-bit, data w~rd ~rom memory.
As each sixtee~l-blt word is received by the DMA, it is ~u~rered in me~mc)ry irl the PCM in eight-bit bytes (characters).
The characters are t~len sent to the appropriate SIA or PIA
b~ the PCM ~or transmittal tothe peripheral devlce. The DMA is then directed by the PCM to fetch another word from core via an NPR.
On the other hand, when the system is receiving data from a peripheral device and needs to store data ln memory, the ~MA mu~t provide:
(1) Data (IN3 command (2) The starting address in core memory The DMA then sends the sixteen-bit data word to memory.
The process is similar but rever~ed when the system is sending data to memory.
Attention is now called to FI~. 2 which illus-trates the programmable controller module (PCM) in sig-nificantly greater detail than its block representation FIG. 1. The PCM is a small programmable parallel computer whose ~ganization has been optimized for the communication control runction. As can be seen in FIG. 2, the PCM ls compriaed of a plurality of' blocks or elements all of which communicate with each other via an internal data bus 30.
Each of the PCM elements will be described in detail here-ina~ter.
Prior to describing the PCM elements separately, the overall characteristics of the PCM will be discussed and the ~nstruction set considered. As noted, the PCM
comprises a~ e~ficient programmable parallel computer. It utllizes a data word length o~ 8 bits, while the instruc-tion and address is 12 bits in length.

The PCM is a microprogrammable processor with a single data b~s, arithmet7c logic unit and a dual ported s~s ~ w~ J:'~ ( " `;.'a~ a~ 3.,1d~im access me!nol~ (R~M) 31 that is addressa~-)ïe "y t;-le T~CM ~ata source Gr ~le D~ for var-iable data. ,~ colltrol program is stored in a programmable read-orlly (R(Jl~l) memoxy ~' t~trpicaJly comprised of 2048 words (eigrht moc3ules Or ~5~-word ROMs). Micro-program instruc-t1ons are s~;ored in a sep~ra~;e programmable read-only memory ~3, as will be discussed. An arithmetic logic unit 31~ provides the capabilit~ for the logical and arithmetic functions required. Instructions read from the ROM pro-10 gram memor~ 32 are executed in a maximum of three or fourstates, dependir~ upon whether or not the RAM memory 31 is to be addressed, and depending upon the particular ROM
command to be executed.
With the foregoing overview of the PCM in mind, the various elements of the PCM will not be considered in greater detail. The programmable read-only memory 32 stores in one ROM module a sequence o~ instructions form-ing control routines applicable to all peripheral devices~
and in additional ROM modules character transmit/receive protocols, each protocol appllcable to a particular com-munication discipline used by one or more of the connected peripheral devices. Instructions read out of the program memory 32 are parallel loaded into an instruction register 35 at the beginning of each instruction execution cycle.
Decoding and control of instruction execution is performed by the microprogram and control logic 33.
The microprogram and control logic 33 lncludes a 256 x 12 bit read-only memory which stores khe micro-program. The microprogram generates/enables control register loading, address increment~n~, memor~ riting, and command generation. The microprogram also controls the arithmetic logic unit 3~-~ and selects data sources.

The inputs to the microprogrram are tr~e Gp-co(ie part of the 5~
ill.',t'~ C t,io!i ( i3i~ > s-ll) in r(l~ist~r 35~ ~ne blt condition selector, and the compare olltplll; of the .~rlthmetic/logic nit; 3l~ .~\rl edge ~ri~gered register ls used to synchron-L~e lhe hit c~nd:il;i~r) arl~3 compare inputs and to sequence throug~ the statcs of lhe microprc~gram.
Instruc~ions read from the program memory 32 are selected by ar-l address coun~er 36. The address counter ls 12 blts -ln length allowing it to address an expanded program memory o~ ~og6 words. The address counter is in-cremented each time the instruction register 35 ls loadedand du~ing a ~ump instruction if the specified condition is not satisfied. The address counter 36 is parallel loaded during a ~ump instruction if the specified condition is satisfied.
Data i5 written into the random access memory 31 during a transfer instruction in which one o~ lts memory cells is de~ined as the data sink~ Data is read from that memory during a trans~er instruction in which one of its memory cells is defined as the data source. Memory con-sists of two sections, each section containing 2~6 8-blt characters. The sectlons conslst of l-bit x 256-bit random access memories operated in parallel to form an 8-bit x 256 character memory section. There is an external port into the memory 31 which can be used by the DMA, as afore-mentioned, to read or write into the memory 31 whenever the PCM is not using the memory 31. Accessing the memory is controlled by a select register 37. The select regis-ver may be used also to select a peripheral device to be serviced, via the SIA, by the PCM. The register 37 is loaded by means of a properly addressed load reglster or transfer lnstruction. The register may be read by the PCM

during a transfer instruction in which it is specified as the data source.

~ )ul; d~ egistor ~,', p ~-~rides an output c}laract,er w~ich is ~l) bc read b~/ the selected perîpheral dev-lce, ~-la th~ . The selection of the device to read ~ e output (h.lr.lct;cr :i~; made by the select reglster 37.
The ou~)ut data charac~er reglster may be loaded b~ means c,f a proper]y addresse(l load register or trans~er instruc-tion. T~le register may not be used as a data source by a transfer ~unction. An I/0 command is the mearls by which the PCM causes a func-ion to be initiated in the selected perlpheral device. The command is generated by means of an I/0 command instruction.
Arithmetic is performed by the arithmetic logic unit 34 and an accumulator register 39. The arithmetic logic unit combines the contents of the accumulator and the speci~ied data source according to the function specl-fied by the instruction register contents. The results are placed in the accumulator register. The accumulator register is the primary operating register of the PCM.
The result~ of all arithmetlc and logic functions are placed in this register. A carry flag 40 is set when a carry out occurs during e~ecution of an arithmetic in-structlon. A ~ump may use the status of the carry flag as the jump condition. The accumulator register may be loaded by a properly addressed load register or transfer instruction. The register may be read during a transfer instruction ln which it is speci~ied as the data source.
Jump instructions may compare the accumulator with in-struction, RAM, input, or other register data. From the discussion thus far, it should now be recognized that the PCM contains two read-only memories, i.e., the program memory 32 and the microprogram memory 33. The rnicro~
program determines -the ~nstructlon set of the PCM and may be changed to suit particular appl,cations. T~!e ~ o~-,r~nlr,l~m-r, ~ores l;he previous,l,v- menttoned firmware which, as mentiolled, corlslsts Or two levels. It will be recalled ~,~at level 1 of the firrnware contains control programs common to all communication disciplines and level 2 Or the rirmware contains discipline dependent programs or protocols.
In executlng each instruction loaded lnto the instruction regist,er 35 from the program memory, two, three, or four states of the microprogram are required depending upon the complexity o~ the fu~ction to be per-~ormed. State zero is always used to load the lnstructlon register and increment the address counter. The next state 1 is used for instruction decoding and to execute operations not requiring random access memory. During states two and three operations requiring random memory access may be executed. The firmware in the program mem-ory enables the PCM to manipulate and transfer data between two or more devices, such as the data processor and a selected perlpheral device.
The select register 37 provides the upper five bits of the RAM address for PDM instructions, thus a specific page of RAM is selected for each I/0 device selec-ted by the select register. During states 0 and 1 on the program, an external device may read or write into the RAM at any address of its choice. If this device is the DMA, the P~M may be used to s~ore computer memory ad-dresses, word counts~ or other parameters required for DMA da~a transfers and interrupt generation. T~lis ex-ternal port ~nto the RAM memory allows ~'ne data processor to load ~he ~M register or the PCM to execute OI~A trans-~ers without interrupting the l-irmware.
~ ata to be transfe~xed ~rom 'he PC~ to a selected per-ipheral de~ice ls placed in the output data register 38.

Trlen an I,f~ COm~lan~l iS use~ to strobe tile data into the devic~. Data to be trans~erred from a selected device to the P~M :ts loaded in~o the ~M memor~ 31, or a register, by a t,ransfer irlstructior~ en an I/0 may be used to acknowledge the data transrer. I~0 commands may ~e used to lnit-Late control functions also. ~evice status may be monitored by the PCM at the lnput ports without trans-ferrin~ the status to a register.
The DMA may read the memory transfer address ~rom the R~M memory using the ~AM DMA port when a read or wrlte command Ls received rrom the PCM. '~he data to be read or written is stored in RAM. After the data trans-fer is completed, the DMA will update the memory transfer address and return it to the RAM memory. The PCM updates and tests the word count. The DMA generates end of trans-fer interrupts when the PCM f~nds the word count equal to zero and sends a channel interrupt I/0 command to the DMA.
The DMA provides status to the PCM uslng an input port.
In the PCM, each channel is scanned sequentially by the ~irst level program. High-speed channels may be scanned more frequently b~J performing a nonsequential or welghted scan.
Prior to describing the implementation of the firmware in accordance with the present invention, the SIA module, depicted in FIG. 3, will be described in gen-eral. As previous-y mentioned, each SIA module comprises a ~lexible serial communicat~on inter~ace providing a wide range of capabilities in terms of bavd rates, com-munication modes, interface levels, character length, and code convers~on. ~he baslc function of the SIA is to convert parallel data to ser~al data for transmission data to a selected peripheral de-~ice and to convert serial data into parallel data on receiving information from a -14~

~)e~ip`~ evl~ ach .~ module COlltaillS rour full duplex comn~unlcation channels anc3 lncludes a PCM ~nterface ~lock 41 which ~unctions to decode the PCM commands and select; reglster addresses. The PCM commands the SIA via an I/O command. As no~ed w-Lth reference to FIG. 1, in this exemplary embodimerlt, the PCM is capahle of inter-facing with four SIA modules~ onl~J one of which is illus-trated in FIG. 3.
Since each SIA module provides four full duplex channels to peripheral devices, a PCM w-ith ~our SIA modules coupled thereto can interface with six~teen full duplex channels. The PCM interface module 41 also decodes channel select addresses. Data is sent to the SIA output channels via I/O commands and transfer commands. The output data ls sent to a data multiplexor 42 which by-passes a code converter 43, ir necessary. An I/O command loads this data into a transceiver ~4. On receiving, the input data channel is selected by the multiplexor 42, by-pa~ses the code converter if necessary, and data is sent to the inter-~ace module 41 as an input to the PCI~. The input datalines are buffered for ~our SIA modules. Trlerefore, no SIA places data on the input lines until it has been addressed. Each SIA can be interrogated to determine its status as indicated by bits Or a status charac~er.
Each bit is set in accordance with the particular status of some part of the SIA. In additiGn to the s~atus char-acter, an addressed channel of an SIA transmits a disci-pline identification (DID) signal to the PCM. The DID
signal line for channel 1 is shown individually in FI~.
~. It should be understood that each channel has its own DID signal line to the PCM. Together the four DID signal lines from an SIA ~o the PDM comprise t'rle cahle 22 shown in FIG. 1.

~lq.'~S~
~ o~e tl~n~ rl vr '.le L)ID si<~nal transmitted 1~ an ad(lr~ssed SIA chlr~ el is ko drivc one of N (for exampl~ o) term-l~lls of the PCM to whicn it is connected to a lo~ric () (~) volt lcvc3) w~len ~he chanrlel is addressed.
I;ach of the '~ tcrmlnals, numbered L-~ in an exemplary em-bodimerlt is preasslg~r~ed to a particular communication discipline, sllch a.; the ASCII-T~FY discipline. When a particular SIA channel ls dedicated to a peripheral device, the DI~ signal line of that channel is connected at the PCM to the ter~inal ass-lgned to the discipline of that peripheral device. Each tlme the PCM addresses the channel, it scans the terminals to determine which one is at the logic O level, and thus determine the discipline of the peripheral device. Once that determination is made, the PCM ~umps to the service routine (protocol) of the device in one of the modular ROMs. For example, lr channel 4 is addressed, and upon scanning the terminals it is found that terminal No. 3 is at the logic O level, the PCM branches to the modular ROM having an address corres-pond~ng to the appropriate protocol. That address couldbe octal 3 for consistency, but it is not necessary that the numbers of the terminals correspond to the numbers of the modular ROMs since the proper modular ROM can be matched to the terminal at the logic O level by the PCM
program.
The code convertor 43 consists of two read-only memorles for transmit and two read-only memorles for re-ceive. The PCM data character or t~le SIA receive charac-ter is used as an address to the ROM location which c;ontains a converked character.
Each SIA channel contains a rlag re~ister ~5 and time out circuikry that holds: request to send, new sync, dlsable sister channel, and sync search enable. rach S:~A

58~
C,la~ Ol i'`lI'tii'~' c~ in~ e ~xiver anc3 receiver circuits 4~') tC) in~erraCC W~ l t'ne re~uired ou~put or input charac-teristics Or the peri~)hexal Aevices to be connected to the ',IA output channels.
The foregoing descript-lon generally defines the significant structural and functional aspects of the seria~ lnterface adapter (SIA) module implemented with a DID signal line in accordance with the present lnvention.
The preferred implementation wlll now be described in ~reater detail with rererence to FIG. 4. A decoder 50 in the PCM interface 41 recelves five bits of a partially ~coded channel address to produce an enable signal on one o~ four lines A, ~, C and D (also shown schematically in FIG. 1 as cable 22) associated with the first, second, third and fourth channels of the SIA.
The enable signal thus generated in the PCM
lnterface is tran3mltted in inverted form over one of four lines tc a "three-state" or "open collector" gate G3 in the channel selected. Each o~ the gates is a posltive-NAND
gate which produces a discipline identification signal DID in response to the inverted enable si~nal (ENAELE).
For each channel, the ~ate G3 thus provi~les a disclpline identi~ication signal, over a line DID because the enable signal is connected to the operatlve control termlnal of the gate such that the output ls off (disabled) when the operative control ls hlgh. ~en the output is off, a pull-up reslstor 51 main~alns the DID line high (+Vc). An activated DID line is thus low ~logic ? . This arrange-ment of a three-state or open collector gate hav-lng its operative control terminal connected to receive the channel enable signal and having its da~a terminal connected to a loglc 0 source (circuit ground) allows more t'r.an one DID

line to be cGnnected to one terminal of t~e PCM such that at~"- o!~ `;ato C;l~.~ dï~ o t;~ tcr~i~aal to a low level (circuit grouild). It i-~ t~lUS ev:lden~ tllat a gate as used 'nere is equ-lvalent l;o a rela~ circu-lt connected as shown in FIG. 5 with its solenoid 5,' energized by signal E~A~LE to close a contact 5' when the si~nal EN~LE is prssent. ~ny one of any nuMber of relays th~ls energized can pull down the termina.l ln the PCM to which the DID line is connected without a~fecting any other line.
There is a separate DID signal line for each channel. Each slgnal line is connected to one of a number of termlnals Or the PCI~ accordin~ to the discipline of the perlpheral device connected to the channel. When a parti-cular channel is selected, its gate G3 will drive the line low (logic O level). The PCM then scans for the terminal that is driven low by a DID line to determine the discipline of the peripheral device connected to the channel Or the active DID line. Only one DID line will be active at any one time because it is activated only as a result of the associated channel being addressed.
In the present exemplary ernbodiment of the in-vention, a 12-bit address is employed ko address a control program in a module of the ROM program memory 32 (FIG. 2).
A subroutine of the control program scans the terminals Nos. O throu~h 7 to which the DID lines of the SIA or PIA
charmels are connected to determine the discipline of the peripheral device connected to an addressed channel.
Once the terminal that is at a low level ~s ~ound~ 4he subroutine ~umps to a. starting address ~or the appropriate one O.t~ a plurality o~ ROM modules in w'nich 'he protocol is stored ~or the particular type of peripheral device associated wi~h the term~.nal ~ound to be at a low level.
For example, assuming the control subroutine is stored in one 256-word ROM, and that there are a total o eight S-~S
p~s.i)l~ d l~ is ~hicn carl be incllded, each as a separate ~ ln modulo Ihe 12-bit address word may employ f;he le?ast si~rlifi~:allt eight bits (bit pcsitions O through T) ~o addre ~ arl~J orle Or 2sG memor-~ locations in a desig-nated modular Ror~, and the next t~lree bits (positions 8 '3 and 10) to designate the I~OM module. Tile last bit in position 11 is not re(~uired ror addressing an 8 x 256 word memory. ~it 11 is used in this exemplary embodimen~ to lock the instruction sequencing in one Or the protocol modules by programminrr all ~ump instructions in a protocol ROM with a loglc O in bit position 11, except for the fir~l Jump lnstruction at the end of a protocol used to Jump back to t~ control program. A modular ROM storing the protocol for a particular peripheral device may thus be programmed with relatlve jump instructions so that it can be plugged into any one of the modular ROM positions, except the one, or two, reserved for the control sub-routine.
When the control program is prepared, it wlll provide a direct, jump to a ~pecific (full) address for each of its N DID terminals. A modular protocol ROM may then be installed into any position other than the two reserved for the control program. Then as long as all the charmels using that protocol have their DID lines connected to the PCM DID terminal corresponding to the location of that protocol ROM, the control program wlll always aump to the proper modular ROM by simply determining which of its ~ID
termir~ls is at a low level. This permits havir~ a large number of different ROM modules to be prepared and held in inventory, and permits each module to be plugged into any one of the possible ROM module positions except those reserved for the control routine.
In the exemplary embodiment having a 12-bit 5~

l ~dres~ `r~ el~c ma; lie C~,~ilt Ror~ modules as shown sche-maticall,~ IG. f.. 'Frle first two module positions at oc~,al addresses O and 1 are reserved for the control pro-~rram, and tiie remaining six module positions at octal addres,es ~ thro~ 7 may be used for any protocol. A
direct Jump rrom the c~ rol routine to a specific address in another P~OM module ~ill cause ttle control program to branchto the starting address of the appropriate protocol in one o~ tr-le other ROM modules. Execution of the lnstruc-tions in that protocol (i.e,, that modular ROM) is undercontrol of the address counter 36 (FIG. 2) which is incre-mented upon executing each instruction. Any jump required within the protocol must be relative to the starting address of the protocol. Therefore, the address bits of the starting address in bit positions 8, 9 and 10 must be retained during each jump, except the last jump of the pro-tocol which is a direct Jump to the control routine in the first ROM module. To distinguish the two types of ~ump instructions -ln a protocol, the most signifi¢ant posltion (bit 11) of each relative jump address is set equal to a logic 0, and for the direct jump address at the end of the protocol, it iS set equal to a logic 1.
The address counter 36 is shown -Ln greater de-tail in FIG. 6. It includes a counter 70, a ,Jump decoder 71, and a multiplexer 72 comp~sed of three sets of 4-bit multiplexing gates 72a, 72b and 72c, each with a select terminal (SEL) ror se]ecting parallel inputs at one o~ two sets of input terminals laheled 1'o~l and "1." Tne input terminals labeled "1" and llO'I of thc 4-bit multiplexers 72a and 72b are selected to be elther from the data bus under control of an instruction in the instruction regls-ter 35 ~FIG. 2) or from ~he program memor~J for a ump Instruction as decoded by the decoder 71 effectively ~ Cl~:Lti "; ~ e~` ',o'~ ;)ii,'~ Or l jurnp in~tructioll in the registor -,~, (-IG. '). Tlle .~ddxess cou~lter 70 is thus loade~ ~rom th~ mu:l.ti.~-lexer 7~. At all other times the ~ ress colinter i. încrem~lll;ed to speclry the address of 1}1~ rlcxt; lnst;rucl~io~l~ The 4-bit Mult~.plexer 7'c does not multiplcx betwecn the dat;a bus and the program memory under control vf the instruction decoder 71; it multiplexes between the output Or thc address counter and the program memory under control o~ the twelfth memory bit -ln bit position 11. I~en that bit -is a bit 0, the selection is from the high order blts ~ and 10 of l;he address counter and at all other times from the program memory. The twelfth bit (bit 11) of the memory address words is not otherwlse used.
Each ~ump in~truction read from a location in the program memory will have the address of the next instruc-tion stored in location, N+l. Upon decoding the jump instruction read from memory, the multiplexers 72a and 72b will load from the program memory regardless Or the twelfth bit in bit position 11 of the jump address read from the location N+l, but the multiplexer 72c loads from the program memory only if bit 11 is a logic 1 for a direct ~ump to a specific (full) address anywhere in memory, and normally in one of the other ~OM modules storing a protocol (rou-tine) for a speciflc communication discipline. If bit 11 is a l.ogic 0, the multiplexer 72c loads from the address counter. The multiplex control bit 11 read .~rom location N-~l of a branch inst~uction is used as the select signal for the multiplexer 72c. It ~s normally set to loglc O
for all branch instructions in the control program stored ln the ~irst ROM module having the octal address 0, excep~
in the case of branching to or from a pro-tocol stored in any one of the other ROM modules having an octa:l ad-l.ress llQ55t~S

from 1 to 7. In that case the multiplex control bit of the jump address read from location N+l is set to a logic level 1 to cause the multiplexers 72a, 72b and 72c to all load from the program memory. That affects a direct jump to or from a protocol. A
jump from a protocol will always be back to the control program in the ROM module having the octal address 0. Bits 8, 9 and 10 of a branch address for an instruction to branch back to the control program will thus all be at the logic level O and bit 11 will be a logical 1.
From the foregoing, it is evident that all jump in-structions must contain a logic O in the most significant bit position of the address of the next instruction if the jump is relative to the last address of a modular ROM loaded into the ad-dress counterO If the jump is to be a direct jump to a specific address anywhere in the program memory, the bit 11 is set to logic 1 in the specific address, That specific address will, of course, be the first instruction of a protocol in one of the other ROM
modules when jumping from the control program in modules 0 and 1 to a protocol, and the appropriate location in the ROM modules containing the control program when jumping from a protocol back to the control program.
This use of bit 11 in a jump address permits every protocol to be programmed in a ROM module with all of its jump instructions relative to its first instructions so that it is not necessary to know in advance in which memory position the ROM
module is to be plugged in, and to permit a direct jump back to the control program at the end of the protocolO It is then pos-sible to select a ROM module preprogrammed ~ith any one of an in-definite number of protocols for any position of the modules 2 through 7, in this exemplary case of using two ROM modules for the ~ 2--.~

11~55~S
co~ rol v7- or ~ r~l~ a~ 7~ the COil trol pro~rarn to select any onc of the remaining p~otGcols ~ scanning the terminals to wll~ h t;he charlrle:L DI~ lines are connected. ~here only six dirferellt prolocols are provided in separate ROM modules, as ill t,~-~e exem~lary e~bocliment just described, only six terminals would be used and scanned. I~owever, it should be recogni~ed that the number of protocol ROM modules may be expanded to some larger number, such as 16, by simply in-creasing the len~th of an address word to 13 in which case the nuinber o~ terminals could be increased to the maximum num~er o~ different protocols that could then be accommo-dated, namely 14. Thus, although particular embodiments Or the invent~on have been de~cribed with only one or two modules for the control program and seven or six modules for protocols, it is evldent that even three or more ROM
modules could be used for the control program~ leaving less ROM modules for protocols. ~ut if a larger array o~
protocols is requlred ~or a greater number of different types of peripheral devices, the system could be imple-~O mented with a larger address word, as just noted, to ac-commodate more modules. Howevert it has been found that using two ROM modules for the control program and six ROM
modules for the protocols is generally adequate rOr the usual installation.
It should be noted that the ROM program memor~J
may be rep}aced with random access memory (RAM) modules to provide the capability o~ loading the control program from a data processor via the data bus, or externally via a communication channel. That would allow changing the control program under external program control, arld would also aliow debugging ol protocols. Still other modifica-tions and equ~valents may readily occur to those skilled in the art. Consequently~ it is intended that the clc~ims -2,-~ ~558S
be :int;~rpret-~(3 ~o cover '311Cil modificat:~ons and equivalents.

Claims

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A communication control unit useful in a data proces-sing system including a data processor, at least one interface adap-ter and a plurality of peripheral devices for communicating with said data processor through an interface adapter, said adapter having a plurality of addressable channels, each channel being de-dicated to a separate peripheral device, each device being capable of handling messages in accordance with one of a number of distinct communication disciplines, said control unit comprising a program-mable controller module for addressing said channels and handling messages between said channels and said data processor in accor-dance with the communication discipline of the device connected to the channel addressed, said programmable controller module having a plurality of input terminals, one discipline identification ter-minal for each of said plurality of distinct communication disci-plines, and said interface adapter having means responsive to ad-dress signals from said programmable controller module for addres-sing said channels, each channel having a discipline identification line connected to one of said discipline identification terminals in accordance with the communication discipline of the device con-nected to the channel, and each channel further having means res-ponsive to said addressing means for activating its discipline identification line, said programmable controller module including means for responding to an activated line to determine which com-munication discipline to use in handling a message between the addressed channel and said data processor.

2. A communication control unit as defined in claim 1 wherein said activating means of each channel for its discipline identification line is comprised of high impedance means for con-necting said line to a voltage source of a predetermined level, and switching means responsive to said channel addressing means for selectively connecting said line to circuit ground when its channel is addressed.

3. A communication control unit as defined in claim 1 wherein said programmable control module includes a program memory means comprised of a plurality of memory modules for storing a control program in two parts, a first part for one level of con-trol stored in a predetermined number of modules for addressing a number of device channels, and a second part for a second level of control which contains a plurality of protocols of discipline dependent routines to be used for servicing the different devices, each protocol of said second part being stored in a separate pro-tocol module uniquely identified by a predetermined number of high order address bits, the remaining lower orders of an address iden-tifying a location within a module, whereby said programmable con-troller module may address said channels under control of said first level of said control program and, upon addressing a selec-ted channel and determining the communication discipline of the device to which the channel has been dedicated, may jump to a pre-determined protocol module in said second level of said control program in accordance with which communication line has been activated.

4. A communication control unit as defined in claim 3 wherein said program memory means includes an address counter in-cremented in response to reading instruction words from a memory module in order to automatically execute instruction in sequence, multiplexing means for entering a jump address into said address counter from a memory module in response to jump instructions, and means for inhibiting said multiplexing means from entering into said address counter said predetermined number of high order ad-dress bits for all jump instructions within a protocol except the last, whereby a jump instruction from said first level of control to a particular protocol module in said second level of control may be effected, and from said particular protocol back to said first level of control only at the end of said particular protocol.

5. A communication control unit as defined in claim 4 wherein said inhibiting means is responsive to a high order bit in each jump address read from any module of said program memory means, said higher order bit being set to a predetermined binary logic value for all jump addresses of said first level of program control to permit jumping to any protocol module and set to the other binary logic value for all jump addresses of a protocol in said second level of program control except the last jump address of each protocol to inhibit jumping out of each protocol, said higher order bit of the last jump address of each protocol being set to said predetermined binary logic value to permit jumping out of the protocol module back to said first level of program control.

6. A communication control unit as defined in claim 5 wherein said multiplexing means is connected to reenter into said address counter said predetermined number of high order address bits in response to said higher order address bit of said other binary logic value from said program memory means whereby the ad-dress of the module storing the protocol to be used in servicing a channel is restored in said address counter in response to each jump instruction except the last.

7. A communication control unit, useful in data proces-sing system including a data processor and a plurality of peri-pheral devices, each for communicating with said data processor through a different channel in accordance with a different commu-nication discipline, each channel having a discipline identifica-tion line, said communication control unit comprising: a program-mable controller module including: program memory means including a plurality of locations each storing an instruction, with sequen-ces of instructions forming a first level of program control com-mon to all peripheral devices for producing device address signals for addressing said channels and a second level of program control consisting of protocols stored in separate modules of said program memory means, each protocol consisting of communication discipline dependent routines unique to one or more of said peripheral devi-ces, each protocol being stored in a separate module uniquely iden-tified by a predetermined number of high order bits of an address;
instruction register means; program address counter means for iden-tifying a location in said program memory means and for transfer-ring the instruction stored therein to said instruction register means; a read/write memory means for storing data; a data bus com-prised of parallel bit lines; means responsive to instructions transferred to said instruction register means for operating on data either in said read/write memory means or appearing on said data bus; a plurality of input terminals, each terminal being con-nected to a discipline identification line of a device communica-tion channel in accordance with the discipline of a device to which the channel is dedicated; a direct memory access module means res-ponsive to instructions transferred into said instruction register for selectively transferring data from said read/write memory means to said data processor and from said data processor to said read/
write memory means; and an interface adapter means coupled between said programmable controller module and said peripheral devices for receiving data from and transmitting data to said peripheral devices through different channels, one channel being dedicated to each peripheral device, said interface adapter means including means responsive to said device address signals from said program-mable controller module for addressing said channels one at a time, and means responsive to said addressing means for activating the discipline identification line of the channel addressed at any given time to identify the protocol to be used in servicing the device to which the addressed channel is dedicated.

8. A communication control unit as defined in claim 7 wherein said second level of program control consisting of commu-nication protocols is stored in a plurality of memory modules, each protocol being stored in a separate module uniquely identified by a predetermined number of high order address bits, the remain-ing lower orders of an address identifying locations within the separate module, and wherein said program memory means includes:
an address counter incremented in response to reading instructions from a memory location in order to automatically execute instruc-tions in sequence, multiplexing means for entering a jump address into said address counter from a memory module in response to jump instructions, and means for inhibiting said multiplexing means from entering into said address counter said predetermined number of high order address bits for all jump instructions within a pro-tocol except the last, whereby a jump instruction from said first level of control to a particular protocol in said second level of control may be effected, and from said particular protocol back to said first level of control only at the end of said particular protocol.

9. A programmable controller module as defined in claim 8 wherein said inhibiting means is responsive to a high order bit in each jump address read from any module of said program memory means, said higher order bit being set to a predetermined binary logic value for all jump addresses of said first level of program control to permit jumping to any protocol module and set to the other binary logic value for all jump addresses of a protocol in said second level of program control except the last jump address of each protocol to inhibit jumping out of each protocol module, said higher order bit of the last jump address of each protocol being set to said predetermined binary logic value to permit jump-ing out of the protocol module back to said first level of program control.

10. A programmable controller module for servicing a plurality of peripheral devices, said module having a plurality of device identification input terminals, each device for communica-ting in accordance with only one of a predetermined number of com-munication disciplines through a separate channel each channel having a discipline identification line, and each channel being addressable by said controller module, said controller module in-cluding a program memory means comprised of a plurality of memory modules for storing a control program arranged in two parts, each part having routines for providing a level of control for said de-vices, a first part stored in a predetermined number of memory mo-dules for addressing any one of said device channels, and a second part having routines for servicing a number of device channels, routines of said second part being divided into a plurality of protocols, each protocol being comprised of discipline dependent routines to be used for servicing the different devices, and each protocol being stored in a separate one of said memory modules uniquely identified by a predetermined number of high order ad-dress bits, the remaining lower orders of an address identifying locations within a separate module, each device identification input terminal being connected to a discipline identification line of a channel in accordance with the discipline of a device to which the channel is dedicated, means responsive to said first part of said control program for addressing said channels one at a time, and means responsive to said addressing means for activat-ing the discipline identification line of the channel, said pro-grammable controller module including means responsive to said ac-tivated line for identifying the protocol to be used in servicing the device to which the addressed channel is dedicated.

11. A programmable controller module as defined in claim 10 wherein said program memory includes an address counter incre-mented in response to reading instruction words from a memory mo-dule in order to automatically execute instructions in sequence, multiplexing means for entering a jump address into said address counter from a memory module in response to jump instructions, and means for inhibiting said multiplexing means from entering into said address counter said predetermined number of high order ad-dress bits for all jump instructions within a protocol except the last, whereby a jump instruction from said first part constituting one level of control to a particular protocol in said second part constituting another level of control may be effected, and from said particular protocol back to said first part for said one le-vel of control only at the end of said particular protocol.

12. A programmable controller module as defined in claim 11 wherein said inhibiting means is responsive to a high order bit in each jump address read from any module of said program memory means, said higher order bit being set to a predetermined binary logic value for all jump addresses of said first level of program control to permit jumping to any protocol module and set to the other binary logic value for all jump addresses of a protocol in said second level of program control except the last jump address of each protocol to inhibit jumping out of each protocol module, said higher order bit of the last jump address of each protocol being set to said predetermined binary logic value to permit jump-ing out of the protocol module back to said first level of program control.