CA1106078A - Method of fabricating itegrated circuits with oxidized isolation and the resulting structure - Google Patents

Method of fabricating itegrated circuits with oxidized isolation and the resulting structure

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Publication number
CA1106078A
CA1106078A CA127,816A CA127816A CA1106078A CA 1106078 A CA1106078 A CA 1106078A CA 127816 A CA127816 A CA 127816A CA 1106078 A CA1106078 A CA 1106078A
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region
epitaxial
layer
silicon
substrate
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CA127816S (en
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Douglas L. Peltzer
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Fairchild Semiconductor Corp
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Fairchild Camera and Instrument Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/761—PN junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0635—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors and diodes, or resistors, or capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0821—Collector regions of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/8605—Resistors with PN junctions
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/03—Diffusion
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/037—Diffusion-deposition
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/049—Equivalence and options
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/117—Oxidation, selective
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/145—Shaped junctions

Abstract

Abstract of the Disclosure A thin silicon epitaxial layer, formed on a silicon substrate, is subdivided into electrically isolated pockets by a grid of oxidized regions of epitaxial silicon material which extend through the epitaxial layer to a laterally extending PN junction.

Description

11~ti~78 T~Lis invention relcltes to semiconductor devices and in particular to integrated circuits of smaller size, higher speed and higher packing density than heretofore obtained, and to the process of making them.
Various ways have been proposed to isolate electrically a plur-ality of pockets of semiconductor material in each of which one or more circuit elements can be formed. Among the ways proposed have been appro-priately biased PN junctions (~oyce, U,S. Patent 3,117,260 issued January 7, 1964), combinations of PN junctions and zones of intrinsic and extrinsic semiconducting materials (Noyce, U,S, Patent 3,1S0,299 issued September 22, 1964), dielectric isolation (Frescura, U.S. Patent 3,391,023 issued ~uly 2, 1968) and mesa etching (Frescura et al~ U.S. ~atent 3,489,961 issued January 13, 1970). Tucker and Barry~ in U.S. Patent 3,736,193 issued May 29, 1973, disclose the use of selectively-doped polycrystalline silicon to help isolate islands of single crysta~[ sil;con in which cir-cuit elements can be formed.
After electrically-isolated pockets of semiconductor material are prepared, active and passive circuit elements are formed within or on the pockets. Many of these circuit elements are typically formed using the planar diffusion techniques disclosed by Hoerni in U.S. Patents 3,025,589 and 3,064,167. In the planar process~ the regions o~ each semiconductor pocket into which circuit elements are diffused are control-led by for~ing a diffusion mask from an insulation layer formed on the surface of the semiconductor material. After the desired elements have been formed in the semicondwctor material, a conductive lead pattern is formed on the insulation and used to interconnect selected active and passive circuit elements into the desired circuit. Additional passive circuit elements can also be formed on the insulation and interconnected into the circuit. Such a structure is disclosed in Noyce, U.S. Patent
2,981,877 issued April 25, 1961.

11~6~t`78 In the mallufacture of integrated circuits, several problems arise.
First, the ~rea of tbe wafer re~uired for the placement of the isolation re-gions between ad~acent pockets of semiconductor material is a significant portion of tbe total wafer area. A large isolation area reduces the number of devices which can be placed in a wafer and thus lowers the "packing den-sity" of the circuit elements formed in the wafer. Second, the leads formed on, and adherent to, the insulation on the wafer surface sometimes crack at steps in the insulation on the wafer surface. These steps are often quite steep. Third, several of the isolation techniques result in significant capacitances being introduced into the integrated circuit. While at low fre-quencies these capacitances do not affect the operation of the circuit, at high frequencies these capacitances can have a significant effect on circuit performance. Fourth, the prior art integrated circuits are usually formed in relatively thick (greater than 5 microns) epitaxial layers formed on support substrates. As a result, the operating speeds of the resulting devices are sometimes slower than desired. Fifth, the processes by which prior art inte-grated circuits are produced are relatively sensitive to defects in masks and to small errors in the sequential placement of masks on the device during the various process steps. Low-defect masks, low defect masking procedures and proper alignment of the masks are important factors in obtaining good yields.
To eliminate cracks in the interconnect leads at steps in the in-sulation, J. S. So, in United States Patent 3,404,~51 issued October 8, 1968, proposes to remove portions of this insulation from the wafer surface during processing. It has also been proposed to slope the edges of the insulation at the contact window. A different approach, disclosed by J. A. Appels, et al in an article entitled "Local Oxidation of Silicon and its Application in Semiconductor-Device Technology" Philips Research Reports 25, page 118 (1970 is to etch grooves into the semiconductor wafer adjacent those regions in which PN junctions are to be formed. The material exposed by the grooves is then thermally oxidized. If the processis properly controlled, the oxide ~ ~ J--6~7~
surface an-~ t~e sur~ace of the semiconductor material are approximately co-planar. An added advantage o~ ~his process" emphasi%ed by Appels et al, is that the portion of the semiconductor warer in which the impurity is diffused has a mesa-like shape. The resulting PN base collector junction is substan-tially flat and has a higher breakdown voltage than does a dish-shaped PN
junction but still contacts passivating oxide, as in the planar process.
In a preferred embodiment of the present invention, a thin silicon epitaxial layer, formed on a silicon substrate, is subdivided into electrical-ly-isolated pockets by a grid of oxidized regions of epitaxial silicon mate-rial (here~fter called "oxidized isolation regions"). These regions are ox-idized through the epitaxial layer to a laterally-extending isolation PN
junction (hereafter called the "isolation PN junction").
At least one side of this isolation PN junction has a resistivity and conductivity type determined by dopants from the substrate. Usually this junction is not coextensive with the metallurgical interface between the epi-taxial silicon layer and the underlying silicon substrate. Rather, during the formation of the epitaxial layer~ the position of the isolation PN junction is determined by dopant concentrations, diffusion constants, and process par-ameters. Its ultimate position is also influenced by the subsequent proces-sing of the wafer.
The isolation PN junction may be made up of a series of P~ junc-tions including PN junctions between buried layers in the substrate and the substrate itself. The isolation PN junction defines a surface which may ex-tend into both the epitaxial layer and the substrate. Each pocket of silicon is isolated by a portion of the isolation PN junction and portions of the ox-idized isolation regions.
Each such pocket can contain active devices, passive devices or both. Cross-under regions of low resistivity can be formed in the substrate to interconnect regions separated by at least one oxidized isolation region.
The top surfaces of the epitaxial layer and the oxidized isolation regions are substalltially coplanar, thereby reducing undesirable elevation variances or "steps" between the isolation oxide and other portions of the wafer sur-face.
~ o form isolated pockets of epitaxial silicon, grooves (sometimes called depressions) are formed in the silicon where isolation regions are to be formed. During groove formation, the remainder of the silicon surface where grooves are not desired is protected by an insulation layer which is substantially unaffected by the silicon etch used to form the grooves. The grooves are etched in a conventional way to a depth of about 50 percent of the desired depth of the oxidized isolation regions. The epitaxial silicon exposed by the grooves is oxidized down to the underlying isolation Pn junc-tion. When the isolation Pn junction lies in the substrate, the oxidation process continues into the substrate so that the oxidized isolation regions penetrate into the substrate to intersect the appropriate portions of the isolation PN junction. Silicon nitride is a convenient insulation to protect underlying silicon from oxidation.
Several different combinations of epitaxial layers and substrates are possible. If the substrate is of one type conductivity (either P-type or n-type), then an epitaxial layer of opposite type conductivity can be grown directly upon the substrate. In addition, buried layers of opposite type conductivity can be formed in the top surface of the substrate and then an epitaxial layer of either type conductivity can be formed on the substrate over the buried layers. In each of these situations, however, the oxidized isolation regions must extend down to the isolation P~ junction.
In one embodiment of this invention, only three diffusion masking steps are required, one to form the buried layer, one to form the oxidized isolation regions and the third to form the emitter regions and the collector sinks in the resulting device. The base mask is eliminated and an unmasked, "sheet" diffusion is used. ~he contact mask alignment is simplified relative to prior art processes because the electrical contacts can be formed abutting 6~

portions o~ the oxide isolation region without danger of short circuits.
Broadly stated, the present invention provides according to a first aspect a dielectrically isolated semiconductor device comprising: a semicon-ductor body; a buried semiconducting region in said body; emitter and base regions located in said body on top of said buried region; and a dielectric-ally isolating region surrounding said emitter and base regions and extending to a depth wherein it intersects with said buried region.
According to a second aspect, the present invention provides a di-electrically isolated semiconductor device comprising: a semiconductor sub-strate; an epitaxial layer on said substrate; a buried semiconducting regionpartially in said substrate and said epitaxial layer; emitter and base re-gions located in said epitaxial layer above said buried region; and a dielec-trically isolating region surrounding said emitter and base regions and ex-tending to a depth wherein it intersects with said buried region.
According to another broad aspect of the present invention, there is provided structure comprising a semiconductor substrate and a semiconduc-tor epitaxial layer upon one surface of said substrate, said epitaxial layer having a substantially flat top surface; and a PN isolation junction extend-ing laterally along the structure forming an isolation barrier between re-gions of said substrate and layer; characterized in that: said epitaxiallayer comprises pockets of epitaxial semiconductor material laterally spaced from each other, each pocket containing selected regions of differing conduc-tivity type, and annular-shaped regions formed at least partly of oxidized portions of said epitaxial semiconductor material surrounding each pocket, said annular-shaped regions extending through said epitaxial layer to said P~
isolation junction, and together therewith electrically isolating said pock-ets of epitaxial semiconductor material from each other, the top surface of said annular-shaped regions being substantially coplanar with the top surface of said epitaxial layer and the underlying substrate having regions of low resistivity interconnecting regions separated by oxidized isolation regions.

According to a ~ur-ther broad aspect of the present invention, there is provided ~ method for fabrica~ing a, dielectrically isolated semiconductor device comprising: forming a region of a first conductivity type within a semiconductor body of a second conductivity type; growing an epitaxial layer onto the surface of said semiconductor body containing said region in a man-ner which results in a movement of impurities of said first conductivity type into the epitaxial layer during its growth which results in an effective ex-tension of said region into said epitaxial layer to form a buried region lo-cated partially within said body and said epitaxial layer; forming a protec-tive layer on the surface of said epitaxial layer in areas where it is sub-sequently intended to have semiconductor devices located; thermally oxidizing the unprotected areas of said surface of said epitaxial layer to a depth which is at least as deep as said buried region wherein a semiconductor reach through region to connect to said buried region remains after said thermal oxidation and said reach through region is dielectrically isolated from other remaining semiconductor regions extending to said surface; removing said pro-tective layer; and forming a semiconductor device in said epitaxial layer.
According to another broad aspect of the present invention, there is provided a method of making a semiconductor structure which comprises the steps of: forming a low resistivity region of one conductivity type in a semiconductor substrate; growing a doped epitaxial semiconductor layer on said semiconductor substrate; forming insulation on said epitaxial semicon-ductor layer; removing portions of said iNsulation overlying the regions of said epitaxial semiconductor layer to be converted into said oxidized isola-tion regions; forming depressions to a specified depth in those portions of said epitaxial semiconductor layer exposed by removal of said insulation;
thermally oxidizing the semiconductor material exposed by said depressions to form in said depressions thermally oxidized semiconductor material extend-ing through said epitaxial layer to an isolation PN junction, thereby to subdivide said epitaxial semiconductor layer into a plurality of electrically ~6~7~3 isolate~ pockets of semiconductor mater:ial, each pocket being surrounded by an annular-shRped re~ion of oxidized semiconductor material; removing said layer of insulation after the epitaxial semiconductor material exposed by said depressions is thermally oxidized through to said isolation PN junction;
and diffusing an impurity of said one conductivity type throug~ a selected region of epitaxial semiconductor material surrounded by an annular-shapea region of oxidized semiconductor material to said low resistivity region of said one conductivity type in said semiconductor substrate thereby to form an electrical contact to said region in said semiconductor substrate.
The above-described invention overcomes a substantial number of disadvantages of prior art integrated circuit structures and provides a sim-plified, improved, and more reliable tecbrlique for their manufacture.
The electrically isolated transistors in integrated circuits fabri-cated according to this invention are more than 65% smaller than comparable transistors isolated using prior art diffusion isolation techniques. Con-trary to normal expectations, despite this size reduction, yields are sig-nificantly improved.
A major portion of the silicon surface area of a representative integrated circuit made according to this invention is not occupied by the circuit elements themselves, but is occupied by the oxidized isolation re-gions. Any defect in the masks used to make the circuit will, therefore, have a very high probability of overlying these isolation regions and not the circuit elements. A mask defect which falls over such an isolation region has absolutely no detrimental effect on the operation of the circuit and is thus rendered harmless. Since mask defects are a major source of integrated circuit yield loss, this neutralization of mask defects in the invented pro-cess enormously increases integrated circuit yields.
Finally, the use of the oxidized isolation regions of this inven-tion decreases unwanted capacitances between adjacent semiconductor pockets and increases the allowable tolerances with which masks must be aligned.

~ ~, ,,, ~, q,i`7~
Indeed, in sollle cases, an entire masking step can be eliminated.
T~le invention will now be described in greater detail with refer-ence to the accompanying drawings, in which:
Fig~re 1 shows in cross-section a typical diffusion isolated inte-grated circuit of the prior art;
Figure 2 shows a top view of a portion of the circuit shown in Fig-ure l;
Figures 3a through 3d illustrate the selective oxidation process disclosed by Appels et al in the article referred to above;
Figure ~ shows an isolated ~P~ transistor and other devices pro-duced using the selective oxidation isolation technique of this invention;
Figure 5 shows an integrated circuit containing an isolated double-diffused transistor, an isolated epitaxial resistor, an isolated base resistor, and an isolated Schottkey barrier diode formed on a wafer selective-ly oxidized according to the techniques of this invention;
Figure 6 shows an isolated PNP transistor formed using the selec-tive oxidation techniques of this invention;
Figures 7a and 7b show a walled-emitter NPN transistor formed using the selective oxidation techniques of this invention;
Figure 8 shows a walled-emitter ~PN transistor and other devices formed using the selective oxidation techniques of this invention;
Figure 9 shows a unique collector sink structure made possible by the structure of this invention, Fig~3res lOa through lOe illustrate the process of this invention;
and Figure 11 illustrates the increase in packing density achieved with this invention by showing in top view the portion of the structure of Figure 7a comparable to the structure shown in Figure 2.
An integrated circuit structure of the prior art is shown in Fig-ures 1 and 2. For clarity, oxide layers, contact windows through the oxide ~ !7 ~

alld lead int;erconnects are not shown. Wafer 10 comprises a P-type substrate r semicondllctor material on which is formed epitaxial layer 12 of N-type semiconductol~ material. A buried collector layer 13 has been formed in sub-strate 11 at the interface of substrate 11 and epitaxial layer 12. Isola-tion grid 14 of P+ type material is shown intersecting the cross-section of the device in two areas, areas 14a and 14b. Each pocket 15a, 15b and 15c of semiconductor material is of a conductivity type opposite to that of the isolation region 14 and substrate. Each pocket is electrically isolated from adjacent pockets of semiconductor material by an isolation PN junction formed around the pocket.
Pocket 15b has formed in it a heavily doped P+ type base region 16.
Base region 16 in turn has formed in it N-type emitter region 17. Contact to the portion of pocket 15b of N-type epitaxial material underlying base re-gion 16 is made through an ~+ type collector sink region 18. ~uried layer 13 insures that most portions of the collector region 15b can be contacted through a low resistance path, as is well known in the art, as disclosed by United States Patent 3,260,902 to Porter.
It should be noted in Figure 1 that the base region 16 is separated from the diffused isolation region 14 by at least the distance dl, deter-mined by masking tolerances and depletion layer thicknesses. In addition,it is desirable to separate buried N+ region 13 from the diffused isolation region 14 by a reasonable distance d2. In certain instances region 13 is allowed to contact the isolation region lL~ with, however, a resulting degrad-ation in breakdown voltage and a significant increase in capacitance. Such devices thus are not suitable for high frequency operation. In addition, it is desirable to maintain the distance d3 between collector sink 18 and iso-lation region 1~. If desired, collector sink 18 can be brought into contact with isolation region 14. However, in such cases the breakdown voltage be-tween the two regions is significantly lower and the capacitance is signif-icantly higher than they are i~ the distance d3 exists between these two re~ions.
In ~daition to tlle prior art structure shown in Figure 1, B. T.Murphy et al, in a paper entitled "~ollector Diffusion Isolated Integrated Circuits" published in ~ol. 57, Proceedings of the IEEE, ~o. 9, pages 1523, 152~ (September 1969) disclose a transistor in which the base region is formed abutting collector sinks contacting an underlying buried collector region. Even with this structure, however, the base region must not contact the P-type region which separates the collector sinks of adjacent transis-tors.
In addition, it is desirable to maintain some clearance between collector sink region 18 and P~ type base region 16 to insure that the col-lector-base junction has a high breakdown voltage and low capacitance. If one accepts the lower breakdown voltage and higher capacitance associated with having the collector sink region 18 in intimate contact with base re-gion 16, the clearance required between collector sink region 18 and base region 16 can be reduced or completely eliminated. However, the usual clear-ance kept between these two regions further increases the size of the device built using these prior art techniques. To achieve the desired separation between the sink region 18 and the base region 16, as well as between the base region 16 and the diffused isolation region 14, very stringent masking tolerances must be maintained. ~ot only does the mask have to be precisely cut to the exact dimension of the collector sink region 18, but the mask must be accurately registered on the device.
P-type resistor region 23 in pocket 15c of ~-type epitaxial semi-conductor material comprises either a base resistor or the emitter of a P~P
transistor which has substrate 11 as its collector. A portion of pocket 15c may be a base region of this transistor, contact to which is made in a stan-dard manner. Region 22, nested in P-type region 21, forms an emitter-base diode with region 21.
Contacts 24a and 24b and the intermediate epitaxial material form 66~l'7~
an epit~ial resistor. Tlle dimerlsions of this epitaxial resistor are de-fined by isolation regions (not shown) similar to region 14 and by the spac-ing between contacts 24a and 21~b.
A typical prior art processing sequence for forming isolated pock-ets of semiconductor material containing ~PN transistors is as follows:
1. Oxidize P-type substrate;
2. Mask and diffuse ~+ buried collector;
3. Strip oxide and grow N-type epitaxial silicon layer;
4. Oxidize surface of epitaxial 1ayer;
5. Mask, diffuse and oxidize isolation regions;
6. Mask, diffuse and oxidize base regions,
7. Mask, diffuse and oxidize emitter and collector sink regions;
8. Mask areas for metal-silicon contacts,
9. Deposit and mask metal interconnections.
The above process has six masking steps. Each masking step except the last involves the opening of windows in the layer of oxide covering the wafer being processed. The remaining oxide serves as a barrier to the dif-fusion of dopant atoms into the semiconductor wafer.
Figure 2 shows in top view the relationship of collector sink 18 to the emitter region 17 and the base region 16 shown in cross-sectional view in Figure 1 as formed in semiconductor pocket 15b. The closed shape of diffused isolation region 14 surrounding pocket 15b is shown in Figure 2.
Base region 16 is necessarily separated from isolation region 14.
This separation is necessary for electrical isolation of these two regions.
Figures 3a through 3d show the technique used by Appels et al in the above-cited reference to form a discrete transistor. Over an ~-type sub-strate 31 (Figure 3a) is deposited silicon nitride layer 33. In some cases, Appels et al use a thin layer 33a of an oxide of the semiconductor material deposited between substrate 31 and silicon nitride layer 33. A layer 34 of an oxide of the semiconductor material is deposited on nitride layer 33.

'~. e:,.

6~7~
Next, willdows are ~ormed in oxide layer 34 in the locations shown b~ the dnshed lines 31~a and 34b (Figure 3a). The nitride exposed through these windows is etched away. The etchant used for silicon nitride (typ-ically phosphoric acid) has little effect on the oxide layers. When the nitride beneath the windows has been removed, a new etchant (such as buf-fered HF) which removes the oxide is used. This etchant has little effect on nitride and thus the remaining portions of nitride layer 33 (Figure 3b) mask the underlying oxide 33a, if any, and the silicon. The portions 35a and 35b of substrate 31 exposed by windows 3~a and 3~b through oxide layer 33a (if any) and nitride layer 33, are etched away to a selected depth to form shallow grooves.
The wafer is then thermally oxidized (Figure 3c). No oxide will grow on the surface of substrate 31 beneath the remaining nitride 33. How-ever, in those portions 35a and 35b of wafer 30 where nitride has been re-moved oxide will grow in the semiconductor material. Tbis local oxidation of silicon, called LOCOS by Appels et al, fills the grooves 35a and 35b with an oxide of the semiconductor material.
Studies cited by Appels et al show that the silicon oxidizes at a much faster rate than does the silicon nitride. Thus, the structure shown in Figure 3c, with grooves 35a and 35b filled with silicon oxide, is ob-tained by placing wafer 30 in an oxidizing environment. The oxidized top portion of nitride layer 33 has been removed from the wafer shown in Figure 3c.
After oxidized regions 35a and 35b have been formed, nitride 33 is removed by a nitride etch, as shown in Figure 3d. Then, oxide 33a (if any) is stripped from substrate 31, and a P-type impurity is diffused into region 36 of substrate 31. Oxide regions 35a and 35b mask the P-type impurity and thus restrict the lateral extent of PN junction 36a to that region of sub-strate 31 between oxidized regions 35a and 35b.
Oxide layer 37 (Figure 3d) is then reformed on the surface of sub-. ~

~1~3~`78 strate 31 q~nd a win~iow 38n is ~orn~ed in this oxide layer. Then an ~-type impurity is dif~lse(l tllrough -this window to form an N-type emitter region 38 in P-type base region 36. Thus Appels et al essentially disclose a tech-nique of obtaining a flat base-collector junction. Because this Junction is flat, its breal~down voltage is higher than the breakdown voltage commonly associated with a t~rpical dish-shaped base-collector junction. The emitter-base junction, however, is dish-shaped as shown.
Figure 4 shows the structure of this invention wherein oxide iso-lation techniques are novelly applied to a silicon epitaxial structure hav-ing a PN isolation junction to subdivide the epitaxial silicon layer intofully isolated pockets. In this specification when a pocket of semiconduc-tor material is described as isolated by an annular-shaped isolation region of oxidized semiconductor material, it shall be understood that in the simp-lest case a PN isolation junction underlies the pocket of semiconductor material and intersects the isolation region of oxidized semiconductor mate-rial so that the line of intersection forms a closed path. This definition also covers the structure which results when a buried collector layer ex-tends in the substrate from one pocket to another pocket so as to inten-tionally connect regions in pockets which would otherwise be electrically isolated. In this case the term "isolated pocket of semiconductor material"
shall be defined to include all pockets of semiconductor material electri-cally connected by the buried layer. In this case from one to many closed paths of intersection between the oxidized semiconductor material and P~
isolation junctions may occur in isolating the interconnected semiconductor material from other pockets of semiconductor material. The term "annular"
will be used to mean any closed path of any shape, whether uniform or non-uniform in width. Thus the term "annular-shaped isolation region" is used in this specification to include all possible shapes of oxidized isolation regions which completely define the lateral limits of one pocket of semi-conductor material.

73~
The ~)rocess o~ this invention yields a structure in which a signif-icant portion of the epitaxial silicon layer is oxidized through to a PN iso-lation Junction. Each annular-shaped isolation region includes all the oxi-dized silicon adjacent to a pocket of isolated epitaxial silicon. A given region of oxidized silicon can serve as part of the annular-shaped oxidized isolation region of more than one isolated pocket of silicon.
Wafer 40 comprises a P-type silicon substrate 41 in which are dif-fused N+ regions 43a and 43b. Region 43a serves as a buried collector, and a cross-under beneath the oxidized isolation region 44b of this invention.
Formed on the top surface of substrate 41 is P-type silicon epitaxial layer 42. Formed in grooves etched in epitaxial layer 42 are oxide isolation re-gions 44a, 44b, 44c, and 44d. These oxidized isolation regions are formed by first covering the surface of epitaxial layer 42 with a nitride layer, typ-ically silicon nitride, and then removing the nitride over those portions of epitaxial layer 42 in which the grooves are to be formed. The grooves are formed and then oxidized to define the isolation regions.
While one embodiment of this invention uses a silicon nitride layer to make those portions of the epitaxial semiconductor material in which grooves are not to be formed, any insulation layer which masks against thermal oxidization of the underlying semiconductor material and which has an etch rate significantly slower than that of the oxide of the semiconductor mate-rial and of the semiconductor material can be used in place of silicon ni-tride.
Epitaxial layer 42 is a true thin film being less than 5 microns thick and typically about 1.25 microns thick. Practical limitations on the thicknesses of adherent oxide limit the thickness of the oxide formed from the silicon to less than three microns. Thicker oxides crack and peel. A
practical limit on the thinness of epitaxial silicon layer 42 is the minimum thickness below which transistor action is no longer obtained. When epi-taxial layer 42 is 1.25 microns thick, the grooves are etched approximately - ~4 -~J~ 7 ~

7,000 angstroms into layer 4i2. T~en the etched grooves are oxidized. The resulting silicon oxide extends both above and below the initial exposed sur-face of eacll groove. For a 1.25 micron epitaxial layer, normally about 1.2 microns of oxide i~i grown. Oxide extends about 1,500 angstroms past the underlying PN isolation junction. When epitaxial silicon layer 42 is another thickness, tbie groove depth is appropriately selected so that the oxide ex-tends past the PN isolation junction, contrary to the teachings of the prior art.
Next, nitride is removed from epitaxial layer 42. (In some varia-tions of the process of this invention, a P-type base contact diffusion through window 48b to a depth shown by line 45d, is incorporated into the process at this point.) Then, the surface of epitaxial silicon layer 42 is oxidized. Oxide is removed from over region 45a. N-type impurities are then diffused into region 45a to form a collector sink which extends to buried col-lector layer 43a. The lateral extent of sink 45a is defined by an annular oxidized region of which sections 44a and 44b are shown in cross-section in Figure ~1. In some circumstances the sequence is reversed to allow the dif-fusion of the collector sink region 45a before the base-contact diffusion.
N-type impurities are next diffused into region 45b of P-type epitaxial layer 42 through window 48a in oxide 46 to form emitter region 47.
Thus, buried collector 43a, epitaxial base 45b and diffused emitter 47 form an NPN transistor. The base 45b of this transistor is completely isolated from adjacent regions of epitaxial layer 42 by an annular oxidized isolation region shown in section as 44b and 44c, extending to or beneath the PN iso-lation junction. Regions 45a and l~5b together with buried layer 43a form cne isolated pocket isolated by annular-shaped oxidized isolation regions of which sections 44a and 44c are shown, and a PN isolation junction comprising the PN junction between buried layer 43a and substrate 41. ~indow 48b, cut through oxide 46, allows contact to be made to epitaxial base 45b.
In section 45c of epitaxial layer 42 is shown a resistor. This ,. j, i iL~lL~6`~7~

resistor cnn be eltller A base resistor or an epi-taxial resistor depending on whether an added ba~e layer diffusion (as indicated by line 45c) is employed in this area or not. This resistor is covered by oxide layer 49 through which windows can be cut for contac-t to the resistor. Material 45c is elec-trically isolated from substrate 41 by ~+ region 43b and isolated laterally by an annular oxidized isolation region (sections 44c and 44d).
Region 45c may be connected through the PN diode formed by region 45c and buried layer 43b to another buried layer in the same substrate 41 by a cross-under, similar to cross-under 43a, which extends an oxidized isola-tion region 44b, 44c.
A lead interconnection pattern is then formed on the surface of thewafer to interconnect selected active and passive components into the desired circuit. The leads are typically metal such as aluminum, although conductive semiconductor material or other conductive material can also be used.
Thus, to make the structure shown in Figure 4, a typical processing sequence is summarized as follows:
1. Oxidize P substrate.
2. Mask and diffuse ~-type regions which serve as buried collec-tors, cross-unders and isolation regions (Figure lOa, regions 43a, 43b).
~O 3. Strip oxide and grow a thin P-type epitaxial silicon layer (Fig-ure lOb, layer 42).
4. Deposit and mask a silicon nitride layer (Figure lOb, layers 141a, 141b, 141c).
5. Etch and oxidize isolation regions (Figures lOc, regions 44a, 44b, 44c, 44d).
6. Remove nitride, either partially or completely according to the following rules:
a. When no base contact predeposition is made, and when no epi-taxial resistors are to be formed in the epitaxial material, completely re-move the nitride without a masking step (Figure lOc, layer 141b).

6~7~3 b. Where epitaxinl resistors, channel regions for MOS devices, or high hf transistors are to be made, leave the nitride as mask against dif-fusion, (Figure lOc, layers 141a, 141c), remove nitride from other regions.
7. Perform base contact predeposition and diffusion if desired (Figure lOc, region 142) masking with photoresist 145a and 145b.
8. Remove the remaining nitride, if any, and oxidize the wafer (Figure lOd, layers 143, 46, 49).
9. Mask (Figure lOd, remove layer 143) diffuse collector sinks (Figure lOd, region 45a) and reoxidize, if desired (Figure lOd, replace layer 143).
10. Mask (Figure lOd, cut window 48a in oxide layer 46) and diffuse the emitters (Figure lOd, region 47).
11. Mask contact cuts (Figure lOe, contact windows 48a, 48b, and removal of layer 143).
12. Deposit metal interconnect layer, mask interconnect pattern (Figure lOe, metal 144a, 144b and 144c) and alloy. A total of six or seven masking steps are required.
In the two cases where there is no masking step associated with the removal of nitride under step 6a, the process of this invention eliminates one masking step compared to those common processes which include a separate collector sink mask and diffusion.
As indicated in Figure 4 this process provides:
1. NP~ transistors (regions 43a, 45b, 47) 2. Diodes (regions 45b, 47 and 43a, 45b) 3. Epitaxial resistors (~5kQ/square) (region 45c) 4. Base resistors (~600Q/square) (region 45b and 45c with base contact predeposition) 5. Buried collector cross-unders under isolation (region 43a).
Step 6 above, the base mask step, demonstrates the advantage of oxide isolation of the invention. Masking the base involves the removal of 6~i7~
nitride. The nitri~le may be removed with very little etching of the oxide isolation so that an oversize base mask (see photoresist 145a and 145b in Figure lOc) may be used. The actual dimensions of the base region are then defined by the isolation regions 44b, 44c. This mask may be eliminated en-tirely if a sheet base diffusion is used.
Similarly, regions covered with a thin oxide, such as collector sink region 45a, Figure lOd, can be etched through an oversized mask without a detrimental effect on the adjacent oxide isolation. The collector sink 45a contacts the buried collector 43a beneath the P-type epitaxial silicon layer.
A separate masking step is used to expose the surface of the collector sink 45a. The boundaries of the sink are defined by the oxide isolation 44a, 44b so that the sink is pre-aligned to the base 45b, the oxidized isolation re-gion 44a, 44b, and the buried collector 43a. Collector sink 45a can be formed either before or after base region 45b is formed.
Step 8 above, removal of nitride and oxidation, places an oxide protective covering over areas which should not receive sink or emitter dif-fusions. Buried collector resistors are formed in the normal fashion. Base resistors and epitaxial resistors can be defined by the boundaries of the oxide isolation and the Q/square is controlled by controlling the dopant con-centration and the depth of the base diffusion and the epi resistivity.
The emitter regions, contacts, metallization and metal delineation are completed in the usual manner.
Unexpected advantages over the prior art accrue from the process and structure of this invention. First, the oxidized isolation regions de-fine the lateral extents of the collector sinks, transistor base regions, and epitaxial and base resistors, thereby in some cases reducing the total number of masking steps required to produce an integrated circuit.
Second, the intimate contact of the base resistor, and the collector sink regions to the oxidized silicon results in a much higher packing density.
With prior art difFused isolation techniques, this was not possible because - 18 ~

~6q~78 the isolation regions were conduc-tive and undesired short circuits would then exist between the bnse and resistor regions on the one hand, and the conduc-tive isola-tion region on the other hand. Since this invention uses insulat-ing oxide for part of the isolation, the base can extend to the isolation region with no danger of breakdown or a short circuit between the base re-gion and the isolation region. Likewise for the same reasons, the emitter can also be formed directly abutting the oxide isolation.
~ hird, use of thinner epitaxial layers than common in the prior art reduces consumption of surface area by lateral movement of the isolation dur-ing its formation. The oxidization of the semiconductor layer is essentiallycompleted when the oxidization reaches the laterally extending PN isolation junction. Packing densities can be higher with thin epitaxial layers than with thick epitaxial layers because less surface area is consumed by lateral expansion of the isolation. This lateral expansion is about twice the depth of the isolation which in turn is about equal to the thickness of the epi-taxial silicon layer.
Fourth, the invented structure reduces the capacitance and in-creases the breakdown voltage to sidewall (i.e. the vertical pocket wall).
Fifth, another advantage is that defects in masks and masking pro-cesses, such as tears and pinholes, have less effect on the resulting cir-cuit. For example, defects in the isolation mask in the prior art result in the formation of undesired fused isolation areas where the pinholes or other defects are located. In this invention, however, these defects merely re-sult in the formation of additional oxide. Defects in other masks have a high probability of falling over oxidized isolation regions of semiconductor material where they have no significant detrimental effect on the resulting circuit. For example, defects in the base diffusion mask which connect the base to the isolation regions have no effect on the performance of the cir-cuit. Similarly, defects in contact masks have little or no effect because a spurious partial penetration of metal in-to an oxidized isolation region of `6~78 the device has no effect on device per~ormance. A defect in an emitter mask, wbich in prior art devices can short an emitter region to a collector region, has no effect on the device of this invention. Finally, defects connecting the emitter region to an isolation region have little or no effect on the performance of the invented device.
Figure 5 shows the oxidized isolation technique of this invention used to form an integrated circuit containing double-diffused transistors.
Wafer 50 comprises P-type substrate 51 having a surface N-type silicon epi-taxial layer 52. Formed in the top surface of substrate 51 adjacent the interface of this substrate with epitaxial layer 52 is N+ buried collector region 53a. Contained in epitaxial layer 52 are oxidized regions shown by cross-sections 54a, 54b, 54c, 54d, 54e, and 54f. The top surfaces of oxi-dized regions 54 are approximately in the same plane as the top surface of epitaxial layer 52. N+ type collector sink 56a formed in epitaxial layer 52 contacts N~ buried collector layer 53a through~N-type epitaxial material 55a.
Sink 56a can be formed simultaneously with emitter region 57a. Collector sink 56a is separated from adjacent regions of epitaxial layer 52 by an annu-lar isolation region of oxidi~ed silicon of which cross-sections 54a and 54b are shown. N+ buried collector layer 53a crosses under a portion of oxidized region 54b and contacts N-type epitaxial material 55b. Region 55b serves as the collector of a transistor. Just above region 55b and separated there-from by a substantially plane PN junction 55f is P~ type base region 56b, formed by a standard diffusion process. During the base diffusion the oxi-dized annular region including sections 5~b and 54c defines the lateral ex-tent of the base.
Annular isolation regions 54 allow masks to be placed on the wafer with less accuracy than would otherwise be the case. This is so since even though some of th~ remaining portions of epitaxial material 52 must be masked to prevent impurity diffusion, oxidized regions 54 limit the lateral extent of the base diffusion. Thus, the tolerances on the masking to form P6~:`7~

base 56b ~re l~elaxed compared to prior art techniques and yet base region 56b is foImed very accurately.
After the base region 56b is formed, oxide 58 is formed over the surfaces of epitaxial semiconductor material 52 and a window 59a is cut through this oxide 58. An N-type dopant is diffused through window 59a to form emitter region 57a of the transistor. Thus, between oxidized regions 54b and 54c is formed an NPN double-diffused, oxide-isolated transistor.
Base contact to this transistor, made through window 59b in oxide 58, can be permitted to overlap -the adjacent oxidized isolation region 54c.
In region 55c of epitaxial layer 52 is formed an epitaxial resis-tor. Contact to this resistor is made through highly-doped N-type regions 57b and 57c formed in openings in oxide 58. Resistor 55c is isolated from adjacent regions of the integrated circuit by an annular oxidized region 54c, 54d. Alternatively, this resistor can be contacted by one or more highly conductive cross-unders similar to ~ region 53a.
A base resistor is formed in region 55d of epitaxial layer 52. A
P-type impurity is diffused into ~-type epitaxial region 55d to form P-type region 56d. Contact to this base resistor is made through winaows 57d and 57e opened on both sides of oxide 58 about P-type semiconductor material 56d.
This resistor is called a base resistor in view of the fact that the conduc-tivity type and dopant level of the resistor are substantially the same as those of the base region 56b of the NPN transistor formed in section 55b of epitaxial layer 52. Sections 54d and 54e are part of an annular oxidized isolation region surrounding layers 55d and 56d to isolate these layers from the remainder of epitaxial layer 52. An N+ buried layer 53b, shown in dashed lines, may, if desired, be placed beneath material 55d and in contact with the surrounding oxidized isolation region 5~d, 5~e to increase the breakdown voltage of this resistor to substrate 51.
Shown attached to the top surface of region 55e of epitaxial mate-rial is metal layer 59c. Layer 59c forms a Schottky-barrier diode with the ,;~4~-D6~!78 underlying ep;taxi~l mnterial. This diode i8 isolated from ad~acent regions of epitaxial layer 52 by annular re~ion 54e~ 54f surrounding N-type epi-taxial material 55e. An N+ buried layer 53c (shown in dashed lines) may also be placed under this diode to increase the device breakdown voltage and decrease series resistance.
The N-type epitaxial layer can be used to form N-type epitaxial resistors as shown by region 55c in Figure 5. These resistors can be used as collector resistors without a special metal connection from resistor to collector.
10 Figure 6 shows a PNP transistor formed using the oxide isolation technique of this invention. Wafer 60 comprises a P-type silicon substrate 61 which serves as the collector of the PNP transistor. Formed in P-type substrate 61 is N+ buried layer 63. Layer 63 extends beneath oxidized iso-lation region 64b formed in N-type epitaxial silicon layer 62. Epitaxial layer 62 overlies the top surface of substrate 61. N+ region 63 connects N-epitaxial material 65a, surrounded by annular shaped oxidized isolation re-gion 64a, 64b with N-type epitaxial region 65b surrounded by annular-shaped oxidized isolation region 64b, 64c. N-type base region 65b is contacted through region 66a of N+ type material, N epitaxial region 65a and N+ buried layer 63. A P-type impurity is diffused into region 66b to form the emitter of the PNP transistor. The emitter-base junction between regions 66b and 65b is substantially flat.
Because the emitter region 66b occupies the complete surface area surrounded by one annular oxidized isolation region 64b, 64c, the masking tolerances on the formation of the emitter region are less critical than with prior art devices of the same size.
In the structure of Figures 5 and 6, it should be noted that epi-taxial layers 52 and 62 are N-type rather than P-type. This means no buried layer is necessary under ~esistors and the collector sink diffusion can be replacea by a shallower emitter diffusion and masked by the emitter-masking , . . .

step~ The base is formed by the base diffusion and the epitaxial layer now acts as the collector of the NPN transistor (Figure 5).
The N-type epitaxial layer is also useful for fabrication of sub-strate PNP transistors in which the P-type base of an NPN transistor forms the emitter of PNP transistor. The N-type epitaxial layer forms the PNP
base and the P-type substrate acts as the collector of the PNP transistor.
With this arrangement, the transistor shown in Figure 5 has buried layer 53a reduced to a size such as shown by dashed line 56e. This device is called a substrate contro]led switching transistor or SCST.
Figures 7a and 7b show a structure in which the layout of the col-lector, the emitter and the base has been changed, thus affecting the emit-ter-isolation spacing. The processes used above to fabricate the structure shown in either Figure L~ or in Figures 5 and 6 can be used. The structure shown in Figures 7a and 7b is called the walled-emitter transistor because the emitter is allowed to contact the oxide isolation. As shown in Figure 7a wafer 70 comprises a P-type silicon substrate 71 in which is diffused an N+
buried collector layer 73. N-type epitaxial layer 72 is grown on the top surface of substrate 71 (this layer could also be P-type). Oxidized isola-tion regions 74a, 74b and 74c are formed in epitaxial layer 72 using the techniques described above. A collector contact region 75a is formed in epitaxial layer 72 and is surrounded by an annular oxidized isolation region 74a, 74b. In region 76 of epitaxial layer 72, an impurity is diffused to form a P+ type base region 75c. The P~ ~unction 74f between P+ base region 75c and the epitaxial region 76 is approximately flat and extends to an annular-isolation region, 74b, 74c. Next, an oxide layer 77 is formed on the top surface of epitaxial layer 72 and a window 77a is formed in this oxide layer. Through window 77a an N-type impurity is diffused to form emit-ter region 75b. Contact to base region 75c is made through window 77b in oxide 77. Emitter region 75b abuts against a part of oxidized isolation re-gion 74b. The top view of the circuit shown in Figure 7b illustrates the 7~3 pO5itiOllS of the collector, base and emitter contacts and the oxidized iso-lation regions. The collector, base and emitter contacts each can extend over the adjacent c,xidized isolation regions thereby significantly decreas-ing the difficulty of aligning the contact mask.
In forming the transistor shown in Figure 7a, care must be taken that the impurity concentration in region 75d of base region 75c is suffi-ciently high to prevent unwanted inversion, depletion, or channel formation, particularly adjacent oxide region 74b.
Figure 8 shows another wallea-emitter NPN transistor constructed using the oxidized isolation regions of this invention. Wafer 80 comprises P-type silicon substrate 81 on which is formed N-type silicon epitaxial layer 82. Formed in subc;trate 81 is N+ type buried collector region 83. Oxidized isolation regions 84a through 84d extend to or through the isolation PN
junction. Collector contact to collector region 85b is made through collec-tor contact 88a attached to collector sink 87a formed in portion 85a of epi-taxial layer 82. ~ase region 86a is diffused into underlying ~-type epi-taxial region 85b of epitaxial layer 82. The P~ junction between the base region 86a and collector region ô5b is approximately flat. Emitter region 87b is formed in one side of base region 86a adjacent the annular-shaped ox-idized isolation region 84b, 84c. Contacts to the emitter region 87b and the base region 86a are made through contacts 88b and 88c overlying windows in oxide layer 89. In this case, both the emitter diffusion mask and the emitter contact metal mask, if used, can overly the adjacent isolation ox-ide, greatly relaxing masking tolerances. An N-type epitaxial resistor is formed in semiconductor region 85c of epitaxial layer 82, surrounded by annular-shaped oxidized isolation region 84c, 84d. Contact to this epitaxial resistor is made through metal layers 88d and 88e contacting regions of epi-taxial material 85c through windows in oxide 89.
Surrounding base region 86a7 collector sink 87a, and epitaxial ~O resistor 85c, and abutting the oxidized isolation regions surrounding these ~r 6q:~'^YB

regions, is a F~+ gnard ring of which cross-sections 86b through 86g are shown. In some structures these guard rings may extend to the isolation PN
junction. These guard rings, in one embodiment, are formed by etching the surfaces of the oxidized isolation regions prior to the removal of the ni-tride and immediately after the oxidized isolation regions are formed, and then diffusing the P-type impurity into the -thus exposed silicon. This solves the problem discussed above in connection with region 75d of base 75c shown in Figure 7c. It should be noted that the guard ring diffusion is self-aligning with respect to the oxidized isolation region and requires no additional masking step. All the other devices disclosed in this applica-tion can also be fabricated with such a self-aligned guard ring of whatever type conductivity is appropriate and with the walled emltter structure.
Furthermore, it should be noticed that in the structure of Figure 5, a pinhole in the isolation mask might very well result in oxidizing a por-tion of epitaxial layer 72 to be surrounded by an emitter region. In this situation, even if the emitter region was not to abut an oxidized isolation region, the emitter in effect abuts a portion of that oxidized isolation region formed inadvertently by the pinhole. Accordingly, in carrying out the diffusion of the P+ guard ring, as discussed above in conjunction with Figure 8, the ring will also be diffused around this spurious portion of oxidized isolation material, thereby reducing or eliminating the effect of inversion layers, aepletion regions and channeling on the performance of the device.
Figure 9 shows a unique collector sink structure made possible by this invention. P-type silicon substrate 91 has N+ buried layer 93 formed in its top surface. Silicon epitaxial layer 92 of more highly-doped N-type material is next formed on the top surface of substrate 91. Oxidized annu-lar regions of epitaxial silicon, of which cross-sections 94a and 94b are shown, define the lateral extent of isolated silicon pockets. Formed in pocket 96a is a collector sink 96f. To form this sink, a portion of the .;

~, `78 oxidized semiconductor material 9~b adJacent this sink is etched away to expose a portion of the side of the adJacent epitaxial silicon. N-type im-purities are then diffused into tbe exposed epitaxial semiconductor material to place a high concentration of impurities along the portion 96f of the epitaxial silicon exposed by etching away part 96e of oxidized isolation re- f gion 94b. This highly conductive semiconductor material contacts directly the underlying ~-type collector 93. Cavity 96e, formed by etching away a portion of the oxidized isolation region, is limited in size such that it does not completely surround the collector sink and rather occupies only a 10small portion of the circumferential area of the collector sink. This allows metal contact to be made to the collector sink without having to go down into portion 96e removed by the etch and back up to the collector sink.
The five masking steps necessary to define completely the structure shown in Figure 9 are as follows:
(1) Definition of buried collector;
(2) Definition of the isolation regions;
(3) Definition of the emitter and collector sink regions (4) Definition of the contact areas; and (5) Definition of the metal interconnect pattern.
Significant advantages are derived from the process and structure of this invention. One major advantage of the process is the size reduction provided by eliminating the need for clearances between the base and emitter regions and oxidized isolation regions. Using the techniques of this inven-tion, the emitter and base regions can be formed directly abutting adjacent oxidized isolation regions.
Figure 11 illustrates the significant reduction in size of a tran-sistor produced using the oxidized isolation techniques of this invention compared to a transistor produced using prior art diffused isolation tech-niques. Figure 11 shows a top view of the transistor shown in Figures 7a and 7b placed within the diffused isolation region 14 surrounding the prior ~1~6~7~

~ t transistor shown in top view ln Figure 2. Both structures are drawn to t~Le s~le scale. ~c is apparent, the centerline l~a of the prior art dif~
fused isolation region 14 surrounds a considerably larger area than does the centerline 74d of t;he oxidized isolation region surrounding the transistor shown in Figure 7a. Shown clearly in this figure is the fact that collector contact 75a is adjacent oxidized isolation region 7~a, emitter contact 75b is adjacent oxidized isolation region 74b and base contact 77b is adjacent oxidized isolation region 74c. ~he buried collector beneath the base emitter and collector regions is denoted by dashed line 73 shown slightly outside the base, emitter and collector contact regions. The area reduction of at least 65% per transistor obtained with this invention is apparen-t from this figure. A second advantage lies in the elimination of the detrimental e~-fects of defects in the masks and masking procedures used to define the iso-lation regions and t~Le di~used regions in the device.
I~ desired, the collector sink can be covered with an oxide layer at various times in the process. Placing oxiae on the collector sink allows the collector sink to be used independently as a low resistivity cross-under beneath an overlying lead.
Different kinds of resistors may also be formed in the invented structure:
1. A buried collector under isolation, (Figure 5, region 53a);
2. A buried collector not under isolation (Figure 5, region 53f).
This buried collector has a slightly lower resistivity than the buried col-lector under oxide;
3. ~pitaxial resistors, using either P-type (Figure 4, region 45c) or ~-type (~igure 5, region 55c) material;
4. A pinched epitaxial resistor which can be pinched by the emitter (Figure 4, region ~5b). Such a resistor is formed in the base re-gion. If pinched by the base (Figure 5, region 55b) the resistor is formed in the epitaxial ~Laterial adjacent, and usually underneath, the base 11~6~7~3 5. A base resistor o~ P-type (Flgllre 5, region 56d) or N-type (obvious frolll structure with all conduc1;ivity types reversed) material;
6. I~nitter resis-tors (made by contacting any emitter region in two places);
7. A co:Llector sink resistor (Figure 5, region 55a). All these resistors give additional design flexibility in working out optimum circuits.
While certain embodiments of this invention have been described, other related structures and processes will be obvious in view of t~is dis-closure. In particular structures complimentary to those described in this specification can be obtained by reversing the conductivity type o~ each region in each structure.

~-r

Claims (61)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. Structure comprising a semiconductor substrate and a semiconductor epitaxial layer upon one surface of said substrate, said epitaxial layer having a substantially flat top surface; and a PN isolation junction extending laterally along the structure forming an isolation barrier between regions of said substrate and layer; characterized in that: said epitaxial layer comprises pockets of epitaxial semiconductor material laterally spaced from each other, each pocket containing selected regions of differing conductivity type, and annular-shaped regions formed at least partly of oxidized portions of said epitaxial semiconductor material surrounding each pocket, said annular-shaped regions extending through said epitaxial layer to said PN
isolation junction, and together therewith electrically isolating said pockets of epitaxial semiconductor material from each other, the top surface of said annular-shaped regions being substantially coplanar with the top surface of said epitaxial layer and the underlying substrate having regions of low resitivity interconnecting regions separated by oxidized isolation regions.
2. Structure as in claim 1 wherein said epitaxial layer has a thick-ness of 1.25 microns.
3. Structure as in claim 1 of wherein said substrate is of one type conductivity and said epitaxial layer is of the opposite type conductivity and including a low resistivity first region of opposite conductivity type formed in said substrate adjacent to said epitaxial layer of semiconductor material, and a low resistivity second region of opposite conductivity type, said second region extending from the surface of said epitaxial layer above said low resistivity first region, said second region being surrounded by an annular-shaped oxidized isolation region extending through said epitaxial layer to said first region in said substrate.
4. Structure as in claim 3 wherein said first region extends under-neath a portion of said oxidized isolation region and into contact with another adjacent region of epitaxial semiconductor material.
5. Structure as in claim 4 wherein said adjacent region of epitaxial semiconductor material comprises: a collector region of opposite conductivity type contacting said first region; a base region of one conductivity type extending to the annular-shaped oxidized isolation region surrounding said adjacent region of epitaxial semiconductor material; and an emitter region formed of opposite conductivity type in said base region.
6. Structure as in claim 5 wherein said emitter region abutts a portion of the annular-shaped oxidized isolation region surrounding said adjacent epitaxial region of semiconductor material.
7. Structure as in claim 5 wherein the surface of said epitaxial semiconductor material is covered by an insulating layer containing therein windows through which a separate first contact is made to each of said second region, said base region and said emitter region.
8. Structure as in claim 7 including a second contact to said second region and a third contact to said second region, said second and third contacts being separated by a selected distance thereby to form a resistive path from said second contact to said third contact through the said second region.
9. Structure as in claim 7 including a second contact to said base region and a third contact to said base region, said second and third contacts to said base region being separated by a selective distance thereby to form a base resistor between said second contact and said third contact to said base region.
10. Structure as in claim 7 wherein two windows are formed in the insulation overlying a pocket of epitaxial semiconductor material thereby to form an epitaxial resistor from the epitaxial semiconductor material between said two contacts.
11. A method of making a semiconductor structure which comprises the steps of: forming a low resistivity region of one conductivity type in a semiconductor substrate; growing a doped epitaxial semiconductor layer on said semiconductor substrate; forming insulation on said epitaxial semi-conductor layer; removing portions of said insulation overlying the regions of said epitaxial semiconductor layer to be converted into said oxidized isolation regions; forming depressions to a specified depth in those portions of said epitaxial semiconductor layer exposed by removal of said insulation;
thermally oxidizing the semiconductor material exposed by said depressions to form in said depressions thermally oxidized semiconductor material extend-ing through said epitaxial layer to an isolation PN junction, thereby to subdivide said epitaxial semiconductor layer into a plurality of electrically isolated pockets of semiconductor material, each pocket being surrounded by an annular-shaped region of oxidized semiconductor material; removing said layer of insulation after the epitaxial semiconductor material exposed by said depressions is thermally oxidized through to said isolation PN junction;
and diffusing an impurity of said one conductivity type through a selected region of epitaxial semiconductor material surrounded by an annular-shaped region of oxidized semiconductor material to said low resistivity region of said one conductivity type in said semiconductor substrate thereby to form an electrical contact to said region in said semiconductor substrate.
12. The method of claim 11 including the additional steps of: masking said epitaxial semiconductor layer to leave exposed another region of epitaxial semiconductor material above said region in said semiconductor substrate; and diffusing an impurity of opposite conductivity type into said another region to a selected depth.
13. The method of claim 12 including the additional steps of: masking a portion of said another region into which said impurity of said opposite conductivity type has been diffused; and diffusing an impurity of said one conductivity type into a selected portion of said another region of epitaxial semiconductor material containing an impurity of said opposite conductivity type.
14. A silicon structure comprising: a semiconductor silicon substrate;
a semiconductor silicon epitaxial layer upon one surface of said substrate, said epitaxial layer having a substantially flat top surface, and a PN
isolation junction extending laterally along the structure forming an isolation barrier between regions of said substrate and layer; said epitaxial layer comprising epitaxial silicon pockets laterally spaced from each other, each pocket of epitaxial silicon material containing selected regions of differing conductivity types, and annular-shaped regions formed of thermally oxidized portions of said epitaxial silicon layer surrounding each pocket, said annular-shaped regions extending at least to said isolation junction and together therewith electrically isolating said epitaxial silicon pockets from each other, and the top surface of said annular-shaped regions being substantially coplanar with the top surface of said epitaxial layer; and regions of low resistivity formed in the underlying silicon substrate to interconnect pockets separated by thermally-oxidized isolation regions.
15. A semiconductor structure comprising: a silicon substrate of one conductivity type, said substrate including a low resistivity first region of opposite conductivity type formed in said substrate adjacent one surface;
an epitaxial silicon layer having a substantially flat top surface formed on said one surface, a PN isolation junction extending laterally along the structure forming an isolation barrier between regions of said substrate and layer, said epitaxial silicon layer comprising epitaxial silicon pockets laterally spaced from each other and annular-shaped regions formed of oxidized portions of silicon material surrounding said epitaxial silicon pockets and defining the lateral extent of each of said pockets, said annular-shaped regions being formed at least partly from, and occupying a significant portion of the epitaxial silicon layer and extending through said epitaxial silicon layer to said PN isolation junction and together therewith electric-ally isolating said epitaxial silicon pockets from each other, and the top surfaces of said annular-shaped regions being substantially coplanar with the top surface of said epitaxial silicon layer; and a second region of opposite conductivity type formed in said epitaxial silicon layer above at least a part of said low resistivity first region, said second region includ-ing a low resistivity portion extending from the surface of said epitaxial silicon layer toward said low resistivity first region, said second region being surrounded by an annular-shaped oxidized isolation region extending through said epitaxial silicon layer to said first region in said substrate, said first region extending underneath a portion of said annular-shaped oxidized isolation region into contact with an adjacent region of said epit-axial silicon layer, said adjacent region comprising a first transistor including a collector region of opposite conductivity type contacting said first region, a base region of one conductivity type formed in said collector region and extending to the annular-shaped oxidized isolation region surround-ing said adjacent region, and an emitter region of opposite conductivity type formed in said base region.
16. Structure as in claim 15 wherein said emitter region abuts a portion of the annular-shaped oxidized isolation region surrounding said adjacent epitaxial region of silicon.
17. A silicon structure comprising: a silicon substrate; a silicon epitaxial layer upon one surface of said substrate, said epitaxial layer having a substantially flat top surface; a PN isolation junction extending laterally along the structure forming an isolation barrier between regions of said substrate and layer; said epitaxial layer comprising epitaxial silicon pockets laterally spaced from each other and annular-shaped regions formed at least in part of oxidized portions of said epitaxial layer surround-ing each pocket, said annular-shaped regions extending through said epitaxial layer to said PN isolation junction and together therewith electrically isolating said epitaxial silicon pockets from each other, and the top sur-face of said annular-shaped regions being substantially coplanar with the top surface of said epitaxial layer; and a transistor formed in one of said epitaxial silicon pockets, said transistor including a collector region of a first conductivity type, a base region of the opposite conductivity type extending to the annular-shaped oxidized isolation region surrounding said epitaxial silicon pocket, and an emitter region of said first conduc-tivity type formed in said base region, said emitter region abutting a portion of the annular-shaped oxidized isolation region surrounding said epitaxial silicon pocket.
18. Structure as in claim 15 wherein said second region of opposite conductivity type comprises low resistivity epitaxial silicon material which contacts directly said low resistivity first region.
19. Structure as in claim 15 wherein said low resistivity portion of s aid second region comprises a low resistivity portion of said epitaxial silicon layer which contacts directly said first region but occupies only a portion of the circumferential area of said second region.
20. Structure as in claim 15 including a resistor formed in at least one of said epitaxial silicon pockets.
21. Structure as in claim 20 wherein said resistor comprises a portion of said epitaxial silicon layer.
22. Structure as in claim 20 wherein said resistor comprises a portion of said epitaxial silicon layer which has the same conductivity type as said base region.
23. Structure as in claim 22 including a low resistivity region of opposite conductivity type formed beneath said resistor and in contact with the oxidized portions of semiconductor material surrounding said at least one epitaxial silicon pocket.
24. Structure as in claim 15 including a guard ring of a highly doped portion of said epitaxial silicon material directly abutting a surface of a selected one of said annular-shaped regions and surrounding the epitaxial silicon pocket surrounded by said selected one of said annular-shaped regions.
25. Structure as in claim 24 wherein said guard ring is of said one conductivity type.
26. Structure as in claim 15 including a Schottky-barrier device formed in a selected one of said epitaxial silicon pockets.
27. Structure as in claim 15 wherein said low resistivity first region extends beneath only a portion of said adjacent region, said silicon sub-strate serves as a collector region of a second transistor, said collector region of opposite conductivity type serves as the base region of said second transistor and said base region of said one conductivity type serves as the emitter region of said second transistor, said structure comprising a sub-strate controlled switching transistor.
28. The method of forming a plurality of electrically isolated pockets of semiconductor material in a semiconductor structure comprising a silicon substrate with an epitaxial silicon layer thereon, which comprises the steps of: forming a low resitivity region of one conductivity type in said sub-strate directly beneath a surface of the substrate; growing a doped epitaxial silicon layer of opposite conductivity type on the surface of the substrate beneath which the low resitivity region is formed, said doped epitaxial silicon layer having a conductivity type relative to the conductivity type of at least a portion of the top surface of said substrate such that a laterally-extending PN junction is formed in at least part of said semi-conductor structure; forming a layer of insulation on said epitaxial silicon layer, said insulation having the properties that it is substantially un-affected by at least: one etchant used to remove epitaxial silicon and sub-stantially masks the diffusion of oxygen; removing portions of said insulation overlying regions of said epitaxial silicon layer to be converted into oxidized silicon; forming depressions to a specified depth in said epitaxial silicon exposed by removal of said insulation by removing part of said epitaxial silicon exposed by removal of said insulation; and subdivid-ing said epitaxial silicon layer into a plurality of electrically isolated pockets of semiconductor material by oxidizing the silicon exposed by said depressions to form oxidized silicon extending through said epitaxial silicon layer to said PN junction thereby both to surround each pocket by an annular-shaped region of oxidized silicon, the top surface of said oxidized silicon being substantially coplanar with the top surface of said epitaxial silicon layer, and to electrically isolate each pocket by an annular-shaped region of oxidized silicon and a portion of said laterally-extending PN junction, at least part of one electrically isolated pocket of semiconductor material lying above the low resistivity region; removing said layer of insulation after the epitaxial silicon exposed by said depressions is oxidized through to said PN junction; and diffusing an impruity of said one conductivity type through a selected region of epitaxial silicon of said one conductivity type surrounded by an annular-shaped region of oxidized silicon to said low resistivity region of said one conductivity type in said silicon substrate thereby to form an electrical contact to said region in said silicon substrate.
29. The method of claim 28 including the additional steps of: masking said epitaxial silicon layer to leave exposed another region of epitaxial silicon above said low resistivity region in said silicon substrate, said another region of epitaxial silicon being surrounded by another annular-shaped region of oxidized silicon; and diffusing an impurity of one conductivity type into said another region to a selected depth less than the thickness of said epitaxial layer.
30. The method of claim 29 including the additional steps of: masking a portion of said another region into which said impurity of said opposite conductivity type has been diffused; and diffusing an impurity of said one conductivity type into the unmasked portion of said another region of epitaxial silicon to form a second region of said one conductivity type.
31. The method of claim 30 wherein said step of diffusing an impurity of said one conductivity type into said another region of epitaxial silicon comprises the step of diffusing an impurity of said one conductivity type into said another region of epitaxial silicon so as to form a second region of said one conductivity type abutting said another annular-shaped region of oxidized silicon.
32. The method of claim 30 wherein said doped epitaxial silicon layer is of said one conductivity type.
33. Structure comprising a semiconductor substrate and a plurality of pockets of epitaxial semiconductor material upon one surface of said sub-strate, said plurality of pockets of epitaxial material having substantially flat top surfaces formed substantially in one plane; and a PN isolation junction extending laterally along the structure forming an isolation barrier between regions of said substrate and pockets; characterized in that: said pockets of epitaxial semiconductor material are laterally spaced from each other by annular-shaped regions formed at least partly of oxidized portions of the epitaxial material from which said pockets are formed, said annular-shaped regions extending through said epitaxial semiconductor material to said PN isolation junction, and together therewith electrically isolating said pockets of epitaxial semiconductor material from each other, and the top surfaces of said annular-shaped regions are substantially coplanar with the top surfaces of said pockets of epitaxial semiconductor material; where-in each pocket of epitaxial semiconductor material contains selected regions of different conductivity type and wherein said structure includes regions of low resistivity formed in the underlying substrate to interconnect regions separated by oxidized isolation regions.
34. Structure comprising a semiconductor substrate and a plurality of pockets of epitaxial semiconductor material upon one surface of said sub-strate, said plurality of pockets of epitaxial material having substantially flat top surfaces formed substantially in one plane; and a PN isolation junction extending laterally along the structure forming an isolation barrier between regions of said substrate and pockets; characterized in that: said pockets of epitaxial semiconductor material are laterally spaced from each other by annular-shaped regions formed at least partly of oxidized portions of the epitaxial material from which said pockets are formed, said annular-shaped regions extending through said epitaxial semiconductor material to said PN isolation junction, and together therewith electrically isolating said pockets of epitaxial semiconductor material from each other, and the top surfaces of said annular-shaped regions are substantially coplanar with the top surfaces of said pockets of epitaxial semiconductor material; where-in said substrate is of one type conductivity and said epitaxial layer is of the opposite type conductivity, and said structure including a low resistivity first region of opposite conductivity type formed in said sub-strate adjacent to said epitaxial layer of semiconductor material, and a low resistivity second region of opposite conductivity type, said second region extending from the surface of said epitaxial layer above said low resistivity first region, said second region being surrounded by an annular-shaped oxidized isolation region extending through said epitaxial layer to said first region in said substrate.
35. Structure comprising a semiconductor substrate and a plurality of pockets of epitaxial semiconductor material upon one surface of said sub-strate, said plurality of pockets of epitaxial material having substantially flat top surfaces formed substantially in one plane; and a PN isolation junction extending laterally along the structure forming an isolation barrier between regions of said substrate and pockets; characterized in that: said pockets of epitaxial semiconductor material are laterally spaced from each other by annular-shaped regions formed at least partly of oxidized portions of the epitaxial material from which said pockets are formed, said annular-shaped regions extending through said epitaxial semiconductor material to said PN isolation junction, and together therewith electrically isolating said pockets of epitaxial semiconductor material from each other, and the top surfaces of said annular-shaped regions are substantially coplanar with the top surfaces of said pockets of epitaxial semiconductor material;
wherein said epitaxial layer has a thickness of 1.25 microns.
36. A dielectrically isolated semiconductor device comprising: a semiconductor body; a buried semiconducting region in said body; emitter and base regions located in said body on top of said buried region; and a dielectrically isolating region surrounding said emitter and base regions and extending to a depth wherein it intersects with said buried region.
37. A dielectrically isolated semiconductor device comprising: a semiconductor substrate; an epitaxial layer on said substrate; a buried semiconducting region partially in said substrate and said epitaxial layer;
emitter and base regions located in said epitaxial layer above said buried region; and a dielectrically isolating region surrounding said emitter and base regions and extending to a depth wherein it intersects with said buried region.
38. The semiconductor device of claim 37 wherein the said dielectric-ally isolating region extends partially through said epitaxial layer.
39. The semiconductor device of claim 37 wherein the said dielectrical-ly isolating region extends completely through said epitaxial layer.
40. The semiconductor device of claim 37 wherein the buried region is the collector element of the device and a semiconductor reach through region to said collector element is isolated from said base and emitter regions by a portion of said dielectrically isolating region.
41. The semiconductor device of claim 40 wherein the surface available for electrical contact to said emitter, base and collector elements is substantially planar.
42. The semiconductor device of claim 36 wherein the base contact is located on the surface of the base region immediately adjacent to the di-electric isolation.
43. A method for fabricating a dielectrically isolated semiconductor device comprising: forming a region of a first conductivity type within a semiconductor body of a second conductivity type; growing an epitaxial layer onto the surface of said semiconductor body containing said region in a manner which results in a movement of impurities of said first conductivity type into the epitaxial layer during its growth which results in an effective extension of said region into said epitaxial layer to form a buried region located partially within said body and said epitaxial layer; forming a protective layer on the surface of said epitaxial layer in areas where it is subsequently intended to have semiconductor devices located; thermally oxidizing the unprotected areas of said surface of said epitaxial layer to a depth which is at least as deep as said buried region wherein a semiconductor reach through region to connect to said buried region remains after said thermal oxidation and said reach through region is dielectrically isolated from other remaining semiconductor regions extending to said surface; removing said protective layer; and forming a semiconductor device in said epitaxial layer.
44. A silicon structure comprising: a semiconductor silicon substrate of one conductivity type; a semiconductor silicon epitaxial layer upon one surface of said substrate, said epitaxial layer being of said one conductivity type and having a substantially flat top surface; and a PN isolation junction extending laterally along the structure forming an isolation barrier between regions of said substrate and layer; said epitaxial layer comprising epitaxial silicon pockets laterally spaced from each other and annular-shaped regions formed of oxidized portions of silicon material surrounding each pocket, said annular-shaped regions extending through said epitaxial layer to said PN isolation junction and together therewith electrically isolating said epitaxial silicon pockets from each other, and the top surface of said annular-shaped regions being substantially coplanar with the top surface of said epitaxial layer.
45. Structure as in claim 44 wherein said substrate is of P-type conductivity.
46. Structure as in claim 44 wherein said substrate is of N-type conductivity.
47. Structure as in claim 45 wherein said substrate contains a plurality of low resistivity regions of P-type conductivity formed in the surface of said substrate directly beneath said epitaxial layer.
48. Structure as in claim 46 wherein said substrate contains a plurality of low resistivity regions of P-type conductivity formed in the surface of said substrate directly beneath said epitaxial layer.
49. Structure as in claim 44 wherein each pocket of epitaxial semi-conductor material contains selected regions of differing conductivity type.
50. Structure as in claim 49 wherein said regions of differing conductivity type comprise active and passive semiconductor devices.
51. Structure as in claim 49 including regions of low resistivity formed in the underlying substrate to interconnect regions separated by oxidized isolation regions.
52. Structure as in claim 44 wherein said epitaxial layer has a thickness of less than 5 microns.
53. A semiconductor device, in particular a monolithic integrated circuit, having a monocrystalline semiconductor substrate body and a semi-conductor layer provided on one side thereof and divided into islands which are separated from each other by an isolation zone, at least one circuit element being formed in at least one island, characterized in said island being isolated from the substrate body by at least one laterally extending p-n junction at least the part of the isolation zone adjoining the surface of the semiconductor layer being constituted by a layer of an insulating material insert in the semiconductor layer and a semiconductor zone associated with the said island being connected in an electrically conduc-tive manner to a zone associated with an adjacent island by means of a connection zone passing underneath the inset insulation layer, the connec-tion zone being isolated from the substrate body and conductively connecting the zones associated with the two islands.
54. A semiconductor device as claimed in claim 53 characterized in that the inset insulation layer is a genetic layer which has been obtained by conversion of the semiconductor material into insulating material.
55. A semiconductor device as claimed in claim 54, characterized in that the semiconductor material is silicon and the inset insulation layer is silicon oxide.
56. A semiconductor device as claimed in claim 53, characterized in that the conductive connection between the two zones which are of the same conductivity type is constituted by a buried layer of the said same conduc-tivity type present below the inset insulation layer.
57. A semiconductor device as claimed in claim 56, characterized in that at least parts of the two connected zones and the conductive connection therebetween together are constituted by a common buried layer.
58. A semiconductor device as claimed in claim 56 or 57, characterized in that the buried layer is of a conductivity type opposite to that of the semiconductor substrate body.
59. A semiconductor device as claimed in claim 53, characterized in that the semiconductor layer provided on the substrate body is an epitaxial layer of the same conductivity type as the substrate body, and along the lower side of each island a buried layer is used which separates the island from the substrate, said buried layer being of a conductivity type opposite to that of the substrate body and the epitaxial layer, such a buried layer being locally connected to the buried layer of an adjacent island by the conductive connection.
60. A semiconductor device as claimed in claim 59, characterized in that the buried layer adjoins the inset insulation layer.
61. A semiconductor device as claimed in claim 59 or 60, characterized in that in each adjacent island the buried layer is connected to a surface zone which extends from the semiconductor surface to the buried layer and surrounds the island on all sides, the connection zone underneath the inset insulation layer interconnecting the thus formed composite zones surrounding each island in an electrically conductive manner.
CA127,816A 1971-02-02 1971-11-16 Method of fabricating itegrated circuits with oxidized isolation and the resulting structure Expired CA1106078A (en)

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Families Citing this family (144)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6979877B1 (en) 1965-09-28 2005-12-27 Li Chou H Solid-state device
US5696402A (en) * 1965-09-28 1997-12-09 Li; Chou H. Integrated circuit device
US4916513A (en) * 1965-09-28 1990-04-10 Li Chou H Dielectrically isolated integrated circuit structure
US7038290B1 (en) 1965-09-28 2006-05-02 Li Chou H Integrated circuit device
US6849918B1 (en) * 1965-09-28 2005-02-01 Chou H. Li Miniaturized dielectrically isolated solid state device
US5082793A (en) * 1965-09-28 1992-01-21 Li Chou H Method for making solid state device utilizing ion implantation techniques
US4946800A (en) * 1965-09-28 1990-08-07 Li Chou H Method for making solid-state device utilizing isolation grooves
USRE28653E (en) * 1968-04-23 1975-12-16 Method of fabricating semiconductor devices
NL170902C (en) * 1970-07-10 1983-01-03 Philips Nv SEMICONDUCTOR DEVICE, IN PARTICULAR MONOLITHICALLY INTEGRATED SEMICONDUCTOR CIRCUIT.
US3648125A (en) * 1971-02-02 1972-03-07 Fairchild Camera Instr Co Method of fabricating integrated circuits with oxidized isolation and the resulting structure
NL170901C (en) * 1971-04-03 1983-01-03 Philips Nv METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE
US3909318A (en) * 1971-04-14 1975-09-30 Philips Corp Method of forming complementary devices utilizing outdiffusion and selective oxidation
US6076652A (en) 1971-04-16 2000-06-20 Texas Instruments Incorporated Assembly line system and apparatus controlling transfer of a workpiece
US3751722A (en) * 1971-04-30 1973-08-07 Standard Microsyst Smc Mos integrated circuit with substrate containing selectively formed resistivity regions
US3947299A (en) * 1971-05-22 1976-03-30 U.S. Philips Corporation Method of manufacturing semiconductor devices
NL7107040A (en) * 1971-05-22 1972-11-24
NL166156C (en) * 1971-05-22 1981-06-15 Philips Nv SEMICONDUCTOR DEVICE CONTAINING AT LEAST ONE on a semiconductor substrate BODY MADE SEMICONDUCTOR LAYER WITH AT LEAST ONE ISOLATION ZONE WHICH ONE IN THE SEMICONDUCTOR LAYER COUNTERSUNk INSULATION FROM SHAPED INSULATING MATERIAL BY LOCAL THERMAL OXIDATION OF HALF OF THE SEMICONDUCTOR LAYER GUIDE MATERIALS CONTAIN AND METHOD FOR MANUFACTURING SAME.
US4965652A (en) * 1971-06-07 1990-10-23 International Business Machines Corporation Dielectric isolation for high density semiconductor devices
US4016594A (en) * 1971-06-08 1977-04-05 U.S. Philips Corporation Semiconductor device and method of manufacturing the device
US3921283A (en) * 1971-06-08 1975-11-25 Philips Corp Semiconductor device and method of manufacturing the device
US4396933A (en) * 1971-06-18 1983-08-02 International Business Machines Corporation Dielectrically isolated semiconductor devices
US3928091A (en) * 1971-09-27 1975-12-23 Hitachi Ltd Method for manufacturing a semiconductor device utilizing selective oxidation
US3828232A (en) * 1972-02-28 1974-08-06 Tokyo Shibaura Electric Co Semiconductor target
US3818289A (en) * 1972-04-10 1974-06-18 Raytheon Co Semiconductor integrated circuit structures
US3999213A (en) * 1972-04-14 1976-12-21 U.S. Philips Corporation Semiconductor device and method of manufacturing the device
IT979178B (en) * 1972-05-11 1974-09-30 Ibm RESISTOR FOR INTEGRATED CIRCUIT DEVICES
US3861968A (en) * 1972-06-19 1975-01-21 Ibm Method of fabricating integrated circuit device structure with complementary elements utilizing selective thermal oxidation and selective epitaxial deposition
US3961355A (en) * 1972-06-30 1976-06-01 International Business Machines Corporation Semiconductor device having electrically insulating barriers for surface leakage sensitive devices and method of forming
US4063271A (en) * 1972-07-26 1977-12-13 Texas Instruments Incorporated FET and bipolar device and circuit process with maximum junction control
SE361232B (en) * 1972-11-09 1973-10-22 Ericsson Telefon Ab L M
US3841918A (en) * 1972-12-01 1974-10-15 Bell Telephone Labor Inc Method of integrated circuit fabrication
DE2262297C2 (en) * 1972-12-20 1985-11-28 Ibm Deutschland Gmbh, 7000 Stuttgart Monolithically integrable, logically linkable semiconductor circuit arrangement with I → 2 → L structure
NL161301C (en) * 1972-12-29 1980-01-15 Philips Nv SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURE THEREOF.
US3959812A (en) * 1973-02-26 1976-05-25 Hitachi, Ltd. High-voltage semiconductor integrated circuit
US3919005A (en) * 1973-05-07 1975-11-11 Fairchild Camera Instr Co Method for fabricating double-diffused, lateral transistor
US3873989A (en) * 1973-05-07 1975-03-25 Fairchild Camera Instr Co Double-diffused, lateral transistor structure
US3992232A (en) * 1973-08-06 1976-11-16 Hitachi, Ltd. Method of manufacturing semiconductor device having oxide isolation structure and guard ring
GB1457139A (en) * 1973-09-27 1976-12-01 Hitachi Ltd Method of manufacturing semiconductor device
US4136435A (en) * 1973-10-10 1979-01-30 Li Chou H Method for making solid-state device
JPS5214594B2 (en) * 1973-10-17 1977-04-22
US3886000A (en) * 1973-11-05 1975-05-27 Ibm Method for controlling dielectric isolation of a semiconductor device
US3962779A (en) * 1974-01-14 1976-06-15 Bell Telephone Laboratories, Incorporated Method for fabricating oxide isolated integrated circuits
NL180466C (en) * 1974-03-15 1987-02-16 Philips Nv METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE WITH A SEMICONDUCTOR BODY PROVIDED WITH A PATTERN OF INSULATING MATERIAL RECOGNIZED IN THE SEMICONDUCTOR BODY.
US3920481A (en) * 1974-06-03 1975-11-18 Fairchild Camera Instr Co Process for fabricating insulated gate field effect transistor structure
US3919060A (en) * 1974-06-14 1975-11-11 Ibm Method of fabricating semiconductor device embodying dielectric isolation
US3945857A (en) * 1974-07-01 1976-03-23 Fairchild Camera And Instrument Corporation Method for fabricating double-diffused, lateral transistors
US3962717A (en) * 1974-10-29 1976-06-08 Fairchild Camera And Instrument Corporation Oxide isolated integrated injection logic with selective guard ring
US3993513A (en) * 1974-10-29 1976-11-23 Fairchild Camera And Instrument Corporation Combined method for fabricating oxide-isolated vertical bipolar transistors and complementary oxide-isolated lateral bipolar transistors and the resulting structures
US3982266A (en) * 1974-12-09 1976-09-21 Texas Instruments Incorporated Integrated injection logic having high inverse current gain
US3988619A (en) * 1974-12-27 1976-10-26 International Business Machines Corporation Random access solid-state image sensor with non-destructive read-out
DE2510593C3 (en) * 1975-03-11 1982-03-18 Siemens AG, 1000 Berlin und 8000 München Integrated semiconductor circuit arrangement
US3954523A (en) * 1975-04-14 1976-05-04 International Business Machines Corporation Process for fabricating devices having dielectric isolation utilizing anodic treatment and selective oxidation
US3972754A (en) * 1975-05-30 1976-08-03 Ibm Corporation Method for forming dielectric isolation in integrated circuits
US4056415A (en) * 1975-08-04 1977-11-01 International Telephone And Telegraph Corporation Method for providing electrical isolating material in selected regions of a semiconductive material
US4025364A (en) * 1975-08-11 1977-05-24 Fairchild Camera And Instrument Corporation Process for simultaneously fabricating epitaxial resistors, base resistors, and vertical transistor bases
JPS5922381B2 (en) * 1975-12-03 1984-05-26 株式会社東芝 Handout Taisoshino Seizouhouhou
JPS5275989A (en) 1975-12-22 1977-06-25 Hitachi Ltd Production of semiconductor device
US4079408A (en) * 1975-12-31 1978-03-14 International Business Machines Corporation Semiconductor structure with annular collector/subcollector region
DE2605641C3 (en) * 1976-02-12 1979-12-20 Siemens Ag, 1000 Berlin Und 8000 Muenchen High frequency transistor and process for its manufacture
US4137109A (en) * 1976-04-12 1979-01-30 Texas Instruments Incorporated Selective diffusion and etching method for isolation of integrated logic circuit
US4149177A (en) * 1976-09-03 1979-04-10 Fairchild Camera And Instrument Corporation Method of fabricating conductive buried regions in integrated circuits and the resulting structures
US4118728A (en) * 1976-09-03 1978-10-03 Fairchild Camera And Instrument Corporation Integrated circuit structures utilizing conductive buried regions
US4228450A (en) * 1977-10-25 1980-10-14 International Business Machines Corporation Buried high sheet resistance structure for high density integrated circuits with reach through contacts
FR2413782A1 (en) * 1977-12-30 1979-07-27 Radiotechnique Compelec INTEGRATED CIRCUIT ELEMENT FOR BIPOLAR MEMORIES WITH LATERAL ISOLATION BY OXIDE
US4140558A (en) * 1978-03-02 1979-02-20 Bell Telephone Laboratories, Incorporated Isolation of integrated circuits utilizing selective etching and diffusion
US4172291A (en) * 1978-08-07 1979-10-23 Fairchild Camera And Instrument Corp. Preset circuit for information storage devices
US4269636A (en) * 1978-12-29 1981-05-26 Harris Corporation Method of fabricating self-aligned bipolar transistor process and device utilizing etching and self-aligned masking
US4466172A (en) * 1979-01-08 1984-08-21 American Microsystems, Inc. Method for fabricating MOS device with self-aligned contacts
US4670769A (en) * 1979-04-09 1987-06-02 Harris Corporation Fabrication of isolated regions for use in self-aligning device process utilizing selective oxidation
US4276616A (en) * 1979-04-23 1981-06-30 Fairchild Camera & Instrument Corp. Merged bipolar/field-effect bistable memory cell
US4251300A (en) * 1979-05-14 1981-02-17 Fairchild Camera And Instrument Corporation Method for forming shaped buried layers in semiconductor devices utilizing etching, epitaxial deposition and oxide formation
US4677456A (en) * 1979-05-25 1987-06-30 Raytheon Company Semiconductor structure and manufacturing method
US4289550A (en) * 1979-05-25 1981-09-15 Raytheon Company Method of forming closely spaced device regions utilizing selective etching and diffusion
US4333227A (en) * 1979-11-29 1982-06-08 International Business Machines Corporation Process for fabricating a self-aligned micrometer bipolar transistor device
US4303933A (en) * 1979-11-29 1981-12-01 International Business Machines Corporation Self-aligned micrometer bipolar transistor device and process
US4252582A (en) * 1980-01-25 1981-02-24 International Business Machines Corporation Self aligned method for making bipolar transistor having minimum base to emitter contact spacing
JPS56127971A (en) * 1980-03-07 1981-10-07 Victor Co Of Japan Ltd Automatic tape loading device
US4318751A (en) * 1980-03-13 1982-03-09 International Business Machines Corporation Self-aligned process for providing an improved high performance bipolar transistor
US4274909A (en) * 1980-03-17 1981-06-23 International Business Machines Corporation Method for forming ultra fine deep dielectric isolation
US4339767A (en) * 1980-05-05 1982-07-13 International Business Machines Corporation High performance PNP and NPN transistor structure
US4412283A (en) * 1980-05-30 1983-10-25 Fairchild Camera & Instrument Corp. High performance microprocessor system
US4758528A (en) * 1980-07-08 1988-07-19 International Business Machines Corporation Self-aligned metal process for integrated circuit metallization
US4359816A (en) * 1980-07-08 1982-11-23 International Business Machines Corporation Self-aligned metal process for field effect transistor integrated circuits
US4545113A (en) * 1980-10-23 1985-10-08 Fairchild Camera & Instrument Corporation Process for fabricating a lateral transistor having self-aligned base and base contact
JPS6212508Y2 (en) * 1980-12-08 1987-04-01
US4398338A (en) * 1980-12-24 1983-08-16 Fairchild Camera & Instrument Corp. Fabrication of high speed, nonvolatile, electrically erasable memory cell and system utilizing selective masking, deposition and etching techniques
US4373252A (en) * 1981-02-17 1983-02-15 Fairchild Camera & Instrument Method for manufacturing a semiconductor structure having reduced lateral spacing between buried regions
US4374011A (en) * 1981-05-08 1983-02-15 Fairchild Camera & Instrument Corp. Process for fabricating non-encroaching planar insulating regions in integrated circuit structures
US4418468A (en) * 1981-05-08 1983-12-06 Fairchild Camera & Instrument Corporation Process for fabricating a logic structure utilizing polycrystalline silicon Schottky diodes
US4506435A (en) * 1981-07-27 1985-03-26 International Business Machines Corporation Method for forming recessed isolated regions
US4454647A (en) * 1981-08-27 1984-06-19 International Business Machines Corporation Isolation for high density integrated circuits
US4454646A (en) * 1981-08-27 1984-06-19 International Business Machines Corporation Isolation for high density integrated circuits
US4472873A (en) 1981-10-22 1984-09-25 Fairchild Camera And Instrument Corporation Method for forming submicron bipolar transistors without epitaxial growth and the resulting structure
US4617071A (en) * 1981-10-27 1986-10-14 Fairchild Semiconductor Corporation Method of fabricating electrically connected regions of opposite conductivity type in a semiconductor structure
US4419809A (en) * 1981-12-30 1983-12-13 International Business Machines Corporation Fabrication process of sub-micrometer channel length MOSFETs
US4419810A (en) * 1981-12-30 1983-12-13 International Business Machines Corporation Self-aligned field effect transistor process
US4961102A (en) * 1982-01-04 1990-10-02 Shideler Jay A Junction programmable vertical transistor with high performance transistor
US4624046A (en) * 1982-01-04 1986-11-25 Fairchild Camera & Instrument Corp. Oxide isolation process for standard RAM/PROM and lateral PNP cell RAM
CA1188418A (en) * 1982-01-04 1985-06-04 Jay A. Shideler Oxide isolation process for standard ram/prom and lateral pnp cell ram
US4443932A (en) * 1982-01-18 1984-04-24 Motorla, Inc. Self-aligned oxide isolated process and device
US4694566A (en) * 1982-04-12 1987-09-22 Signetics Corporation Method for manufacturing programmable read-only memory containing cells formed with opposing diodes
US4712125A (en) * 1982-08-06 1987-12-08 International Business Machines Corporation Structure for contacting a narrow width PN junction region
JPS5946065A (en) * 1982-09-09 1984-03-15 Toshiba Corp Manufacture of semiconductor device
US4507848A (en) * 1982-11-22 1985-04-02 Fairchild Camera & Instrument Corporation Control of substrate injection in lateral bipolar transistors
US4508757A (en) * 1982-12-20 1985-04-02 International Business Machines Corporation Method of manufacturing a minimum bird's beak recessed oxide isolation structure
JPS6042866A (en) * 1983-08-19 1985-03-07 Toshiba Corp Semiconductor device and manufacture thereof
US4551906A (en) * 1983-12-12 1985-11-12 International Business Machines Corporation Method for making self-aligned lateral bipolar transistors
US4860082A (en) * 1984-07-08 1989-08-22 Nec Corporation Bipolar transistor
JPS6142955A (en) * 1984-08-07 1986-03-01 Nec Corp Manufacture of semiconductor device
EP0190070B1 (en) 1985-01-22 1992-08-26 Fairchild Semiconductor Corporation Semiconductor structure
US4686000A (en) * 1985-04-02 1987-08-11 Heath Barbara A Self-aligned contact process
US4619033A (en) * 1985-05-10 1986-10-28 Rca Corporation Fabricating of a CMOS FET with reduced latchup susceptibility
US4648173A (en) * 1985-05-28 1987-03-10 International Business Machines Corporation Fabrication of stud-defined integrated circuit structure
US4721682A (en) * 1985-09-25 1988-01-26 Monolithic Memories, Inc. Isolation and substrate connection for a bipolar integrated circuit
US4849344A (en) * 1986-12-11 1989-07-18 Fairchild Semiconductor Corporation Enhanced density modified isoplanar process
DE3751773T2 (en) * 1986-12-11 1996-11-28 Fairchild Semiconductor MODIFIED ISOPLANAR METHOD WITH INCREASED DENSITY
US4775644A (en) * 1987-06-03 1988-10-04 Lsi Logic Corporation Zero bird-beak oxide isolation scheme for integrated circuits
US5014107A (en) * 1987-07-29 1991-05-07 Fairchild Semiconductor Corporation Process for fabricating complementary contactless vertical bipolar transistors
GB8726367D0 (en) * 1987-11-11 1987-12-16 Lsi Logic Ltd Cmos devices
US4847672A (en) 1988-02-29 1989-07-11 Fairchild Semiconductor Corporation Integrated circuit die with resistive substrate isolation of multiple circuits
US5094972A (en) * 1990-06-14 1992-03-10 National Semiconductor Corp. Means of planarizing integrated circuits with fully recessed isolation dielectric
US5289024A (en) * 1990-08-07 1994-02-22 National Semiconductor Corporation Bipolar transistor with diffusion compensation
US5059555A (en) * 1990-08-20 1991-10-22 National Semiconductor Corporation Method to fabricate vertical fuse devices and Schottky diodes using thin sacrificial layer
US5212102A (en) * 1990-08-22 1993-05-18 National Semiconductor Corporation Method of making polysilicon Schottky clamped transistor and vertical fuse devices
US5144404A (en) * 1990-08-22 1992-09-01 National Semiconductor Corporation Polysilicon Schottky clamped transistor and vertical fuse devices
JP3111500B2 (en) * 1991-05-09 2000-11-20 富士電機株式会社 Manufacturing method of dielectric isolation wafer
US5422289A (en) * 1992-04-27 1995-06-06 National Semiconductor Corporation Method of manufacturing a fully planarized MOSFET and resulting structure
US20040144999A1 (en) * 1995-06-07 2004-07-29 Li Chou H. Integrated circuit device
US6376293B1 (en) * 1999-03-30 2002-04-23 Texas Instruments Incorporated Shallow drain extenders for CMOS transistors using replacement gate design
KR100350648B1 (en) * 2000-01-17 2002-08-28 페어차일드코리아반도체 주식회사 Mos transistor and method for manufacturing the same
US6599781B1 (en) * 2000-09-27 2003-07-29 Chou H. Li Solid state device
US6613592B1 (en) 2002-04-25 2003-09-02 Taiwan Semiconductor Manufacturing Company IMD oxide crack monitor pattern and design rule
US7119401B2 (en) * 2004-01-07 2006-10-10 International Business Machines Corporation Tunable semiconductor diodes
US7095092B2 (en) * 2004-04-30 2006-08-22 Freescale Semiconductor, Inc. Semiconductor device and method of forming the same
JP5096708B2 (en) * 2006-07-28 2012-12-12 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
US7691734B2 (en) * 2007-03-01 2010-04-06 International Business Machines Corporation Deep trench based far subcollector reachthrough
JP4759590B2 (en) * 2008-05-09 2011-08-31 キヤノン株式会社 Photoelectric conversion device and imaging system using the same
TWI405250B (en) * 2010-04-13 2013-08-11 Richtek Technology Corp Method for controlling impurity density distribution in semiconductor device and semiconductor device made thereby
CN102222609B (en) * 2010-04-16 2013-07-31 立锜科技股份有限公司 Impurity concentration distribution control method of semiconductor component and related semiconductor component
US8525258B2 (en) * 2010-06-17 2013-09-03 Richtek Technology Corporation, R.O.C. Method for controlling impurity density distribution in semiconductor device and semiconductor device made thereby
EP3528288B1 (en) 2013-06-20 2020-08-26 Stratio, Inc. Gate-controlled charge modulated device for cmos image sensors
KR101885942B1 (en) * 2014-11-19 2018-08-07 매그나칩 반도체 유한회사 Semiconductor and Method of fabricating the same
US11088031B2 (en) 2014-11-19 2021-08-10 Key Foundry Co., Ltd. Semiconductor and method of fabricating the same
US10872950B2 (en) 2016-10-04 2020-12-22 Nanohenry Inc. Method for growing very thick thermal local silicon oxide structures and silicon oxide embedded spiral inductors

Family Cites Families (57)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA861139A (en) * 1971-01-12 Kooi Else Method of manufacturing a semiconductor device and device manufactured by said method
US28653A (en) * 1860-06-12 Tewonim-g-augek
NL121810C (en) * 1955-11-04
US2981877A (en) * 1959-07-30 1961-04-25 Fairchild Semiconductor Semiconductor device-and-lead structure
US3117260A (en) * 1959-09-11 1964-01-07 Fairchild Camera Instr Co Semiconductor circuit complexes
US3150299A (en) * 1959-09-11 1964-09-22 Fairchild Camera Instr Co Semiconductor circuit complex having isolation means
US3189798A (en) * 1960-11-29 1965-06-15 Westinghouse Electric Corp Monolithic semiconductor device and method of preparing same
US3136897A (en) * 1961-09-25 1964-06-09 Westinghouse Electric Corp Monolithic semiconductor structure comprising at least one junction transistor and associated diodes to form logic element
US3210620A (en) * 1961-10-04 1965-10-05 Westinghouse Electric Corp Semiconductor device providing diode functions
NL286507A (en) * 1961-12-11
US3241010A (en) * 1962-03-23 1966-03-15 Texas Instruments Inc Semiconductor junction passivation
US3210677A (en) * 1962-05-28 1965-10-05 Westinghouse Electric Corp Unipolar-bipolar semiconductor amplifier
US3296040A (en) * 1962-08-17 1967-01-03 Fairchild Camera Instr Co Epitaxially growing layers of semiconductor through openings in oxide mask
NL297601A (en) * 1962-09-07 Rca Corp
GB1047388A (en) * 1962-10-05
US3290753A (en) * 1963-08-19 1966-12-13 Bell Telephone Labor Inc Method of making semiconductor integrated circuit elements
US3341755A (en) * 1964-03-20 1967-09-12 Westinghouse Electric Corp Switching transistor structure and method of making the same
US3598664A (en) * 1964-12-29 1971-08-10 Texas Instruments Inc High frequency transistor and process for fabricating same
US3391023A (en) * 1965-03-29 1968-07-02 Fairchild Camera Instr Co Dielecteric isolation process
US3386865A (en) * 1965-05-10 1968-06-04 Ibm Process of making planar semiconductor devices isolated by encapsulating oxide filled channels
US3442011A (en) * 1965-06-30 1969-05-06 Texas Instruments Inc Method for isolating individual devices in an integrated circuit monolithic bar
US3615929A (en) * 1965-07-08 1971-10-26 Texas Instruments Inc Method of forming epitaxial region of predetermined thickness and article of manufacture
US3370995A (en) * 1965-08-02 1968-02-27 Texas Instruments Inc Method for fabricating electrically isolated semiconductor devices in integrated circuits
US3511702A (en) * 1965-08-20 1970-05-12 Motorola Inc Epitaxial growth process from an atmosphere composed of a hydrogen halide,semiconductor halide and hydrogen
US3404450A (en) * 1966-01-26 1968-10-08 Westinghouse Electric Corp Method of fabricating an integrated circuit structure including unipolar transistor and bipolar transistor portions
US3404451A (en) * 1966-06-29 1968-10-08 Fairchild Camera Instr Co Method of manufacturing semiconductor devices
US3489961A (en) * 1966-09-29 1970-01-13 Fairchild Camera Instr Co Mesa etching for isolation of functional elements in integrated circuits
GB1208577A (en) * 1966-10-05 1970-10-14 Philips Electronic Associated Methods of manufacturing semiconductor devices
NL153374B (en) * 1966-10-05 1977-05-16 Philips Nv PROCESS FOR THE MANUFACTURE OF A SEMICONDUCTOR DEVICE PROVIDED WITH AN OXIDE LAYER AND SEMI-CONDUCTOR DEVICE MANUFACTURED ACCORDING TO THE PROCEDURE.
US3474308A (en) * 1966-12-13 1969-10-21 Texas Instruments Inc Monolithic circuits having matched complementary transistors,sub-epitaxial and surface resistors,and n and p channel field effect transistors
US3534234A (en) * 1966-12-15 1970-10-13 Texas Instruments Inc Modified planar process for making semiconductor devices having ultrafine mesa type geometry
FR1527898A (en) * 1967-03-16 1968-06-07 Radiotechnique Coprim Rtc Arrangement of semiconductor devices carried by a common support and its manufacturing method
US3576683A (en) * 1967-04-07 1971-04-27 Sony Corp Transistor structure with thin, vaporgrown base layer
US3510735A (en) * 1967-04-13 1970-05-05 Scient Data Systems Inc Transistor with integral pinch resistor
NL6706735A (en) * 1967-05-13 1968-11-14
NL158024B (en) * 1967-05-13 1978-09-15 Philips Nv PROCESS FOR THE MANUFACTURE OF A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE OBTAINED BY APPLYING THE PROCEDURE.
US3506502A (en) * 1967-06-05 1970-04-14 Sony Corp Method of making a glass passivated mesa semiconductor device
US3575740A (en) * 1967-06-08 1971-04-20 Ibm Method of fabricating planar dielectric isolated integrated circuits
US3596149A (en) * 1967-08-16 1971-07-27 Hitachi Ltd Semiconductor integrated circuit with reduced minority carrier storage effect
US3514846A (en) * 1967-11-15 1970-06-02 Bell Telephone Labor Inc Method of fabricating a planar avalanche photodiode
US3575741A (en) * 1968-02-05 1971-04-20 Bell Telephone Labor Inc Method for producing semiconductor integrated circuit device and product produced thereby
US3488564A (en) * 1968-04-01 1970-01-06 Fairchild Camera Instr Co Planar epitaxial resistors
US3649386A (en) * 1968-04-23 1972-03-14 Bell Telephone Labor Inc Method of fabricating semiconductor devices
USRE28653E (en) 1968-04-23 1975-12-16 Method of fabricating semiconductor devices
US3550292A (en) * 1968-08-23 1970-12-29 Nippon Electric Co Semiconductor device and method of manufacturing the same
US3586542A (en) * 1968-11-22 1971-06-22 Bell Telephone Labor Inc Semiconductor junction devices
CH516871A (en) * 1969-07-30 1971-12-15 Soc Gen Semiconduttori Spa Process for obtaining semiconductor devices with minimal surface unevenness, and semiconductor device obtained using said process
US3640806A (en) * 1970-01-05 1972-02-08 Nippon Telegraph & Telephone Semiconductor device and method of producing the same
NL159819B (en) * 1970-09-10 1979-03-15 Philips Nv SEMICONDUCTOR DEVICE WITH A SEMICONDUCTOR BODY CONTAINING A TRANSISTOR INCLUDING A PATTERN OF INSULATING MATERIAL CURED INTO THE SEMICONDUCTOR BODY THAT IS RESULTED BY LOCAL OXYDATION OF THE SEMICONDUCTIVE BODY.
NL170902C (en) * 1970-07-10 1983-01-03 Philips Nv SEMICONDUCTOR DEVICE, IN PARTICULAR MONOLITHICALLY INTEGRATED SEMICONDUCTOR CIRCUIT.
CA926029A (en) * 1970-07-10 1973-05-08 N.V. Philips Gloeilampenfabrieken Semiconductor device having a transistor
US3736193A (en) * 1970-10-26 1973-05-29 Fairchild Camera Instr Co Single crystal-polycrystalline process for electrical isolation in integrated circuits
US3648125A (en) * 1971-02-02 1972-03-07 Fairchild Camera Instr Co Method of fabricating integrated circuits with oxidized isolation and the resulting structure
US3751722A (en) * 1971-04-30 1973-08-07 Standard Microsyst Smc Mos integrated circuit with substrate containing selectively formed resistivity regions
US3861968A (en) * 1972-06-19 1975-01-21 Ibm Method of fabricating integrated circuit device structure with complementary elements utilizing selective thermal oxidation and selective epitaxial deposition
US3858231A (en) * 1973-04-16 1974-12-31 Ibm Dielectrically isolated schottky barrier structure and method of forming the same
US4118728A (en) * 1976-09-03 1978-10-03 Fairchild Camera And Instrument Corporation Integrated circuit structures utilizing conductive buried regions

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AU3612371A (en) 1973-05-31

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