CA1117211A - Method of inserting an address signal in a video signal - Google Patents
Method of inserting an address signal in a video signalInfo
- Publication number
- CA1117211A CA1117211A CA000289309A CA289309A CA1117211A CA 1117211 A CA1117211 A CA 1117211A CA 000289309 A CA000289309 A CA 000289309A CA 289309 A CA289309 A CA 289309A CA 1117211 A CA1117211 A CA 1117211A
- Authority
- CA
- Canada
- Prior art keywords
- signal
- code
- address signal
- address
- video signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B27/00—Editing; Indexing; Addressing; Timing or synchronising; Monitoring; Measuring tape travel
- G11B27/10—Indexing; Addressing; Timing or synchronising; Measuring tape travel
- G11B27/19—Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier
- G11B27/28—Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier by using information signals recorded by the same method as the main recording
- G11B27/32—Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier by using information signals recorded by the same method as the main recording on separate auxiliary tracks of the same or an auxiliary record carrier
- G11B27/322—Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier by using information signals recorded by the same method as the main recording on separate auxiliary tracks of the same or an auxiliary record carrier used signal is digitally coded
- G11B27/323—Time code signal, e.g. on a cue track as SMPTE- or EBU-time code
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B27/00—Editing; Indexing; Addressing; Timing or synchronising; Monitoring; Measuring tape travel
- G11B27/02—Editing, e.g. varying the order of information signals recorded on, or reproduced from, record carriers
- G11B27/022—Electronic editing of analogue information signals, e.g. audio or video signals
- G11B27/024—Electronic editing of analogue information signals, e.g. audio or video signals on tapes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/08—Systems for the simultaneous or sequential transmission of more than one television signal, e.g. additional information signals, the signals occupying wholly or partially the same frequency band, e.g. by time division
- H04N7/087—Systems for the simultaneous or sequential transmission of more than one television signal, e.g. additional information signals, the signals occupying wholly or partially the same frequency band, e.g. by time division with signal insertion during the vertical blanking interval only
- H04N7/088—Systems for the simultaneous or sequential transmission of more than one television signal, e.g. additional information signals, the signals occupying wholly or partially the same frequency band, e.g. by time division with signal insertion during the vertical blanking interval only the inserted signal being digital
- H04N7/0881—Systems for the simultaneous or sequential transmission of more than one television signal, e.g. additional information signals, the signals occupying wholly or partially the same frequency band, e.g. by time division with signal insertion during the vertical blanking interval only the inserted signal being digital the signal being time-compressed before its insertion and subsequently decompressed at reception
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B2220/00—Record carriers by type
- G11B2220/90—Tape-like record carriers
Abstract
ABSTRACT OF THE DISCLOSURE
Method and apparatus for inserting an address signal in a video signal by compressing the time code signal including synchronizing bits inserted at every predetermined bit and cyclic redundancy check code and then inserting the compressed time code signal into at least one horizontal line period within a vertical blanking period of the video signal. The invention allows the time code signals to be reconstructed where the record medium is stopped or transported at very low speeds.
Method and apparatus for inserting an address signal in a video signal by compressing the time code signal including synchronizing bits inserted at every predetermined bit and cyclic redundancy check code and then inserting the compressed time code signal into at least one horizontal line period within a vertical blanking period of the video signal. The invention allows the time code signals to be reconstructed where the record medium is stopped or transported at very low speeds.
Description
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~r,,~, BACKGROVND OF T~ INVENTION
Field of the Inventlon:
This invention relates in general to a method and apparatus for inserting address signals in a video signal for a video tape apparatus.
~escription of the Prior Art:
In order to edit video and/or audio signals rapidly and precisely, it has been proposed in the prior art to record an ; address signal on the magnetic tape in addition to the video ; and/or audio signal. In this case, as the address signals are provided signals of various codes, but the SMPTE time code signal ~-~ is recommended as an ~merican National Standard and the EBU time code signal is recommended as a standard code for 625 line/50 field television tape recordings. In the art, the above two time code signals are recorded on a record medium along its longitudinal track and read out of the signals can be achieved at tape speeds from slow to high speed. In the case where the record medium is stopped or transported at very low speeds, how-ever, the reproduction of the time code signals becomes impossibl~
In fact, upon editing a video tape by a video tape recorder, it ', .
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is very advantageous for an editor to be able to choose indivi-dual frames presented visually at very low tape speeds but the disadvantages of this method of operation is that the address of a chosen ~rame cannot be readily known with prior art systems.
The time code signals identify each television frame but the identificatlon of its even or odd field and that of the ~-phase of the burst signal of each television ield are impossible.
Therefore, precise editing cannot be achieved by the known prior art systems.
In a video tape recorder having a still reproduction mode, in order to obtain an addr~ss sigr.al in the still repro-duction mode, it has been proposed to convert the synchronizing signal ln the vertical blanking period of a television signal to a signal corresponding to an address. For example, Japanese Patent Publication No. 42j~540 flled by Nippon Hoso Kyokal, published on February 24, 19~7 discloses this method. This Japanese Patent Publication dlscloses an address signal including frame identlfication that can be reproduced even i.n a stlll re-production mode but since there is no ordinary synchronizing pulse in the vertical blanking period, a special processing is necessary so as to supply the reproduced address signal to other video tape recorders (VTRs~ and a time base corrector.
In -these prior art devices since one address signal is recorded for each frame reading errors caused by dropouts or guard band noise during reproduction cannot be prevented.
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SUMMARY OF T~IE INVENTION
~_, It is an object o this inventlon to provlde a method ;~ of lnserting an address signal in the vertical interval of a video signal.
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Another object of the invention is to provide a method of record;ng an address signal which prevents reading errors.
A further object of the invention is to provide a .
method of inserting an address si~nal which includes an error check code.
A still furtl.er object of the invention is to provide - a method of recording an address signal which is suitable for a helical scan video tape recorder.
A still further object of the invention is to provide 1~ a method of inserting an address signal which overcomes the ` time base error.
A still further object of the invention is to provide a circuit which can read out an address signal without errors.
A yet further object of the invention i5 to provide a circuit which derives an address signal from a video tape re-corder independent of the tape speeds. -~
In accordance with the foregoing, there is provided:
A method of iIIS erting an address signal in a video signal comprising the steps of:
a) providing the address signal having a plurality of time code bits corresponding to the video signal recorded Oll one track followed by an error check code -~
signal;
` b) selecting at least one predetermined horizontal ~ , . .
line period ~ithin a ~ertical blanking period from each field or frame of said video signal; and :, .
c~ inserting said address signal in said selected one horizontal line.
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There is also provided:
A method of inserting an address signal in a video signal comprising the steps of:
a) provi.ding the address signal having a plurality of time code bits corresponding to one field of the video signal followed by an error check code signal;
. b) sel.ecting at least one predetermined horizontal line period ~ithin a vertical blanking period ~rom each . field or frame of said video signal;
'. 10 c) inserting said address signal in said selected ~.
: one horizontal line.
There is also provided:
A method of inserting an address sigr,al in a video signal comprising the steps of:
'~ a) providing the address signal having a plurality .. of time code bits corresponding to one frame of the video signal followed by an error check code signal;
b) selecting at least one predetermined horizontal . line period within a ~ertical blanking period ~rom each field or frame of said video signal;
c) inserting said address signal in said selected one horizontal line.
There is further provided:
An apparatus for producing a video signal with an address signal therein, comprisin~:
- a) means for providing the address signal corresponding to one field or frame of the video `
signal, said address signal consisting of a plurality of time code bits;
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b) means for providing a cyclic redundancy ~ ' check code signal for the address signal;
c) means for selecting at least o~e predeter-mined horizontal line period,within a vertical blanking period of each field or frame of said video signal; and d) means for inserting said address signal in ,:
, said selected one horizontal line period. :~
There is further provided:
An apparatus for producing a video si~nal with an address signal therein, comprising:
a) means for producing the address signal / ,.
corresponding to one field or frame of the video ~ ~' signal, said address signal consisting of a plurality of time code bits;
b) means for encoding the address code into an address signal; ~:
c) means for providing a cyclic redundancy check code signal for the address signal;
' 20 d) means for selecting at least one predeter- ' ,~ mined horizontal line period within a vertical blanking ., period of each field or frame of said video signal;
and e) means for inserting said address signal in ';
said selected one horizontal line period.
-' Other objects, features and advantages of the invention ~ will be readily apparent from the following description of ~;
~ certain preferred ~mbodiments thereof taken in conjunction with the accompanying drawings although variations and modifications may be effected without departing from the spirit and scope of the novel concepts of the disclosure and in which:
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7;2 . , BRIEF DESCRIPTIOM OF THE DRAWINGS
Figure 1 is a top plan view of a part of a magnetic tape on which a video signal is recorded as slant tracks and an address signal is also recorded by a prior art method;
Figure 2 is a schematic diagram illustrating an S~IPTE
time code signal recorded on the tape;
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Z~ ' Fi.gure 3 is a top plan view of a part o~ a magn~tic tape on which a video signal and address si.gnal are r~corded by the method o~ the invention;
Figures 4A and 4B are diagrams illustrat,ing a recorded. pattern of signals on a tape according to the invention;
Figure 4C is a schematie diagram illustrating a time ' code signal of the present invention which is recorded on the tape;
Figure 5A is a diagram illustrating a recorded pattern . of signals.on a tape according toithe present invention;
Figures 5B through SK, 8.and 9 illustrate waveform diagrams'used for explaining the operation of -the circuit of ~ ~
. the present invention; ' :
Figure 6 is a block diagram illustrating a circuit according to the invention which, is to be used to produce the time code signals and record them on a magnetic tape., ~,' ~,. Figure 7 is a block diagram illustrating a circuit of the invention for reading out the time code signals from a ~ magnetic tape and decode the address;
. Figures 8A - 8H show the wave form~ of the various pulses existant in the circuit of Figure 7; and .~ Figures 9A - 9D show further wave forms relating to ,~ the synchronizing bit.
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DESCRIPTION OF THE PREFERRED EMBODIMENTS
Figure 1 illustrates a prior art method of recording an address signal on a magnetic tape comprising a magnetic tape T upon which an address signal is recorded in addition to '~ a video signal.
': In Figure 1, TV represents a number of video tracks formed on a magnetic tape T and each of the video tracks TV
includes a video signal of one field. Of course, a video signal of one form may be recorded on one video track. TA designates a track on the tape T which carries the audio signal. Track TQ
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represents the track which carries the cue signals and TC
designates a track which carries the control signals. On the cue track TQ is recorded an address signal. In this case, a SMPTE time code signal is used as the address signal and two video tracks TV which form one frame are identiied by one SMPTE time code signal.
The SMPTE time code is approved as the American National Standard time and control code for video and audio tape for 525 line/60 field television systems on April 2, 1975 and published in the journal of the SMPTE, Volume 84, July 9, 1975.
As shown in Figure 2, which schematically illustrates the SMPTE code signal, each address correspon~s to one frame and consists of 80 bits numbered O through 79 and the bit fre-quency is selected as 2.4 KHz. As illustrated in Figure 2, time address bits consisting o~ 26 bits indicate 29 frames, 59 seconds, S9 minutes and 23 hours. The bi-t number 10 is the drop frame flag, the bit numbers 11, 27, ~3, 58 and 59 are unassigned address bits and the bit numbers 4 through 7, 12 through 15, 20 through 23, 28 through 31, 36 through 39, 44 through 47, 52 through 55 and 60 through 63 are user bits;
respectively. The synchronizing word of 16 bits is arranged such that it is determined whether the tape is transported in the forward direction and, thus, the SMPTE time code signal when read out in the direction indicated by an arrow F or whether the tape is transported in the backward direction and hence the SMPTE time code signal is read out in the direction indicated by an arrow R. Thus, the time code signal can be correctly read out even if the tape is transported in either 72~
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direction. In this case, the code signal is so recorded that the information "1" and "O" thereof are recorded as bi-phase mark as illustrated in Figura 2.
As described above, if the address signal for each frame of the video signal is recorded on the ~rack TQ which extends in the lengthwise direction of the tape T, editing of the tape can be accomplished very rapidly and precisely.
However, in the case of slow or still motion repro-duction mode, the speed of the tape becomes very slow or the tape is actually stopped, then the code signal recorded on the track TQ cannot be read out.
Figures 3 through 9 illustrate an example of the - invention which provides an address signal that can be read out even in slow or still reproduction modes and, thus, editing of a tape can be efficiently accomplished. The video signal of the NTSC system is used as -an exarnple.
Figure 3 is a top plan view of magnetic tape T on which the video signal and address signals are recorded by the method and apparatus of the invention.
With the invention, an address signal SA, identifying a video signal corresponding to each T~ track, is inserted in the video signal as a digital signal and the video signal are recorded on the tape as slant tracks Tv. The address signals SA recorded on the video tracks TV are indicated as hatched areas in Figure 3. The address signals SA are inserted into the video signals of odd and even fields of one frame and then recorded as shown in Figure 3.
In ~`his invention, the time code signal includes synchronizing bits which are inserted in th4 time code signal ~ .
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at every predetermined bit and then recorded on the video track TV so that by correcting the phase of the clock at every predeterminecl bit by utilizing the synchronizilig signal upon read out, the code signal and the address signal can be read out precisely even lf the bit frequency of the code signal varies by jitter~ skew or other noise factors or by the variation of the horizontal frequency în a slow or still motion reproduction mode.
Further in this invention, there is provided an error check code in the code signal to avoid read out error.
As shown with hatches in Figures 4A and 4B which comprises a record pattern of signals on the tape, not shown, . according to the invention, one address signal is inserted into one horizontal line period in the suppressed line period within the vertical blanki.ng period or vertical interval excepting that por~ion which comprises a vertical synchronizing pulse !
period Tvp and equalizing pulse period TEp. The address signal is inserted in the periocl af-ter burst signals S~ and it is desired that the same address signals be inserted repeatedly .
- into three successive horizontal line periods. Hereinafter, this address signal will be referred to simply as the VITC
~ (vertical interval time code) signal. The above suppressed .~ periods correspond -to the 10th through 21st l.ine periods in `: the NTSC system.
~ The bit frequency fB of the VITC signal is selected . as the color subcarrier frequency fsc which equals 3.58 MHz ; divided by an integer, for example, one-half (1/2) of the .~'. frequency fsc If ~he horizontal line frequency is taken as fH and the vertical frequency as fv~ respectively, -the following :. -. . .
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relationship is established:
455 455 x 525 . .. ..(1) Thus, if the following relationship is established:
., ; , B -~- fsc ........................... (2) . and the ollowing equation 3 is obtained:
fB -~- fH ...~...(3j , ` . ' ' Now, referring to Figure 4C, the arrangement of code signal of the invention will be explained. The code signal is recorded on the video track Tv, so it is not necessary to employ the synchronizing word at the top of the code SMPTE
time code signal shown in Figure 2. First, synchronizing bits consisting of 2 bits are placed at the top o the code signal as shown by a hatched portion in Figure 4C.
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Synchronizing bits, each consisting of 2 bits are placed at every ten bits, which are shown by hatched portions in Figure 4C. So, the bit numbers 0, 1, 10, 11, 20, 21, 30, 31, 40, 41, .
; 50, 51, S0, 61, 70, 71, 80 and 31 are synchronizing bits.
Time address bits are arranged similar to that of SMPTE time code. The bit numbers 2 to 5 are units of frames, 12 to 13 are tens of frames, 22 to 25 are units of seconds, 32 to 34 are tens of seconds, 42 to 45 are units o minutes, 52 to 54 are tens of minutes, 62 to 65 are units of hours and 72 to 73 are tens of hours, respectively. The bit number 14 is the drop frame flag, the bit number 15 is a field mark, the bit numbers , :
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35, 55, 74 and 75 are unassigned address bits and the bit numbers 6 through 9, 16 through 19, 26 through 29, 36 through 39, 46 through 49, 56 through 59, 66 through 69 and 76 through 79 are user bits.
By making the bit numbers 15 be "O" for 1 and 3 field or ~'1" for 2 and 4 field, the fiel~ identification as to whether the field is even or odd can be accomplished.
Total bits number of these information bits, synchronizing bits, time code bits, user bits and so on, are 82 bits. After these information bits, there is provided an error check code for the preceding code, for example, ~cyclic redundancy check code ~hereinafter referred to as CRC code) consisting of 8 bits.
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~` In using CRC code, the data presented between b and 81 bit (in all ~2 bits) are divided by a predetermined code or polynomial( `~ ~x8 + 1) and the residual is coded into the final 8 bits. The !-' last 8 bits are the CRC code. In the; decoding process, all 90 -~` bits, including the CRC code are di~ided by the predetermined ~,~ code which is constant and can be expressed by X~ + l. The . f ~
predetermined code used in the decoding process is the same predetermined code as used in the encoding process. The residual acts as an indicator of error. If there is a residual the information is incorrect, if not, the information is correct.
Figure 5A i]lustrates an example of the time code signal representing an address according to the present-inven-tion. The code signal consisting of 90 bits is inserted in the period of 50.286 micro seconds and is inserted from the timing Ts (for example 10.616 micro seconds~ after the front edge of the horizontal synchronizing si~nal till the timing 2.65 micro 1. .
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seconds before the front edge of the following horizontal synchronizing signals. The code signal illustrated in Figure 5A indicates an address of 29 frames, 59 seconds, 59 ~minutes, 23 hours, the same as the address shown in Figure 2, In this case, it is sufficient that the informations "1" and "O" of the ~ITC signal are expressed as different ~ ~ lev ~ shown in Figure 5A. For example, information "O" is Oct.l~,77 selected as the pedestal level and the information "1" is selected as 50 IRE units or a signal hlgher than the "O"
level and then the signals are recorded with opposite level to the horizontal synchronizing pulse viewed from the pedestal level.
Figure 6 iIlustrates a circuit for producing the VITC
signal and for recording the same on a magnetic tape.
- In Figure 6, an input terminal 1 receives a video signal which is to be recorded. The video signal is fed to a ..clamp circuit 2 and synchronizing signal separator 3 which separates a synchronizing signal from the video signal. There is provided a clamp pulse generator 4 which generates a clamp pulse from the synchronizing signal. The video signal through the clamp circuit 2 is fed to an adder circuit 6 through a vertical blanking period shaping circuit 5 and also fed to a synchronizing signal separator 7. Frame pulses are separated by a frame pulse separator 8 which receives an output of the synchronizing signal separator 7. The frame pulses are fed to a time counter 9. The output of the synchronizing signal separator 7 is fed to a mono-stable multivibrator 10. The ;mono-stable multivibrator 10 removes an equalizing pulse from the signal and generates a signal having a horizontal fre-quency fH, which is fed to a phase comparator 11. The phase .
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, comparator 11, a variable frequency oscillator 12 and a timing clock generator 13 form a PLL (phase lock loop) circuit.
The timing clock generator 13 generates a signal having a frequency f~I and clock pulses Pl through Plo shown in Figures 5B through 5K. The signal having a frequency fH generated by the timing clock generator 13 is fed to the phase comparator 11 to compare with the input from the mono-stable multivibrator 10. The resulting output from the phase comparator 11 is fed to the variable frequency oscillator 12 as a control signai for it. Thus, the clock pulses Pl through Plo are generated which are synchronized with the horizontal synchronizing signal of the video signal.
The clock pulse Pl has the same frequency as the color subcarrier frequency fsc~ The clock pulse P2 has a frequency of 1/2 fsc, and one cycle of the clock pulse P2 is equal to one bi ~of the code signal shown in Figure 5A. Further, the clock pulse P3 has a frequency of 1/4 fsc. The timing clock generator 13 is constructed so as to generate the clock puLses P~ through P6 by a decimal counter rom ~he clock pulse P3, and the clock pulses P7 through Plo by a hexadecimal counter. ;~
The clock pulses from the timing clock generator 13 and an output from the time counter 9 are fed to a time code encoder 14 to form a time code (frame code, second code, minute code, and hour code) which is fed to an adder circuit 15. While synchronizing bits are formed by the synchronizing bit generator 16 by using the pulses from the timing clock generator 13, and user bits are formed at a user bit encoder 17. These synchron-izing bits and user bits are ~ed to the adder circuit 15.
Accordingly, the output of the adder circuit 15 is the code signal which consists of the time code, the user bits and ~L~17Z$1 synchronizing bits arranged in the manner shorn in Figure 4C.
Then the output of the adder circuit 15 is fed to a CRC code encoder 18. Then the code signal shown in Figure 4C is derived from an adder circuit 19 which is added with the CRC
code which is derived by the CRC code encoder 18. The code signal is fed to a gate circuit 20.
While gate pulses which are corresponding to three successive horizontal line periods in the vertical blanking period are derived at the gate pulse generator 22 based on a vertical synchronizing pulse separated by a vertical syn-chronizing signal separator 21 from the output o synchroniz-ing signal separator 7. Then the gate pulses are fed to the gate circuit 20. Thus, the code signal gated by the gate signal is fed to the adder circuit 6. A code signal which may have been inserted in the vertical blanking period is removed at the vertical blanking period shaping circuit 5 from the video si.gnal by gating by the gate pulse from the gate pulse generator 22. Then the output from the circuit 5 is fed to the adder circuit 6.
Thus, the video signal in which the code signals are inserted into three successive horizontal line periods within the vertical blanking period is derived from an output terminal 23. The output video signal is recorded on a magnetic record-ing tape through a signal recording system of the VTR which includes ~M modulator and -so on.
Further, it is possible to provide the SMPTE time code from a terminal 24 and to synchronize the S~TE time code with the time code whlch is to be inserted into the video signal.
The synchronization can be achieved by pre-setting the time ~7Z~L
counter 9 when a preset switch 26 is on. The SMPTE time code is fed through a decoder 25 and the preset switch 26.
Figure 7 is a block diagram illustrating a circuit of the invention for reproducing the video signal recorded on the tape explained in the above, reading out the code signal from the video signal and, decoding the address.
In Figure 7, an input terminal 31 receives a video signal reproduced from the video signal recorded on track Tv.
The code signal is derived at an output terminal 32 by the following way. First of all, the video signal is fed to a code separator 33. The code signal ijs separated from the video signal by a synchronizing signal which is separated from the video signal at the synchronizing signal separator 34. There is provided an oscillator 35 which oscillates with a frequency which is n times of the color subcarrier frequency fsc (n is integer, for example, n equals to 8 ).
An output of the oscillator 35 is ed to a hexadeci-mal counter 36. An output of the hexadecimal counter 36 having a frequency of 1/2 fsc is fed to a decimal counter 37. An outpu~ of the decimal counter 37 is fed to a hexadecimal .
.- counter 38. Thus, the clock pulses Pl and P2 which are the same as the pulses of recording, are obtained (derived) from the counter 36, the clock pulses P3 through P6 are obtained from the counter 37, and the clock pulses P7 through Plo are obtained from the counter 38. These pulses are synchronized with the code signal separated from the reproduced video signal.
Thus, a mono-stable~multivibrator 39 generates a pulse Pll which is narrower than a horizontal line period but : .
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- ,' wider than the period where code signal of 90 bits exists ~
shown in Figure 8C, while an edge pulse generator ~0 generates edge pulse corresponding to a trailing edge of the code signal .
The output of the counter 37 is fed to a synchroniz- ;
ing bit gate pulse generator 41 to generate a synchronizing bit gate pulse shown in Figure 8B which is similar to the .
clock pulse P6 which has a value "l" at the phase corresponding to synchronizing bits.
Now, let us assume that the code signal including synchronizing bits of "~10)" as show~ in Figure 9A is separated from the video signal. Then the edge pulse generator 40 generates an edge pulse corresponding (synchronized) to th trailing edge of code signal, as shown in Figure 9B. This edge pulse and the synchronizing bit gate pulse Pl2 shown in Figure 9C are fed to an AND gate 42 to derive only an edge pulse synchronized with the trailing edge of the synchronizing bit.
This edge pulse is fed to the counter 36 as a reset pulse through an OR gate 43 and an AND gate 44. Accordingly, as shown in Figure 9D, the phase difference 7between the output of the counter 36 having a frequency of 1/2 fsc and the timing of the code signal is corrected and the output of the counter 36 is synchronized with the code slgnal. By the above construction, even when the time base fluctuates from the normal time hase by jitter or slow motion reproduction, the timing of the clock pulse is synchronized wi.th the reproduced code. Further, the synchronizing bits are inserted at every ten bits, so it is possible to achieve a very precise syn-chronization.
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In the above example, the osci~lator 35 is a fixed oscillator. However, such an oscillator that is phase locked to, for example, the horizontal synchronizing signal of the reproduced video signal, can further widen t~e extent of the .. timing that can be synchronized. Then it is possible to read .. the code signal even at the still mode reproduction i~ which: a magnetic tape is stopped and at the fast mode in which the tape is run at the speed of several times of the normal speed of reproduction. The counters 37 and 38 are reset by the .~ leading edge of the pulse Pll which is an output of the mono-`i~ stable multivibrator 39 through the AND gate 45.
The output pulses of the counters 36, 37, and 38 : are fed to a timing pulse generator 46 to form required timing ,: pulses.
- The code signal separated by the code separator 33 and output pulse of counter 36 is ~ed to a series-parallel transformation circuit 47 which comprises a shift register to rearrange the code signal except synchronizing bits and CRC code, that is, time codes. and user bits (in all 64 bits) ~ into parallel codes in which each code ~onsists of 4 bits : These parallel codes are written into a buffer memory 48 of a RAM (Random Access Memory) and also fed to a code check circuit 49.
- The code check circuit 49 decodes the time code consisting of 4 bits which is supplied from the circuit 47 by the timing pulse P14 corresponding to the timing of t~e time code signal shown in Figure 8E, which is generated by the -timing pulse generator 4~, and check the decoded numbers whether they are possible numbers or not. There are some ~7;~
possibilities that, for example, hour code shows 27 hours Gr second code shows 81 seconds which are apparently incorrect caused by dropout.
The code check circuit 49 generates a signal "1"
when the code is correct, and a signal 1'0ll when the code is incorrect. The code signal from the code signal separator 33 is fed to a CRC code check circuit 50. The pulse P13 shown in Figure 8D which coincides the phase of the CRC code generated by the timing pulse generator 46 is fed to the CRC code check circuit 50. In the CRC code check circuit 50, the code signal including the information code and th,e CRC code (in all 90'~its~
is divided by the predetermined code o~ polynomial and the ~es~d~àl is checked. If there is no residual the code is correct then the circuit SO derives ;a signal "1". When there are residuals the code is incorrect, the circuit derives a signal "O". Further, the synchronizing bits are separated from the code signal by gating a-t a gate circuit 51 by the synchron~
izLng bit gate pulse P12 shown in Figure 8B. The separated synchronizing bits are ed to a synchronizin~ bit check circuit 52. Whether the synchronizing bits are correct or not, is cherked by the suspected synchronizing bits from the timing pulse generator 46. If it is correct, the circuit 52 derives a signal "1", if not, it derives a signal "0"~
The outputs of the synchronizing bit check circuit 52, the code check circuit 49 and the CRC code check circuit 50 are fed to an AND gate 53. When the output of the A~ID ga'te 53 is "1", which means the code signal is correct, a hold circuit 54 generates a pulse P15 which is "1" shown in Figure 8G by the timing pulse from the timing pulse generator 46. The , . .
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hold circuit 54 is reset by a vertical synchronizing puls~ T~Jp (shown in Figure 8F) from the vertical synchronizing separator `; 55 which is connected to a synchronizing separator 34.
The output pulse P15 of the hold circuit 54 is fed to . .
the AND gates 44, 45. Thus, when the pulse P15 becomes "1", reset of the counters 36, 37 and 38 is forbidden.
The pulse P15 is fed to an A~ID gate 56 and ` a memory pulse generator 57. The AND gate 56 supplies a writing clock pulse for the buffer memory 48. During the period !' that the pulse P15 is "0" codes of 4 bits from the series-parallel transformation circuit 47 are continuously written into , the buffer memory, but the pulse P15 becomes "1'~, the writing . , into the memory is forbidden.
And, the memory pulse generator 57 generates a memory pulse P16 which coincides the leading edge of the pulse P15 as shown in Figure 8G. By feeding the memory pulse P16 to the AND gate 58, writing clock pulse is fed to a buEfer memory 59 through the AND gate 58. Thus, contents of the buffer memory 43 is transferréd to the buffer memory 59. The output data consisting of the time code and the user bits (in all 64 bits) is derived at the output terminal 32 by supplying a read-out address signal through a terminal 60. The read out data is fed to a display and/or editing apparatus.
As mentioned previously, the code signals are inserted into three successive horizontal scanning interval o~ the vertical blanking period. If the code signal inserted in-the first horizontal line period is incorrect, the pulse P15 from the hold circuit 54 does not rise then the date is not trans-ferred from the buffer memory 48 to ~he buffer memory 59.
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. , The code signal of the next horizontal line period is check~d in the same manner. Then only the correct code signal is stored in the bufer memory S9. Then it is not necessary to insert the code signals into successive horizontal scanning interval. The code signal may be inserted in any of the in-tervals if it is not in the useful scanning lines. Further, the number of the repetition of the code signal is not re-stricted.
In this invention, even only one o~ the code signals is read correctly, the hold circuit 54 generates the pulse P15 and the system works well.
In the above example, the code signal which repre-sents an address is recorded on the track Tv. But at the same time, the SMPTE time code signal which represents the same address which is recorded on the track TV can be recorded on the track TQ which is extending in the longitudinal direction of the magnetic tape. The S~PTE time code signai can be recorded as a bi-phase signal the same as the signal recorded on the track Tv.
Due to construction of the recording apparatus of the present invention, since an address signal showing a video signal i~ recorded as a digital signal on the track of the video signal, the digital signal corresponding to the addres~
can be read out positively even in slow or stiLl motion re-production mode and, thus, editing of the video tape can be very efficiently carried out.
Also, in the invention, the synchronizing pulses and other pulses are not processed but the address signal is inserted in the horizontal line period between the horizontal ~ .72~
~; synchronizing pulses within t~e vertical blanking period so i that no undesirable influences are caused on signal process-ing such as clamping the vidPo signal, separating the synchronizing signal and so forth and the reproduction will not be interferred with in any manner.
The bit frequency fB of the inserted VITC signal is selected to be a fraction of the subcarrier frequency fSC
by an integer so that if the video signal with the VITC
signal is routed through the time base corrector the repro duced video signal is written in the memory by the clock pulse whose frequency is higher than the color subcarrier frequency by an integer time and then the written signal is read out in the memory to correct its time base. Thus, the ~ clock references are the same in number at every one bi ~of Oct .. I ~q~7 the address signal and the condition of the address code is not affected by the time base correction.
Further, in this invention there are inserted synchronizing bits ak every predetermined bit in the code signal, the read out error can be checked by the synchronizing bits, and by forming pulses synchronized with the synchronizing bits, read out of the code can be achieved precisely even if - the bit frequency of the code signal varies by jitter, skew, or other noise factors or by the variation of the horizontal frequency in a slow or still motion reproduction.
In this invention, error check code of CRC code is added to the code signal, so read out of the code signal can be achieved ~ore precisely.
The above examples of the invention correspond to the cases in which the video signal of the NTSC system are utilized . . .
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so that the bit frequency of the VITC signal is selected as , . , . .
n- fsc (n being an integer). However, when video signals of other systems such as PAL systems or other types are utilized, it is necessary to select the bit frequency of the VITC signal in view of the predetermined relationship to the horizontal r, frequency such that all bits of the VITC signal can be in-serted in one horizontal line period as, for example, 455f4 fH
horizontal line frequency.
Although the invention has been described with respect to preferred embodiments, it is to be realized that modifica-. tions and variatio-ns can be made by one skilled in the art without departing from the spirit and scope of the novel con-cepts of tbe invention as defined by the appended claims.
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~r,,~, BACKGROVND OF T~ INVENTION
Field of the Inventlon:
This invention relates in general to a method and apparatus for inserting address signals in a video signal for a video tape apparatus.
~escription of the Prior Art:
In order to edit video and/or audio signals rapidly and precisely, it has been proposed in the prior art to record an ; address signal on the magnetic tape in addition to the video ; and/or audio signal. In this case, as the address signals are provided signals of various codes, but the SMPTE time code signal ~-~ is recommended as an ~merican National Standard and the EBU time code signal is recommended as a standard code for 625 line/50 field television tape recordings. In the art, the above two time code signals are recorded on a record medium along its longitudinal track and read out of the signals can be achieved at tape speeds from slow to high speed. In the case where the record medium is stopped or transported at very low speeds, how-ever, the reproduction of the time code signals becomes impossibl~
In fact, upon editing a video tape by a video tape recorder, it ', .
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is very advantageous for an editor to be able to choose indivi-dual frames presented visually at very low tape speeds but the disadvantages of this method of operation is that the address of a chosen ~rame cannot be readily known with prior art systems.
The time code signals identify each television frame but the identificatlon of its even or odd field and that of the ~-phase of the burst signal of each television ield are impossible.
Therefore, precise editing cannot be achieved by the known prior art systems.
In a video tape recorder having a still reproduction mode, in order to obtain an addr~ss sigr.al in the still repro-duction mode, it has been proposed to convert the synchronizing signal ln the vertical blanking period of a television signal to a signal corresponding to an address. For example, Japanese Patent Publication No. 42j~540 flled by Nippon Hoso Kyokal, published on February 24, 19~7 discloses this method. This Japanese Patent Publication dlscloses an address signal including frame identlfication that can be reproduced even i.n a stlll re-production mode but since there is no ordinary synchronizing pulse in the vertical blanking period, a special processing is necessary so as to supply the reproduced address signal to other video tape recorders (VTRs~ and a time base corrector.
In -these prior art devices since one address signal is recorded for each frame reading errors caused by dropouts or guard band noise during reproduction cannot be prevented.
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SUMMARY OF T~IE INVENTION
~_, It is an object o this inventlon to provlde a method ;~ of lnserting an address signal in the vertical interval of a video signal.
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Another object of the invention is to provide a method of record;ng an address signal which prevents reading errors.
A further object of the invention is to provide a .
method of inserting an address si~nal which includes an error check code.
A still furtl.er object of the invention is to provide - a method of recording an address signal which is suitable for a helical scan video tape recorder.
A still further object of the invention is to provide 1~ a method of inserting an address signal which overcomes the ` time base error.
A still further object of the invention is to provide a circuit which can read out an address signal without errors.
A yet further object of the invention i5 to provide a circuit which derives an address signal from a video tape re-corder independent of the tape speeds. -~
In accordance with the foregoing, there is provided:
A method of iIIS erting an address signal in a video signal comprising the steps of:
a) providing the address signal having a plurality of time code bits corresponding to the video signal recorded Oll one track followed by an error check code -~
signal;
` b) selecting at least one predetermined horizontal ~ , . .
line period ~ithin a ~ertical blanking period from each field or frame of said video signal; and :, .
c~ inserting said address signal in said selected one horizontal line.
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There is also provided:
A method of inserting an address signal in a video signal comprising the steps of:
a) provi.ding the address signal having a plurality of time code bits corresponding to one field of the video signal followed by an error check code signal;
. b) sel.ecting at least one predetermined horizontal line period ~ithin a vertical blanking period ~rom each . field or frame of said video signal;
'. 10 c) inserting said address signal in said selected ~.
: one horizontal line.
There is also provided:
A method of inserting an address sigr,al in a video signal comprising the steps of:
'~ a) providing the address signal having a plurality .. of time code bits corresponding to one frame of the video signal followed by an error check code signal;
b) selecting at least one predetermined horizontal . line period within a ~ertical blanking period ~rom each field or frame of said video signal;
c) inserting said address signal in said selected one horizontal line.
There is further provided:
An apparatus for producing a video signal with an address signal therein, comprisin~:
- a) means for providing the address signal corresponding to one field or frame of the video `
signal, said address signal consisting of a plurality of time code bits;
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b) means for providing a cyclic redundancy ~ ' check code signal for the address signal;
c) means for selecting at least o~e predeter-mined horizontal line period,within a vertical blanking period of each field or frame of said video signal; and d) means for inserting said address signal in ,:
, said selected one horizontal line period. :~
There is further provided:
An apparatus for producing a video si~nal with an address signal therein, comprising:
a) means for producing the address signal / ,.
corresponding to one field or frame of the video ~ ~' signal, said address signal consisting of a plurality of time code bits;
b) means for encoding the address code into an address signal; ~:
c) means for providing a cyclic redundancy check code signal for the address signal;
' 20 d) means for selecting at least one predeter- ' ,~ mined horizontal line period within a vertical blanking ., period of each field or frame of said video signal;
and e) means for inserting said address signal in ';
said selected one horizontal line period.
-' Other objects, features and advantages of the invention ~ will be readily apparent from the following description of ~;
~ certain preferred ~mbodiments thereof taken in conjunction with the accompanying drawings although variations and modifications may be effected without departing from the spirit and scope of the novel concepts of the disclosure and in which:
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7;2 . , BRIEF DESCRIPTIOM OF THE DRAWINGS
Figure 1 is a top plan view of a part of a magnetic tape on which a video signal is recorded as slant tracks and an address signal is also recorded by a prior art method;
Figure 2 is a schematic diagram illustrating an S~IPTE
time code signal recorded on the tape;
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Z~ ' Fi.gure 3 is a top plan view of a part o~ a magn~tic tape on which a video signal and address si.gnal are r~corded by the method o~ the invention;
Figures 4A and 4B are diagrams illustrat,ing a recorded. pattern of signals on a tape according to the invention;
Figure 4C is a schematie diagram illustrating a time ' code signal of the present invention which is recorded on the tape;
Figure 5A is a diagram illustrating a recorded pattern . of signals.on a tape according toithe present invention;
Figures 5B through SK, 8.and 9 illustrate waveform diagrams'used for explaining the operation of -the circuit of ~ ~
. the present invention; ' :
Figure 6 is a block diagram illustrating a circuit according to the invention which, is to be used to produce the time code signals and record them on a magnetic tape., ~,' ~,. Figure 7 is a block diagram illustrating a circuit of the invention for reading out the time code signals from a ~ magnetic tape and decode the address;
. Figures 8A - 8H show the wave form~ of the various pulses existant in the circuit of Figure 7; and .~ Figures 9A - 9D show further wave forms relating to ,~ the synchronizing bit.
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DESCRIPTION OF THE PREFERRED EMBODIMENTS
Figure 1 illustrates a prior art method of recording an address signal on a magnetic tape comprising a magnetic tape T upon which an address signal is recorded in addition to '~ a video signal.
': In Figure 1, TV represents a number of video tracks formed on a magnetic tape T and each of the video tracks TV
includes a video signal of one field. Of course, a video signal of one form may be recorded on one video track. TA designates a track on the tape T which carries the audio signal. Track TQ
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represents the track which carries the cue signals and TC
designates a track which carries the control signals. On the cue track TQ is recorded an address signal. In this case, a SMPTE time code signal is used as the address signal and two video tracks TV which form one frame are identiied by one SMPTE time code signal.
The SMPTE time code is approved as the American National Standard time and control code for video and audio tape for 525 line/60 field television systems on April 2, 1975 and published in the journal of the SMPTE, Volume 84, July 9, 1975.
As shown in Figure 2, which schematically illustrates the SMPTE code signal, each address correspon~s to one frame and consists of 80 bits numbered O through 79 and the bit fre-quency is selected as 2.4 KHz. As illustrated in Figure 2, time address bits consisting o~ 26 bits indicate 29 frames, 59 seconds, S9 minutes and 23 hours. The bi-t number 10 is the drop frame flag, the bit numbers 11, 27, ~3, 58 and 59 are unassigned address bits and the bit numbers 4 through 7, 12 through 15, 20 through 23, 28 through 31, 36 through 39, 44 through 47, 52 through 55 and 60 through 63 are user bits;
respectively. The synchronizing word of 16 bits is arranged such that it is determined whether the tape is transported in the forward direction and, thus, the SMPTE time code signal when read out in the direction indicated by an arrow F or whether the tape is transported in the backward direction and hence the SMPTE time code signal is read out in the direction indicated by an arrow R. Thus, the time code signal can be correctly read out even if the tape is transported in either 72~
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direction. In this case, the code signal is so recorded that the information "1" and "O" thereof are recorded as bi-phase mark as illustrated in Figura 2.
As described above, if the address signal for each frame of the video signal is recorded on the ~rack TQ which extends in the lengthwise direction of the tape T, editing of the tape can be accomplished very rapidly and precisely.
However, in the case of slow or still motion repro-duction mode, the speed of the tape becomes very slow or the tape is actually stopped, then the code signal recorded on the track TQ cannot be read out.
Figures 3 through 9 illustrate an example of the - invention which provides an address signal that can be read out even in slow or still reproduction modes and, thus, editing of a tape can be efficiently accomplished. The video signal of the NTSC system is used as -an exarnple.
Figure 3 is a top plan view of magnetic tape T on which the video signal and address signals are recorded by the method and apparatus of the invention.
With the invention, an address signal SA, identifying a video signal corresponding to each T~ track, is inserted in the video signal as a digital signal and the video signal are recorded on the tape as slant tracks Tv. The address signals SA recorded on the video tracks TV are indicated as hatched areas in Figure 3. The address signals SA are inserted into the video signals of odd and even fields of one frame and then recorded as shown in Figure 3.
In ~`his invention, the time code signal includes synchronizing bits which are inserted in th4 time code signal ~ .
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at every predetermined bit and then recorded on the video track TV so that by correcting the phase of the clock at every predeterminecl bit by utilizing the synchronizilig signal upon read out, the code signal and the address signal can be read out precisely even lf the bit frequency of the code signal varies by jitter~ skew or other noise factors or by the variation of the horizontal frequency în a slow or still motion reproduction mode.
Further in this invention, there is provided an error check code in the code signal to avoid read out error.
As shown with hatches in Figures 4A and 4B which comprises a record pattern of signals on the tape, not shown, . according to the invention, one address signal is inserted into one horizontal line period in the suppressed line period within the vertical blanki.ng period or vertical interval excepting that por~ion which comprises a vertical synchronizing pulse !
period Tvp and equalizing pulse period TEp. The address signal is inserted in the periocl af-ter burst signals S~ and it is desired that the same address signals be inserted repeatedly .
- into three successive horizontal line periods. Hereinafter, this address signal will be referred to simply as the VITC
~ (vertical interval time code) signal. The above suppressed .~ periods correspond -to the 10th through 21st l.ine periods in `: the NTSC system.
~ The bit frequency fB of the VITC signal is selected . as the color subcarrier frequency fsc which equals 3.58 MHz ; divided by an integer, for example, one-half (1/2) of the .~'. frequency fsc If ~he horizontal line frequency is taken as fH and the vertical frequency as fv~ respectively, -the following :. -. . .
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relationship is established:
455 455 x 525 . .. ..(1) Thus, if the following relationship is established:
., ; , B -~- fsc ........................... (2) . and the ollowing equation 3 is obtained:
fB -~- fH ...~...(3j , ` . ' ' Now, referring to Figure 4C, the arrangement of code signal of the invention will be explained. The code signal is recorded on the video track Tv, so it is not necessary to employ the synchronizing word at the top of the code SMPTE
time code signal shown in Figure 2. First, synchronizing bits consisting of 2 bits are placed at the top o the code signal as shown by a hatched portion in Figure 4C.
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Synchronizing bits, each consisting of 2 bits are placed at every ten bits, which are shown by hatched portions in Figure 4C. So, the bit numbers 0, 1, 10, 11, 20, 21, 30, 31, 40, 41, .
; 50, 51, S0, 61, 70, 71, 80 and 31 are synchronizing bits.
Time address bits are arranged similar to that of SMPTE time code. The bit numbers 2 to 5 are units of frames, 12 to 13 are tens of frames, 22 to 25 are units of seconds, 32 to 34 are tens of seconds, 42 to 45 are units o minutes, 52 to 54 are tens of minutes, 62 to 65 are units of hours and 72 to 73 are tens of hours, respectively. The bit number 14 is the drop frame flag, the bit number 15 is a field mark, the bit numbers , :
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35, 55, 74 and 75 are unassigned address bits and the bit numbers 6 through 9, 16 through 19, 26 through 29, 36 through 39, 46 through 49, 56 through 59, 66 through 69 and 76 through 79 are user bits.
By making the bit numbers 15 be "O" for 1 and 3 field or ~'1" for 2 and 4 field, the fiel~ identification as to whether the field is even or odd can be accomplished.
Total bits number of these information bits, synchronizing bits, time code bits, user bits and so on, are 82 bits. After these information bits, there is provided an error check code for the preceding code, for example, ~cyclic redundancy check code ~hereinafter referred to as CRC code) consisting of 8 bits.
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~` In using CRC code, the data presented between b and 81 bit (in all ~2 bits) are divided by a predetermined code or polynomial( `~ ~x8 + 1) and the residual is coded into the final 8 bits. The !-' last 8 bits are the CRC code. In the; decoding process, all 90 -~` bits, including the CRC code are di~ided by the predetermined ~,~ code which is constant and can be expressed by X~ + l. The . f ~
predetermined code used in the decoding process is the same predetermined code as used in the encoding process. The residual acts as an indicator of error. If there is a residual the information is incorrect, if not, the information is correct.
Figure 5A i]lustrates an example of the time code signal representing an address according to the present-inven-tion. The code signal consisting of 90 bits is inserted in the period of 50.286 micro seconds and is inserted from the timing Ts (for example 10.616 micro seconds~ after the front edge of the horizontal synchronizing si~nal till the timing 2.65 micro 1. .
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seconds before the front edge of the following horizontal synchronizing signals. The code signal illustrated in Figure 5A indicates an address of 29 frames, 59 seconds, 59 ~minutes, 23 hours, the same as the address shown in Figure 2, In this case, it is sufficient that the informations "1" and "O" of the ~ITC signal are expressed as different ~ ~ lev ~ shown in Figure 5A. For example, information "O" is Oct.l~,77 selected as the pedestal level and the information "1" is selected as 50 IRE units or a signal hlgher than the "O"
level and then the signals are recorded with opposite level to the horizontal synchronizing pulse viewed from the pedestal level.
Figure 6 iIlustrates a circuit for producing the VITC
signal and for recording the same on a magnetic tape.
- In Figure 6, an input terminal 1 receives a video signal which is to be recorded. The video signal is fed to a ..clamp circuit 2 and synchronizing signal separator 3 which separates a synchronizing signal from the video signal. There is provided a clamp pulse generator 4 which generates a clamp pulse from the synchronizing signal. The video signal through the clamp circuit 2 is fed to an adder circuit 6 through a vertical blanking period shaping circuit 5 and also fed to a synchronizing signal separator 7. Frame pulses are separated by a frame pulse separator 8 which receives an output of the synchronizing signal separator 7. The frame pulses are fed to a time counter 9. The output of the synchronizing signal separator 7 is fed to a mono-stable multivibrator 10. The ;mono-stable multivibrator 10 removes an equalizing pulse from the signal and generates a signal having a horizontal fre-quency fH, which is fed to a phase comparator 11. The phase .
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, comparator 11, a variable frequency oscillator 12 and a timing clock generator 13 form a PLL (phase lock loop) circuit.
The timing clock generator 13 generates a signal having a frequency f~I and clock pulses Pl through Plo shown in Figures 5B through 5K. The signal having a frequency fH generated by the timing clock generator 13 is fed to the phase comparator 11 to compare with the input from the mono-stable multivibrator 10. The resulting output from the phase comparator 11 is fed to the variable frequency oscillator 12 as a control signai for it. Thus, the clock pulses Pl through Plo are generated which are synchronized with the horizontal synchronizing signal of the video signal.
The clock pulse Pl has the same frequency as the color subcarrier frequency fsc~ The clock pulse P2 has a frequency of 1/2 fsc, and one cycle of the clock pulse P2 is equal to one bi ~of the code signal shown in Figure 5A. Further, the clock pulse P3 has a frequency of 1/4 fsc. The timing clock generator 13 is constructed so as to generate the clock puLses P~ through P6 by a decimal counter rom ~he clock pulse P3, and the clock pulses P7 through Plo by a hexadecimal counter. ;~
The clock pulses from the timing clock generator 13 and an output from the time counter 9 are fed to a time code encoder 14 to form a time code (frame code, second code, minute code, and hour code) which is fed to an adder circuit 15. While synchronizing bits are formed by the synchronizing bit generator 16 by using the pulses from the timing clock generator 13, and user bits are formed at a user bit encoder 17. These synchron-izing bits and user bits are ~ed to the adder circuit 15.
Accordingly, the output of the adder circuit 15 is the code signal which consists of the time code, the user bits and ~L~17Z$1 synchronizing bits arranged in the manner shorn in Figure 4C.
Then the output of the adder circuit 15 is fed to a CRC code encoder 18. Then the code signal shown in Figure 4C is derived from an adder circuit 19 which is added with the CRC
code which is derived by the CRC code encoder 18. The code signal is fed to a gate circuit 20.
While gate pulses which are corresponding to three successive horizontal line periods in the vertical blanking period are derived at the gate pulse generator 22 based on a vertical synchronizing pulse separated by a vertical syn-chronizing signal separator 21 from the output o synchroniz-ing signal separator 7. Then the gate pulses are fed to the gate circuit 20. Thus, the code signal gated by the gate signal is fed to the adder circuit 6. A code signal which may have been inserted in the vertical blanking period is removed at the vertical blanking period shaping circuit 5 from the video si.gnal by gating by the gate pulse from the gate pulse generator 22. Then the output from the circuit 5 is fed to the adder circuit 6.
Thus, the video signal in which the code signals are inserted into three successive horizontal line periods within the vertical blanking period is derived from an output terminal 23. The output video signal is recorded on a magnetic record-ing tape through a signal recording system of the VTR which includes ~M modulator and -so on.
Further, it is possible to provide the SMPTE time code from a terminal 24 and to synchronize the S~TE time code with the time code whlch is to be inserted into the video signal.
The synchronization can be achieved by pre-setting the time ~7Z~L
counter 9 when a preset switch 26 is on. The SMPTE time code is fed through a decoder 25 and the preset switch 26.
Figure 7 is a block diagram illustrating a circuit of the invention for reproducing the video signal recorded on the tape explained in the above, reading out the code signal from the video signal and, decoding the address.
In Figure 7, an input terminal 31 receives a video signal reproduced from the video signal recorded on track Tv.
The code signal is derived at an output terminal 32 by the following way. First of all, the video signal is fed to a code separator 33. The code signal ijs separated from the video signal by a synchronizing signal which is separated from the video signal at the synchronizing signal separator 34. There is provided an oscillator 35 which oscillates with a frequency which is n times of the color subcarrier frequency fsc (n is integer, for example, n equals to 8 ).
An output of the oscillator 35 is ed to a hexadeci-mal counter 36. An output of the hexadecimal counter 36 having a frequency of 1/2 fsc is fed to a decimal counter 37. An outpu~ of the decimal counter 37 is fed to a hexadecimal .
.- counter 38. Thus, the clock pulses Pl and P2 which are the same as the pulses of recording, are obtained (derived) from the counter 36, the clock pulses P3 through P6 are obtained from the counter 37, and the clock pulses P7 through Plo are obtained from the counter 38. These pulses are synchronized with the code signal separated from the reproduced video signal.
Thus, a mono-stable~multivibrator 39 generates a pulse Pll which is narrower than a horizontal line period but : .
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- ,' wider than the period where code signal of 90 bits exists ~
shown in Figure 8C, while an edge pulse generator ~0 generates edge pulse corresponding to a trailing edge of the code signal .
The output of the counter 37 is fed to a synchroniz- ;
ing bit gate pulse generator 41 to generate a synchronizing bit gate pulse shown in Figure 8B which is similar to the .
clock pulse P6 which has a value "l" at the phase corresponding to synchronizing bits.
Now, let us assume that the code signal including synchronizing bits of "~10)" as show~ in Figure 9A is separated from the video signal. Then the edge pulse generator 40 generates an edge pulse corresponding (synchronized) to th trailing edge of code signal, as shown in Figure 9B. This edge pulse and the synchronizing bit gate pulse Pl2 shown in Figure 9C are fed to an AND gate 42 to derive only an edge pulse synchronized with the trailing edge of the synchronizing bit.
This edge pulse is fed to the counter 36 as a reset pulse through an OR gate 43 and an AND gate 44. Accordingly, as shown in Figure 9D, the phase difference 7between the output of the counter 36 having a frequency of 1/2 fsc and the timing of the code signal is corrected and the output of the counter 36 is synchronized with the code slgnal. By the above construction, even when the time base fluctuates from the normal time hase by jitter or slow motion reproduction, the timing of the clock pulse is synchronized wi.th the reproduced code. Further, the synchronizing bits are inserted at every ten bits, so it is possible to achieve a very precise syn-chronization.
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In the above example, the osci~lator 35 is a fixed oscillator. However, such an oscillator that is phase locked to, for example, the horizontal synchronizing signal of the reproduced video signal, can further widen t~e extent of the .. timing that can be synchronized. Then it is possible to read .. the code signal even at the still mode reproduction i~ which: a magnetic tape is stopped and at the fast mode in which the tape is run at the speed of several times of the normal speed of reproduction. The counters 37 and 38 are reset by the .~ leading edge of the pulse Pll which is an output of the mono-`i~ stable multivibrator 39 through the AND gate 45.
The output pulses of the counters 36, 37, and 38 : are fed to a timing pulse generator 46 to form required timing ,: pulses.
- The code signal separated by the code separator 33 and output pulse of counter 36 is ~ed to a series-parallel transformation circuit 47 which comprises a shift register to rearrange the code signal except synchronizing bits and CRC code, that is, time codes. and user bits (in all 64 bits) ~ into parallel codes in which each code ~onsists of 4 bits : These parallel codes are written into a buffer memory 48 of a RAM (Random Access Memory) and also fed to a code check circuit 49.
- The code check circuit 49 decodes the time code consisting of 4 bits which is supplied from the circuit 47 by the timing pulse P14 corresponding to the timing of t~e time code signal shown in Figure 8E, which is generated by the -timing pulse generator 4~, and check the decoded numbers whether they are possible numbers or not. There are some ~7;~
possibilities that, for example, hour code shows 27 hours Gr second code shows 81 seconds which are apparently incorrect caused by dropout.
The code check circuit 49 generates a signal "1"
when the code is correct, and a signal 1'0ll when the code is incorrect. The code signal from the code signal separator 33 is fed to a CRC code check circuit 50. The pulse P13 shown in Figure 8D which coincides the phase of the CRC code generated by the timing pulse generator 46 is fed to the CRC code check circuit 50. In the CRC code check circuit 50, the code signal including the information code and th,e CRC code (in all 90'~its~
is divided by the predetermined code o~ polynomial and the ~es~d~àl is checked. If there is no residual the code is correct then the circuit SO derives ;a signal "1". When there are residuals the code is incorrect, the circuit derives a signal "O". Further, the synchronizing bits are separated from the code signal by gating a-t a gate circuit 51 by the synchron~
izLng bit gate pulse P12 shown in Figure 8B. The separated synchronizing bits are ed to a synchronizin~ bit check circuit 52. Whether the synchronizing bits are correct or not, is cherked by the suspected synchronizing bits from the timing pulse generator 46. If it is correct, the circuit 52 derives a signal "1", if not, it derives a signal "0"~
The outputs of the synchronizing bit check circuit 52, the code check circuit 49 and the CRC code check circuit 50 are fed to an AND gate 53. When the output of the A~ID ga'te 53 is "1", which means the code signal is correct, a hold circuit 54 generates a pulse P15 which is "1" shown in Figure 8G by the timing pulse from the timing pulse generator 46. The , . .
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.:
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hold circuit 54 is reset by a vertical synchronizing puls~ T~Jp (shown in Figure 8F) from the vertical synchronizing separator `; 55 which is connected to a synchronizing separator 34.
The output pulse P15 of the hold circuit 54 is fed to . .
the AND gates 44, 45. Thus, when the pulse P15 becomes "1", reset of the counters 36, 37 and 38 is forbidden.
The pulse P15 is fed to an A~ID gate 56 and ` a memory pulse generator 57. The AND gate 56 supplies a writing clock pulse for the buffer memory 48. During the period !' that the pulse P15 is "0" codes of 4 bits from the series-parallel transformation circuit 47 are continuously written into , the buffer memory, but the pulse P15 becomes "1'~, the writing . , into the memory is forbidden.
And, the memory pulse generator 57 generates a memory pulse P16 which coincides the leading edge of the pulse P15 as shown in Figure 8G. By feeding the memory pulse P16 to the AND gate 58, writing clock pulse is fed to a buEfer memory 59 through the AND gate 58. Thus, contents of the buffer memory 43 is transferréd to the buffer memory 59. The output data consisting of the time code and the user bits (in all 64 bits) is derived at the output terminal 32 by supplying a read-out address signal through a terminal 60. The read out data is fed to a display and/or editing apparatus.
As mentioned previously, the code signals are inserted into three successive horizontal scanning interval o~ the vertical blanking period. If the code signal inserted in-the first horizontal line period is incorrect, the pulse P15 from the hold circuit 54 does not rise then the date is not trans-ferred from the buffer memory 48 to ~he buffer memory 59.
:
,. .
1~ -~7~
. , The code signal of the next horizontal line period is check~d in the same manner. Then only the correct code signal is stored in the bufer memory S9. Then it is not necessary to insert the code signals into successive horizontal scanning interval. The code signal may be inserted in any of the in-tervals if it is not in the useful scanning lines. Further, the number of the repetition of the code signal is not re-stricted.
In this invention, even only one o~ the code signals is read correctly, the hold circuit 54 generates the pulse P15 and the system works well.
In the above example, the code signal which repre-sents an address is recorded on the track Tv. But at the same time, the SMPTE time code signal which represents the same address which is recorded on the track TV can be recorded on the track TQ which is extending in the longitudinal direction of the magnetic tape. The S~PTE time code signai can be recorded as a bi-phase signal the same as the signal recorded on the track Tv.
Due to construction of the recording apparatus of the present invention, since an address signal showing a video signal i~ recorded as a digital signal on the track of the video signal, the digital signal corresponding to the addres~
can be read out positively even in slow or stiLl motion re-production mode and, thus, editing of the video tape can be very efficiently carried out.
Also, in the invention, the synchronizing pulses and other pulses are not processed but the address signal is inserted in the horizontal line period between the horizontal ~ .72~
~; synchronizing pulses within t~e vertical blanking period so i that no undesirable influences are caused on signal process-ing such as clamping the vidPo signal, separating the synchronizing signal and so forth and the reproduction will not be interferred with in any manner.
The bit frequency fB of the inserted VITC signal is selected to be a fraction of the subcarrier frequency fSC
by an integer so that if the video signal with the VITC
signal is routed through the time base corrector the repro duced video signal is written in the memory by the clock pulse whose frequency is higher than the color subcarrier frequency by an integer time and then the written signal is read out in the memory to correct its time base. Thus, the ~ clock references are the same in number at every one bi ~of Oct .. I ~q~7 the address signal and the condition of the address code is not affected by the time base correction.
Further, in this invention there are inserted synchronizing bits ak every predetermined bit in the code signal, the read out error can be checked by the synchronizing bits, and by forming pulses synchronized with the synchronizing bits, read out of the code can be achieved precisely even if - the bit frequency of the code signal varies by jitter, skew, or other noise factors or by the variation of the horizontal frequency in a slow or still motion reproduction.
In this invention, error check code of CRC code is added to the code signal, so read out of the code signal can be achieved ~ore precisely.
The above examples of the invention correspond to the cases in which the video signal of the NTSC system are utilized . . .
7Z~
. ~
,.;.
so that the bit frequency of the VITC signal is selected as , . , . .
n- fsc (n being an integer). However, when video signals of other systems such as PAL systems or other types are utilized, it is necessary to select the bit frequency of the VITC signal in view of the predetermined relationship to the horizontal r, frequency such that all bits of the VITC signal can be in-serted in one horizontal line period as, for example, 455f4 fH
horizontal line frequency.
Although the invention has been described with respect to preferred embodiments, it is to be realized that modifica-. tions and variatio-ns can be made by one skilled in the art without departing from the spirit and scope of the novel con-cepts of tbe invention as defined by the appended claims.
:~.
:`:
~21-
Claims (11)
1. A method of inserting an address signal in a video signal comprising the steps of:
a) providing the address signal having a plurality of time code bits corresponding to the video signal recorded on one track followed by an error check code signal;
b) selecting at least one predetermined horizontal line period within a vertical blanking period from each field or frame of said video signal; and c) inserting said address signal in said selected one horizontal line.
a) providing the address signal having a plurality of time code bits corresponding to the video signal recorded on one track followed by an error check code signal;
b) selecting at least one predetermined horizontal line period within a vertical blanking period from each field or frame of said video signal; and c) inserting said address signal in said selected one horizontal line.
2. A method of inserting an address signal in a video signal comprising the steps of:
a) providing the address signal having a plurality of time code bits corresponding to one field of the video signal followed by an error check code signal;
b) selecting at least one predetermined horizontal line period within a vertical blanking period from each field or frame of said video signal;
c) inserting said address signal in said selected one horizontal line.
a) providing the address signal having a plurality of time code bits corresponding to one field of the video signal followed by an error check code signal;
b) selecting at least one predetermined horizontal line period within a vertical blanking period from each field or frame of said video signal;
c) inserting said address signal in said selected one horizontal line.
3, A method of inserting an address signal in a video signal comprising the steps of:
a) providing the address signal having a plurality of time code bits corresponding to one frame of the video signal followed by an error check code signal;
b) selecting at least one predetermined horizontal line period within a vertical blanking period from each field or frame of said video signal;
c) inserting said address signal in said selected one horizontal line.
a) providing the address signal having a plurality of time code bits corresponding to one frame of the video signal followed by an error check code signal;
b) selecting at least one predetermined horizontal line period within a vertical blanking period from each field or frame of said video signal;
c) inserting said address signal in said selected one horizontal line.
4. A method according to claim 1, in which said error check code is a cyclic redundancy check code.
5. A method according to claim 1, in which a bit frequency of said address signal is selected at 1/N of the color subcarrier frequency, wherein N
is an integer more than 1.
is an integer more than 1.
6. A method according to claim 1, in which said bit frequency is 1/2 of the subcarrier fre-quency.
7. A method according to claim 1, in which said address signal includes synchronizing bits at every predetermined bits.
8. A method according to claim 2, in which said address signal includes a field identi-fication bits.
9. An apparatus for producing a video signal with an address signal therein, comprising:
a) means for providing the address signal corresponding to one field or frame of the video signal, said address signal consisting of a plurality of time code bits;
b) means for providing a cyclic redundancy check code signal for the address signal;
c) means for selecting at least one predeter-mined horizontal line period within a vertical blanking period of each field or frame of said video signal; and d) means for inserting said address signal in said selected one horizontal line period.
a) means for providing the address signal corresponding to one field or frame of the video signal, said address signal consisting of a plurality of time code bits;
b) means for providing a cyclic redundancy check code signal for the address signal;
c) means for selecting at least one predeter-mined horizontal line period within a vertical blanking period of each field or frame of said video signal; and d) means for inserting said address signal in said selected one horizontal line period.
10. An apparatus for producing a video signal with an address signal therein, comprising:
a) means for producing the address signal corresponding of one field or frame of the video signal, said address signal consisting of a plurality of time code bits;
b) means for encoding the address code into an address signal;
c) means for providing a cyclic redundancy check code signal for the address signal;
d) means for selecting at least one predeter-mined horizontal line period within a vertical blanking period of each field or frame of said video signal;
and e) means for inserting said address signal in said selected one horizontal line period.
a) means for producing the address signal corresponding of one field or frame of the video signal, said address signal consisting of a plurality of time code bits;
b) means for encoding the address code into an address signal;
c) means for providing a cyclic redundancy check code signal for the address signal;
d) means for selecting at least one predeter-mined horizontal line period within a vertical blanking period of each field or frame of said video signal;
and e) means for inserting said address signal in said selected one horizontal line period.
11. An apparatus according to claim 9, further comprising means for providing synchronizing bits which is inserted into said address code at every prede-termined number of bits.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA387,329A CA1124834A (en) | 1976-10-27 | 1981-10-05 | Method of inserting an address signal in a video signal |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP128991/76 | 1976-10-27 | ||
| JP12899176A JPS5353916A (en) | 1976-10-27 | 1976-10-27 | Recording unit for video signal |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1117211A true CA1117211A (en) | 1982-01-26 |
Family
ID=14998411
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000289309A Expired CA1117211A (en) | 1976-10-27 | 1977-10-24 | Method of inserting an address signal in a video signal |
Country Status (11)
| Country | Link |
|---|---|
| JP (1) | JPS5353916A (en) |
| AT (1) | AT376537B (en) |
| AU (1) | AU511726B2 (en) |
| CA (1) | CA1117211A (en) |
| DE (1) | DE2748233C2 (en) |
| DK (2) | DK158694C (en) |
| FR (1) | FR2369762A1 (en) |
| GB (1) | GB1566177A (en) |
| IT (1) | IT1088613B (en) |
| NL (1) | NL7711844A (en) |
| SE (1) | SE419278B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4734764A (en) * | 1985-04-29 | 1988-03-29 | Cableshare, Inc. | Cable television system selectively distributing pre-recorded video and audio messages |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3531465A (en) * | 1962-06-07 | 1970-09-29 | Tee Pak Inc | Preparation of organic derivatives from decausticized xanthates |
| JPS6049981B2 (en) * | 1978-03-31 | 1985-11-06 | ソニー株式会社 | Recording medium running direction detection device |
| JPS551622A (en) * | 1978-06-19 | 1980-01-08 | Sony Corp | Code signal reader |
| US4313134A (en) | 1979-10-12 | 1982-01-26 | Rca Corporation | Track error correction system as for video disc player |
| JPS5693159A (en) * | 1979-12-25 | 1981-07-28 | Sony Corp | Error correcting system for advance data |
| JPS57125589A (en) * | 1981-01-29 | 1982-08-04 | Hoei:Kk | Readout circuit for video signal multiplex code |
| GB2155683B (en) * | 1984-02-10 | 1987-11-11 | Pioneer Electronic Corp | Video tape recording |
| GB2200493B (en) * | 1987-01-29 | 1991-06-19 | Tape Automation Ltd | Improved production of pre-recorded tape cassettes |
| GB8701983D0 (en) * | 1987-01-29 | 1987-03-04 | Tape Automation Ltd | Pre-recorded tape cassettes |
| DE3886556T2 (en) * | 1987-01-29 | 1994-04-21 | Sony Magnescale Inc | Manufacture of pre-recorded tape cassettes. |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| BE757737A (en) * | 1969-10-27 | 1971-04-01 | Ampex | NEW MODE OF INFORMATION RECORDING |
| JPS5348053B2 (en) * | 1972-12-01 | 1978-12-26 | ||
| US3890638A (en) * | 1973-08-22 | 1975-06-17 | Cmx Systems | Color phase matching system for magnetic video tape recordings |
-
1976
- 1976-10-27 JP JP12899176A patent/JPS5353916A/en active Granted
-
1977
- 1977-10-24 AU AU29978/77A patent/AU511726B2/en not_active Expired
- 1977-10-24 AT AT758577A patent/AT376537B/en not_active IP Right Cessation
- 1977-10-24 CA CA000289309A patent/CA1117211A/en not_active Expired
- 1977-10-26 DK DK476177A patent/DK158694C/en not_active IP Right Cessation
- 1977-10-26 GB GB4457077A patent/GB1566177A/en not_active Expired
- 1977-10-27 FR FR7732518A patent/FR2369762A1/en active Granted
- 1977-10-27 IT IT2906677A patent/IT1088613B/en active
- 1977-10-27 SE SE7712096A patent/SE419278B/en not_active IP Right Cessation
- 1977-10-27 NL NL7711844A patent/NL7711844A/en not_active Application Discontinuation
- 1977-10-27 DE DE19772748233 patent/DE2748233C2/en not_active Expired
-
1987
- 1987-05-01 DK DK224487A patent/DK224487A/en unknown
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4734764A (en) * | 1985-04-29 | 1988-03-29 | Cableshare, Inc. | Cable television system selectively distributing pre-recorded video and audio messages |
Also Published As
| Publication number | Publication date |
|---|---|
| DE2748233A1 (en) | 1978-05-03 |
| AU2997877A (en) | 1979-05-03 |
| IT1088613B (en) | 1985-06-10 |
| AU511726B2 (en) | 1980-09-04 |
| DE2748233C2 (en) | 1985-02-28 |
| ATA758577A (en) | 1984-04-15 |
| DK158694C (en) | 1991-02-25 |
| AT376537B (en) | 1984-11-26 |
| DK158694B (en) | 1990-07-02 |
| GB1566177A (en) | 1980-04-30 |
| JPS6215946B2 (en) | 1987-04-09 |
| JPS5353916A (en) | 1978-05-16 |
| DK476177A (en) | 1978-04-28 |
| FR2369762B1 (en) | 1980-05-16 |
| SE7712096L (en) | 1978-04-28 |
| SE419278B (en) | 1981-07-20 |
| DK224487D0 (en) | 1987-05-01 |
| NL7711844A (en) | 1978-05-02 |
| FR2369762A1 (en) | 1978-05-26 |
| DK224487A (en) | 1987-05-01 |
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