CA1118843A - Cardiac monitoring apparatus - Google Patents
Cardiac monitoring apparatusInfo
- Publication number
- CA1118843A CA1118843A CA000328142A CA328142A CA1118843A CA 1118843 A CA1118843 A CA 1118843A CA 000328142 A CA000328142 A CA 000328142A CA 328142 A CA328142 A CA 328142A CA 1118843 A CA1118843 A CA 1118843A
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- Prior art keywords
- signal
- voltage
- counter
- rate
- count
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Classifications
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- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
- A61B5/00—Measuring for diagnostic purposes; Identification of persons
- A61B5/24—Detecting, measuring or recording bioelectric or biomagnetic signals of the body or parts thereof
- A61B5/316—Modalities, i.e. specific diagnostic methods
- A61B5/318—Heart-related electrical modalities, e.g. electrocardiography [ECG]
- A61B5/332—Portable devices specially adapted therefor
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- Health & Medical Sciences (AREA)
- Life Sciences & Earth Sciences (AREA)
- Heart & Thoracic Surgery (AREA)
- Medical Informatics (AREA)
- Biophysics (AREA)
- Pathology (AREA)
- Engineering & Computer Science (AREA)
- Biomedical Technology (AREA)
- Cardiology (AREA)
- Physics & Mathematics (AREA)
- Molecular Biology (AREA)
- Surgery (AREA)
- Animal Behavior & Ethology (AREA)
- General Health & Medical Sciences (AREA)
- Public Health (AREA)
- Veterinary Medicine (AREA)
- Measuring Pulse, Heart Rate, Blood Pressure Or Blood Flow (AREA)
- Measuring Frequencies, Analyzing Spectra (AREA)
Abstract
Abstract of the Disclosure There is disclosed herein a wristwatch size cardiac monitoring apparatus which is worn on the wrist of one arm. A conductive material housing acts as one electrode when held firmly in contact with the wrist of the arm on which it is worn. A finger of the other limb is placed on a receiving electrode of the casing which acts as the second electrode.
Together, these two electrodes provide a Lead I electrocardiac signal to electronics within the housing. The second electrode consists of a metal layer on which is placed a dielectric material and when the finger is placed on top of the dielectric material, a capacitor is formed and the electric signal on the finger is transferred to the metal layer. Additional-ly, there is described circuitry which is used to operate the rate monitor.
The circuitry includes means for detecting a QRS complex and for causing a count in beats per minute to be displayed, manifesting the heartbeat rate.
The circuitry includes means for updating the heartbeat rate displayed every two seconds and for automatically turning the system off when no heart-beats are detected for a six second interval.
Together, these two electrodes provide a Lead I electrocardiac signal to electronics within the housing. The second electrode consists of a metal layer on which is placed a dielectric material and when the finger is placed on top of the dielectric material, a capacitor is formed and the electric signal on the finger is transferred to the metal layer. Additional-ly, there is described circuitry which is used to operate the rate monitor.
The circuitry includes means for detecting a QRS complex and for causing a count in beats per minute to be displayed, manifesting the heartbeat rate.
The circuitry includes means for updating the heartbeat rate displayed every two seconds and for automatically turning the system off when no heart-beats are detected for a six second interval.
Description
This invention relates to portable cardiac monitoring apparatus and, more particularly, to such apparatus adapted to be worn on the wrist of a user in which the back of the watch casing constitutes one input electrode and an electrode insulated from the casing placed on the front of the watch constitutes a second electrode, whereby a Lead I EKG signal can be deri~ed.
In the prior art there exists a number of devices which are capable of being worn on the wrist of a user and monitoring his heartbeat rate. These devices fall into two classifications. One monitors the pulse rate of the wearer by either an acoustical, optical or pressure-sensitive transducer. The other type of unit is connected to skin electrodes which are attached to the person's body and monitors the electro-cardiac signal to determine the heartbeat rate. This invention relates to the latter type o~ device, that is, the one which monitors the elec-trocardiac (EKG) ~ signal and determines the heartbeat rate therefrom.
The problem with the EKG signal monitoring type devices has always been that it is necessary to provide wires ~rom the device to electrodes attached to an appropriate point, generally on the chest, of the person using the device in oxder to derive the EXG
signal. These wires and electrodes are a majox cause o~ ~ailure in the proper operation of the devices.
In the prior art there exists a number of devices which are capable of being worn on the wrist of a user and monitoring his heartbeat rate. These devices fall into two classifications. One monitors the pulse rate of the wearer by either an acoustical, optical or pressure-sensitive transducer. The other type of unit is connected to skin electrodes which are attached to the person's body and monitors the electro-cardiac signal to determine the heartbeat rate. This invention relates to the latter type o~ device, that is, the one which monitors the elec-trocardiac (EKG) ~ signal and determines the heartbeat rate therefrom.
The problem with the EKG signal monitoring type devices has always been that it is necessary to provide wires ~rom the device to electrodes attached to an appropriate point, generally on the chest, of the person using the device in oxder to derive the EXG
signal. These wires and electrodes are a majox cause o~ ~ailure in the proper operation of the devices.
- 2 -Problems generally associated wi-th the wire electrodes are that they dis-loclge~ the conductive jelly used to attach the electrodes cLries out, -thereby causing inadequate or extremely noisy signals to be applied to the monitoring de~ice, or the wires themselves break. One type of device which eliminates the need -Eor the wires is described in Canadian Patent Number 1,088,63~ issued October 28, 1980 in the name of John M. Adams, which patent is assigned to the present assignee hereof. In the Adams patent two embodiments are shown for eliminating the need for the wires. The first enlbodiment utilizes a wristband, such as a commercially available expansion band utilized with a common wristwatch, on the two wrists of the user.
~hen it is desired to take a cardiac rate, the user ~erely places the bands together so as to derive an EKG signal taken between the two arms, or in other words, a Lead I EKG signal. In the second embodiment the user merely grasps two electrodes on the sides of the watch, which side electrodes are in~sulated from the band or casing. In this manner the two side electrodes upon pressure being applied from the fingers detect a Lead I EKG signal.
Problems have been encountered in attempting to derive signals from a per-centage o~ the population with the above described Adams device because of poor pickup, which has been found to exist in the case of the metal receiv-ing electrodes described therein. In addition, the placement of the sideelectrodes is cumbersome and would be better placed on the face of the monitor.
, ,~
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r.-f, One type of cardiac signal detecting electrode which has been described in the prior art utilizes a capacitive input to receive the electric skin signals. Such capacitive electrodes include a metal material on to which is attached a dielectric material, adapted to be placed in physical contact with the body. When so placed, the body acts as one plate and the metal material as the second plate o e a capacitor. The EKG signal on the skin is thus passed to the metal material from where it can be easily applied to the electric circuits. ~or a more detailed description of swch an elec~rode re~erence should be made to the textbook entitled "Biomedical Electrode Technology Theory and Practice", edited by Harry A.
Miller and Donald C. ~larrison, Academic Press, Inc. 1974, and specifically Section 1 therein entitled "Material Sciences", Chairman Allan Pin]cerson, M.D. The devices described in this reference relate to electrodes designed to be utilized as permanent fixtures attached to the body, such as are commonly used with electrocardiograph machines and with the prior art wrist-watch size portable EKG rate monitors.
Other problems which exist in prior art wristwatch size cardiac rate monitors are found in the circuitry for processing the detected cardiac signals. Typical of the circuits of these devices is the one described in the above-referenced Adams patent. These include counting the number of pulses over a defined time interval of, for instance, six seconds and then displaying ten times the number counted during the s:ix second interval so that the displayed count is in , ;~
beat per minute t~rms. This type o~ displaying system is accurate to o-nly the tens significant digit; thus, a person with a heartbeat rate of 77 beats per minute may have a rate of either 70 or 80 displayed. Also, with this type of circuitry, it is difficult to continually update a preexisting average rate with ne~ data so that one is displaying an average rate over a period of time rather than the number of beats during a six second time interval.
Another feature which is not shown or described in the prior art is circuitry for automatically turning off the rate monitor whenever no beats are detected for a certain time. Typically, the monitor must be manually turned off by the depression of a switch means. In many instances, the user ma~ forget to operate the switch to turn off the device, and thus the device continues drawing current from the battery powering it. This, of course, causes the battery to become depleted and the device to then be inoperative until such time as a new battery may be inserted.
In accordance ~ith one broad aspect of this invention there is provided circui~. means for a cardiac rate monitoring circuit comprising:
~ eans for detecting a signal manifesting a heartbeat in response to an electrocardiac signal applied thereto;
means responsive to the rate of said detected signals for pro-viding a voltage related to said rate;
integrating means for integrating said voltage and providing first and second control signals as said integrated signal increases beyond r~spective first and second magnitude;
counter means for being reset by said first signal to count from an initial value and to provide a signal manifesting said heart rate as re-lated to the count therein upon the occurrence of sal~ second signal;
~herein said counter counts to a certain count above ths co~mt theroin at the time said second control signal is provided; and ~herein said circuit means ~urther includes means responsive to said counter reaching said certain count for resetting said integrating means.
A preferred embodiment of the presen-t invention is hereafter described with specific reference being made to the following FIGURES, in which:
FIGU~E 1 shows a rate monitor in accordance with the present invention;
FIGURE 2 is an exploded view from one direction of the various components assembled to form the portion other ~han the band of the rate monitor shown in FIGURE l;
FIGURE 3 is an exploded view from the other side of selected ~, clcments in FIGURE. 2;
FIGURES 4A, 4B and 4C rcspectively show, in cross sect:ion~ three different methods taken across Line 4-4 o$ PIGURE 2, three different ~eceiving electrodes; and l'IGURE 5 is a schematic electrical diagram showing the electrical circuit used with the rate monitor of this invention.
FIGURES 3, 4A, 'IB and 4C appear on the same sheet of drawings as PIGURE 1.
Re.t`erring now to FIGURE 1, wrist rate monitor 10 is shown and includes a casing 12 which may be o~ a conductive material such as stainl~ss steel having a faceplate 14, ~hich may be o.~ a material such as -6a-t mineral glass that is silkscreened with a paint on the rear surface, and inserted therein. Faceplate 14 has in-serted therein an electrode 16 which will be described in more detail with respect to FIGURES 4A, 4B and 4C. In addition, on faceplate 14 there is a clear opening for a display 18, such as commercially available liquid crystal displays or light emitting diode disp:Lays. Housing 12 also includes an on-off switch 20 which is to be depressed and spring released each time it is desirous to turn on rate monitor 10~ Finally, rate monitor 10 includes~a conventional expansion watchband 22 attached in a manner similar to the way one is attached to a conventional wristwatch. The purpose of watchband 22 is to hold casing 12 firmly in contact with the wrist in order to get an electrical signal provided thereto as one part of a Lead I EKG signal.
As is well known in the art, a Lead I EKG
signal is a signal taken generally horizontally across the heart. This signal is conventionally derived by looking at the difference in signals taken between the two arms of the subject. Conventionally the signals are derived from the wrist area of the arm although they could be derived from any area, ~uch as the shoulders or the fingers. In monitor 10, the Lead I
EKG is taken between the wrist of one arm and a ~inger of the other arm b~ casing 12 being held by band 22 in contact with the wrist of one arm and the user placing a finger ~rom the other arm in aontact with electrode 16.
As will ~e described in more detail hereafter, electrode 16 is a capacitive type electrode which includes a layer of conductive material, such as silver, and a layer of dielectric material/ such as the Product Number 8289 manufactured by the DuPont Company of Wilmington, Delaware. The dielectric material is facing the outside of monitor 10 and covers th~ con-ductive material. Both of these materials may be attached to a ceramic substrate for physical s-trength and an electrical connection is provided between the conductive material and the electronic components within housing 12. When a finger is placed on the dielectric material of receiving means 16 a capacitor is formed with the finger being one plate and the conductive material being the second plate. The voltage and the skin of the finger is transferred through the dielectric material to the other plate of the capacitor and from there to the electrical components of the circuit, where the heart rate is determlned and ~o displayed on display 18.
Referring now to FIGURES 2 and 3, there is shown, in exploded view, monitor 10. Housing 12 which may b~ of a conductive material such as stainless steel, has a general shape oE a commercial wristwatch.
It includes a recess 2~ into which is placed rnineral glass 14. Mineral glass 14 may be sil~screened on the reverse side thereo~ with a paint to give it an appro-priately pleasing color. ~owever, an area 26 af mineral glass 14 is left clear in order that the display may be seen. In addition, an area 28 is etched in mineral glass 14 in order to receive electrode 16. Etch area 28 includes a hole 30 therein through glass 14 in order that electrical contact may be made with the conductive layer of electrode 16 and the remainder of the electronic circuitry. Electrode 16 is then placed in the etched area ~8 of glass 14. Housing 12 also has a hole 29 in alignment with hole 30 and a square opening 25 in -alignment with clear area 26.
In addition~ on-off switch 20, which is a conventional pushbutton momentary relay closing switch is attached to one side of casing 12.
Inserted into the rear portion of housing 12 is a plastic member 31 having a rectangular opening 32 therein wh.ich is in alignment with openings 25 and 26 through which the display element 18 is to be inserted.
In addition, a hole 34 is included in plastic member 30 which is in alignment with holes 29 and 30, through which a conductive rubber connector member 36 is placed so as to be in contact with the conductive layer of electrode 16.
Inserted next to member 31 is a plastic member 38 which holds the display member 18 in rectangular opening 39r which is in alignment with openings 25, 26 and 32. Electrical contact i5 prov.ided from the output pads on display 18 to component holder 40 through holes ~2 and 44 in element 38 by the use o~ two xebra connector devices 46 and 48. These devices ar~ well known in the art and consist of alternating çonductor insulator layers such that conduction is provided in the vertical d.irection shown in FIGU~E 2 rom pads on the bottom end of display member 18 to corresponding ~ g _ pads on component holder 40. In addition, there is provided a hole 49 in alignrnent with holes 29, 30 and 34 through which conductive rubber member 49 fits to electrically connect the conductive layer of electrode 16 to a pad on component holder 40.
Component holder 40 may be a cer~nic element of an appropriate shape to fit behind component holder 38 and contains a variety of electrical components which have only been generally drawn in for illustrative purposes. It should be noted that the electrical pads on component holder 40 must be positioned to be in alignrnent with the pads of display 18. Also a pad must be provided which makes contact with conductive rubber member 36. On the other side of component holder 40 will be other components. Another plastic member 50 is placed in physical contact with component holder 40.
Two batteries 52 and 54 ara then placed in battery holder 55, which includes a pair o~ holes 56 and 58, in member 50. Batteries 5~ and 54 are eleckrically connected to component holder 40 by conductive rubber members 60 and 62 inserted through holes 56 and 58. Finally, a plate 63 of a highly conductive material, such as stainless steell is po~itioned on the back of housing 12 to hold all oE the cornponents within housing 12, and to elec-trically connect the positive termlnal oE battery 54 to the r~egative terminal of batter~ 52. Plate 64, so connected is at a point of reference potential, such as system ground, and acts as one of the two electrodes oE monitor 10.
Referring now to FIGURES 4A, 4B and 4C, there is shown three different embodiments for electrode 16.
In Fiaure 4A/ a substrate 64 has been dipped in a metal material, such as silver, to be entirely encased by a conductive layer such as palladium/silver. There is sputtered by conventional sputtering techniques~ a layer of a dielectric material #4520, which may be pur-chased from the Electro-Science Laboratories, Inc., (hereinafter ELS 4520) on top of conductive layer 66.
When a finger is placed on top of layer 68 a capacitor is formed with conductive material 66 being one plate and the finger being the second plate of the capacitor and layer 68 being the dielectric material between the two plates. The electric sigrlals from the heart appear-ing on the s~in of the finger are transferred through dielectric material 68 to plate 66~
Referring again to FIGURE 2, the conductive rubber member 36 is in firm compressed contact wîth the bottom portion of conductive material 66 when plate 63 is fit into casing 12 to provide an electric path from the plate formed of material 66 oE the capacitor to the remaining portion o~ the electric circuitry on member 40 and shown schematically in FIGURE 5.
In FIGURE 4B a ~ubstrate 70 is provided with a hole 72 therethrough. Placed on top of member 70 and through the hole 72 is a conductive layer 74 which may be silver m2tal. Again a dielec~ric material layer 76 is sputtered on top of layer 74. The operation of the electrode shown in FIGURE 4B is the same as that shown in FIGURE 4A, except that conductive rubbex member 36 is compressed against the bottom of hole 72 which has been filled with the silver conductive material.
Referring now to FIGURE 4C, a third type of electrode 16 is shown, which includes a substrate 78 of ceramis material which has had affixed thereto a layer 80 of a conductive material such ~s silver. Conductive layer 80 is continued, a~ least as a strip around the side to cover a portion of the bottom of substrate 78.
Substrate 78 is then positioned so that conductive rubber member 36 makes contact therewith. Applied over the top of layer 80 is a dielectric material 82 o the same type previously described. Again, the operation of ~IGURE 4C is identical to that described with respect to FIGURE 4A.
Referring now to ~IGURE 5, there is shown an electrical schematic diagram of the circuitry used in operating ~onitor 10. The input signals applied from finger electrode 16 and case 12 are applied to inputs o~ a preamp and filter circuit 100 which amplifies the approximately .S Mv signal received and filters out muscle noise and other electrical noi~e which may be superimposed on the detected EXG signal. Circuit 100 includes conventional preamp and filter circuits utilizing operational amplifiers with appropriate b.iasin~ and feedback. The biasing circui-ts may be reversed bias by a negative voltage signal applied to line 101 so that circuit 100 draws virtually no current during the time monitor 1~ is not in use.
- 12 ~
Characteristics o~ the filter portion of the circuit are a center frequency of approximately 20 Hz and a center frequency gain of approximately 3.6. The band pass filter reduces muscle artifact ahove and below the center frequency and in addition reduces 60 Hz inter-erence.
The output from the preamp and filter circuit 100 is applied to a conventional cardiac signal detecting amplifier. Such an amplifier may be of a type conven-tionally used in a cardiac pacemaker. One such acceptable amplifier is described in U.S. Patent No. 4,059,116.
In addition to amplifying the signal, sense amplifier 102 provides other functions such as the rejection of continuous sine wave signals. The output pulse from sense amplifier 102 is a nega~ive-going 2 msec. wide pulse which is provided each time a QRS complex of ~he EKG signal is detected.
Following the provision of the output pulse from sense amplifier 102, sense amplifier 102 causes itself to be immune from receiving any subsequent signals for a period of approximately 300 msec. Th:is is similar to the reEractory period which is well known in the cardiac pacing sense amplifier art. The reason ~ox this, of course, is that the EK~ signal includes several other waves ~ollowing the QRS wave which should not be detected as addi~ional heartbeat waves.
The output oE sense ampliEier 102 is connected to one end of a capacitor 104, the other end of which is connected to the cathode end of a zener diode 106~
The anode end of diode 106 is connected to the gate of N channel junction field effect transistor 108.
The junction between capacitor 104 ~nd diode 106 is connected to one en~ of a resistor 110 and to the cathode end of a diode 112. The other end of resistor 110 and the anode end of diode 112 are connected together and to a source of negative voltage -V.
The main electrodes of transistor 108 are connected across a capacitor 114. One end of capacitor 114 is connected to point of reference voltage, such as ground, and the other end to capacitor 114 has applied thereto, over line 116, a constant current i~, which is provided from constant current source 118. Current source 118 may be a conventional voltage controlled constant current ~Qurce well known in the art. Current ic may be selected to be 100 nAmp and the controlling voltage may be 1.2 volts above the lowest battery voltage -V.
The junction between transistor 108, capacitor 114 and line 116 is connected to one of the main electrodes of an N channel junction field ePfect transistor 120.
The other main electrode of transistor 120 is connected to one end of a capacitor 122, the other end of which is oonnected to ground. The output ~rom sense ampliier 102 is connected through an inverter 124 and the cathode-anode path of a zener diode 126 to the base of transistor 120.
~he opera~ion of this portion oP FIGURE S
is described herea~tar. Between the time successive Q~S complexes oE the EKG signal are detected, capacitor 114 is charging up and storing an increasing voltage due to the application thereto of current ic over line 116~ When a QRS complex of the EKG signal is detected, ' ' , ' ' . , the output of sense amplifier 102 goes to a volta~e approxima-tely equal to -V volts ~rom a voltage pre-viously at approximately ground. When this happens, transistor 120 is rendered conductive by the output from sense amplifier 102 through inverter 124 and the zener diode 126. This condition remains for the 2 msec. during which the pulse from sense amplifier 102 i5 provided. During this time, the voltage on capacitor 114 ls applied through transistor 120 to capacitor 122.
After this occurs a number of times, the voltage across capacitor 122 will manifest the average value of the rate of ~he heartbeat.
During the 2 msec. time that a pulse is provided at the output of operational amplifier 102, capacitor 104 charges up through diode 112 because the side of capacitor 104 remote from amplifier 102 was forced towards -2V. After the end of the pulse from the ampli~ier 102, the voltage at the end of capacitor 104 remote from amplifier 102 will be sufficient to turn on transistor 108. This condition will remain for approximately 2 msec., which is the time determined by the chaxge of capacitor 104 through resistor 110.
While transistor 108 is turned on~ capacitor 114 discharges through transis-tor 108 to ground. AEter transistor 108 is turned o~ by capacitor 104 charging suf~iciently, capacitor 11~ again begins chargin~ due to the current ic on line 116.
The junction of transistor 120 and capacitor 122 is applied to the noninverting input of an operational amplifier 128. Operational amplifier 128 additionally has applied thereto a source of bias voltage through resistor 130. The output of operational ampli~ier 128 is connected through serially connected capacitors 132 and 134 to the inverting input of opqrational amplifier 128. Capacitors 132 and 134 are oppositely poled polarized capacitors in order to have the effect of a single nonpolarized capacitor. The junction between capacitor 134 and the noninverting input of amplifier 128 is connected through resistor 136 to ground. In addition, that junction is also connected through resistor 138 and the main electrodes of N channel junction field effect transistor 140 to source of positive voltage +V.
Connected in this manner, operational ampli-fier 120, capacitors 132 and 134 ~nd resistor 136 form an integrating circuit. Thus, the output from amplifier 128 is a ramp voltage, which is the integral of the voltage appearing across capacitor 122.
The output of amplifier 128 is connected to the noninverting inputs of operational amplifiers 142 and 144. Each of amplifiers 142 and 144 have a biased voltage applied thereto through respective resistors 146 and 148. The inverting input of amplifier 142 is connected to a source of low re~erence voltage -VR
volts and the inverting input o~ amplifier 144 is connected to a source oE high re~erence voltage +VR
volts. Each of these volkages -VR and ~VR are provided from voltage reference source 150, which also provides ~ control voltage ko current source 118 over line 151.
The relative value of reference voltage -VR is greater than the voltage at which operational amplifier 128 provides voltage immediately after reset. In addition, the relative value of voltage +VR is less than the maximum magni~ude reached by the voltage ramp provided from operational amplifier 128. The control voltage to current source 118 e~uals and tracks the absolute difference between +VR and -VR.
The output from operational amplifier 142 is provided to one input of the two input NAND gate 152.
The other input of NAND gate 152 is a signal which is high during normal operation of the circuit, but after automatic shutdown becomes low to thereby disable the passage of any signals through gate 152. The output of gate 152 is applied to the master reset (MR) of a three-digit binary coded decimal (BCD~ counter 154.
Whenever the output of gate 152 goes to a logic l-o-l or ~' low level, counter 154 is enabled to count the pulses applied to the clock (CLK) input thereof.
The output from operational amplifier 144 is applied through inverter 156 to the latch enable (LE) input of counter 154. A single negative going pulse signal applied to the latch enable input of counter 154 causes signals to appear on the output lines 158 of counter 154l which signals mani~ests the count of counter 154 at the time the signal was applied through lnverter 156 to the latch enable input. The signals on lines 158 continue to appear until another signal is applied to the latch ena,ble input of counter 154. Lines 158 are applied to corresponding inputs o~ a binary coded decimal (BCD) to seven segment converter and driver circuit 160, which in turn supplies signals on lines 162 to a liquid crystal display 164. In this manner, the counter which was latched in counter 154 by the sig~al through inverter 156 is converted and displayed at display 164. As will be explained in detail hereafter t this count is equal to the beat per minute heartbeat rate of the person utilizing rate monitor 10.
Counter 154 continues counting after a signal is applied to the latch enable input thereof, until it reaches a full count. The frequency of the clock pro-viding the clock signals, the clock input of counter 154 and the maximum count of counter 154 are preselected so that counter 154 reaches a full count a~ter a preselected update time, which may be approximately two seconds. For instance, the frequency o~ the clock signal may be 500 Hz and the maximum count of counter lS4 may be 1000. When counter 154 reaches a full count, a signal appears at the overflow (OF) output : thereof. This siynal is applied to the base o~ transistor 140 to render it conductive. This causes a high voltage to be applied to the inverting input of operational amplifier 128, which in turn causes the output thereof to go low~
When the OY signal is removed, transis~tor 140 turns off and capacitors 132 and 134 begin charging, thereby raising the voltage at the inverting input o amplifier lZ8 causing the voltage at iks output to begin increasing in a linear xamp Pashion.
During the time when th~ voltage at the output of operational ampli~ier 128 is more positive than -VR volts, the output of operational ampliPier 142 is high and thus the output from gate 152 is low. During this period oE time, counter 154 remains in the overflow condition because the overflow output is additionally provided to one input of NOR gate 166. The other input of NOR gate 166 has applied thereto the output from oscillator 168 which provides pulses at a frequency of 500 Hz when enabled by a signal on the enable input thereof. The output o~ NOR gate 166 is provided to inverter 170 to the clock input of counter 154. Whenever counter 154 goes to the overflow state, NOR gate 166 is blocked from passing the oscillator pulses and counter 154 remains in the overflow stage until reset by a high signal applied to the master reset input.
As the voltage at the output of integrator ampli-fier 128 decreases below the -VR value, the output of amplifier 142 changes states, thereby causing the output of NAND gate 152 to become positive. This low-to-high swing at the output of NAND gate 152 causes counter 154 to be reset to a low count, thereby removing the signal from the over-flow output thereof. This, in turn, removes the inhibition at gate 166 and clock pulses are again applied to counter 154. However, counter 154 cannot count upward because of the high signal applied to its reset input. As the voltage at the output of integrator amplifier 128 increases above the -VR value, the output of amplifier 142 changes state, thereby causing the output of NAND gate 152 to become low~ This will remove the reset condition o~ counter 154, so it begins to count upwards.
As the output oE amplifier 128 goes above ~VR
volts~ the OlltpUt of amplifier 14~ changes states, as does the output at inverter 156 and the latch enab~e input of counter 154 again causes the signal to be latched to the output lines 158. This continues such that appro~imately every two seconds, the output lines 158 receive a new reading o~ the heartbeat.
a;~
As previously explained, the voltage on capacitor 122 is inversely pro~ortional to the rate at which heart-beats are detected by sense amplifier 102. This voltage acts as a reference input to integrator 128 and as it varies the slope of the ramp voltage at the output of amplifier 128 also varies. Thus, the greater the heart rate, the less the voltage will be across the capacitor 122 and the smaller the slope will be of the ramp voltage at the output of amplifier 128. With a small slope, the time for the voltage to increase from -VR to ~VR
will be longer and hence the count in counter 154 will increase, manifesting the increased heart rate. In the case of a decreased rate, the time capacitor 114 is charged is longer and hence it will charge to a greater value. Hence, the voltage on capacitor 122 will be at a greater value and the slope of the ramp provided at the output of amplifier 128 will be greater. Thus, the time for the voltage to increase from -VR to +VR will be less and the count in counter }54 will be smaller, manifesting the decreased heart rate.
~ y proper selection of component values for resistor 136, capacitors 114, 132 and~l34, voltages +VR and -VR and the frequency fo of oscillator 168, th~ heart rate in beats per minute for a time TSA between successive heartbeats can be directly displayed according to the following conver~ion formula:
1 . R136 C114 ~C132 ~ C134) ~ R-~-~R)) CO~NT ' T - -- ~---SA ic C132 C
In the above formula, it should be recalled that the control voltage applied from voltage regulator lS0 over line 151 to control current ic from current source 18 is equal to and tracks the absolute difference between +VR and -VR. Hence, one utilizes the expression (+VR-(-VR)) in place of the control voltaye for ic in selecting the variables.
In order to make utilization of this equation, resis-tor 136 should be of a type which can be functionally trimmed during the manufacturing process from approximately 250 Kohms to a desired value of approximately 413 Kohm to compensate for othar circuit parameter variables. The 413 Kohm value for resistor 136 assumes fo to be 500 Hz, capacitors 114, 132 and 134 to each be .22 microfarads, (+VR-(-VR)3 ~o be 1.2 volts and ic to be 100 nanoamps.
~ he over10w output from counter 154 is additionally applied to the clock (C~ inpu~ of two three-stage shift register circuits 172 and 174. In addition, each of shift registers 172 and 174 have a data : (D) input and a reset (R) input and a Q output. Each time a signal is applied to the clock input of one of ~0 shift registers 172 and 174, the signal appearing at the data input is stored in the first stage thereof, the signal previously in the first stage is stored in the second stage and the signal previously stored in the second stage is stored in the third stage and appears as the ~ignal at th~ Q output of the shift register.
~he Q output from shit register 174 is coupled to the data (D) input of shiEt register 172 and additionally coupled to provide voltage to the BCD to seven segment converter and driver circuit 160. Until the Q output of shift register 174 goes high, there can be no display of a signal because no supply voltage is applied to BCD to seven segment convert~r and driver 160. The Q
output from shift register 172 is applied to the reset input of shift register 174 and, in addition, through inverter 176 to one input oE two input NAND gate 178.
The output of NAND gate 178 is applied to one input of two input N~ND gate 180, the output of which is applied back to the other input of NAND gate 178. The other input of NAND gate 180 receives a low, or logic "0", signal from inverter 182 each time the switch 20 of rate monitor 10 is momentarily depressed, thereby causing a high, or logic "1" signal to be provided to the input of inverter 182.
NAND gates 178 and 180 connected in a manner descri~ed constitute a conventionally set-reset latch circuit which becomes set whenever a low signal is applied from inverter 182 to gate 180 whereby the output of . gate 180 becomes high and the output of gate 178 to be low. The low output from gate 178 is fed back to the input of NAND gate 180 to maintain it at a high state.
Whenever a low signal is applied from the output of inverter 176, as a result of the Q output of shi.ft register 172 going high, the output of NAND gate 178 i5 forced high, thereby forcing the input of NAND gate 180 low.
Th.is, in turn, maintains the output of NAND gate 178 high.
The output from NANV gate 178 i.s applied to control the bias of ampliEier~ 128, 142 and 144. This is done by applying the output from NAND gate 178 through respective resistors 130, 146 and 148. When the output of NAND gate 178 goes low, the amplifiers 128, 142 and 144 are allowed to operate. When the output of NAND gate 178 goes high, the biasing mechanisms within amplifiers 128, 142 ancl 144 are reverse biased and thus the amplifiers 128, 142 and 144 are shut down and draw negliyible current. This is provided in order to save power when the rate monitor is not being used.
In addition, the output from NAND gate 178 is coupled to line 101 to reverse bias the operational amplifiers included in preamp and filter circuit 100 in the same manner as just described with respect to amplifiers 128, 142 and 144.
The output from N~ND gate 180 is applied as the second input from two NAND gate 152 and enable NAND gate 152 to operate and pass signals to reset counter 154.
At the time of shutdown of the circuit shown in Figure 5, the output of NAND gate 180 goes low, which causes the output o NAND gate 152 to become high, thereby resettlng counter 154.
The output of NAND gate 1~0 is also applied as the data input of shift~register 174 and as one input to NAND gate la4. The other input of NAND gate 184 is the pulse provided at the output of sense amplifier 102.
Thus, as long as the circuit is powered up, that is, NAND
gate 180 is set and provides a high output, the output from NAND gate 184 will be high each time a pulse is de-tected, thereby resetting all the stages of shift register 172. In addition, the output of NAND gate 180 is applied to the enable input of oscillator 168 to enable it to pro-vide pulses ~o counter 154 through gates 166 and 170.
In opera~ion, the above described circuit com-ponents prevent a display from happening for six s~conds a~ter t~e switch 20 is depressec~ and signals be~in appear-ing at the input of amplifier 102. At the time switch 20 is closed, the output of gate 180 goes high, counter 154 begins counting and approximately two seconds later, the first signal appears at the overflow output therefrom.
. .
This shifts the high value -then appearing at the data input of shift register 174 into the first stag~. It also shifts a low value into the first stage of shift register 172. After two seconds, a second overflow signal appears and shifts high values into both the first and second stages of shift register 174. After the third two second period, all three of the stages of shift register 174 will contain high values and the Q output of shift register 174 becomes a high value. This provides voltage to enable BCD to seven segment converter and driver circuit 160 and to enable gate 152 to pass reset signals to counter 154. This initial six second period is required in order to enable capacitor 122 to stabilize to the voltage to which capacitor 114 is charged and to maintain its value.
If for some reason the user of the device re-moves his finger from electrode 10, heartbeats will stop being applied through circuit 100 and detected by ampli-fier 120. During the period when heartbeats were contin-ually detected, shift register 172 was continually reset by the output from gate 184 and -the Q output thereof never achieved a high state. However, with removal of an applied cardiac signal, shift register 172 will now begin shifting high values therethrough and six seconds later the Q output thereof will attain a high state. This high state will be inverted by inverter 176 and reset the latch consisting of flip-flops 178 and 180, -thereby causing the output of NAND gate 178 to go high and the output of NAND gate 180 to go low. When the output of NAND ga-te 178 goes high, the bias is removed and amplifiers and the circuit begins shutting down. Also at the time that shift register 172 goes high, shift register 174 is reset and power is re-moved from the BCD to seven segment driver 160.
A battery monitor circuit is also provided which monitors the battery voltage and provides a signal to the user whenever the ba-ttery begins wearing down. The battery monitor circuit additionally includes exclusive OR gates 1~8 and 190, each of which has two inputs and one output.
Coupled to one input of exclusive OR gate 188 is the output of sense amplifier 102 with the other input of exclusive OR
gate 188 coupled to a point of negative battery voltage -V.
The output of exclusive OR gate 188 is coupled to capacitor 192 and resistor 194 to the point of negative battery voltage -V. The junction of capacitor 192 and re istor 194 is coup-led to one input of exclusive OR gate 190. In addition, the output of battery monitor circuit 186 is coupled to that same input of gate 190. Battery monitor circuit 186 provides an open circuit as long as the ~attery voltage is above a proper level and a high signal whenever the battery voltage falls below that predetermined level. The other input o gate 190 is coupled to the back plane output of BCD to seven seg-ment converter and driver 160 and back plane input of display : 20 164. The output of exclusive OR gate 190 is coupled to the colon input of display 164. Whenever the output of exclu-sive OR gate 190 is high, the colon is eliminated and when-ever it is low, the colon is not eliminated.
Exclusive OR gate 188 and capacitor 192 and resis-tor 194 connected a8 such constitute a monostable multivi-brator which yenerates a pulse signal each time a signal is received from sense amplifier 1.02. This signal is passed through exclusive OR gate 190. Since the back plane output from converter and driver 160 is low and thus the colon is caused to blink each time a heartbeat is detected. The blinking of the colon indicates to the user that the battery is providing sufficie~t voltage for proper use.
In the event the battery monitor senses.a low voltage, the inpu-t to exclusive OR gate 190 from the battery monitor circuit 186 is forced high and thus the output of exclusive OR gate 190 is out of phase with the other input. This in turn maintains the colon in a continuous display state and thus indicates to the user that the battery should be changed.
In the ci.rcuit described above, the following component values are utilized:
capacitor 104: .001 microfarads diode 106: MZC 5~lA10 transistor 108: 2N4338 resistor 110: 2 Mohms diode 112: IN914 capacitor 114: .22 microfarads transistor 120: 2N4338 capacitor 122: .47 microarads inverter 124: MCC14572E
diode 126: MZC 5.lA10 amplifier 128: IC~8023C
resistor 130: 20 Mohms capacitor 132: .22 microfarads capacitor 134~ .22 microfarads resistor 136: approximately 250 Kohm (trimmed for requency conversion) resistor 138: 10 Kohms transistor 140: 2N4338 amplifier 142: ICL8023C
amplifier 144: ICL8023C
resistor 146: 1 Mohm resistor 148: 1 Mohm gate 152: MCC14011B
counter lS4: MCC14553B
inverter 156: MCC14572 converte.r and driver 160: DF411 display 164: MCL154 NO~ gak~ 166: MCC14572 ~ate 170: MCC14572 ~hi~t register 172: MCC14015B
shiEt register 174: MCC14015B
inver-ter 176: MC14572 gate 178: MCC14011B
gate 180: MCC14011B
gate 182: MCC14572 gate 184: MCC14011B
gate 188: MCC14070B
gate 190: MCC14070B
capacitor 192: 0.033 microfarads resistor 194: 20 Mohm ~V: 1.5 volts -~: ~1.5 ~olts +VR: ~.3 volts -VR: -.9 volts
~hen it is desired to take a cardiac rate, the user ~erely places the bands together so as to derive an EKG signal taken between the two arms, or in other words, a Lead I EKG signal. In the second embodiment the user merely grasps two electrodes on the sides of the watch, which side electrodes are in~sulated from the band or casing. In this manner the two side electrodes upon pressure being applied from the fingers detect a Lead I EKG signal.
Problems have been encountered in attempting to derive signals from a per-centage o~ the population with the above described Adams device because of poor pickup, which has been found to exist in the case of the metal receiv-ing electrodes described therein. In addition, the placement of the sideelectrodes is cumbersome and would be better placed on the face of the monitor.
, ,~
r :'S
r.-f, One type of cardiac signal detecting electrode which has been described in the prior art utilizes a capacitive input to receive the electric skin signals. Such capacitive electrodes include a metal material on to which is attached a dielectric material, adapted to be placed in physical contact with the body. When so placed, the body acts as one plate and the metal material as the second plate o e a capacitor. The EKG signal on the skin is thus passed to the metal material from where it can be easily applied to the electric circuits. ~or a more detailed description of swch an elec~rode re~erence should be made to the textbook entitled "Biomedical Electrode Technology Theory and Practice", edited by Harry A.
Miller and Donald C. ~larrison, Academic Press, Inc. 1974, and specifically Section 1 therein entitled "Material Sciences", Chairman Allan Pin]cerson, M.D. The devices described in this reference relate to electrodes designed to be utilized as permanent fixtures attached to the body, such as are commonly used with electrocardiograph machines and with the prior art wrist-watch size portable EKG rate monitors.
Other problems which exist in prior art wristwatch size cardiac rate monitors are found in the circuitry for processing the detected cardiac signals. Typical of the circuits of these devices is the one described in the above-referenced Adams patent. These include counting the number of pulses over a defined time interval of, for instance, six seconds and then displaying ten times the number counted during the s:ix second interval so that the displayed count is in , ;~
beat per minute t~rms. This type o~ displaying system is accurate to o-nly the tens significant digit; thus, a person with a heartbeat rate of 77 beats per minute may have a rate of either 70 or 80 displayed. Also, with this type of circuitry, it is difficult to continually update a preexisting average rate with ne~ data so that one is displaying an average rate over a period of time rather than the number of beats during a six second time interval.
Another feature which is not shown or described in the prior art is circuitry for automatically turning off the rate monitor whenever no beats are detected for a certain time. Typically, the monitor must be manually turned off by the depression of a switch means. In many instances, the user ma~ forget to operate the switch to turn off the device, and thus the device continues drawing current from the battery powering it. This, of course, causes the battery to become depleted and the device to then be inoperative until such time as a new battery may be inserted.
In accordance ~ith one broad aspect of this invention there is provided circui~. means for a cardiac rate monitoring circuit comprising:
~ eans for detecting a signal manifesting a heartbeat in response to an electrocardiac signal applied thereto;
means responsive to the rate of said detected signals for pro-viding a voltage related to said rate;
integrating means for integrating said voltage and providing first and second control signals as said integrated signal increases beyond r~spective first and second magnitude;
counter means for being reset by said first signal to count from an initial value and to provide a signal manifesting said heart rate as re-lated to the count therein upon the occurrence of sal~ second signal;
~herein said counter counts to a certain count above ths co~mt theroin at the time said second control signal is provided; and ~herein said circuit means ~urther includes means responsive to said counter reaching said certain count for resetting said integrating means.
A preferred embodiment of the presen-t invention is hereafter described with specific reference being made to the following FIGURES, in which:
FIGU~E 1 shows a rate monitor in accordance with the present invention;
FIGURE 2 is an exploded view from one direction of the various components assembled to form the portion other ~han the band of the rate monitor shown in FIGURE l;
FIGURE 3 is an exploded view from the other side of selected ~, clcments in FIGURE. 2;
FIGURES 4A, 4B and 4C rcspectively show, in cross sect:ion~ three different methods taken across Line 4-4 o$ PIGURE 2, three different ~eceiving electrodes; and l'IGURE 5 is a schematic electrical diagram showing the electrical circuit used with the rate monitor of this invention.
FIGURES 3, 4A, 'IB and 4C appear on the same sheet of drawings as PIGURE 1.
Re.t`erring now to FIGURE 1, wrist rate monitor 10 is shown and includes a casing 12 which may be o~ a conductive material such as stainl~ss steel having a faceplate 14, ~hich may be o.~ a material such as -6a-t mineral glass that is silkscreened with a paint on the rear surface, and inserted therein. Faceplate 14 has in-serted therein an electrode 16 which will be described in more detail with respect to FIGURES 4A, 4B and 4C. In addition, on faceplate 14 there is a clear opening for a display 18, such as commercially available liquid crystal displays or light emitting diode disp:Lays. Housing 12 also includes an on-off switch 20 which is to be depressed and spring released each time it is desirous to turn on rate monitor 10~ Finally, rate monitor 10 includes~a conventional expansion watchband 22 attached in a manner similar to the way one is attached to a conventional wristwatch. The purpose of watchband 22 is to hold casing 12 firmly in contact with the wrist in order to get an electrical signal provided thereto as one part of a Lead I EKG signal.
As is well known in the art, a Lead I EKG
signal is a signal taken generally horizontally across the heart. This signal is conventionally derived by looking at the difference in signals taken between the two arms of the subject. Conventionally the signals are derived from the wrist area of the arm although they could be derived from any area, ~uch as the shoulders or the fingers. In monitor 10, the Lead I
EKG is taken between the wrist of one arm and a ~inger of the other arm b~ casing 12 being held by band 22 in contact with the wrist of one arm and the user placing a finger ~rom the other arm in aontact with electrode 16.
As will ~e described in more detail hereafter, electrode 16 is a capacitive type electrode which includes a layer of conductive material, such as silver, and a layer of dielectric material/ such as the Product Number 8289 manufactured by the DuPont Company of Wilmington, Delaware. The dielectric material is facing the outside of monitor 10 and covers th~ con-ductive material. Both of these materials may be attached to a ceramic substrate for physical s-trength and an electrical connection is provided between the conductive material and the electronic components within housing 12. When a finger is placed on the dielectric material of receiving means 16 a capacitor is formed with the finger being one plate and the conductive material being the second plate. The voltage and the skin of the finger is transferred through the dielectric material to the other plate of the capacitor and from there to the electrical components of the circuit, where the heart rate is determlned and ~o displayed on display 18.
Referring now to FIGURES 2 and 3, there is shown, in exploded view, monitor 10. Housing 12 which may b~ of a conductive material such as stainless steel, has a general shape oE a commercial wristwatch.
It includes a recess 2~ into which is placed rnineral glass 14. Mineral glass 14 may be sil~screened on the reverse side thereo~ with a paint to give it an appro-priately pleasing color. ~owever, an area 26 af mineral glass 14 is left clear in order that the display may be seen. In addition, an area 28 is etched in mineral glass 14 in order to receive electrode 16. Etch area 28 includes a hole 30 therein through glass 14 in order that electrical contact may be made with the conductive layer of electrode 16 and the remainder of the electronic circuitry. Electrode 16 is then placed in the etched area ~8 of glass 14. Housing 12 also has a hole 29 in alignment with hole 30 and a square opening 25 in -alignment with clear area 26.
In addition~ on-off switch 20, which is a conventional pushbutton momentary relay closing switch is attached to one side of casing 12.
Inserted into the rear portion of housing 12 is a plastic member 31 having a rectangular opening 32 therein wh.ich is in alignment with openings 25 and 26 through which the display element 18 is to be inserted.
In addition, a hole 34 is included in plastic member 30 which is in alignment with holes 29 and 30, through which a conductive rubber connector member 36 is placed so as to be in contact with the conductive layer of electrode 16.
Inserted next to member 31 is a plastic member 38 which holds the display member 18 in rectangular opening 39r which is in alignment with openings 25, 26 and 32. Electrical contact i5 prov.ided from the output pads on display 18 to component holder 40 through holes ~2 and 44 in element 38 by the use o~ two xebra connector devices 46 and 48. These devices ar~ well known in the art and consist of alternating çonductor insulator layers such that conduction is provided in the vertical d.irection shown in FIGU~E 2 rom pads on the bottom end of display member 18 to corresponding ~ g _ pads on component holder 40. In addition, there is provided a hole 49 in alignrnent with holes 29, 30 and 34 through which conductive rubber member 49 fits to electrically connect the conductive layer of electrode 16 to a pad on component holder 40.
Component holder 40 may be a cer~nic element of an appropriate shape to fit behind component holder 38 and contains a variety of electrical components which have only been generally drawn in for illustrative purposes. It should be noted that the electrical pads on component holder 40 must be positioned to be in alignrnent with the pads of display 18. Also a pad must be provided which makes contact with conductive rubber member 36. On the other side of component holder 40 will be other components. Another plastic member 50 is placed in physical contact with component holder 40.
Two batteries 52 and 54 ara then placed in battery holder 55, which includes a pair o~ holes 56 and 58, in member 50. Batteries 5~ and 54 are eleckrically connected to component holder 40 by conductive rubber members 60 and 62 inserted through holes 56 and 58. Finally, a plate 63 of a highly conductive material, such as stainless steell is po~itioned on the back of housing 12 to hold all oE the cornponents within housing 12, and to elec-trically connect the positive termlnal oE battery 54 to the r~egative terminal of batter~ 52. Plate 64, so connected is at a point of reference potential, such as system ground, and acts as one of the two electrodes oE monitor 10.
Referring now to FIGURES 4A, 4B and 4C, there is shown three different embodiments for electrode 16.
In Fiaure 4A/ a substrate 64 has been dipped in a metal material, such as silver, to be entirely encased by a conductive layer such as palladium/silver. There is sputtered by conventional sputtering techniques~ a layer of a dielectric material #4520, which may be pur-chased from the Electro-Science Laboratories, Inc., (hereinafter ELS 4520) on top of conductive layer 66.
When a finger is placed on top of layer 68 a capacitor is formed with conductive material 66 being one plate and the finger being the second plate of the capacitor and layer 68 being the dielectric material between the two plates. The electric sigrlals from the heart appear-ing on the s~in of the finger are transferred through dielectric material 68 to plate 66~
Referring again to FIGURE 2, the conductive rubber member 36 is in firm compressed contact wîth the bottom portion of conductive material 66 when plate 63 is fit into casing 12 to provide an electric path from the plate formed of material 66 oE the capacitor to the remaining portion o~ the electric circuitry on member 40 and shown schematically in FIGURE 5.
In FIGURE 4B a ~ubstrate 70 is provided with a hole 72 therethrough. Placed on top of member 70 and through the hole 72 is a conductive layer 74 which may be silver m2tal. Again a dielec~ric material layer 76 is sputtered on top of layer 74. The operation of the electrode shown in FIGURE 4B is the same as that shown in FIGURE 4A, except that conductive rubbex member 36 is compressed against the bottom of hole 72 which has been filled with the silver conductive material.
Referring now to FIGURE 4C, a third type of electrode 16 is shown, which includes a substrate 78 of ceramis material which has had affixed thereto a layer 80 of a conductive material such ~s silver. Conductive layer 80 is continued, a~ least as a strip around the side to cover a portion of the bottom of substrate 78.
Substrate 78 is then positioned so that conductive rubber member 36 makes contact therewith. Applied over the top of layer 80 is a dielectric material 82 o the same type previously described. Again, the operation of ~IGURE 4C is identical to that described with respect to FIGURE 4A.
Referring now to ~IGURE 5, there is shown an electrical schematic diagram of the circuitry used in operating ~onitor 10. The input signals applied from finger electrode 16 and case 12 are applied to inputs o~ a preamp and filter circuit 100 which amplifies the approximately .S Mv signal received and filters out muscle noise and other electrical noi~e which may be superimposed on the detected EXG signal. Circuit 100 includes conventional preamp and filter circuits utilizing operational amplifiers with appropriate b.iasin~ and feedback. The biasing circui-ts may be reversed bias by a negative voltage signal applied to line 101 so that circuit 100 draws virtually no current during the time monitor 1~ is not in use.
- 12 ~
Characteristics o~ the filter portion of the circuit are a center frequency of approximately 20 Hz and a center frequency gain of approximately 3.6. The band pass filter reduces muscle artifact ahove and below the center frequency and in addition reduces 60 Hz inter-erence.
The output from the preamp and filter circuit 100 is applied to a conventional cardiac signal detecting amplifier. Such an amplifier may be of a type conven-tionally used in a cardiac pacemaker. One such acceptable amplifier is described in U.S. Patent No. 4,059,116.
In addition to amplifying the signal, sense amplifier 102 provides other functions such as the rejection of continuous sine wave signals. The output pulse from sense amplifier 102 is a nega~ive-going 2 msec. wide pulse which is provided each time a QRS complex of ~he EKG signal is detected.
Following the provision of the output pulse from sense amplifier 102, sense amplifier 102 causes itself to be immune from receiving any subsequent signals for a period of approximately 300 msec. Th:is is similar to the reEractory period which is well known in the cardiac pacing sense amplifier art. The reason ~ox this, of course, is that the EK~ signal includes several other waves ~ollowing the QRS wave which should not be detected as addi~ional heartbeat waves.
The output oE sense ampliEier 102 is connected to one end of a capacitor 104, the other end of which is connected to the cathode end of a zener diode 106~
The anode end of diode 106 is connected to the gate of N channel junction field effect transistor 108.
The junction between capacitor 104 ~nd diode 106 is connected to one en~ of a resistor 110 and to the cathode end of a diode 112. The other end of resistor 110 and the anode end of diode 112 are connected together and to a source of negative voltage -V.
The main electrodes of transistor 108 are connected across a capacitor 114. One end of capacitor 114 is connected to point of reference voltage, such as ground, and the other end to capacitor 114 has applied thereto, over line 116, a constant current i~, which is provided from constant current source 118. Current source 118 may be a conventional voltage controlled constant current ~Qurce well known in the art. Current ic may be selected to be 100 nAmp and the controlling voltage may be 1.2 volts above the lowest battery voltage -V.
The junction between transistor 108, capacitor 114 and line 116 is connected to one of the main electrodes of an N channel junction field ePfect transistor 120.
The other main electrode of transistor 120 is connected to one end of a capacitor 122, the other end of which is oonnected to ground. The output ~rom sense ampliier 102 is connected through an inverter 124 and the cathode-anode path of a zener diode 126 to the base of transistor 120.
~he opera~ion of this portion oP FIGURE S
is described herea~tar. Between the time successive Q~S complexes oE the EKG signal are detected, capacitor 114 is charging up and storing an increasing voltage due to the application thereto of current ic over line 116~ When a QRS complex of the EKG signal is detected, ' ' , ' ' . , the output of sense amplifier 102 goes to a volta~e approxima-tely equal to -V volts ~rom a voltage pre-viously at approximately ground. When this happens, transistor 120 is rendered conductive by the output from sense amplifier 102 through inverter 124 and the zener diode 126. This condition remains for the 2 msec. during which the pulse from sense amplifier 102 i5 provided. During this time, the voltage on capacitor 114 ls applied through transistor 120 to capacitor 122.
After this occurs a number of times, the voltage across capacitor 122 will manifest the average value of the rate of ~he heartbeat.
During the 2 msec. time that a pulse is provided at the output of operational amplifier 102, capacitor 104 charges up through diode 112 because the side of capacitor 104 remote from amplifier 102 was forced towards -2V. After the end of the pulse from the ampli~ier 102, the voltage at the end of capacitor 104 remote from amplifier 102 will be sufficient to turn on transistor 108. This condition will remain for approximately 2 msec., which is the time determined by the chaxge of capacitor 104 through resistor 110.
While transistor 108 is turned on~ capacitor 114 discharges through transis-tor 108 to ground. AEter transistor 108 is turned o~ by capacitor 104 charging suf~iciently, capacitor 11~ again begins chargin~ due to the current ic on line 116.
The junction of transistor 120 and capacitor 122 is applied to the noninverting input of an operational amplifier 128. Operational amplifier 128 additionally has applied thereto a source of bias voltage through resistor 130. The output of operational ampli~ier 128 is connected through serially connected capacitors 132 and 134 to the inverting input of opqrational amplifier 128. Capacitors 132 and 134 are oppositely poled polarized capacitors in order to have the effect of a single nonpolarized capacitor. The junction between capacitor 134 and the noninverting input of amplifier 128 is connected through resistor 136 to ground. In addition, that junction is also connected through resistor 138 and the main electrodes of N channel junction field effect transistor 140 to source of positive voltage +V.
Connected in this manner, operational ampli-fier 120, capacitors 132 and 134 ~nd resistor 136 form an integrating circuit. Thus, the output from amplifier 128 is a ramp voltage, which is the integral of the voltage appearing across capacitor 122.
The output of amplifier 128 is connected to the noninverting inputs of operational amplifiers 142 and 144. Each of amplifiers 142 and 144 have a biased voltage applied thereto through respective resistors 146 and 148. The inverting input of amplifier 142 is connected to a source of low re~erence voltage -VR
volts and the inverting input o~ amplifier 144 is connected to a source oE high re~erence voltage +VR
volts. Each of these volkages -VR and ~VR are provided from voltage reference source 150, which also provides ~ control voltage ko current source 118 over line 151.
The relative value of reference voltage -VR is greater than the voltage at which operational amplifier 128 provides voltage immediately after reset. In addition, the relative value of voltage +VR is less than the maximum magni~ude reached by the voltage ramp provided from operational amplifier 128. The control voltage to current source 118 e~uals and tracks the absolute difference between +VR and -VR.
The output from operational amplifier 142 is provided to one input of the two input NAND gate 152.
The other input of NAND gate 152 is a signal which is high during normal operation of the circuit, but after automatic shutdown becomes low to thereby disable the passage of any signals through gate 152. The output of gate 152 is applied to the master reset (MR) of a three-digit binary coded decimal (BCD~ counter 154.
Whenever the output of gate 152 goes to a logic l-o-l or ~' low level, counter 154 is enabled to count the pulses applied to the clock (CLK) input thereof.
The output from operational amplifier 144 is applied through inverter 156 to the latch enable (LE) input of counter 154. A single negative going pulse signal applied to the latch enable input of counter 154 causes signals to appear on the output lines 158 of counter 154l which signals mani~ests the count of counter 154 at the time the signal was applied through lnverter 156 to the latch enable input. The signals on lines 158 continue to appear until another signal is applied to the latch ena,ble input of counter 154. Lines 158 are applied to corresponding inputs o~ a binary coded decimal (BCD) to seven segment converter and driver circuit 160, which in turn supplies signals on lines 162 to a liquid crystal display 164. In this manner, the counter which was latched in counter 154 by the sig~al through inverter 156 is converted and displayed at display 164. As will be explained in detail hereafter t this count is equal to the beat per minute heartbeat rate of the person utilizing rate monitor 10.
Counter 154 continues counting after a signal is applied to the latch enable input thereof, until it reaches a full count. The frequency of the clock pro-viding the clock signals, the clock input of counter 154 and the maximum count of counter 154 are preselected so that counter 154 reaches a full count a~ter a preselected update time, which may be approximately two seconds. For instance, the frequency o~ the clock signal may be 500 Hz and the maximum count of counter lS4 may be 1000. When counter 154 reaches a full count, a signal appears at the overflow (OF) output : thereof. This siynal is applied to the base o~ transistor 140 to render it conductive. This causes a high voltage to be applied to the inverting input of operational amplifier 128, which in turn causes the output thereof to go low~
When the OY signal is removed, transis~tor 140 turns off and capacitors 132 and 134 begin charging, thereby raising the voltage at the inverting input o amplifier lZ8 causing the voltage at iks output to begin increasing in a linear xamp Pashion.
During the time when th~ voltage at the output of operational ampli~ier 128 is more positive than -VR volts, the output of operational ampliPier 142 is high and thus the output from gate 152 is low. During this period oE time, counter 154 remains in the overflow condition because the overflow output is additionally provided to one input of NOR gate 166. The other input of NOR gate 166 has applied thereto the output from oscillator 168 which provides pulses at a frequency of 500 Hz when enabled by a signal on the enable input thereof. The output o~ NOR gate 166 is provided to inverter 170 to the clock input of counter 154. Whenever counter 154 goes to the overflow state, NOR gate 166 is blocked from passing the oscillator pulses and counter 154 remains in the overflow stage until reset by a high signal applied to the master reset input.
As the voltage at the output of integrator ampli-fier 128 decreases below the -VR value, the output of amplifier 142 changes states, thereby causing the output of NAND gate 152 to become positive. This low-to-high swing at the output of NAND gate 152 causes counter 154 to be reset to a low count, thereby removing the signal from the over-flow output thereof. This, in turn, removes the inhibition at gate 166 and clock pulses are again applied to counter 154. However, counter 154 cannot count upward because of the high signal applied to its reset input. As the voltage at the output of integrator amplifier 128 increases above the -VR value, the output of amplifier 142 changes state, thereby causing the output of NAND gate 152 to become low~ This will remove the reset condition o~ counter 154, so it begins to count upwards.
As the output oE amplifier 128 goes above ~VR
volts~ the OlltpUt of amplifier 14~ changes states, as does the output at inverter 156 and the latch enab~e input of counter 154 again causes the signal to be latched to the output lines 158. This continues such that appro~imately every two seconds, the output lines 158 receive a new reading o~ the heartbeat.
a;~
As previously explained, the voltage on capacitor 122 is inversely pro~ortional to the rate at which heart-beats are detected by sense amplifier 102. This voltage acts as a reference input to integrator 128 and as it varies the slope of the ramp voltage at the output of amplifier 128 also varies. Thus, the greater the heart rate, the less the voltage will be across the capacitor 122 and the smaller the slope will be of the ramp voltage at the output of amplifier 128. With a small slope, the time for the voltage to increase from -VR to ~VR
will be longer and hence the count in counter 154 will increase, manifesting the increased heart rate. In the case of a decreased rate, the time capacitor 114 is charged is longer and hence it will charge to a greater value. Hence, the voltage on capacitor 122 will be at a greater value and the slope of the ramp provided at the output of amplifier 128 will be greater. Thus, the time for the voltage to increase from -VR to +VR will be less and the count in counter }54 will be smaller, manifesting the decreased heart rate.
~ y proper selection of component values for resistor 136, capacitors 114, 132 and~l34, voltages +VR and -VR and the frequency fo of oscillator 168, th~ heart rate in beats per minute for a time TSA between successive heartbeats can be directly displayed according to the following conver~ion formula:
1 . R136 C114 ~C132 ~ C134) ~ R-~-~R)) CO~NT ' T - -- ~---SA ic C132 C
In the above formula, it should be recalled that the control voltage applied from voltage regulator lS0 over line 151 to control current ic from current source 18 is equal to and tracks the absolute difference between +VR and -VR. Hence, one utilizes the expression (+VR-(-VR)) in place of the control voltaye for ic in selecting the variables.
In order to make utilization of this equation, resis-tor 136 should be of a type which can be functionally trimmed during the manufacturing process from approximately 250 Kohms to a desired value of approximately 413 Kohm to compensate for othar circuit parameter variables. The 413 Kohm value for resistor 136 assumes fo to be 500 Hz, capacitors 114, 132 and 134 to each be .22 microfarads, (+VR-(-VR)3 ~o be 1.2 volts and ic to be 100 nanoamps.
~ he over10w output from counter 154 is additionally applied to the clock (C~ inpu~ of two three-stage shift register circuits 172 and 174. In addition, each of shift registers 172 and 174 have a data : (D) input and a reset (R) input and a Q output. Each time a signal is applied to the clock input of one of ~0 shift registers 172 and 174, the signal appearing at the data input is stored in the first stage thereof, the signal previously in the first stage is stored in the second stage and the signal previously stored in the second stage is stored in the third stage and appears as the ~ignal at th~ Q output of the shift register.
~he Q output from shit register 174 is coupled to the data (D) input of shiEt register 172 and additionally coupled to provide voltage to the BCD to seven segment converter and driver circuit 160. Until the Q output of shift register 174 goes high, there can be no display of a signal because no supply voltage is applied to BCD to seven segment convert~r and driver 160. The Q
output from shift register 172 is applied to the reset input of shift register 174 and, in addition, through inverter 176 to one input oE two input NAND gate 178.
The output of NAND gate 178 is applied to one input of two input N~ND gate 180, the output of which is applied back to the other input of NAND gate 178. The other input of NAND gate 180 receives a low, or logic "0", signal from inverter 182 each time the switch 20 of rate monitor 10 is momentarily depressed, thereby causing a high, or logic "1" signal to be provided to the input of inverter 182.
NAND gates 178 and 180 connected in a manner descri~ed constitute a conventionally set-reset latch circuit which becomes set whenever a low signal is applied from inverter 182 to gate 180 whereby the output of . gate 180 becomes high and the output of gate 178 to be low. The low output from gate 178 is fed back to the input of NAND gate 180 to maintain it at a high state.
Whenever a low signal is applied from the output of inverter 176, as a result of the Q output of shi.ft register 172 going high, the output of NAND gate 178 i5 forced high, thereby forcing the input of NAND gate 180 low.
Th.is, in turn, maintains the output of NAND gate 178 high.
The output from NANV gate 178 i.s applied to control the bias of ampliEier~ 128, 142 and 144. This is done by applying the output from NAND gate 178 through respective resistors 130, 146 and 148. When the output of NAND gate 178 goes low, the amplifiers 128, 142 and 144 are allowed to operate. When the output of NAND gate 178 goes high, the biasing mechanisms within amplifiers 128, 142 ancl 144 are reverse biased and thus the amplifiers 128, 142 and 144 are shut down and draw negliyible current. This is provided in order to save power when the rate monitor is not being used.
In addition, the output from NAND gate 178 is coupled to line 101 to reverse bias the operational amplifiers included in preamp and filter circuit 100 in the same manner as just described with respect to amplifiers 128, 142 and 144.
The output from N~ND gate 180 is applied as the second input from two NAND gate 152 and enable NAND gate 152 to operate and pass signals to reset counter 154.
At the time of shutdown of the circuit shown in Figure 5, the output of NAND gate 180 goes low, which causes the output o NAND gate 152 to become high, thereby resettlng counter 154.
The output of NAND gate 1~0 is also applied as the data input of shift~register 174 and as one input to NAND gate la4. The other input of NAND gate 184 is the pulse provided at the output of sense amplifier 102.
Thus, as long as the circuit is powered up, that is, NAND
gate 180 is set and provides a high output, the output from NAND gate 184 will be high each time a pulse is de-tected, thereby resetting all the stages of shift register 172. In addition, the output of NAND gate 180 is applied to the enable input of oscillator 168 to enable it to pro-vide pulses ~o counter 154 through gates 166 and 170.
In opera~ion, the above described circuit com-ponents prevent a display from happening for six s~conds a~ter t~e switch 20 is depressec~ and signals be~in appear-ing at the input of amplifier 102. At the time switch 20 is closed, the output of gate 180 goes high, counter 154 begins counting and approximately two seconds later, the first signal appears at the overflow output therefrom.
. .
This shifts the high value -then appearing at the data input of shift register 174 into the first stag~. It also shifts a low value into the first stage of shift register 172. After two seconds, a second overflow signal appears and shifts high values into both the first and second stages of shift register 174. After the third two second period, all three of the stages of shift register 174 will contain high values and the Q output of shift register 174 becomes a high value. This provides voltage to enable BCD to seven segment converter and driver circuit 160 and to enable gate 152 to pass reset signals to counter 154. This initial six second period is required in order to enable capacitor 122 to stabilize to the voltage to which capacitor 114 is charged and to maintain its value.
If for some reason the user of the device re-moves his finger from electrode 10, heartbeats will stop being applied through circuit 100 and detected by ampli-fier 120. During the period when heartbeats were contin-ually detected, shift register 172 was continually reset by the output from gate 184 and -the Q output thereof never achieved a high state. However, with removal of an applied cardiac signal, shift register 172 will now begin shifting high values therethrough and six seconds later the Q output thereof will attain a high state. This high state will be inverted by inverter 176 and reset the latch consisting of flip-flops 178 and 180, -thereby causing the output of NAND gate 178 to go high and the output of NAND gate 180 to go low. When the output of NAND ga-te 178 goes high, the bias is removed and amplifiers and the circuit begins shutting down. Also at the time that shift register 172 goes high, shift register 174 is reset and power is re-moved from the BCD to seven segment driver 160.
A battery monitor circuit is also provided which monitors the battery voltage and provides a signal to the user whenever the ba-ttery begins wearing down. The battery monitor circuit additionally includes exclusive OR gates 1~8 and 190, each of which has two inputs and one output.
Coupled to one input of exclusive OR gate 188 is the output of sense amplifier 102 with the other input of exclusive OR
gate 188 coupled to a point of negative battery voltage -V.
The output of exclusive OR gate 188 is coupled to capacitor 192 and resistor 194 to the point of negative battery voltage -V. The junction of capacitor 192 and re istor 194 is coup-led to one input of exclusive OR gate 190. In addition, the output of battery monitor circuit 186 is coupled to that same input of gate 190. Battery monitor circuit 186 provides an open circuit as long as the ~attery voltage is above a proper level and a high signal whenever the battery voltage falls below that predetermined level. The other input o gate 190 is coupled to the back plane output of BCD to seven seg-ment converter and driver 160 and back plane input of display : 20 164. The output of exclusive OR gate 190 is coupled to the colon input of display 164. Whenever the output of exclu-sive OR gate 190 is high, the colon is eliminated and when-ever it is low, the colon is not eliminated.
Exclusive OR gate 188 and capacitor 192 and resis-tor 194 connected a8 such constitute a monostable multivi-brator which yenerates a pulse signal each time a signal is received from sense amplifier 1.02. This signal is passed through exclusive OR gate 190. Since the back plane output from converter and driver 160 is low and thus the colon is caused to blink each time a heartbeat is detected. The blinking of the colon indicates to the user that the battery is providing sufficie~t voltage for proper use.
In the event the battery monitor senses.a low voltage, the inpu-t to exclusive OR gate 190 from the battery monitor circuit 186 is forced high and thus the output of exclusive OR gate 190 is out of phase with the other input. This in turn maintains the colon in a continuous display state and thus indicates to the user that the battery should be changed.
In the ci.rcuit described above, the following component values are utilized:
capacitor 104: .001 microfarads diode 106: MZC 5~lA10 transistor 108: 2N4338 resistor 110: 2 Mohms diode 112: IN914 capacitor 114: .22 microfarads transistor 120: 2N4338 capacitor 122: .47 microarads inverter 124: MCC14572E
diode 126: MZC 5.lA10 amplifier 128: IC~8023C
resistor 130: 20 Mohms capacitor 132: .22 microfarads capacitor 134~ .22 microfarads resistor 136: approximately 250 Kohm (trimmed for requency conversion) resistor 138: 10 Kohms transistor 140: 2N4338 amplifier 142: ICL8023C
amplifier 144: ICL8023C
resistor 146: 1 Mohm resistor 148: 1 Mohm gate 152: MCC14011B
counter lS4: MCC14553B
inverter 156: MCC14572 converte.r and driver 160: DF411 display 164: MCL154 NO~ gak~ 166: MCC14572 ~ate 170: MCC14572 ~hi~t register 172: MCC14015B
shiEt register 174: MCC14015B
inver-ter 176: MC14572 gate 178: MCC14011B
gate 180: MCC14011B
gate 182: MCC14572 gate 184: MCC14011B
gate 188: MCC14070B
gate 190: MCC14070B
capacitor 192: 0.033 microfarads resistor 194: 20 Mohm ~V: 1.5 volts -~: ~1.5 ~olts +VR: ~.3 volts -VR: -.9 volts
Claims (10)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. Circuit means for a cardiac rate monitoring circuit comprising:
means for detecting a signal manifesting a heartbeat in response to an electrocardiac signal applied thereto;
means responsive to the rate of said detected signals for pro-viding a voltage related to said rate;
integrating means for integrating said voltage and providing first and second control signals as said integrated signal increases beyond respec-tive first and second magnitude;
counter means for being reset by said first signal to count from an initial value and to provide a signal manifesting said heart rate as related to the count therein upon the occurrence of said second signal;
wherein said counter counts to a certain count above the count therein at the time said second control signal is provided; and wherein said circuit means further includes means responsive to said counter reaching said certain count for resetting said integrating means.
means for detecting a signal manifesting a heartbeat in response to an electrocardiac signal applied thereto;
means responsive to the rate of said detected signals for pro-viding a voltage related to said rate;
integrating means for integrating said voltage and providing first and second control signals as said integrated signal increases beyond respec-tive first and second magnitude;
counter means for being reset by said first signal to count from an initial value and to provide a signal manifesting said heart rate as related to the count therein upon the occurrence of said second signal;
wherein said counter counts to a certain count above the count therein at the time said second control signal is provided; and wherein said circuit means further includes means responsive to said counter reaching said certain count for resetting said integrating means.
2. The invention according to claim 1:
wherein said circuit means further includes clock means for pro-viding constant frequency clock signals to be counted to said counter means and wherein said circuit means further includes means for inhibiting the provision of said clock signals upon said counter reaching said certain count.
wherein said circuit means further includes clock means for pro-viding constant frequency clock signals to be counted to said counter means and wherein said circuit means further includes means for inhibiting the provision of said clock signals upon said counter reaching said certain count.
3. The invention according to claim 2 wherein said means for inhibi-ting the provision of said clock signals is operative until said first con-trol signal is provided by said integrating means.
4. Circuit means for a cardiac rate monitoring circuit comprising:
means for detecting a signal manifesting a heartbeat in response to an electrocardiac signal applied thereto;
means responsive to the rate of said detected signals for pro-viding a voltage related to said rate;
integrating means for integrating said voltage and providing first and second control signals as said integrated signal increases beyond re-spective first and second magnitudes;
counter means for being reset by said first signal to count from an initial value and to provide a signal manifesting said heart rate as related to the count therein upon the occurrence of said second signal;
wherein said means for providing said voltage related to said heart rate includes first capacitance means for being charged at a determined rate, second capacitance means switch means for transferring the voltage on said first capacitance means to said second capacitance mmeans each time a heartbeat is detected, means for discharging said first capacitance means after each heartbeat is detected, and means for applying the voltage stored by said second capacitance means to said integrating means as said voltage related to said rate;
wherein said counter counts to a certain count above the count therein at the time said second control signal is provided; and wherein said circuit means further includes means responsive to said counter reaching said certain count for resetting said integrating means
means for detecting a signal manifesting a heartbeat in response to an electrocardiac signal applied thereto;
means responsive to the rate of said detected signals for pro-viding a voltage related to said rate;
integrating means for integrating said voltage and providing first and second control signals as said integrated signal increases beyond re-spective first and second magnitudes;
counter means for being reset by said first signal to count from an initial value and to provide a signal manifesting said heart rate as related to the count therein upon the occurrence of said second signal;
wherein said means for providing said voltage related to said heart rate includes first capacitance means for being charged at a determined rate, second capacitance means switch means for transferring the voltage on said first capacitance means to said second capacitance mmeans each time a heartbeat is detected, means for discharging said first capacitance means after each heartbeat is detected, and means for applying the voltage stored by said second capacitance means to said integrating means as said voltage related to said rate;
wherein said counter counts to a certain count above the count therein at the time said second control signal is provided; and wherein said circuit means further includes means responsive to said counter reaching said certain count for resetting said integrating means
5. 5. The invention according to claim 4:
wherein said circuit means further includes clock means for pro-viding constant frequency clock signals to be counted to said counter means;
and wherein said circuit means further includes means for inhibiting the provision of said clock signals to said counter reaching said certain
wherein said circuit means further includes clock means for pro-viding constant frequency clock signals to be counted to said counter means;
and wherein said circuit means further includes means for inhibiting the provision of said clock signals to said counter reaching said certain
6. The invention according to claim 5 wherein said means for inhibi-ting the provision of said clock signals is operative until said first con-trol signal is provided by said integrating means.
7. The invention according to claim 6 wherein said first capacitance means is charged from a constant current source providing a constant current.
8. The invention according to claim 7: wherein said integrating means includes an amplifier having inverting and noninverting inputs, and all output, third capacitance means coupled between said output and said inverting input, resistance means coupled between said inverting input and a point of reference potential and coupling means coupling one side of said second capacitance means to said noninverting input; and wherein the other side of said second capacitance means is coupled to said point of reference potential.
9. The invention according to claim 8 wherein heartbeat rate as manifested by said counter is directly proportional to said constant frequency, the value of said resistance means, the difference in voltage between said first and second signals, the value of said first and third capacitance means and inversely proportional to said constant current and the real time between detected heartbeats.
10. The invention according to claim 9 wherein said resistance means is functionally trimmed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA386,538A CA1133991A (en) | 1978-05-24 | 1981-09-23 | Cardiac monitoring apparatus |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US909,229 | 1978-05-24 | ||
| US05/909,229 US4221223A (en) | 1978-05-24 | 1978-05-24 | Cardiac monitoring apparatus |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1118843A true CA1118843A (en) | 1982-02-23 |
Family
ID=25426852
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000328142A Expired CA1118843A (en) | 1978-05-24 | 1979-05-23 | Cardiac monitoring apparatus |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US4221223A (en) |
| JP (1) | JPS54154181A (en) |
| AU (1) | AU521201B2 (en) |
| CA (1) | CA1118843A (en) |
| DE (1) | DE2920965A1 (en) |
| FR (1) | FR2426446B1 (en) |
| GB (2) | GB2022839B (en) |
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| US4444200A (en) * | 1981-09-04 | 1984-04-24 | Senoh Kabushiki Kaisha | Heart pulse rate measuring system |
| US4475558A (en) * | 1982-05-28 | 1984-10-09 | Healthdyne, Inc. | System for providing short-term event data and long-term trend data |
| FR2551647A1 (en) * | 1983-09-13 | 1985-03-15 | Gilles Ascher | Portable apparatus with a bracelet intended for the recording of electrocardiograms |
| US4540001A (en) * | 1982-12-02 | 1985-09-10 | Ewing John G | Heart monitor for horses |
| US4478225A (en) * | 1982-12-02 | 1984-10-23 | Ewing John G | Heart monitor for horses |
| US4538619A (en) * | 1983-11-09 | 1985-09-03 | Iosif Baumberg | Analyzer of impulse processes of heart activity |
| JPS60163634A (en) * | 1984-02-06 | 1985-08-26 | 日置電機株式会社 | Heart rate meter |
| JPS6146566A (en) * | 1984-08-13 | 1986-03-06 | Victor Co Of Japan Ltd | Absolute value circuit |
| US5164898A (en) * | 1988-06-10 | 1992-11-17 | Ricoh Company, Ltd. | System for determining hazardous substance exposure rate from concentration measurement and heart rate data |
| US5226425A (en) * | 1991-09-10 | 1993-07-13 | Ralin, Inc. | Portable ECG monitor/recorder |
| US5191891A (en) * | 1991-09-10 | 1993-03-09 | Ralin, Inc. | Portable ECG monitor/recorder |
| US5966692A (en) * | 1992-05-12 | 1999-10-12 | Telemed Technologies International Corporation | Method and system for monitoring the heart of a patient |
| US5581369A (en) * | 1992-09-25 | 1996-12-03 | Ralin, Inc. | Apparatus and method for communicating electrocardiographic data to a facsimile machine |
| US5428640A (en) * | 1992-10-22 | 1995-06-27 | Digital Equipment Corporation | Switch circuit for setting and signaling a voltage level |
| WO1996010442A1 (en) * | 1994-09-30 | 1996-04-11 | Becton Dickinson And Company | Improved iontophoretic drug delivery device |
| US5738104A (en) * | 1995-11-08 | 1998-04-14 | Salutron, Inc. | EKG based heart rate monitor |
| US6115629A (en) * | 1999-03-01 | 2000-09-05 | Digital Concepts Of Missouri, Inc. | Two electrode heart rate monitor measuring power spectrum for use with exercise equipment |
| US6430436B1 (en) | 1999-03-01 | 2002-08-06 | Digital Concepts Of Missouri, Inc. | Two electrode heart rate monitor measuring power spectrum for use on road bikes |
| GB0022979D0 (en) * | 2000-09-19 | 2000-11-01 | Lall Sardool S | System for controlling the seconds display on a watch |
| AU2002255568B8 (en) | 2001-02-20 | 2014-01-09 | Adidas Ag | Modular personal network systems and methods |
| US7379770B2 (en) * | 2003-05-13 | 2008-05-27 | Dayton Technologies Limited | Devices and methods for heart rate measurement and wrist-watch incorporating same |
| US8702430B2 (en) | 2007-08-17 | 2014-04-22 | Adidas International Marketing B.V. | Sports electronic training system, and applications thereof |
| US8360904B2 (en) | 2007-08-17 | 2013-01-29 | Adidas International Marketing Bv | Sports electronic training system with sport ball, and applications thereof |
| US8221290B2 (en) | 2007-08-17 | 2012-07-17 | Adidas International Marketing B.V. | Sports electronic training system with electronic gaming features, and applications thereof |
| DE102009015273A1 (en) | 2009-04-01 | 2010-10-14 | Albert-Ludwigs-Universität Freiburg | Method and device for determining the endurance performance of a subject |
| KR101270089B1 (en) * | 2009-04-02 | 2013-05-31 | 가부시키가이샤 무라타 세이사쿠쇼 | Cardiac signal detection device |
| US8200323B2 (en) | 2009-05-18 | 2012-06-12 | Adidas Ag | Program products, methods, and systems for providing fitness monitoring services |
| US8105208B2 (en) | 2009-05-18 | 2012-01-31 | Adidas Ag | Portable fitness monitoring systems with displays and applications thereof |
| US8509882B2 (en) | 2010-06-08 | 2013-08-13 | Alivecor, Inc. | Heart monitoring system usable with a smartphone or computer |
| US9351654B2 (en) | 2010-06-08 | 2016-05-31 | Alivecor, Inc. | Two electrode apparatus and methods for twelve lead ECG |
| US20120258433A1 (en) | 2011-04-05 | 2012-10-11 | Adidas Ag | Fitness Monitoring Methods, Systems, And Program Products, And Applications Thereof |
| US10413251B2 (en) | 2012-10-07 | 2019-09-17 | Rhythm Diagnostic Systems, Inc. | Wearable cardiac monitor |
| US10244949B2 (en) | 2012-10-07 | 2019-04-02 | Rhythm Diagnostic Systems, Inc. | Health monitoring systems and methods |
| USD850626S1 (en) | 2013-03-15 | 2019-06-04 | Rhythm Diagnostic Systems, Inc. | Health monitoring apparatuses |
| US10610159B2 (en) | 2012-10-07 | 2020-04-07 | Rhythm Diagnostic Systems, Inc. | Health monitoring systems and methods |
| US9254095B2 (en) | 2012-11-08 | 2016-02-09 | Alivecor | Electrocardiogram signal detection |
| WO2014107700A1 (en) | 2013-01-07 | 2014-07-10 | Alivecor, Inc. | Methods and systems for electrode placement |
| USD921204S1 (en) | 2013-03-15 | 2021-06-01 | Rds | Health monitoring apparatus |
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| US9247911B2 (en) | 2013-07-10 | 2016-02-02 | Alivecor, Inc. | Devices and methods for real-time denoising of electrocardiograms |
| EP3079571A4 (en) | 2013-12-12 | 2017-08-02 | Alivecor, Inc. | Methods and systems for arrhythmia tracking and scoring |
| EP3282933B1 (en) | 2015-05-13 | 2020-07-08 | Alivecor, Inc. | Discordance monitoring |
| CN108348749B (en) | 2015-09-21 | 2022-07-12 | 齐夫医疗公司 | Monitoring and stimulation module |
| JP2022546991A (en) | 2019-08-28 | 2022-11-10 | アールディーエス | Vital signs or health monitoring system and method |
| US20210169392A1 (en) | 2019-12-10 | 2021-06-10 | Alivecor, Inc. | Twelve-lead electrocardiogram using a three-electrode device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3734086A (en) * | 1971-03-24 | 1973-05-22 | J Phelps | Equipment for measuring and displaying the time lapse between a given heartbeat and the corresponding arterial pulse |
| US3773038A (en) * | 1972-04-07 | 1973-11-20 | Nasa | Digital computing cardiotachometer |
| CH595825A5 (en) * | 1975-06-04 | 1978-02-28 | Heuer Leonidas Sa | |
| JPS585146B2 (en) * | 1975-09-29 | 1983-01-29 | 豊田工機株式会社 | Toishi Gourmano Tsuruing Dressing Hohou |
| US4096854A (en) * | 1976-03-01 | 1978-06-27 | Jacob E. Perica | Cardiac monitor with rate limit means |
| US4034745A (en) * | 1976-03-15 | 1977-07-12 | Bloom Kenneth A | Cardiotachometer |
| DE2618323C3 (en) * | 1976-04-27 | 1980-12-04 | Technitron Elektrik Ag, Baar (Schweiz) | Arrangement for measuring the pulse frequency |
| CH615334A5 (en) * | 1976-08-17 | 1980-01-31 | Laurent Chapuis | Instrument for measuring the pulse of an individual |
| US4120294A (en) * | 1976-08-26 | 1978-10-17 | Wolfe Donna L | Electrode system for acquiring electrical signals from the heart |
| FI55293C (en) * | 1977-05-23 | 1979-07-10 | Seppo Juhani Saeynaejaekangas | FOERFARANDE SAMT I ARMLEDEN OCH I FICKAN ANVAENDBAR ANORDNING FOER KONTUERLIG UPPMAETNING AV HJAERTPULSEN OCH PULSENS AOTERSTAELLNING |
-
1978
- 1978-05-24 US US05/909,229 patent/US4221223A/en not_active Expired - Lifetime
-
1979
- 1979-05-15 AU AU47081/79A patent/AU521201B2/en not_active Ceased
- 1979-05-23 CA CA000328142A patent/CA1118843A/en not_active Expired
- 1979-05-23 FR FR7913234A patent/FR2426446B1/en not_active Expired
- 1979-05-23 DE DE19792920965 patent/DE2920965A1/en active Granted
- 1979-05-24 GB GB7918102A patent/GB2022839B/en not_active Expired
- 1979-05-24 GB GB8138849A patent/GB2090983B/en not_active Expired
- 1979-05-24 JP JP6456879A patent/JPS54154181A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| GB2022839A (en) | 1979-12-19 |
| JPS54154181A (en) | 1979-12-05 |
| DE2920965C2 (en) | 1987-10-08 |
| GB2022839B (en) | 1982-10-20 |
| FR2426446B1 (en) | 1985-07-19 |
| FR2426446A1 (en) | 1979-12-21 |
| DE2920965A1 (en) | 1979-11-29 |
| GB2090983A (en) | 1982-07-21 |
| GB2090983B (en) | 1983-02-02 |
| AU521201B2 (en) | 1982-03-18 |
| AU4708179A (en) | 1979-11-29 |
| US4221223A (en) | 1980-09-09 |
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