CA1127770A - Method and device for speech signal reconstruction in packet switched telecommunication networks - Google Patents
Method and device for speech signal reconstruction in packet switched telecommunication networksInfo
- Publication number
- CA1127770A CA1127770A CA348,438A CA348438A CA1127770A CA 1127770 A CA1127770 A CA 1127770A CA 348438 A CA348438 A CA 348438A CA 1127770 A CA1127770 A CA 1127770A
- Authority
- CA
- Canada
- Prior art keywords
- packet
- delay
- time
- clock
- talkspurt
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
- H04J3/0632—Synchronisation of packets and cells, e.g. transmission of voice via a packet network, circuit emulation service [CES]
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/64—Hybrid switching systems
Abstract
ABSTRACT OF THE DISCLOSURE
In a packet-switched communications network, the variable component of a delay suffered by the first packet of a message is estimated at a receiving node and compared with a desired minimum delay selected to be just sufficiently large to encompass most expected delay variations, the result of the comparison being used to set a clock controlling reconstitution of the received signal so as to subject the received packets to a delay approximating to but not less than the desired delay. The estimate of the variable delay component is successively updated during reception of further packets to converge on the actual value of that component, the clock at the receiving node being updated accordingly to bring it into synchronization with a transmitter clock, sub-ject to a lag equal to the desired minimum delay.
In a packet-switched communications network, the variable component of a delay suffered by the first packet of a message is estimated at a receiving node and compared with a desired minimum delay selected to be just sufficiently large to encompass most expected delay variations, the result of the comparison being used to set a clock controlling reconstitution of the received signal so as to subject the received packets to a delay approximating to but not less than the desired delay. The estimate of the variable delay component is successively updated during reception of further packets to converge on the actual value of that component, the clock at the receiving node being updated accordingly to bring it into synchronization with a transmitter clock, sub-ject to a lag equal to the desired minimum delay.
Description
llzmo The present invention relates to digital speech transmission systems that utilize packet switching techniques, and more particularly it concerns a method and a device for speech signal reconstruction at the receiving end of such transmission system.
As is known, in a packet-switched c~mmunication net-work the information at the source is digitized, coded and sent into the network in block (packet) form; the packets are generally of fixed length and are each associated with a heading containing an address, serial number, control informa-- tion, etc.
A communication network of this kind is advantageous in that it operatesindependently of the nature of the trans-mitted information (e.g. telephone signals, data, video sig-nals) and conse~uently is particularly suited for realizing the service integration that is the goal of telecommunications operators.
In a packet-switched network, however, a random de-lay is introduced between the packet source and the receiver, and this delay can be different for each packet; in case of speech signals this causes disburtance in reception, as un-wanted pauses can be introduced into the active voice periods (talkspurts) and these talkspurts can be separated by different pauses from those existing at the source.
This problem is well known in the technical litera-ture, but no solution has been suggested till now.
Studies carried out by the inventors have established that the influence of this random delay can be minimized if the fir~t packet of each talkspurt is allowed a random delay no smaller than a minimum value determined so as to reduce the delay variance.
Thus, it is a particular object of the present invention to provide a method for the correct reconstruction 1~70 of a speech signal at a receiving node of a packet switched network in which a transmitting node emits packets built-up from digitized samples of active signal periods of said signal, the packets being received with a random delay varying accor-ding to the packet and the receiving operations being controlled by a clock independent of the transmission clock and started upon the reception at said receiving node of a first packet relevant to a call, wherein the delay suffered by the first packet of each talkspurt is estimated, the estimate being pro-gressively updated to converge on an actual value by progres-sive synchronization the reception and transmission clocks, and wherein said packet is stored before being introduced into the output queue of the receiving node for a time dependent on said estimated delay and such that the overall delay suffered ffl said packet is not less than a minimum predetermined delay predictedto encompass mostexpected variances ofsaid random delay.
It is a further object of the device to provide apparatus for carrying out the method.
These and other characteristics of the invention will become clearer from the following description of a prefer-red embodiment thereof given by way of non limitative example and shown in the annexed drawings, in which:
Figure 1 is a block diagram of a packet-switched spee¢h transmission system;
- Figure 2 is a block diagram of the device according to the invention;
Figure 3 is a flow chart of the operation of the device of Figure 2.
~ Figure 1 shows the connection between two subscri-bers, schematized by microphone MF and receiver RC, in a packet switched network RT including the apparatus of the invention.
Microphone MF is connected to node Nl (in the 11~7770 following referred to as transmitting node or source) of net-work RT through an analog-to-digital converter AD, converting the analog speech signal into asignalsay ofPCM type,an active speech detector RVA, eliminating phonetic and expressive pauses in the signal, and a packetizer CP organizing the PCM samples into fixed-length packets. By way of example, a packet can comprise 256 PCM samples corresponding to 32 ms of conversation.
Each packet comprises, in addition to the speech signals (that is to the 256 samplesj, a header containing service information.
Of this information, the time of origin of the packet ~if ~he packet itself is the first of a talkspurt) and the serial num-ber of the packet within the talkspurt are of interest in the pre6ent invention.
A second node N2 of the network (hereinafter referred to as receiving node) is followed by a packet receiver RP, which reconstructs the PCM samples of speech signal by accept-ing the packets in the same order in which they have been transmitted, an analog-to-digital converter DA, and receiver RC. The reception at node N2 is controlled by a clock that is independent of the transmission alock and is started when the node receives the first packet of a conversation.
In network RT the packets suffer a determinable delay, equal for all packets and due to service times (transmission, switching, etc.), and a random delay varying for each packet.
This latter, which is due to the asynchronism of packet switched communications and is fun¢tion of the traffic level, causes a reception disturbance. To overcome this drawback, node N2 is associated with the apparatus of the invention, denoted by SR, whose tasks are:
1) to estimate the delay suffered by the first packet of each talkspurt: information at the receiver as to the magni-tude of this delay is not precise and can be only estimated owing to the unknown random offset between the transmission l~Z77'70 and reception clocks. The better the synchronism between the two clocks, the better the estimate, so the device SR
must also synchronize the two clocks;
As is known, in a packet-switched c~mmunication net-work the information at the source is digitized, coded and sent into the network in block (packet) form; the packets are generally of fixed length and are each associated with a heading containing an address, serial number, control informa-- tion, etc.
A communication network of this kind is advantageous in that it operatesindependently of the nature of the trans-mitted information (e.g. telephone signals, data, video sig-nals) and conse~uently is particularly suited for realizing the service integration that is the goal of telecommunications operators.
In a packet-switched network, however, a random de-lay is introduced between the packet source and the receiver, and this delay can be different for each packet; in case of speech signals this causes disburtance in reception, as un-wanted pauses can be introduced into the active voice periods (talkspurts) and these talkspurts can be separated by different pauses from those existing at the source.
This problem is well known in the technical litera-ture, but no solution has been suggested till now.
Studies carried out by the inventors have established that the influence of this random delay can be minimized if the fir~t packet of each talkspurt is allowed a random delay no smaller than a minimum value determined so as to reduce the delay variance.
Thus, it is a particular object of the present invention to provide a method for the correct reconstruction 1~70 of a speech signal at a receiving node of a packet switched network in which a transmitting node emits packets built-up from digitized samples of active signal periods of said signal, the packets being received with a random delay varying accor-ding to the packet and the receiving operations being controlled by a clock independent of the transmission clock and started upon the reception at said receiving node of a first packet relevant to a call, wherein the delay suffered by the first packet of each talkspurt is estimated, the estimate being pro-gressively updated to converge on an actual value by progres-sive synchronization the reception and transmission clocks, and wherein said packet is stored before being introduced into the output queue of the receiving node for a time dependent on said estimated delay and such that the overall delay suffered ffl said packet is not less than a minimum predetermined delay predictedto encompass mostexpected variances ofsaid random delay.
It is a further object of the device to provide apparatus for carrying out the method.
These and other characteristics of the invention will become clearer from the following description of a prefer-red embodiment thereof given by way of non limitative example and shown in the annexed drawings, in which:
Figure 1 is a block diagram of a packet-switched spee¢h transmission system;
- Figure 2 is a block diagram of the device according to the invention;
Figure 3 is a flow chart of the operation of the device of Figure 2.
~ Figure 1 shows the connection between two subscri-bers, schematized by microphone MF and receiver RC, in a packet switched network RT including the apparatus of the invention.
Microphone MF is connected to node Nl (in the 11~7770 following referred to as transmitting node or source) of net-work RT through an analog-to-digital converter AD, converting the analog speech signal into asignalsay ofPCM type,an active speech detector RVA, eliminating phonetic and expressive pauses in the signal, and a packetizer CP organizing the PCM samples into fixed-length packets. By way of example, a packet can comprise 256 PCM samples corresponding to 32 ms of conversation.
Each packet comprises, in addition to the speech signals (that is to the 256 samplesj, a header containing service information.
Of this information, the time of origin of the packet ~if ~he packet itself is the first of a talkspurt) and the serial num-ber of the packet within the talkspurt are of interest in the pre6ent invention.
A second node N2 of the network (hereinafter referred to as receiving node) is followed by a packet receiver RP, which reconstructs the PCM samples of speech signal by accept-ing the packets in the same order in which they have been transmitted, an analog-to-digital converter DA, and receiver RC. The reception at node N2 is controlled by a clock that is independent of the transmission alock and is started when the node receives the first packet of a conversation.
In network RT the packets suffer a determinable delay, equal for all packets and due to service times (transmission, switching, etc.), and a random delay varying for each packet.
This latter, which is due to the asynchronism of packet switched communications and is fun¢tion of the traffic level, causes a reception disturbance. To overcome this drawback, node N2 is associated with the apparatus of the invention, denoted by SR, whose tasks are:
1) to estimate the delay suffered by the first packet of each talkspurt: information at the receiver as to the magni-tude of this delay is not precise and can be only estimated owing to the unknown random offset between the transmission l~Z77'70 and reception clocks. The better the synchronism between the two clocks, the better the estimate, so the device SR
must also synchronize the two clocks;
2) by utilizing the delay estimate, to introduce an additional delay whenever required, for the first packet of a talk-spurt so as to reduce the delay variance. By applying the additional delay to the first packet of a talkspurt, irre-gular reception and the probability of unwanted idle periods inside the reconstructed talkspurt can be reduced.
The structure of SR is described with reference to Figure 2; the blocks RVA, CP, Nl, N2, RP discussed above will not be described in detail since they are well understood in the art.
In Figure 2 Ml, M2, M3, M4, M5 denote five memories or registers that receive data written by the proaessor EL of the node N2; the content of such memories is presented on respective output connections 1, 2, 3, 4, 5 so that it can be transferred to other units of device SR upon receipt of commands from a sequential programmable logic network LS.
Memory Ml stores, for each packet received from pro-ces80r EL, the associated serial number reduced by a unit (k-l); the value k is supplied by processor EL which reads it from the packet heading.
Memory M2 stores the value Ts which is the emission or reception time of a packet, i.e. the time necessary to build up a packet from a determined number of samples or to recon-struct the samples from the packet. This value Ts is obviously constant for the whole network.
Memory M3 ~tores a control time T~ corresponding to the minimum delay that, for the above mentioned reasons, must be applied to the first packet of each talkspurt to encompass predicted delay variances; this time depends on the degree of occupation of the network and is estimated by well known ~lZ77~70 teGhniques which form no part of the invention. An example i8 described by G. Barberis and G. Micca in the paper "A New Routing Algorithm for Computer Communication Network" presented at the ICC 78 meeting (Memory 27.5).
Memory M4 stores the value TD of the total service time (switching, transmission and so on), that is the common determinable component of the delay of the packets. Memory M5 stores ts, the time of origin of the first packet of a talk-spurt according to the source cloak; value ~s is stored in the packet heading. M6 denotes a buffer memory that stores each packet arriving at EL for a time, which may be zero, deter-mined by the method according to the present invention, as it will be described in more detail hereinafter. When this time is over, the packet is fed again to the processor EL to be sent to packet receiver RP (Figure 1). This transfer takes place through a gate Pl and is controlled by a signal Pl coming from LS.
References P2, P3, P4, P5, P6, P7 denote si~ further gates, that open upon command of signals P2 Pl supplied by LS, to allow communication among the various units of synchro-nizing device SR.
More particularly the input of gate P2 is connected to the output connection 1 of memory MEl, and its output on connection 6 is conneated to a first input of a comparator Cl.
A second input of thi6 comparator is connected with a compari-son threshold equal to 0, so that Cl is able through connec-tion 10 to inform LS when the content of Ml is 0, that is when the processed packet is the first of a talkspurt.
The input of gate P3 i8 connected to the output 1 of memory Ml and its output is connected to a further memory ~or register) M7 through connection 7. This memory M7 stores the content of Ml whenever its content is updated by proces-sor EL.
li~27~70 Gate P4 has five inputs and two outputs. The inputs are connected through connections 1, 3, 8, 9, 10, respectively to the outputs of memories Ml, M3, M7, to an output of a sum-ming register RS and to one output of a programmable clock oP;
the outputs are connected through connections 11, 12 with the inputs of a two-input comparator C2. Upon command of signal p4, the gate connects outputs 11, 12 to inputs 1, 8, or in-puts 9, 10, or inputs 9, 3. The characteristics and tasks of C2, RS, OP are described hereinafter.
Gate P5 has two inputs connected to outputs 1, 2 of memories Ml and M2 respectively. Output 13 of P5 is con-nected to the input of a multiplying register RM that, for each packet with serial numberk~l, computes the time elapsed from the transmission of the first packet to the transmission of the packet in question. Hence register RM computes the value (k-l) Ts.
Gate P6 has five inputs and one output. The inputs are connected, through connections 3, 4, 5, 14, 15 respectively to the outputs of M3, M4, M5, RM and to a second output of programmable clock OP. The output of P6 is connected through connection 16 to the input of adding register RS.
The input of gate P7 is connected to a second output 17 of RS, and its output is connected through connection 18 to the input of programmable clock OP.
Programmable clock OP counts the reception time tr, beginning from the first arrival at N2 (Figure 1) of a packet relevant to a certain conversation. Therefore, initially it will be delayed in phase with respect to the transmission clock and it will be adjusted at the arrival of each packet to match said transmission clock. Information as to the mag-nitude of the necessary adjustment of OP is supplied by RS
through connection 17.
The adding register RS, in the different phases of 11~77 70 the process, computes:
- the estimated instant tx of arrival of the various packets at the receiver in the absence of random delay; this value is obtained by adding the time taken to assemble the pac-kets, the first one excepted (time calculated in RM), the determinable delay Td (supplied by M4) and the time of origin ts f the first packet of a talkspurt (information supplied by M2). Consequently, for the k-th packet value tx will be given by the expression . tx = (k-l) Ts ~ Td + ts - the delay td suffered by a packet with respect to its esti-mated arrival instant (supposing tr> tx, otherwise the delay is equal to 0); this delay is obtained by subtrac-ting tx, previously calculated, from value tr of the actual instant of arrival of the packet, supplied by programmable clock OP.
- delay T~ - td to be introduced for the first talkspurt packet; this value is supplied to LS through connection 20. ~:
Comparator C2 indicates whether two equal values are present at its inputs or, in case the values are different, which is higher. The comparator must:
- compare the contents of memories Ml and M7 to enable up-dating of the latter if required;
- check whether the estimated value tx of the arrival instant of the k-th packet ~value supplied by RS), is less than the value tr~ provided by the programmable clock; the compari-son will generally provide a negative result for the first packets received, and thus causes OP to be set to value tx;
- check whether the value of control time T~ stored in M3 is greater than estimated delay value td = tr ~ tx (the more synchronized the clocks, the more correct this esti-mate). The results of the comparisons are applied to LS
on connection 21.
_ 7 _ Finally programmable logic LS controls all the de-vice operations, by receiving information from Cl, C2, RS and generating opening commands for gates Pl ... P7.
Operation of the apparatus will be described with reference also to Figure 3, in which such operation is repre-sented as a flow chart. In this chart, as is conventional rectangles represent operations to be carried out and rhombs represent decisions to be taken.
Before the beginning of a conversation, value 1 is present in memory Ml, and con~equently in M7, and clock OP is set to zero (tr = O); logic LScondition~gateP4 so that it can connect to comparator C2 the memories Ml, M7 (that is it connects to the outputs 11, 12 the inputs 1 and 8) and cycli-cally (for instance every tl seconds) scans the output 21 of C2 to detect the first arrival of a packet relevant to a con-versation. The serial number k of this packet may differ from 1, that is the packet may not be the first packet of the first talkspurt, owing to possible disturbances that can affect re-gular transmission.
The arrival of this packet is recognized due to the change of state at the output of C2, which signals the diffe-rence between the two inputs; in fact value k-l will be pre-sent in Ml while value-l will be still present in M7.
The packet on arrival at node N2 is transferred, on command of processor EL, into memory M6, awaiting the accom-lishment in the other devices of SR of the operations allow-ing the adjustment of clock OP and a decision as to whether the packet should be delayed or transferred again to EL in order to be inserted into the output queue of the node. At the same time the information contained in the packet and of intere~t to the process ~serial number and time of origin if present) is transferred into the memories Ml and M2.
In consequence of the recognition of the arrival of 7~70 a packet, LS starts programmable clock OP; it also opens gate P3 in order to allow storage in M7 of the value k-l, opens gate P5 to allow the transfer of values k-l and Ts from memories Ml, M~ to the multiplying register RM, and passes in sequence to the output 16 of gate P6 the inputs 4, 5 to allow the storage in RS of values Td and ts. This last value will be the actual time of origin according to the source clock, if the packet is the first of the talkspurt, otherwise it will be 0.
Register RM computes the products ~k-l) Ts and then LS connects input 14 of P6 with output 16 thereof so as to transfer the product to RS, where it is added to values Td and ts to give value tx, i.e. the minimum possible value for the time of arrival of the packet. ~ -Once tx has been computed, logic network LS operates P4 so as to connect inputs 9, 10 with outputs 11, 12; the value tx and value tr indicated by OP are then applied to C2 where they are compared.
As the first packet received for the conversation in progress is being examined, OP has only just been started, so value tx will be higher than tr. Logic netowrk L5 then opens ~ gate P7 to allow the setting of clook oP to value tr computed ; by RS and the advance of OP from the indicated value tr to value tx. After this updating of OP lor immediately after the comparison, if C2 indicates that tr~ tx), logic LS opens gate P2 to allow the transfer of value k-l, stored in Ml, to com-parator Cl. Comparator Cl checks whether this value is null or not.
If k-l ~ 0, that is if the packet is not the first of a talkspurt, logic network LS opens gate Pl so that the examined packet is transferred again into EL, which inserts it into the output queue of node ~2, for the reconstruction of a speech signal in devices RP, DA and its transfer to subscri-ber RC. Of course the time necessary to carry out the ~Z7~0 operations described above is negligible with respect to the average queueing time of a packet, which is why the slight de-lay introduced by SR does not in practice affect the normal operation of the node.
If k-l = 0, LS connects input 15 of gate P6 with output 16 so that time tr indicated by clock OP is stored in register RS. Register RS subtracts from that value the value tx previously computed and supplies an estimated value td f the delay suffered by the first packet.
As tx has been assumed to be higher than trl OP has been set to tx and the estimated delay will be zero. LS then operates gate P4 so that comparator C2 receives value td and value T~ stored in M3. With the above assumptions, td is zero and therefore T~ i8 necessarily greater than td. This infor-mation is sent to LS where a clock is started to count up to T~; when T~ is reached, ~S opens P1 and the packet is sent from M6 to the processor to be introduced in the output queue - of the node.
If by any chance td were not null (for instance be-cause tx was lower than tr)~ logic network LS can open gateP1 after a time T~ - td~ if tdC T~, or as soon as it receives - the result of the comparison, if td> T~. It will be appreci-ated that the first packet of a talkspurt is always inserted into the queue with a minimum delay T~, which is possibly subject to estimating error.
. Once the processing of the first packet is finished, the contents of Ml, M7 are compared again, to detect the arri-val of a further packet, and the operations described above will be repeated. More particularly, for each packet the earliest possible time of arrival will be compared with the time indicated by clock OP and the clock will be possibly regulated again and progressively synchronized with the trans-mission clock.
` ~Z7770 It iS clear that after quite a small number of pac-kets the time of arrival tx will be not higher than value tr, that is the two clocks can be considered synchronized.
After estimation of their arrival instant, packets with serial number k ~ 1 are inserted into the output queue of the node, while for packets with k = 1 the delay is esti-mated. Of course the precision of this estimate, which uti-lizes the value tr indicated by OP after possible setting to value tx, will increase as times goes by through improving synchronization of the two clocks.
The structure of SR is described with reference to Figure 2; the blocks RVA, CP, Nl, N2, RP discussed above will not be described in detail since they are well understood in the art.
In Figure 2 Ml, M2, M3, M4, M5 denote five memories or registers that receive data written by the proaessor EL of the node N2; the content of such memories is presented on respective output connections 1, 2, 3, 4, 5 so that it can be transferred to other units of device SR upon receipt of commands from a sequential programmable logic network LS.
Memory Ml stores, for each packet received from pro-ces80r EL, the associated serial number reduced by a unit (k-l); the value k is supplied by processor EL which reads it from the packet heading.
Memory M2 stores the value Ts which is the emission or reception time of a packet, i.e. the time necessary to build up a packet from a determined number of samples or to recon-struct the samples from the packet. This value Ts is obviously constant for the whole network.
Memory M3 ~tores a control time T~ corresponding to the minimum delay that, for the above mentioned reasons, must be applied to the first packet of each talkspurt to encompass predicted delay variances; this time depends on the degree of occupation of the network and is estimated by well known ~lZ77~70 teGhniques which form no part of the invention. An example i8 described by G. Barberis and G. Micca in the paper "A New Routing Algorithm for Computer Communication Network" presented at the ICC 78 meeting (Memory 27.5).
Memory M4 stores the value TD of the total service time (switching, transmission and so on), that is the common determinable component of the delay of the packets. Memory M5 stores ts, the time of origin of the first packet of a talk-spurt according to the source cloak; value ~s is stored in the packet heading. M6 denotes a buffer memory that stores each packet arriving at EL for a time, which may be zero, deter-mined by the method according to the present invention, as it will be described in more detail hereinafter. When this time is over, the packet is fed again to the processor EL to be sent to packet receiver RP (Figure 1). This transfer takes place through a gate Pl and is controlled by a signal Pl coming from LS.
References P2, P3, P4, P5, P6, P7 denote si~ further gates, that open upon command of signals P2 Pl supplied by LS, to allow communication among the various units of synchro-nizing device SR.
More particularly the input of gate P2 is connected to the output connection 1 of memory MEl, and its output on connection 6 is conneated to a first input of a comparator Cl.
A second input of thi6 comparator is connected with a compari-son threshold equal to 0, so that Cl is able through connec-tion 10 to inform LS when the content of Ml is 0, that is when the processed packet is the first of a talkspurt.
The input of gate P3 i8 connected to the output 1 of memory Ml and its output is connected to a further memory ~or register) M7 through connection 7. This memory M7 stores the content of Ml whenever its content is updated by proces-sor EL.
li~27~70 Gate P4 has five inputs and two outputs. The inputs are connected through connections 1, 3, 8, 9, 10, respectively to the outputs of memories Ml, M3, M7, to an output of a sum-ming register RS and to one output of a programmable clock oP;
the outputs are connected through connections 11, 12 with the inputs of a two-input comparator C2. Upon command of signal p4, the gate connects outputs 11, 12 to inputs 1, 8, or in-puts 9, 10, or inputs 9, 3. The characteristics and tasks of C2, RS, OP are described hereinafter.
Gate P5 has two inputs connected to outputs 1, 2 of memories Ml and M2 respectively. Output 13 of P5 is con-nected to the input of a multiplying register RM that, for each packet with serial numberk~l, computes the time elapsed from the transmission of the first packet to the transmission of the packet in question. Hence register RM computes the value (k-l) Ts.
Gate P6 has five inputs and one output. The inputs are connected, through connections 3, 4, 5, 14, 15 respectively to the outputs of M3, M4, M5, RM and to a second output of programmable clock OP. The output of P6 is connected through connection 16 to the input of adding register RS.
The input of gate P7 is connected to a second output 17 of RS, and its output is connected through connection 18 to the input of programmable clock OP.
Programmable clock OP counts the reception time tr, beginning from the first arrival at N2 (Figure 1) of a packet relevant to a certain conversation. Therefore, initially it will be delayed in phase with respect to the transmission clock and it will be adjusted at the arrival of each packet to match said transmission clock. Information as to the mag-nitude of the necessary adjustment of OP is supplied by RS
through connection 17.
The adding register RS, in the different phases of 11~77 70 the process, computes:
- the estimated instant tx of arrival of the various packets at the receiver in the absence of random delay; this value is obtained by adding the time taken to assemble the pac-kets, the first one excepted (time calculated in RM), the determinable delay Td (supplied by M4) and the time of origin ts f the first packet of a talkspurt (information supplied by M2). Consequently, for the k-th packet value tx will be given by the expression . tx = (k-l) Ts ~ Td + ts - the delay td suffered by a packet with respect to its esti-mated arrival instant (supposing tr> tx, otherwise the delay is equal to 0); this delay is obtained by subtrac-ting tx, previously calculated, from value tr of the actual instant of arrival of the packet, supplied by programmable clock OP.
- delay T~ - td to be introduced for the first talkspurt packet; this value is supplied to LS through connection 20. ~:
Comparator C2 indicates whether two equal values are present at its inputs or, in case the values are different, which is higher. The comparator must:
- compare the contents of memories Ml and M7 to enable up-dating of the latter if required;
- check whether the estimated value tx of the arrival instant of the k-th packet ~value supplied by RS), is less than the value tr~ provided by the programmable clock; the compari-son will generally provide a negative result for the first packets received, and thus causes OP to be set to value tx;
- check whether the value of control time T~ stored in M3 is greater than estimated delay value td = tr ~ tx (the more synchronized the clocks, the more correct this esti-mate). The results of the comparisons are applied to LS
on connection 21.
_ 7 _ Finally programmable logic LS controls all the de-vice operations, by receiving information from Cl, C2, RS and generating opening commands for gates Pl ... P7.
Operation of the apparatus will be described with reference also to Figure 3, in which such operation is repre-sented as a flow chart. In this chart, as is conventional rectangles represent operations to be carried out and rhombs represent decisions to be taken.
Before the beginning of a conversation, value 1 is present in memory Ml, and con~equently in M7, and clock OP is set to zero (tr = O); logic LScondition~gateP4 so that it can connect to comparator C2 the memories Ml, M7 (that is it connects to the outputs 11, 12 the inputs 1 and 8) and cycli-cally (for instance every tl seconds) scans the output 21 of C2 to detect the first arrival of a packet relevant to a con-versation. The serial number k of this packet may differ from 1, that is the packet may not be the first packet of the first talkspurt, owing to possible disturbances that can affect re-gular transmission.
The arrival of this packet is recognized due to the change of state at the output of C2, which signals the diffe-rence between the two inputs; in fact value k-l will be pre-sent in Ml while value-l will be still present in M7.
The packet on arrival at node N2 is transferred, on command of processor EL, into memory M6, awaiting the accom-lishment in the other devices of SR of the operations allow-ing the adjustment of clock OP and a decision as to whether the packet should be delayed or transferred again to EL in order to be inserted into the output queue of the node. At the same time the information contained in the packet and of intere~t to the process ~serial number and time of origin if present) is transferred into the memories Ml and M2.
In consequence of the recognition of the arrival of 7~70 a packet, LS starts programmable clock OP; it also opens gate P3 in order to allow storage in M7 of the value k-l, opens gate P5 to allow the transfer of values k-l and Ts from memories Ml, M~ to the multiplying register RM, and passes in sequence to the output 16 of gate P6 the inputs 4, 5 to allow the storage in RS of values Td and ts. This last value will be the actual time of origin according to the source clock, if the packet is the first of the talkspurt, otherwise it will be 0.
Register RM computes the products ~k-l) Ts and then LS connects input 14 of P6 with output 16 thereof so as to transfer the product to RS, where it is added to values Td and ts to give value tx, i.e. the minimum possible value for the time of arrival of the packet. ~ -Once tx has been computed, logic network LS operates P4 so as to connect inputs 9, 10 with outputs 11, 12; the value tx and value tr indicated by OP are then applied to C2 where they are compared.
As the first packet received for the conversation in progress is being examined, OP has only just been started, so value tx will be higher than tr. Logic netowrk L5 then opens ~ gate P7 to allow the setting of clook oP to value tr computed ; by RS and the advance of OP from the indicated value tr to value tx. After this updating of OP lor immediately after the comparison, if C2 indicates that tr~ tx), logic LS opens gate P2 to allow the transfer of value k-l, stored in Ml, to com-parator Cl. Comparator Cl checks whether this value is null or not.
If k-l ~ 0, that is if the packet is not the first of a talkspurt, logic network LS opens gate Pl so that the examined packet is transferred again into EL, which inserts it into the output queue of node ~2, for the reconstruction of a speech signal in devices RP, DA and its transfer to subscri-ber RC. Of course the time necessary to carry out the ~Z7~0 operations described above is negligible with respect to the average queueing time of a packet, which is why the slight de-lay introduced by SR does not in practice affect the normal operation of the node.
If k-l = 0, LS connects input 15 of gate P6 with output 16 so that time tr indicated by clock OP is stored in register RS. Register RS subtracts from that value the value tx previously computed and supplies an estimated value td f the delay suffered by the first packet.
As tx has been assumed to be higher than trl OP has been set to tx and the estimated delay will be zero. LS then operates gate P4 so that comparator C2 receives value td and value T~ stored in M3. With the above assumptions, td is zero and therefore T~ i8 necessarily greater than td. This infor-mation is sent to LS where a clock is started to count up to T~; when T~ is reached, ~S opens P1 and the packet is sent from M6 to the processor to be introduced in the output queue - of the node.
If by any chance td were not null (for instance be-cause tx was lower than tr)~ logic network LS can open gateP1 after a time T~ - td~ if tdC T~, or as soon as it receives - the result of the comparison, if td> T~. It will be appreci-ated that the first packet of a talkspurt is always inserted into the queue with a minimum delay T~, which is possibly subject to estimating error.
. Once the processing of the first packet is finished, the contents of Ml, M7 are compared again, to detect the arri-val of a further packet, and the operations described above will be repeated. More particularly, for each packet the earliest possible time of arrival will be compared with the time indicated by clock OP and the clock will be possibly regulated again and progressively synchronized with the trans-mission clock.
` ~Z7770 It iS clear that after quite a small number of pac-kets the time of arrival tx will be not higher than value tr, that is the two clocks can be considered synchronized.
After estimation of their arrival instant, packets with serial number k ~ 1 are inserted into the output queue of the node, while for packets with k = 1 the delay is esti-mated. Of course the precision of this estimate, which uti-lizes the value tr indicated by OP after possible setting to value tx, will increase as times goes by through improving synchronization of the two clocks.
Claims (3)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A method for reconstruction of a speech signal at a receiving node of a packet switched communication network in which a transmitting node emits packets built up from digitized samples of talkspurts of said signal, the packets being received with a random delay varying according to the packet and the receiving operations being controlled by a clock that is independent of the transmission clock and is started upon the reception at the receiving node of a first packet relevant to a message, wherein the delay suffered by the first packet of each talkspurt is estimated, the estimate being progressively updated to converge on an actual value by progressive synchronization of the receiving and transmitting clocks, and wherein said packet is temporarily stored before being introduced into the output queue of the receiving node, for a time dependent on said estimated delay and such that the overall delay suffered by said packet is not less than a predetermined minimum desired delay predicted to encompass most expected variances of said random delay.
2. A method according to Claim 1, wherein sychroni-zation of the clocks is effected by determining the earliest possible time of arrival of each packet, on the basis of the time taken to assemble all the preceding packets, the time of origin of the first packet of a talkspurt and the determi-nable delay of the network, comparing this earliest time with that indicated by the receiving clock and advancing the receiving clock to said earliest time in the event that this is later than that indicated by the receiving clock.
3. Apparatus for association with the receiving node of a packet-switched communication network, comprising:
- a buffer memory for temporarily storing packets received by said node whereby to subject the first packet of each talkspurt to possible delay;
- first, second, third, fourth and fifth memories storing respectively: the serial number of each packet received, decremented by one; the time taken to assemble a packet;
the magnitude of a minimum desired delay to which the first packet of a talkspurt should be subject to encompass expec-ted variances in delay time; the determinable delay in-herent in the network; and the time of origin of the first packet of a talkspurt;
- a further memory connected to the first memory and storing the contents thereof whenever said first memory is updated;
- a first comparator having one input connected to the first memory and a second input connected to a comparison thres-hold fixed at zero, said comparator comparing the contents of said first memory with said threshold to determine whether or not a packet being processed is the first of a talkspurt;
- a multiplying register, connected with the first and second memories, and computing the product of the data stored in said memories which is the time elapsed between the trans-mission of the first packet of a talkspurt and the transmis-sion of the packet being processed;
- a programmable clock, arranged to be started at the instant of first reception of a packet relating to a message, and which, on arrival of a packet, is controllable to advance it towards an earliest time possible for the arrival of such a packet until the time registered by it is later than or coincident with said earliest time;
- an adding register that receives outputs from said multi-plying register, said programmable clock and the third, fourth, fifth memories, to compute said earliest possible time for arrival, to estimate the delay suffered by the first packet of a talkspurt and to determine, on the basis of said delay, the possible additional delay said packet should suffer, being the time by the minimum desired delay exceeds the estimated delay;
- a second comparator with two inputs, and providing diffe-rent outputs according to whether two values present on said inputs are equal, one is higher or the other is higher, said inputs being connectable in sequence to the first memory and to said further memory to recognize the arrival of a new packet, to said adding register and to said pro-grammable clock to compare the time indicated by the clock with said computed earliest possible time of arrival of the packet, and to the third memory and to said adding regi-ster, to determine whether the estimated delay of a packet of a talkspurt is still less than the minimum desired delay;
- a first gate operable to establish connection between said buffer memory and a processor in said node;
- further gates operable to establish connections between the various units of the device; and - a sequential logic network programmed so as to control the opening of said gates on the basis of information received from the first and second comparators and the adding regi-ster.
- a buffer memory for temporarily storing packets received by said node whereby to subject the first packet of each talkspurt to possible delay;
- first, second, third, fourth and fifth memories storing respectively: the serial number of each packet received, decremented by one; the time taken to assemble a packet;
the magnitude of a minimum desired delay to which the first packet of a talkspurt should be subject to encompass expec-ted variances in delay time; the determinable delay in-herent in the network; and the time of origin of the first packet of a talkspurt;
- a further memory connected to the first memory and storing the contents thereof whenever said first memory is updated;
- a first comparator having one input connected to the first memory and a second input connected to a comparison thres-hold fixed at zero, said comparator comparing the contents of said first memory with said threshold to determine whether or not a packet being processed is the first of a talkspurt;
- a multiplying register, connected with the first and second memories, and computing the product of the data stored in said memories which is the time elapsed between the trans-mission of the first packet of a talkspurt and the transmis-sion of the packet being processed;
- a programmable clock, arranged to be started at the instant of first reception of a packet relating to a message, and which, on arrival of a packet, is controllable to advance it towards an earliest time possible for the arrival of such a packet until the time registered by it is later than or coincident with said earliest time;
- an adding register that receives outputs from said multi-plying register, said programmable clock and the third, fourth, fifth memories, to compute said earliest possible time for arrival, to estimate the delay suffered by the first packet of a talkspurt and to determine, on the basis of said delay, the possible additional delay said packet should suffer, being the time by the minimum desired delay exceeds the estimated delay;
- a second comparator with two inputs, and providing diffe-rent outputs according to whether two values present on said inputs are equal, one is higher or the other is higher, said inputs being connectable in sequence to the first memory and to said further memory to recognize the arrival of a new packet, to said adding register and to said pro-grammable clock to compare the time indicated by the clock with said computed earliest possible time of arrival of the packet, and to the third memory and to said adding regi-ster, to determine whether the estimated delay of a packet of a talkspurt is still less than the minimum desired delay;
- a first gate operable to establish connection between said buffer memory and a processor in said node;
- further gates operable to establish connections between the various units of the device; and - a sequential logic network programmed so as to control the opening of said gates on the basis of information received from the first and second comparators and the adding regi-ster.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IT67628/79A IT1118518B (en) | 1979-03-27 | 1979-03-27 | PROCEDURE AND DEVICE FOR THE RECONSTRUCTION OF THE VOICE SIGNAL IN A PACKAGE SWITCHING COMMUNICATION SYSTEM |
| IT67628-A/79 | 1979-03-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1127770A true CA1127770A (en) | 1982-07-13 |
Family
ID=11304020
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA348,438A Expired CA1127770A (en) | 1979-03-27 | 1980-03-26 | Method and device for speech signal reconstruction in packet switched telecommunication networks |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US4317195A (en) |
| EP (1) | EP0016477B1 (en) |
| JP (1) | JPS55132159A (en) |
| CA (1) | CA1127770A (en) |
| DE (1) | DE3061480D1 (en) |
| IT (1) | IT1118518B (en) |
Families Citing this family (38)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2479620B1 (en) * | 1980-03-28 | 1988-01-08 | Thomson Csf | DEVICE FOR SYNCHRONIZING PACKET TRANSMITTED DIGITAL INFORMATION AND RECEIVER COMPRISING SUCH A DEVICE |
| JPS57159192A (en) * | 1981-03-27 | 1982-10-01 | Hitachi Ltd | Audio packet exchange system |
| US4506358A (en) * | 1982-06-25 | 1985-03-19 | At&T Bell Laboratories | Time stamping for a packet switching system |
| US4556970A (en) * | 1982-10-05 | 1985-12-03 | United Technologies Corporation | PBX Telephone system remote synchronization |
| US4551833A (en) * | 1983-08-10 | 1985-11-05 | At&T Bell Laboratories | Distributed monitoring of packet transmission delay |
| US4569042A (en) * | 1983-12-23 | 1986-02-04 | At&T Bell Laboratories | Time measurements in a transmission path |
| US4570257A (en) * | 1984-02-14 | 1986-02-11 | Rosemount Inc. | Communication system with slot time error detection |
| EP0172884B1 (en) * | 1984-02-14 | 1990-09-26 | Rosemount Inc. | Multipriority communication system |
| US4583219A (en) * | 1984-07-16 | 1986-04-15 | At&T Bell Laboratories | Trunk for packet switching |
| GB2177877A (en) * | 1985-07-13 | 1987-01-28 | Stc Plc | Packet systems |
| EP0215526B1 (en) * | 1985-09-19 | 1991-05-08 | BELL TELEPHONE MANUFACTURING COMPANY Naamloze Vennootschap | Data communication system |
| US4726019A (en) * | 1986-02-28 | 1988-02-16 | American Telephone And Telegraph Company, At&T Bell Laboratories | Digital encoder and decoder synchronization in the presence of late arriving packets |
| US4894823A (en) * | 1986-02-28 | 1990-01-16 | American Telephone And Telegraph Company | Time stamping for packet system nodes |
| US4748620A (en) * | 1986-02-28 | 1988-05-31 | American Telephone And Telegraph Company, At&T Bell Laboratories | Time stamp and packet virtual sequence numbering for reconstructing information signals from packets |
| JP2569493B2 (en) * | 1986-08-08 | 1997-01-08 | 日本電信電話株式会社 | Transfer fluctuation absorption processing method in packet communication |
| US4769815A (en) * | 1987-04-10 | 1988-09-06 | American Telephone And Telegraph Company, At&T Bell Laboratories | Packet flow control method |
| EP0289400A3 (en) * | 1987-04-30 | 1990-01-24 | Fairchild Weston Systems Inc. | High speed asynchronous data multiplexer/demultiplexer |
| US4813038A (en) * | 1987-06-29 | 1989-03-14 | Bell Communications Research, Inc. | Non-blocking copy network for multicast packet switching |
| US5058111A (en) * | 1989-06-19 | 1991-10-15 | Oki Electric Industry Co., Ltd. | Subscriber line interface circuit in a switching system |
| US6389010B1 (en) * | 1995-10-05 | 2002-05-14 | Intermec Ip Corp. | Hierarchical data collection network supporting packetized voice communications among wireless terminals and telephones |
| AU634915B2 (en) * | 1990-11-14 | 1993-03-04 | Fujitsu Limited | Delay distortion suppressing system for atm communication system |
| US5257258A (en) * | 1991-02-15 | 1993-10-26 | International Business Machines Corporation | "Least time to reach bound" service policy for buffer systems |
| GB2267200B (en) * | 1992-05-19 | 1995-10-25 | Dowty Communications Ltd | Packet transmission system |
| DE69422852T2 (en) * | 1993-05-26 | 2000-06-15 | Nec Corp | Network synchronization for cellular TDMA communication using signals from mobile stations in neighboring cells |
| US5563885A (en) * | 1995-05-24 | 1996-10-08 | Loral Fairchild Corporation | Method and system for processing multiple channel data |
| US6064673A (en) * | 1996-08-02 | 2000-05-16 | 3Com Corporation | Communications system having distributed control and real-time bandwidth management |
| SE511881C2 (en) * | 1997-08-08 | 1999-12-13 | Ericsson Telefon Ab L M | Method and arrangement for transmitting packet information in a digital telecommunication system |
| US6049537A (en) * | 1997-09-05 | 2000-04-11 | Motorola, Inc. | Method and system for controlling speech encoding in a communication system |
| US5898696A (en) * | 1997-09-05 | 1999-04-27 | Motorola, Inc. | Method and system for controlling an encoding rate in a variable rate communication system |
| US6400733B1 (en) * | 1998-12-02 | 2002-06-04 | Agere Systems Guardian Corp. | Apparatus and method for recovery of relative signal timing |
| US7161931B1 (en) * | 1999-09-20 | 2007-01-09 | Broadcom Corporation | Voice and data exchange over a packet based network |
| GB2359216B (en) * | 2000-02-11 | 2003-10-29 | Purple Voice Ltd | A method of synchronising the replay of audio data in a network of computers |
| US7321557B1 (en) * | 2000-10-30 | 2008-01-22 | Lucent Technologies Inc. | Dynamic latency assignment methodology for bandwidth optimization of packet flows |
| US20020126707A1 (en) * | 2001-03-08 | 2002-09-12 | Marcus Tong | System and method for rate adaptation in a wireless communication system |
| US7035210B2 (en) * | 2001-07-12 | 2006-04-25 | Telefonaktiebolaget Lm Ericsson (Publ) | Media stream delay monitoring for node |
| GB0205350D0 (en) * | 2002-03-07 | 2002-04-24 | Zarlink Semiconductor Inc | Clock synchronisation over a packet network using SRTS without a common network clock |
| DE10232988B4 (en) * | 2002-07-19 | 2007-11-22 | Infineon Technologies Ag | Method and device for the clocked output of asynchronously received digital signals |
| DE102011087472B4 (en) * | 2011-11-30 | 2016-10-20 | Continental Automotive Gmbh | Method for synchronizing clocks in nodes of a vehicle network and for implementing the method of established nodes |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3663172A (en) * | 1970-06-29 | 1972-05-16 | Cities Service Co | Carbon black production process |
| FR2242829B1 (en) * | 1973-08-29 | 1980-12-19 | Labo Cent Telecommunicat | |
| FR2267669B1 (en) * | 1974-04-12 | 1977-03-04 | Ibm France | |
| CH608924A5 (en) * | 1975-11-03 | 1979-01-31 | Hasler Ag | |
| FR2386211A1 (en) * | 1977-03-31 | 1978-10-27 | Europ Teletransmission | DIGITAL COMMUNICATION SYSTEM |
| US4100377A (en) * | 1977-04-28 | 1978-07-11 | Bell Telephone Laboratories, Incorporated | Packet transmission of speech |
| JPS54141504A (en) * | 1978-04-26 | 1979-11-02 | Fujitsu Ltd | Message transfer system in packet exchange network |
| FR2429526A1 (en) * | 1978-06-20 | 1980-01-18 | Thomson Csf | HIGH-SPEED DIGITAL COMMUNICATION SYSTEM, IN A MESH NETWORK |
-
1979
- 1979-03-27 IT IT67628/79A patent/IT1118518B/en active
-
1980
- 1980-03-24 JP JP3632580A patent/JPS55132159A/en active Pending
- 1980-03-26 DE DE8080101591T patent/DE3061480D1/en not_active Expired
- 1980-03-26 EP EP80101591A patent/EP0016477B1/en not_active Expired
- 1980-03-26 CA CA348,438A patent/CA1127770A/en not_active Expired
- 1980-03-26 US US06/134,269 patent/US4317195A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| EP0016477A1 (en) | 1980-10-01 |
| JPS55132159A (en) | 1980-10-14 |
| EP0016477B1 (en) | 1982-12-29 |
| US4317195A (en) | 1982-02-23 |
| IT1118518B (en) | 1986-03-03 |
| DE3061480D1 (en) | 1983-02-03 |
| IT7967628A0 (en) | 1979-03-27 |
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