CA1129543A

CA1129543A - Video signal processing circuit

Info

Publication number: CA1129543A
Application number: CA303,679A
Authority: CA
Inventors: Katsuhito Tsujimura
Original assignee: Sony Corp
Current assignee: Sony Corp
Priority date: 1977-05-24
Filing date: 1978-05-18
Publication date: 1982-08-10
Also published as: DE2822719A1; DE2822719C2; JPS6114706B2; NL7805642A; IT1095912B; AT378641B; JPS53144621A; IT7823719A0; FR2392559A1; FR2392559B1; AU3638378A; US4223351A; SE7805898L; SE438402B; GB1585953A; AU516733B2

Abstract

ABSTRACT
A video signal processing circuit for producing a dissolve signal to control dissolving of a video signal uses primarily digital circuitry to derive the dissolve signal. A phase locked loop is used to produce a clock signal having a frequency which is a multiple of the vertical synchronizing signal in the video signal, this output frequency is frequency divided by a fraction determined by a programmable counter which defines the rate of dissolve, is processed by a signal processor and delivered to an up/down counter controlling a digital to analogue converter, the output of which is processed to produce as said control signal a ramp signal of which the slope is determined by the programmable counter.

Description

11~954~ - 2 - .
- Thls invention relates to a video signal processing circuit for producing a dissolve signal to control dissolving of a video signal.
According to the present invention, there is provided a video signal processing circuit for producing a dissolve signal to control dissolving of a video signal by control of the amplitude of said video signal in a gain control circuit which is controlled in response to a control signal, said video signal processing circuit comprising: means for generating a clock signal having a frequency which is synchronous with a vertical synchronizing signal of said video signal, ~ means for frequen'cy-'dividi'n'g~~'''sai'd c~o~ signal by a preset value ~, means for-counting said frequency-divided clock signal during at least one vertical period of said video signal, and means for converting the digital output of said counting means into a corresponding an~o~ signal, whereby said an~k~ signal is supplied to said gain j: control circuit as said control signal.
,~ . More pa~t~cul~ there is pro~de~:
.... . . . .
A video signal processing circu~t for producing a dissolve signal to control dissolving of a video s~gnal by control of the amplitude of said video signal in a gain control circuit which is controlled in response to a control signal, said video signal processing circu;t compris;ng:
means for generating a cloc~ signal having a frequency which is synchronous with a vertical synchronizing signal of h .` . ` . . . - . . ; .. .

l 129543 - 2a -said video signal;
means for frequency-dividing said cloc~ signal by a preset value n;
means for counting said frequency-~ividing clock signal during at least one vertical period of said video signal;
means for converting the digital output of said count-ing means into a corresponding analogue signal, whereby said analogue signal is supplied to sa~d gain control circuit as said gain control signal; and first signal processing means connected between said frequency-dividing means and said counting means for pre-venting the supply of said clock signals during a predetermined interval, when the dissol~e duration in said circuit is set at a value in excess of a predetermined period of time.
~~ 15 ~ here is~ aIso prov~ded: ~
A videa signal processing circuit for producing a ~ ~issolve.signal t~ control d~ssolving of a ~ideo signal by control of the amplitude of said video signal ~n a gain control circuit which is controlled in response to a control signal, said video signal processing circuit comprising: means for generating a cloc~ signal having a frequency which is synchronous with a vertical synchronizing signal of said video signal; means for frequency-dividing said cloc~ signal by a preset value n; means for counting said frequency-divided clock signal during at least one vertical period of said video signal; means for converting the digital output of said counti:ng means into a corresponding analogue signal, ~.

~- - - . , ~ .. .. . . .

~ 1~9543 2b -where~y said analog signal is supplied to said gain control circuit as sa~d control signal; and signal processing means con-nected with said means for converting for chang~ng the level of said control signal at initii~tion and term~nation of the duration period.
, . . . .
T~ere ~s also provided.
h video signal processing circuit for producing a .
dissolve signal to control dissolving o~ a video signal by control of the amplitude of said video signal in a gain lQ control circuit which is controlled in response to a control signal, said video signal processing circuit comprising: means for generating a clock signal having a frequency which is synchronous ~ith a vertical synchronizing signal of said video signal; means for frequency-di~iding said clock signal by a preset value n; means for counting said frequency-divided clock signal during at least one vert~cal period of said video signal; means for converting the digital output of said count~ng means into a corresponding analogue signal, whereby said analogue signal is supplied to said gain control circuit as said control signal; said means for generating a clock signal ~e;ng a phase locked loop circuit generating an oscillating signal having a frequency ~xfv, where M is an integer and fv is the frame frequency and said means for frequency-dividing said clock signal being arranged to frequency div:ide said oscillating signal so as to have the frequency M/n fv, w~ere n is an integer, ~n accordance with the duration of the dissolve.

2 ~43 - 2c -There is further provided:
A circuit for controlling dissolve between at least first and second video signals comprising:
dissolve switcher means for dissolving between at least first and second video sign21s in response to a dissolve control signal;
phase locked loop means for generating a first fixed frequency signal related to a synchronizing signal in at least one of said first and second video signals by a fixed factor M;
programmable counter means for dividing said first fre-quency signal by a selectable factor n and providing a corresponding second frequency signal;
up-dcwn counter means for selectably counting up and down the cycles of said second frequency signal;
a digital to analogue converter operative to generate an analogue signal having a voltage proportional to the .. . . .. . . .. . . . . . .. .
digital number in said up-down counter means, and signal processing means operating on said analogue signal for producing therefrom said dissolve control signal which is operative to control said dissolve s~itcher means such that the perceived dissolve duration of a video display fed by sa~d dissolve switcher means is substantialiy equal to the duration of said analogue signal, A pré~erred embodiment of the present invention will now be described by way of example with reference to the accompanying drawings, in which:

. ~,.

Figure 1 is a block diagram showing a signal - processing system in which the present invention is employed Figures 2A and 2B are diagrams used for explaining the effect on a television screen obtained by operating the signal processing system shown in Figure 1, Figure 3 is a circuit diagram showing an example of the practical circuit of the system shown in Figure 1, Figure 4 is a block diagram showing an example of the wipe (key) generator which is used together with the circuits shown in Figures 1 and 3, Figures 5 and 6 are waveform diagrams used for explaining the operation of some elements used in the circuit shown in Figure 4, Figure 7 is a diagram used for explaining a picture on a television screen by the operation of the elements described in connection with Figure 5;
Figure 8 is a waveform diagram used for explaining the operation of the other element of the circuit shown in Figure 4, Figure 9 is a diagram used for explaining a tele-vision picture by the operation of the element described in connection with Figure 8, Figures 10, 11, 12, 13, 14, lS and 15' are diagrams showing television pictures provided by changing the operating state of the circui-t shown in Figure 4, Figure 16 is a diagram showing a television picture produced by the operation of a certain element of the - 12954 -.

Circuit shown in figure 4.

Figures 17, 18 and 19 are diagrams showing television picturès and waveform diagrams associated therewith used for the explanation of a certain element of the circuit shown in Figure 4, Figure 20 is a bloc]k diagram of the soft-edge generator;
Figures 21l 22 and 23 are diagrams showing a circuit which produces a signal fed to the circuit shown in Figure 4 and waveforms used for explaining the operation of the circuit;
Figure 24 is a block diagram showing an exam~le of the dissolve signal generator which is used together with the circuits shown in Figures 1 and 3;
Figure 25 is a graph showing a waveform which is used for explaining the operation of a certain element of the dissolve signal generator shown in Figure 24;
Figure 26 is a block diagram showing an example of the practical circuit of the element described in connection with Figure 25;
Figures 27 and 28 are waveform diagrams used for explaining the other elements of the ramp signal generator shown in Figure 24;
Figure 29 is a block diagram showing an example of .
the practical circuit of the elements described in connection with Figures 27 and 28 ~ Figure 30 shows the soft edge generator of Figure 20 in yreater detail, and Figure 31 illustrates waveforms occurring in use of the generator of Figure 30.
~igure 1 is a block diagram showin~ the signal processing system in which a video special effect generator according to the present invention is employed. In the figure, signal processing system 10 has two input terminals 12 and 14 and an output terminal 16. Video signals to be processed are fed to the input terminals 12 and 14, respectively. The signal processing system 10 also includes a wipe and key switcher 18 and a dissolve switcher 20. The first switcher 18 receives a wipe and key switching pulse applied to an input terminal 22 connected thereto, while the second switcher 20 receives a dissolve control signal applied to an input terminal 24 connected thereto. The first switcher 18 also receives first and second video signals fed to the terminals 12 and 14 and has an output terminal connected to a fixed contact 1 of a switch 28. A switch 26 is also provided which has one fixed contact 1 connected to the input terminal-12 directly and the other fixed contact 2 grounded, The switch 28 has the other fixed contact 2 connected to the lnput terminal 14 directly. Signals delivered to the movable contacts of the switches 26 and 28 are fed to inputs of the dissolve switcher 20 whose output is delivered to a fixed contact 1 of a switch 30. The ~ .
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:~ ~.2~5'~3 movable contact of the switch 28 is also connected directly to the other fixed contact 2 of the switch 30. The movable contact of the switch 30 i5 connected to the output terminal 16.
In the above signal processing system 10, when the movable contact of the switch 26 is connected to its fixed contact 2, the movable contact of the switch 28 to its fixed contact 1 and the movable contact of the switch 30 to its fixed contact 2, the output from the switcher 18 is delivered to the output terminal 16, whereby the wipe (key) mode is set.
When the movable contact of switch 26 is connected to its fixed contact 1, that of the switch 28 to its fixed contact 2 and that of the switch 30 to its fixed contact 1, the output from the switcher 20 is delivered to the output terminal 16, whereby the dissolve (fade) mode is provided.
Furthermore, if the switches 26, 28 and 30 are connected with their respective fixed contact 1, as shown in Figure 1, key-in(or key-out) can be achieved, if the movable contact of the switch 26 is changed over to its fixed contact 2 from the switching condition of Figure 1, the key-with-fade-in(out) operation will be achieved.
Figure 2A shows a chart of the key-in (key-out) operation on the screen. Firstly, the screen (a) imaging only a picture A is dissolved to the screen (b) superimposed a portion of picture B on the picture _, and then the key screen (c) on which the portion of picture B is inserted in the picture A is obtained. The technique of a picture conversion from Figure 2A (a) to Figure 2A (c) is called ;~ ?9 ~, 4 ~, thQ key-in operation, while the technique of picture conver-sion from Figure 2A (c) to Figure 2A (a) is called the key-out operation. If the above technique is achieved by the signal processing system 10 shown in Figure 1, the video signal which corresponds to the picture A is applied to input terminal 12 and the video signal which corresponds to the picture B is applied to input terminal 14, In this case, the switcher 18 is operated to provide a video signal which will produce the picture represented by Figure 2A (c).
At this time, the movable contacts of switches 26 and 28 are connected to their fixed contacts 1, respectively, so that the dissolve switcher 20 is supplied with the video signals corresponding to the pictures represented by Figure 2A (a) and (c). The switcher 20 dissolves both the input video signals such that the video signal corresponding to the picture represented by Figure 2A (b) is delivered to the output terminal 16 through the switch 30 whose movab1e contact is connected to the fixed contact 1 thereof.
Figure 2B is a chart showing pictures of the key-with-fade in (out) operation by operating the switches 26, 28 and 30 of the signal processing system 10 shown in Figure 1. From a picture screen which is initially black as shown in Figure 2B (a), a picture combined of the picture portions A and B appears gradually as shown in Figure 2B;(b), and finally a picture combined of the picture portions A and B completely appears as shown on a 1 1295~3 - picture screen (c) in Figure 2B. The technique that the combined picture of pictures A and B are faded-in in the order of (a), (b) and (c) as clescribed just above is called the key-with-fade-in operation, while the technique that the picture on the screen (c) of the key state is converted to the black picture on the screen (a) through the picture on the screen (b) is called the key-with-fade-out operation. The above effects on the television screen are achieved by connecting the movable contact of the first switch 26 to its fixed contact 2 and that of the second switch 28 to its fixed contact 1 and by dissolving the black video signal from the first switch 26 and the output signal from the wipe and key switcher 18 in the dissolve switcher 20.
Figure 3 is a diagram showing an example of the practical circuit of the signal processing system 10 shown in Figure 1. In Figure 3, transistors Ql and Q2 buffer the video signal applied to the input terminal 12, while transistors Q3 and Q4 buffer the video signal applied to the ! 20 input terminal 14. Transistors Q6' Q7' Q16~ Q17' Q18 Ql9 form the wipe and key switcher 18, and transistors Qg, Qlo' Qll' Q12' Q13 and Q14 form the dissolve switcher 20.
$he other transistors Q5, Q8 and Q15 are provided for voltage balance or impedance conversion.
]Figure 4 is a block diagram showing an example of circuit for generating the key and wipe switching pulse .~ : . .
:.

1 ~29543 wh-ich is applied through the terminal 22 to the wipe and key switcher 18. In this exc~mple, a wipe (key) generator 32 includes an X1 counter 34, X2 counter 36, Yl counter 38, Y2 counter 40 and speed counter 42. The Xl and X2 counters 34 and 36 are supplied with a clock signal fx applied to a terminal 44 and which has a frequency corresponding to 43 fsc Cfsc: frequency of chrominance subcarrier signal], prepared by multiplying the subcarrier frequency (3.58 MHz) by 4 and counting-down the multiplied frequency b~ 1/3. The Xl and X2 counters 34 and 36 are also supplied at their load input terminals with a signal fy' fed to a terminal 46. This signal fyl consists of pulses of a narrow width which are formed from the half-H rejected horizontal synchronizing - signal. The Y1 and Y2 counters 38 and 40 are supplied at their clock input terminals with a signal fy applied to a terminal 48 and also at their load input terminals with a signal VBP fed to an input terminal 50, respectively. The signal fy is the half-H rejected horizontal synchronizing signal and the signal VBP is the vertical blanking pulse, respectively. The speed counter 42 is supplied at its clock input terminal with a speed pulse signal SP fed to a terminal 52. As hereinafter described in detail, the speed pulse SP determines the wipe speed.
Each of these counter: 34, 36, 38, 40 and 42 comprises an 8-bit counter, so that they produce carry signal at a count of 256. Each of these counters has data ~ ~ .
_ g _~

, . . ; ~ . .

112g5~3 input terminals which receive data input signals of 8 bits.
The Yl and Y2 counters 38 and 40 ànd the speed counter 42 have data output terminals of 8 bits. These counters can be preset to a desired counting condition by applying data desired to be preset to their data input terminals at a time when a load signal having a level "0" is applied to their load input terminals.
As will be described later, the system consisting of Xl counter 34 and Yl counter 38 can operate complementary to the system consisting of X2 counter 36 and Y2 counter 40. Accordingly, for the sake of simplifying the explanation, the system consisting of Xl counter 34 and Yl counter 38 is described, and thereafter the system consisting of X~
counter 36 and Y2 counter 40 will be described in connection with the system consisting of Xl counter 34 and Y2 counter 38.
According to the standard of the ~TSC system, one frame of the video signal includes 525 video lines, each of which contains one horizontal synchronizing pulse, and hence,one field includes 262.5 video lines. ~ow, it is assumed that the speed counter 42 is in its cleared state and the data of 8 bits to the Yl counter 38 is "0".
The vertical blanking pulse V~P applied to terminal 50 has the waveform illustrated in Figure 5a, which comprises a 9H time period having a low level and the following 253.5H having a high level. When the vertical . " . , . ~ .

1 12954~, blanking pulse VBP with the waveform shown on Figure Sa is fed to the Yl counter 38 at its load input terminal, it starts to count the signal fy fed to terminal 48 after the VBP pulse becomes "1". However, in the practical embodiment, the vertical blanking signal VBP is selected to be somewhat, shorter than 9H, for example 8.5H, as shown in Figure 5(b), and thereby the carry from the Yl coun~er is produced within the subsequent, vertical blanking pulse.
` If the data "1" is loaded at the data input terminal of Yl counter 38 by speed counter 42, the carry is produced from the Yl counter 38 at the starting edge of the blanking pulse - as shown in Figure Sc. Further, when the data "2" is loaded, the carry appears at the position before 2H from the front edge of the blanking pulse VBP. Thus, it is noted that if the data "n" (0 _ n _ 255) is loaded at the data input terminal of the Y counter, the carry appears at a position before nH from the front edge of the blanking pulse. Thie carry signal from the Yl counter 38 is applied to a D flip-flop 54 as a clock signal. m is D flip-flop 54 is supplied at its clear input terminal with the vertical blanking signal VBP fed to terminal 50.
Figures 6a, 6b and 6c show the vertical blanking pulse VBP, the carry signal which is produced from the Yl counter 38 when the data "n" is loaded and a Q-output of the D flip-flop 5~, respectively. The flip-flop 54 is triggered by the carry signa~ and reset by the pulse VBP, - . , ~ . .- . ,, . , : ,; ", ~ 3 ~ ~ .. , -: . ~ ,, . .: : : - , -so that a Yl switching signal shown in Figure 6C will be generated from the Q-output of the flip-flop 54. When this Yl switching signal is fed through a co~t~ol circuit 56, a soft edge circuit 58 and an output terminal 60 to the terminal 22 shown in Figures 1 and 3 as the wipe (key) ~witchlng pulse, the picture A is selected during the low level of Yl switching signal and during the high level thereof the picture B is selected in the switcher 18.
Accordingly, such a picture as shown in Figure 7 will be produced on the television screen.
~ ow, if data "n" which increases at every vertical interval is loaded at the data input tenminal of the Y
counter 38, the picture B is expanded or wiped upwards gradually as indicated by the arrows in Figure 7 and finally l$ occupies the whole screen. On the contrary, if the data "n"
which decreases gradually at every vertical interval i9 loaded in the Yl counter, the picture portion A is expanded downwards and finally occupies the whole screen. If the preset data from the speed counter 42 is fixed, the picture in the key state can be produced on the screen.
Next, the operation of Xl counter 34 will be explained with reference to Figure 8. The Xl counter 34 is supplied with 8 bits of data from an exclusive OR-gate 62. Though only one exclusive OR-gate 62 is shown in Figure 4 for simplicity, in a practical form of the circuit there is a num~er of OR-gates corresponding to the , 12 "` 1 t ~ ?~

number of bits, in thi.s embodiment, 8 OR gates. One of the i~p~t terminals of OR-gate 62 is connected to the movable contact of a switch 64 whose one fixed contact 1 is connected to the 8-bits output terminal of a latch circuit 66 and whose other fixed contact 2 is connected to the 8-bits out-put terminal of the Yl counter 38, respectively. Depending on whether a "1" or a "0" is applied to the second inputs of the gates 62, the data from counter 38 is either inverted or uninverted.
~ow, it is assumed that the .input data from speed counter 42 is "0" and the movable contact of switch 64 is connected to i~s fixed contact 1. As described previously, the frequency of the clock signal fx to the Xl counter 34 is selected to be the subcarrier frequency 3.58 MHz 3, The lS reason is that if the subcarrier frequency 3.58 MHz is selected as the clock signal fx the number of pulses to be counted ih IH duration amounts to 227 and it is appa.rent that a number of pulses is lacking for generation of the carry in . the 8 bit counter at every horizontal interval. Therefore, if the frequency of the clock signal fx is selected to be

3.58 x 43 MHz. The number of pulses to be counted in IH
period amounts to 303.3. As a result in order to count 25S pulses in IH duration it is~ëcessar~ that thë~idth of ~h~ load pulse to the Xl counter 34 is selected about 10 ~$
(micro seconds). Thus, it is apparent that the load pulse becomes equivalent to the horizontal blanking pulse. For ; ; : . . :. :, . . , : , ,: . .: . , 95~ ~

, this reason J the input terminal 46 is supplied, as the load input to the Xl counter, with the pulse fy' of a narrow widt~ (shown in Figure 8a) which is prod~ced from the half-H
reject~d H synchronizing signal and which has a low level period of about 10 ~S. This period is equivalent to the period of 49.3 pulses of the signal fx (~igure 8b) having the frequency 3.58 x 3 M~z. Accordingly, the period of signal fy' in high level corresponds to the period of 254 pulses of the signal fx. Thus in the same manner as the Yl counter 38, the carriers can be obtained at the desired position in response to the corresponding preset - value applied to the data input terminal of the Xl counter 34. The carry signal therefrom is fed to a D flip-flop 68 as a clock input si~nal. The flip-flop 68 is supplied at its clear input terminal with the signal fy' fed to the terminal 46, so that it produces at its Q-output terminal an X switching pulse shown in Figure 8d. This X switching pulse is fed through the control circuit 56, soft edge circuit 58 and output terminal 60 to the terminal 22, shown in Figures 1 and 3, as the key and wipe switching pulse. In this case, if the switcher 18 is such that the signal corresponding to the picture A is delivered during the low lever of the X switching pulse and the signal corresponding to the picture B i9 delivered during the high level of the X switching pul~e, on the television screen the picture portion B i9 e~panded to the left gradually as n increases .

.

l129543 gradually with respect to the succeeding H blanking pulses as shown in Figure 9 and finàlly occupies the whole screen,~while the picture portion A~ls expanded to..the right ~radually as n decreases gradually and finally.
occupies the whole screen. .When`~the input data valuè. to the Xl counter 34 is fixed, the key state'where the picture portions A and B are not changed is produced on the screen.
The above explanatioD represent~ the case where the movable contact of swltch 64 i9 connected to its fixed contact 1. If the movable contact of switch 64 is.
turned to its other fixed contact 2, the Xl counter 34 is supplied with the 8 bit input data from the Yl counter 38.
If it is assumed that the output from the speed counter 42 is "0", the 8-bits output datn~from the Yl'counter 38 is loaded at the Xl counter 34 at every:horizontal i.nterval.
Since the Yl counter 38 counta.the horizontal synchronizing pulse fy fed to terminal 4a during the high level perlod of the vertic`al bl~nking signal-shown`in:Figure Sb, the ~' output data from the Yl counter;38 lncreases by 1 àt every H interval. This output data-~from~the Yl-counter 38 is loaded to the Xl counter.-34 at~the~time-~hen the load pulse fy' having horizontal synchornizlng frequency is:applied thereto and then the Xl counter 34 counts up the'clock pulse fx from the load value. Therefore, it is to be noted that the c,eneration of the carry.output from the Xl counter 34 is !shifted t~ the leDt by one pulse fx at every time when ` - 15 ~

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~ 1 2954V

when the Q-outpu~s of the Yl counter 38 increases. I'hat is to say, the output data from the Yl counter 38 is "0" in the first horizohtal interval, so that the carry output from the Xl counter 34 is fallen within the H blanking period. ~ext, when the output data from the Y1 counter 38 becomes "1", in the second hori~ontal interval, the carry output from the Xl counter 34 appears at the position of 1 pulse before the subsequent hori20ntai sync signal which corresponds to the right upper side of the screen. In this manner, when the Yl counter 38 counts 254 H, the carry from the Xl counter 34 appears at the positlbn of 254 pulses before the subsequent horizontal sync signal which corresponds to the left down side of the screen. If the succeeding carry outputs from the Xl counter 34 which are formed in the above manner are used to set the D flip-flop 68 and in turn this D flip-flop 68 is reset by the clear pulse y', the flip-flop 68 produces such X-switching pulses that the picture on the television screen is diagonally divided with the picture portions A and B as -shown in Figure 10.
If the speed counter 42 counts up at a cetain speed, the output from the Yl counter 38 is offset by an amount corresponding the output data from the speed counter 42. Accordingly, at every time when the speed counter 42 counts up, such as "0", 'il".... "n",..... "255"0 the diagonal dividin~ line o~ the television picture moves , towards the top of the screen as shown in Figure 11. On the contrary, w~len the contents of the speed counter 42 is counted down, such as "255",.... ,"n",..... , "1", "O", the diagonal boundary moves downwards. m e 8-bit speed counter 42 is supplied at its clock input terminal with the wipe speed pulse SP fed to the terminal 52 and also at its data input terminal with the key size data through a line 70. When a switch 72 is closed and hence the load input terminal of speed counter 42 is grounded, the content of this speed counter 42 is fixed by the key data and the wipe (key) generator 32 is changed from the wipe generation mode to the key generation mode.
The data output from the speed counter 42 is app~ed to an exclusive OR-gate 74. Only one OR-gate 74 is shown in Figure 4, but in practice the number of OR-gates 74 corresponds to the bit number of the data outputs f:rom the speed counter 42.. A control input terminal 74' is provided for the exclusive OR-gate 74. As well known~ when the state of a control input to the control input terminal 74' is selectively changed to high or low, the speed counter 42 can be operated as up-counter or down-counter, respectively. For example, it is possible in the wipe mode of the composite television picture consisting of the picture portions A and B shown in Figure 12 that if the control input to the exclusive OR-gate 74 is changed, a wipe in the dlrection 76 or 78 ~in Figure 12~ can be ~.

I i! 2g~43 selectively car~ied out.
The exclusive OR-gate 62 is provided with a control input terminal 62' which is operated similar to the control input terminal 74'. The exclusive OR-gate 74 controls the whole operating direction of the wipe generator 32, while the exc:Lusive OR-gate 62 merely determines the direction of the wipe operation in the .
horizontal direction. m e levels of the control signals fed to the control input terminals 62' and 74' are controlled in response to the wipe pattern and key pattern desired.
The wipe (key) generator 32 shown in Figure 4 is also provided with Y2 counter 40 similar to the Yl counter 38, X2 counter 36 similar to the Xl counter 34, exclusive OR-gate 84 similar to the exclusive OR-gate 62, switch 86 similar to the switch 64, D flip-flop 80 similar to D
flip-flop 54 which receives the carry output from the Y2 counter 40, and D flip-flop 82 similar to the D flip-flop 68 which receive the carry output from the X2 counter 36. The 8-bit data output from the exclusive OR-gate 74 is applied directly to the Yl counter 38 but through an inverter 84 to the Y2 counter 40. Thls inverter 84 is used for complementary operation of the Y2 counter 40 relative to the Yl counter 38. That is, if a composite Y switching pulse is formed from the Yl and Y2 switching pulses, there is produced a picture in which the upper and lower picture portions B are wiped over the picture portion .; . .. : ~ . , ~ . .
.:-, . . :.
. ~ :. ;. ::, ; . -: . , 1 1 29~43 A therebetween ~s shown in Figure 13a, or a picture in which the picture portion B between the upper ar.d lower picture portions A i.s wiped over the picture portions A as shown in Figure 13bo Similarly, if the movable contacts of switches 64 and 86 are connected to their fixed contacts 1, respectively, and the ~eve~sof the control inputs to the exclusive OR-gates 62 and 84 are different to each other (a) composite X switching pulse of the Xl and X2 switching pulses produces a picture in which the left and right picture portions B are wiped to the picture portion A therebetween as shown in Figure 14a, or in which the picture portion B
between the left and right picture portions A is wiped over both the picture portions A as shown in Figure 14b. ~ext, if the movable contacts of switches 64 and 86 are connected to their fixed contacts 2, respectively, and the composite switching pulses are produced from the Xl, Yl switching pulses and X2, Y~ switching pulses, pictures can `
be obtained in which the picture portions A and B are wiped as shown in Figures 15a, 15b, 15c and 15d, respectively.
In addition to the foregoi:ng, if the conditions of the control inputs to the exclusive OR-gates 62, 74 .:
and 84 are selectably changed, the switches 64 and 86 are `
controlled and the combination of Xl, X2, Yl and Y2 switching pulses is selected in various manners, various wipe effects shown in Figure 15' can be obtained on the -`
screen.

-- 19 _ ,:

~ i 235q3 In Figure 4, as described previously, there is provided a latch circuit 66 which receives at its data input terminal the 8 bit output data from the speed counter 42 through the exclusive OR-gates 74. This latch circuit 5 66 has a clock input terminal which receives the vertical blanking pulse VBP fed to the terminal 50, and a data output terminal from which the 8 bit data output is fed to the data input terminals of the Xl counter 34 and X2 counter 36 through the fixed contacts l of switches 64 and 86 and the exclusive OR-gates 62 and 84, respectively. The Xl and X2 counters 34 and 36 are loaded with the input data at every load pulse fy' having the horizontal synchronizing frequency. If the latch circuit 66 is omitted, the Xl and X2 counters 34 and 36 are loaded 15 with the data output from the speed counter 42 as it is.
This means that the data of speed counter 42 may be renewed in the picture being reproduced in the television screen that is, during certain horizontal intervals other than the vertical blanking period. For this reason, the 20 boundary between the two picture portions A and B does not become a straight line and the boundary line is terraced,~as shown in Figure 16a. In order to avoid the above disturbance on the screen, the output data from speed counter 42 is latched by the pulse VBP having the vertical 25 synchronizing frequency and held during one field period.
The held data in the altch circuit 66 is used as the preset :
,~ . ...

I~ ~954~

data for the Xl and X2 counters 34 and 36, so that the effect of the steps shown in Figure 16a disappears and hence the boundary line between the picture portions A and B becomes straight, as shown in Figure 16b. In Figure 16, a numeral 90 designates the boundary line at the first field and 92 designates the boundary line at the subsequent field, respectively. As the wipe speed becomes faster the distance between the boundary lines 90 and 92 becomes wider.
As to the Yl and Y2 counters 38 and 40, they are loaded with the output data from the speed counter 42 by the vertical synchronizing blanking pulse VBP, so that there is no , need to provide such a latch circult for the Yl and Y2 counters 38 and 40.
me control circuit 56 shown in Figure 4 is supplied with the Xl switching pulse from the flip-flop 68, the Yl switching pulse from the flip-flop 54, the X2 switching pulse from the flip-flop 82, and the Y2 switching pulse from the flip-flop 80. This control circuit 56 is made of the combination of various gates and produces various typ~s of composite switching pulses in response to a control logic signal Sc applied thereto.
m e soft edge circuit 58 shown in Figure 4 , receives the composite switching pulse from the control circuit 56 has a sharp rising edge as shown in Figure 17a, so that the border line between the picture portions A and B `
is rapidly changed, as shown in Figure 17b. On the ~, ~ ~2~543 contrary, if the-composite switching pulse is formed with a slope in a certain period on the border line as shown ln Figure 17c, the signals corresponding to the picture portions A and B are mixed with each other in that period. Accordingly, the boundary between the picture portions A and B becomes soft in view of visual sense a~d good for the viewer, as shown in Figure 17d. In order to obtain the soft edge effect on the border line, the signals of the picture portions A and B are multiplied in analogue manner in the well-known circuit. Therefore, the construction of the ~onventional circuit becomes complicated and hence expensive. In order to practice the same effect, there is provided with the soft edge circuit 58 which processes the composite switching signal from the control circuit 56 in digital manner. As shown in Figure 18b, the circuit 58 generates a series of switching pulses for the boundary area A + B of the picture portions A and B shown in Figure 18a. It should be noted that the mark to space ratio of the pulses in Figure 18c increases continuously. The mark to space ratio or duty cycle is low at the boundary portion A + B near the picture portion A but becomes high near the picture portion B. Accordingly, due to the visual integrating effect on the screen such a picture with a soft edge effect similar to that by the analogue method. Since the soft edge effect can be performed by the digital processing of the switching signal, the linearity on the boundary portion A + B is improved.

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.

~ 1 29543 In addition to the above soft edge effect in the vertical direction, it is possible that the soft edge effect in the horizontal direction is achieved by the manner similar to the above.
Figure l9a shows a screen in which the boundary portion _ + B between the upper and lower picture portions A and B is subjected to the soft edging. In this case, the boundary portion A + B includes nH lines. A line near the upper picture portion A is switched by the pulse whose duty cycle is low as shown in Figure l9b and the last line of n lines is switched by the pulse whose duty cycle is highest, as shown in Figure l9c. Thus, the boundary portion A + B, which is soft-edged by changing the distribution of the signals corresponding to the picture portions A and B at each line in time, can be obtained on the screen.
Figure 20 is a block diagram showing an embodiment of the soft edge circuit 58. The soft edge circuit 58 shown in Figure 20 consists of two 4-bit counters 100 and 1 102 and an inverter 104. An integrated circuit type S~ 74161 made by Texas Instruments Inc. can be used for each of the above counters. A clock signal fc applied to an input terminal 106 is fed to the first counter 100 at its clock input terminal. If no clear input signal is applied to the counter 100 at its clear input terminal, because of switch 108 being OFF, the counter 100 produces the carry output signal when it counts up the 15th clock pulse. The carry .

,, . ... `. ,,, ! ~ ; , output signal is inverted by an inverter 104 and then fed to the second counter 102 at its clock input terminal and also to the first counter 100 at its load input terminal. When the load input becomes low by the above load input, A, B, C and D inputs of the ~irst counter 100 P Y QA ~ QB ~ QC and QD outputs from the second counter 102. Upon the arrival of the first carry pulse, the second counter 102 produces the output of "0" and hence the first counter 100 is preset by this output "0".
Next, the first counter 100 is preset by the value "1" at the next carry output. In this manner, the first counter 100 is preset up to "15". As a result, at an output terminal 110, which is connected with the carry output terminal of the first counter 100, there is obtained a sub-pulse signal fOUT having a changing period which becomes narrower at the occurrence of each pulse of the clock signal fc. The composite switching signal with the ;~
soft edge effect will be obtained by suitably gating the composite switching signal from the circuit 56 with the pulse signal fOUT
Figure 30 shows a complete circuit diagram of the soft edge effect generator, the upper portion of which corresponds to the circuit of Figure 20 that generates a series of pulses having different mark to space ratios at ~;
each cycle, as described above. m e series of pulses from the terminal 110 are supplied to the lower portion of the : , : : , , ,:-, . : . .~ . - :. : . i :: : :::.: :: :- . :: :.: :. .:: :

1 ~ ~9543 circuit which is mainly composed of a counter 101 and a set of gate circuits. The switching signal from the gate circuit 56 (Figure 4) is supplied to the counter 101 which produces the switching signal A in itself and another S switching signal B delayed by a predetermined time corresponding to the width oE the soft edge region. The switching signals A and B are processed in the gate circuits in the manner shown in Figure 31. The signal F
thus obtained in the circuits is supplied to the clear-terminals CL of the counters 100 and 102 to enable the counters while the signal F is high. Therefore, during the intervals, there will be obtained a series of pulses gradually reducing in mark to space ratio from the terminal `~
110, The series of pulses are supplied to exclusive OR
lS circuit 103 together with the signal C shown in Figure 31 C
so that the signal G shown in Figure 31 G, is gen0rated from the circuit 103. The signal G is further supplied to a NOR circuit 105 together with the signal D shown in Figure 31, so that the circuit 105 produces the signal H shown in Figure 31 H which should be supplied to the output 60. As apparent from Figure 31 H, the signal H has an increasing duty cycle during a front soft edge region Tl and a decreasing duty cycle during a back soft edge region T2.
The signal H thus obtained is supplied to the wipe switcher 18 (Figure 30) and hence the video signals respectively ~;
supplied to the inputs 12 and 14 are finely switched in the ~29543 switcher 18 during the regions in response to the signal H.
The switched video signals are supplied to the television monitor to produce the image picture on the screen and the finely switched areas of the picture are softly edged owing to the integrating effect of human eyes, Further, it is noted that when the switching signal to the counter 101 i,s the horizontal switching signal from the X-counter, the clock signal fc has a relatively high frequency, for example 50 MHZ and the ~;
counters lOl and 102 are constituted by the 4-bit counter.
However, in case of the vertical switching signal from the Y-counter, the clock signal fc has a horizontal synchronizing frequency and the counters 101 and 102 are constituted by the 2-bit counter.
As described above, the elements which form the wipe generator 32 shown in Figure 4 are all digital ;
elements, Therefore, it is desired that the circuit which generates the above signals fy and fy' and VBP from the vertical and horizontal synchronizing signals separated from the composite video signal is also constituted by a digital circuit. Conventionally, in order that the vertical synchronizing signal is derived from the composite synchronizing signal, an anak~ecircuit is employed in which an integrating circuit is used, In the system described below, the vertical synchronizing signal is extracted in digital manner by counting out the 3.58 MHz subcarrier.

: : , : . ~ :. : .. :::., , :,: .. - ,:: , - 1 1295~3 As shown in Figure 21, the waveform of the composite synchronizing signals of the video signal comprises the horizontal synchronizing signal having a pulse width of about 4 ~ seconds and the vertical synchronizing signal having a pulse width of about 30 seconds. Figure 22 is a block diagram showing a circuit which will produce a pulse representing the vertical synchronisation by using the above difference between the pulse widths of the horizontal and vertical synchronizing pulses. Tne vertical synchronizing separating circuit shown in Figure 22 consists of two 4-bit counters 112 and 114 which are connected in a look-ahead connection manner to form an 8-bit counter. A Texas Instrument Inc. S~ 74161 integrated circuit can be employed as the counters 112 and 114. The clock input terminals o~ the first and second counters 112 and 114 are connected to a terminal 116 to receive the subcarrier signal of 3.58 L~Hz fed thereto, and the clear input terminals of the first and second counters 112 and 114 and the count enable input terminals P and T of the first counter 112 are connected to a terminal 118 through an inverter 120 to receive the composite synchronizing signal which is inverted by the inverter 120. The carry output terminal of the first counter 112 is connected to the count enable input terminal P and T of the second counter 114, and a Q7-output terminal of the second counter 114 is connected to an output terminal 122 i.e. the 7-bit . ~

I 1 ~9543 -output signal o~f the 8-bit counter is delivered to the output terminal 122.
According to the circuit described just above, the 8-bit counter counts about 15 pulses of the clock signal having frequency 3.58 MHz during the horizontal synchronizing pulse period, while the counter counts more than 100 pulses during the low level period in the vertical synchronizing pulse period. Accordingly, the vertical synchronizing pulse can be distinguished by detecting the output of the 7th bit of the counter since the count value 15 is indicated by (1111) in binary number and the count value 100 is indicated by (1100010) in binary number.
Figure 23a is a waveform diagram showing the composite synchronizing signal and Figure 23b is a waveform diagram showing a waveform which is derived from the 7th bit output terminal of the counter. m e pulse thus produced is shaped suitably and then can be used as the signal VBP
fed to the terminal 50 of Figure 4.
The ramp signal fed through the terminal 24 to the dissolve switcher 20 shown in Figures 1 and 3 is produced by a ramp signal generator 130 shown in Figure 24. The dissolve switcher 20 differentially combines the video signals A and B fed thereto through the terminals 12 and 14. mis means that the output levels of both the video signals thus combined are always constant. The ,~
- 28 - ;

~29543 picture appearing when the video signals A and B are combined half and half is called a mix ef~ect, while the fade effect is a kind of dissolve effect, in which one of the video signals to be combined is of the black burst form. If the other video signal is gradually emphasized, this effect is called a fade-in, while if the black burst signal is emphasized gradually and finally the screen becomes a blank picture, this effect is called a fade-out. Further, the dissolve period is especially called the "duration". This dissolve effect is controlled by the ramp signal applied to the terminal 24.
The ramp signal generator circuit 130 shown in Figure 24 receives the frame pulse at its input terminal 132. The generator circuit 130 includes a phase comparator 134, a voltage controlled oscillator (VC0) 136 and a feed-back path 138 which form a PLL (phase locked loop) circuit If the frequency of the frame pulse is taken fv, the output frequency of the ~LL circuit is applied to a programmable counter 140 having the frequency dividing ratio of l/n, in which the output frequency of the PLL
circuit is frequency-divided by the duration value n to be set. The frequency-divided signal from the counter 140 is fed to a first signal processor 142 which has a start control input terminal 144 and a stop control input terminal 146 and also output lines lS0 and 152 connected to up and down input terminals of a counter 148 respectively. The - .

', ! . ~ , i .

-7- 129;,43 output signal from the counter 140 is also supplied to the terminal 52 of the speed counter 70 as the speed pulse SP-. A most significant bit (MSB) outputs of the couner 148 is applied through a line 154 to the first signal processor 142. The outputs of the counter 148 are fed to a D-A converter 156 which converts the digital output from the counter 148 into an analogue ramp signal. The analogue ramp signal from the converter 156 is fed through a second signal processor or ramp signal generator 158 and an amplifier 160 to an output te~minal 162. At this output terminal 162 there appears the ramp signal which is applied to the ramp control signal input terminal 24 shown in Figures 1 and 3. .
By use of the ramp signal generator 130, a desired duration from 0 to 255 rames can be set and accordingly it is possible to set the duration from 0 to 8.5 seconds. In the prior art circuit which provides various slopes up to a constant amplitude value, a clock of a.constant frequency, such as the frame frequency, is fed to an n-bit counter, the counter output is D-A
converted, and the analogue output signal therefrom is amplified by an amplifier whose gain is varied in response to the duration. In order to obtain a linear analogue output signal within a desired range it is necessary to use a counter and a D-A converter, having a relatively ;
large number of bits. Further, in order to provide ramp ~ ~ ~954~

signals with various slopes, it is necessary to control the amplification factor of the anlogue amplifier over a relatively wide range. Increasingly steep slopes encounter non-linearity difficulties while the minimum slope is limited by-the number of bits of the counter and D/A converter.
The ramp signal generator 130 shown in Figure 24 overcomes the above defects effectively. With this generator 130, the signal synchronized with the vertical synchornizing signal in the video signal i.e. the frame pulse signal fv is converted to a signal with a frequency of 256 fv by the PLL circuit which consists of the phase comparator 134, the voltage controlled oscillator 136 and the feedback path 138. The frequency 256 fv is divided in the programmable counter 140 by the desired dissolve -~
duration value n and then the divided frequency signal is counted by the 8-bit counter 148. The time TD in which the 8-bit counter 148 counts up 256 pulses is expressed as follows:
n TD = 256 fv ~ 256 = v ' n Accordingly, the time TD is in proportion to the set duration value n. The output from the counter 148 is converted by the D-A converter 156 to the corresponding analogue value, and then amplified by the amplifier 160 having a constant amplification factor. The ramp signal delivered to the output terminal 162 has the gradient corresponding,to the desired duration value.

-~1295~3 If a~ relatively long duration is desired by the control of the dissolve and fade, it would be necessary to increase the number of bits of the counter and D-A
converter. However, the increase in bit number results in increase of cost. To avoid such a defect, the first signal processor 142 is provided. The processor 142 carries out the ordinary operation as long as the duration n satisfies the condition 1 <n ~255, while when n _ 256, the processor 142 operates to produce a ramp signal with the same gradient as that in n = 255 and temporarily halts its operation at n = 128. Thereafter, it will start the - operation thereof in accordance with a re-start command signal.
Figure 25 is a waveform diagram showing an output ramp signal produced at the output terminal 162 of the ramp signal generator 130 by the above operatlon. In the graph of Figure 25, the ordinate represents a voltage le~el in VO and the abscissa represents the time in the frame unit~
In the graph of Figure 25, the solid line curve 164 indicat~s the output ramp signal when the number of bits of the counter and D-A converter are selected to make a gentle gradient of the ramp signal which is substantially s~raight up to a predetermined value n. Over the value n the output voltage is saturated as indicated at 166. By using the first signal process circuit 142, the output ramp signal waveform rises up with the same gradient as that~of n = 255 from a start ~2~9543 position 168, as indicated at 170. At the time when n =
128, the gradient becomes 0 and hence the output voltage becomes constant, as shown at 172. The output ramp signal waveform starts to rise again at a position 174 in response to the re-start co:mmand signal and then arrives at the prede~ermined saturation voltage, as indicated at 166. By this system, the duration of the dissolve will be expanded over a wide range using an 8-bit counter 140. It is of course possible for the various examplified values to be changed and also for the frequency of the clock pulse to be selected other than the frame frequency of 30 Hz.

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~2~5~3 Figure 26 is a block diagram showing a practical embodiment of the first signal processor 142 s'hown in Figure 24. In Figure 26, the start command signal is fed to a terminal 144 and the stop command signal is fed to a terminal 146, respectivelyn Strictly it is incorrect that this latter signal is called the stop command signal.
As described later, the stop command signal is used for starting the count-down operation of the counter 148 from the saturation level 166 to the zero level 162 in Figure 25.
The frame pulse is applied to a terminal 180, the speed pulse from the programmable counter 140 is applied to a terminal 182. and a reset signal is applied to a terminal 184, respectively. The signal processor 142 includes five D flip-flop 186, 188, 190, 192 and 194 and two AND-gates 196 and 198. The output from the AND-gate 196 is fed through the lead line 150 to the up-count input terminal of t'he , counter 148, and the output from the AND-gate 198 is fed through the lead line 152 to the down-count input '~
terminal of the counter 148. The,128 count is most significant but output from the 8-'bit counter 148 is fed through the line 154 to the clock input terminal of the flip-flop 1940- ~ext, the operation of the circuit s'hown in Figure 26 will be explained with reference to Figure 25.
~ow assuming that several parameters, suc'h as duration and start time, are stored~ in a computer (not shown~, a start signal having high level ~ is applied to the input ?

. , ' ` ` '' ` . .: . ' . ' -Z ~295~3 144 at the time preset by the computer. Therefore, the "Q"
output signal of the flip-flop :L86 will be obtained at the time when the frame pulse i5 supplied -to the clock terminal CK thereof, and thus the start signal SRT will be synchronous with the frame pulse. Further, the "Q"
output signal from the flip-flop 186 is applied to the D-terminal of the flip-flop 190. in which the former signal is in synchronism with the speed pulse supplied to the clock terminal of the flip-flop 190. The synchronizing "Q" output signal from the flip-flop 190 is further supplied to the AND gate 196, and thereby the gate 196 is opened to supply the speed pulse to the up-terminal of the counter 148~ ;
When the counter 148 finishes counting the 128 speed pulses, the MSB (most significant bit) output 158 of the 8-bit counter 148 becomes "1". The MSB output 158 is supplied to the clock terminal CK of the flip-flop 194, so that the Q-output thereof generates the clear signal "1", because an input signal having high level "1"
from the "128" counts to the restart point is supplied to the D-input terminal 200 under control of the computer.
The clear signal is supplied to the clear terminal CK
of the flip-flop 186, so that the Q-output thereof becomes "0". As a result of the "0" outputs of the flip-flops 25 186 and 190/ the speed puIse SP from the counter 140 is not applied to the counter 148, and hence the output from .

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1 12g5~3 the D-A converter 156 keeps constant, as indicated by the broken line 172 of Figure 25.
At the restart point 174 the reset signal PST from the computer is supplied to the clear terminal CL of the flip-flop 194, so that the Q-output thereof becomes "0".
Accordingly, the Q-output o~ the flip-flop 186 again becomes "1" at the time when the subsequent frame pulse fv is applied to the clock terminal CK of the flip-flop 186.
The Q-output of the flip-flop 190 also becomes "1" owing to the Q-output "1" of the flip-flop 186. As a result, the speed pulse is again applied to the up-terminal of the counter 148 and hence the output from the ~/A converter 156 goes up linearly. Thus, it is apparent that when the counter 148 counts to tis full scale, the output of the D/A converter 156 reaches the saturation level 166.
Then, the counter 148 generates a carry output which is used for resetting the start signal SRT~
On the contrary, when the output signal obtained from the terminal 162 is dissolved from the saturation level to the zero level, the stop command signal is supplied to the input terminal 146 and the circuit comprising the flip-flops 188 and 192 and the AND gate 198 operates in the same manner as the circuit of the flip-flops 186 and 190 and the AND gate 196~ However, it is noted that the speed pulse from the AND gate 198 is supplied to the down-terminal of the counter 148O In this case, , .

;, 1~295~1~

the flip-flop 194 is formed of an integrated circuit of the SN 7474 type, flip-flops 186 and 188 are each formed of an integrated circuit of the SN 74175 type, and flip-flops 190 and 192 are each formed of the S~ 74175 type, similarly.
The counter 148 shown in Figure 24 consists of an octal reversible counter which is made by connecting two integrated circuits of SN 74193 type in cascadeO The output terminal of the counter 148 is aonnected to the input terminal of the octal D-A converter 1S6 whose analoyue output is processed by the second signal processor 158 and then delivered through the amplifier 160 to the output terminal 162.
If the level of the video signals A and B fed to the dissolve switcher 20 are controlled as shown in Figure 27a by this dissolve switcher 20 and if the dissolve switcher 20 is controlled by a ramp signal with the waveform shown in Figure 27b, the video signals will be switched in a time period T from a time tl when the dissolve operation starts and to a time t2 when the dissolve operation terminates. Accordingly, in the period T the signals A and B are mixed with a voltage ratio of the gradient of the ramp signal and the levels of the signals A and B are changed gradually from high to low and from low to high, respectively. However, it is noted t~at the duration period T gives an impression of a shorter ... . . ..... . . .

, - ,:: :, ' ' ~ '' .. :
., - . , ~
.. . .`i , `~:

~9s~
-dissolve than the actual set time duration T. The reason is that a lower portion x of the ramp signal (up to a voltage level vl) and an upper portion y of the ramp signal (up to a voltage level v2) are dead zones where no movement is sensed by a viewer's eyes. As a result, the time period in which the viewer can perceive the dissolve effect becomes a shorter time period T' as shown in Figure 27b.
The second signal processor 158 is provided to make the set time period T equal to the time period T' in which the viewer recognizes the effect on the screen to improve the property of the dissolve operation. For this purpose the signal processor 158 operates such that the whole amplitude V' of the ramp signal is made V-(Vl+V2) as shown in Figure 28 by a solid line. That is the ramp signal is increased by the voltage level Vl at the start time tl and at the same time t2 the ramp signal is decreased by the voltage level V2 to coincide the time period T with the effective time period T'.
Figure 29 shows a circuit diagram of th~ second signal processor 158, in which the output from the D/A
converter 156 is added to an input 202 of operational amplifier 201 consituting the amplifier 160, the output terminal of which is connected with the output 162.
The processor 158 is provided with a first elec-tronic switching device 218 having two switch elements Sl an~S2 ~ ~ .

~ ' ' , ' . . ~ ! ' . ' . ` . ,~

which are controlled by output YO and Yl from a second switch device 219. The'~ovable arms" of the switch elements Sl and S2 are connected through respective resistors with the input of the amplifier 201. while the "fixed contacts" thereof are connected with D.C. voltage terminals 224 and 220, to which the respective DC voltages corresponding to the voltage levels Vl and V2 are supplied.
The second switching device 219 includes four switch elements TO, Tl, T2 and T3 having a first set of terminals YO, Yl, Y2 and Y3 and a second set of terminals AO-BO, Al-Bl, A2-B2 and A3-B3, and which is controlled by a control signal from terminal 216. The terminals of the first set are connected with respective ones of the terminals of the second set while the control signal being "1", while the terminals of the first set are connected with resp~ctive ones of the terminals of the second set while the control signal being "O".
When the control signal is high ("1") and the start signal is supplied to a start command signal input terminal 204, the start signal is supplied through the switch element T3 to clock terminal CK of D-type flip-flop 211, and thereby the Q-output of the flip-flop 211 becomes "1" which is further supplied through the switch element TO to control terminal Cl of the switch element Sl.
Accordingly, the switch Sl becomes ON and hence the voltage at the terminal 224 is applied to the input of the amplifier `:~
~ 39 -:

. . ~ . , . . , - . .

201. As a result, the output voltage at the output 162 rapidly rises up by the voltage Vl. From this condition, the output signal from the D/A converter 156 will be gradually applied to the input of the amplifier 201, so that the voltage at the output 162 rises linearly as shown in Figure 28.
When the counter 1~8 counts to its full scale, that is. the output of the D/A converter reaches the saturation level at the time t2. the counter 148 generates the carry signal to supply the latter signal to a terminal 208. The carry signal is further supplied through the switch T2 to clock terminal CK of the flip-flop 213, so that the Q-output of the flip-flop 213 becomes "1" owing to high level at the D-terminal thereof. The Q-terminal of the flip-flop 213 is applied through the switch Tl to control terminal C2 of the switch S2. As a result, the switch S2 becomes O~ and hence the voltage at the terminal 220 is applied to the input of the amplifier 201. Then. the output voltage appeared at the output 162 rapidly goes up by the voltage V2 at the time t2. as shown in Figure 28.
Thus. the dissolve signal shown in Figure 29 is formed in the circuit 130 and the dissolve operation by the signal is performed in the dissolve switcher 20.
On the contrary, when the dissolve operation shown in the dot-dash line of Figure 28 is desired. the . : . .: , . , :: - . ,, - .: ~ . ~: .. .

-11295~3 - control signal from the terminal 216 becomes low. Therefore, the terminals of the switches TO to T3 are switched over the respective terminals AO to A4, so that the Q-outputs of the`flip-flop 211 and 213 having high levels at the initial time tl are respectively supplied through the switches TO and Tl to the control terminals C1 and C2 of the switches Sl and S2. As a result, both the switches Sl and S2 become ON and hence both the voltages Vl and V2 from the terminals 220 and 224 are supplied to the input of the amplifi~r 201.
When the start signal (stop command signal) is applied to terminal 206 at the time tl, the former signal is supplied through the switch T3 to the clock terminal CK of the flip-flop 211 and hence the Q-output thereof becomes "0" which is further supplied through the switch Tl to the control terminal C2 of the switch S2. As a result, the switch S2 becomes OFF and hence the output voltage at the terminal 162 decreases rapidly by the voltage V2 at the time Tl.
Thereafter. the output voltage from the D/A
converter is linearly decreasing until the time t2. When the counter 1~8 is counted down until "", it generates a borrow signal which is supplied to a terminal 210.
The borrow signal is supplied through the switch T2 to the clock terminal CK o~ the flip-flop 213 and thereby the Q-output of the flip-flop 213 goes down to the low level "O"

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: - . . . :

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11295~3 which is further supplied through the switch TO to the control terminal Cl of the switch Sl. Consequently, the switch Sl becomes OFF, so that the voltage from the terminal 224 applied to the input of the amplifier 201 is cut-off. Accordingly, the output voltage at the output terminal 162 rapidly decreases by the voltage Vl at the time t2.
Thus as described above, a ramp signal as shown in Figure 28 is obtained which is controlled in the digital manner.

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Claims

1. A video signal processing circuit for producing a dissolve signal to control dissolving of a video signal by control of the amplitude of said video signal in a gain control circuit which is controlled in response to a control signal, said video signal processing circuit comprising:
means for generating a clock signal having a frequency which is synchronous with a vertical synchronizing signal of said video signal;
means for frequency-dividing said clock signal by a preset value n;
means for counting said frequency-dividing clock signal during at least one vertical period of said video signal;
means for converting the digital output of said count-ing means into a corresponding analogue signal, whereby said analogue signal is supplied to said gain control circuit as said gain control signal; and first signal processing means connected between said frequency-dividing means and said counting means for pre-venting the supply of said clock signals during a predetermined interval, when the dissolve duration in said circuit is set at a value in excess of a predetermined period of time.

2. A video signal processing circuit according to claim 1, in which said counting means comprises an up-down counter, the arrangement being such that said clock signal is select-ively supplied in a manner to cause up or down counting of said counting means in dependence upon the direction of dissolve.

3. A video signal processing circuit according to claim 2, in which counting means has up and down counting direction control terminals and said first signal processing means comprises first and second gate circuits connected to said up and down terminals of the counting means for supplying said clock signal thereto in response to gate signals applied to the gate circuits.

4. A video signal processing circuit according to claim 3, in which said first signal processing means further comprises a first means for synchronizing said gate signals with at least a vertical synchronizing signal of the video signal.

5. A video signal processing circuit according to claim 4, in which said first signal processing means further comprises a second means connected with said first synchroniz-ing means for sychronizing said gate signals with said clock signal.