CA1131363A - Pcm signal transmitting system - Google Patents
Pcm signal transmitting systemInfo
- Publication number
- CA1131363A CA1131363A CA338,114A CA338114A CA1131363A CA 1131363 A CA1131363 A CA 1131363A CA 338114 A CA338114 A CA 338114A CA 1131363 A CA1131363 A CA 1131363A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
- G11B20/1806—Pulse code modulation systems for audio signals
- G11B20/1809—Pulse code modulation systems for audio signals by interleaving
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- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Error Detection And Correction (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
- Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
Abstract
ABSTRACT OF THE DISCLOSURE
A PCM (pulse code modulation) signal transmission system processes sequentially transferred digital infor-mation words including two error correcting words consisting of a parity code word and a b-adjacent code word and adds them to the digital information words, time-interleaves each of the information words and its error correcting words in the block into time-interleave blocks distributed over a predetermined time, adds an error detecting code to at least one of the time-inter-leaved blocks, and transmits at least one time-interleaved block and error correcting code associated therewith.
Method and apparatus for de-intervleaving and error correction based on the three appended codes are included.
A PCM (pulse code modulation) signal transmission system processes sequentially transferred digital infor-mation words including two error correcting words consisting of a parity code word and a b-adjacent code word and adds them to the digital information words, time-interleaves each of the information words and its error correcting words in the block into time-interleave blocks distributed over a predetermined time, adds an error detecting code to at least one of the time-inter-leaved blocks, and transmits at least one time-interleaved block and error correcting code associated therewith.
Method and apparatus for de-intervleaving and error correction based on the three appended codes are included.
Description
BACKGROU~.~D OF THE INVENTION
Field of the Invention The present invention relates g~nerally to a PCM
signal transmission ~ystem, and is directed more particularly èO a method and apparatus for processing sequentially transferret digital information wor~s.
Description of the Prior Art British Patent ~o. 1,481,849 disclo~es a system in which an error detecting s~gnal i~ added to each signal.-A plurality of ~uch signals, including the added erros detecting signals, form a block. An error correcting signal, such as a parity ~i~nal, is added to each bloc~. When an error is detected in one information s~gnal in one block at the recei~ing end, all bits of the signal containing an error are set to zero and the remaining correctly
Field of the Invention The present invention relates g~nerally to a PCM
signal transmission ~ystem, and is directed more particularly èO a method and apparatus for processing sequentially transferret digital information wor~s.
Description of the Prior Art British Patent ~o. 1,481,849 disclo~es a system in which an error detecting s~gnal i~ added to each signal.-A plurality of ~uch signals, including the added erros detecting signals, form a block. An error correcting signal, such as a parity ~i~nal, is added to each bloc~. When an error is detected in one information s~gnal in one block at the recei~ing end, all bits of the signal containing an error are set to zero and the remaining correctly
2-~ ~ .
.
~1 31363 received signal and the error correcting signal in the block are added by modulo 2 addition to provide a correct signal to replace the one containing an error. When more than 2 signals in one block contain errors due to, for example, burst errors which typically endure for longer than~the transmission time of one word, the resulting error in t~o or more contiguous words in a block cannot be corrected.
In an error correcting system applied in the field of computers as disclosed in U.S. Patent No. 3,697,948, an encoding and decoding system provides information as to which bytes are in error and extends the error correcting capability of the system to two bytes of data containing error. The transmitted message comprises k bytes ( o,Dl>D2,~~~~~Dk_l), each having b bits, plus two check bytes Cl and C2, each having small b bits.
The message is encoded by computing the check bytes accordin~ to the following relationship:
Cl = I Do~ I Dl + ---- ~3 I Dk 1 C2 ~ I Do 63 T Kl e3 T2D~ 63 ---- 63 Tk lDk 1 Wherein I is an identity matrix and T, T2, ---- Tk 1 are distinct non-zero elements of a Galois Field (2b), wherein the indicated multiplication and addition are Galois Field defined operations, and wherein b is an integer < 1 and k is an integer 2 > k > 2b. Cl is a simple parity code and C2 is a b-adjacent code.
A decoder is effective to recover the data without error when not more than two of the bytes in the message are in error no matter how many bits in the two bytes are
.
~1 31363 received signal and the error correcting signal in the block are added by modulo 2 addition to provide a correct signal to replace the one containing an error. When more than 2 signals in one block contain errors due to, for example, burst errors which typically endure for longer than~the transmission time of one word, the resulting error in t~o or more contiguous words in a block cannot be corrected.
In an error correcting system applied in the field of computers as disclosed in U.S. Patent No. 3,697,948, an encoding and decoding system provides information as to which bytes are in error and extends the error correcting capability of the system to two bytes of data containing error. The transmitted message comprises k bytes ( o,Dl>D2,~~~~~Dk_l), each having b bits, plus two check bytes Cl and C2, each having small b bits.
The message is encoded by computing the check bytes accordin~ to the following relationship:
Cl = I Do~ I Dl + ---- ~3 I Dk 1 C2 ~ I Do 63 T Kl e3 T2D~ 63 ---- 63 Tk lDk 1 Wherein I is an identity matrix and T, T2, ---- Tk 1 are distinct non-zero elements of a Galois Field (2b), wherein the indicated multiplication and addition are Galois Field defined operations, and wherein b is an integer < 1 and k is an integer 2 > k > 2b. Cl is a simple parity code and C2 is a b-adjacent code.
A decoder is effective to recover the data without error when not more than two of the bytes in the message are in error no matter how many bits in the two bytes are
3-~ 3~ 3 in error. Pointers are required to indicate the two bytes containing errors. In the absence of pointers or in the pre~ence of a single false pointer, the decoder is effect-ive to recover the data without error when not more than a single byte is in error no matter how many bits may be in e~ror in the single byte. When more than 3 bytes in k bytes simultaneously contain errors due to burst error or the like during the data transmission, such errors cannot be corrected.
OBJECTS AND SUMMARY OF THE INVENTION
-Accordingly, an ob~ect of the present invention is to provide a PCM signal transmitting system which converts analog audio signals into digital signals and transmits them as PCM signals.
It is another object of the present invention to provide a PCM signal transmitting syatem which uses a VTR as an apparatus for recording and reproducing the PCM eignals.
According to the present invention, since the data is interleaved before transmission, a burst error resulting from a signal dropout appearing in a transmission system such as, for example, in a VTR, is dispersed over tim~ and thus, when de-interleaved on reception, produces no more than a random error in the de-interleaved signal. Such random error can usually be corrected using error correcting codes appended to information words in the signal. By providing error correction using a parity and a b-ad~acent code, error~ within two words in a de-inter-leaved block can be corrected. A PCM signal transmission system according to the present invention thus provides I li31363 improved error correction capability with less chance of failing to detect an error.
According to the present invention, a PC~. signal transmission system may be used in a signal recording and reproducing apparatus in which7 for example, a 2-channel stereo signal is pulse code modulated and the resulting PCM signal is recorded and reproduced by a VTR.
According to this invention, a block of information words is defined having bits in rows and columns. A
first parity signal consi,sting of vertical parity bits is formed from a plurality of rows of the PCM signal, and a second parity signal is formed by supplying a predetermined bit of the PCM signal to a b-adjacent coder. An adjacent code or b-adjacent code has a symbol on GF (2b) (which is a Galois Field having 2b elements) and is a general name for codes which can correct errors in bit groups.
Examples of b-adjacent codes include the Hamming code and the Reed-Solomon code and so on. In the following example, a matrix code multiplied by a generating matrix T is used as a eode symbol of a b-adjacent signal. A
generating matrix T corresponding to the d'th order of a generating polynomial G (x) is expressed as follows:
G(x) - ~ O gi xi , gO = gd = 1 ~~~~~~ I go ~
`~ I gl T ~ ~ d-l ~ gd-l J ~' of (d x d). 1~ this case, Id 1 is aunit matrix sf (d-l)x~d-l).
If the informatl~n words containin~ error~ can be identified, errors in a second word in a block can be corrected using the b-adjacent signal. To detect the position of errors, an error detecting code produces a pointer whlch is added after interleaving to the trans-mitted signal which contains PC~I interleaved from a plurality of time-separated information words with their first and second error correcting codes.
According to the invention, errors in two infor-mation words can be completely corrected. If an error i8 not identified by a pointer, an error in one word can be corrected in a block. Since the PCM signal is reconstructed by time de-interleaving word by word from each of a plurality of ~ime interleaved blocks to form one block, when the correction of errors is impossible, words in error can be replaced by an average value of correc, words before and after the uncorrectable word.
Further, since the word in which an error exists is indicated by a pointer, a simple encoder and decoder can be used.
More particularly, there is provided:
A method of processing sequentially transferred digital information words, said method comprising the steps of:
forming a block of a plurality of said information words;
forming a parity error correcting word corresponding to said block and adding said parity error correcting word to said block;
forming a b-adjacent error correcting word correspond-ing to said block and adding said b-adjacent error correcting word to said block;
time-interleaving each of said information words and said parity and b-adjacent error correcting words in said block ~1~1363 into time-interleaved ~locks distributed over a predetermined time;
adding an error detecting code to at least one of said time-interlea~ed blocks; and transmitting said at least one time-interleaved block and said error detecting code associated therewith.
There is also provided:
An apparatus for processing digital information words comprising:
means for forming a block of a plurality of said in-formation words;
means for forming and adding a parity error correcting word and a b-adjacent code error correcting word to said block;
means for time-interleaving each of said information words and said error correcting words in said block into time-interleaved blocks distributed over a predetermined time means for adding an error detecting code to at least one of said time-interleaved blocks; and means for transmitting said at least one time-interleaved block and said error detectlng code associated there-with.
There is ~urther provided:
An attachment for r)ermit~inF; a-video tape recorder to record and reproduce at lesst one high quality audio signal on a video tape, comprising:
means for converting 8aid audio signal to a plur~lity of multi-bit diE~ital words, each of said digital words containing a representation of a characteriætic of said audio signal at a discrete point in time;
means for defining a block consisting of a fixed plurality of said digital words;
means for producing a first error correc~in~
word for said block and for adding said first error ~1363 orrecting word to said block;
means for producln~ a second error correcting word for said block and for adding said second error correcting word to said block;
. said first and second error correeting words having a characteristic which permit~ correction of errors in first and second digital words in said block if said irst and second digital words which contain errors are identified and which permits correction of errors in a single digital word in said block if identl-fication of digital words containing errors is not possible;
means for time-in~erleaving each of said digital words and said firs~ and second error correcting word~ from said block each ~nto different time inte-;leaved blocks;
mean~ for produclng an error detecting word for each time-interleaved block and for adding each said error detecting word to its respective time interleaved block;
and means for transmitting said time interleaved block including said error detectin~ code as a serial si~nal including at least horizontal synchronizin~ pulses to a ~Jideo tape recorder for recording therein.
The above, and other objects, features and advantages of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. l~s a signal recording and reproducing apparatus which includes a PCM signal transmitting system according to an embodiment of the present invention;
~ -6b-Fig. 2 is a block diagram showing an encoder suitable for use in the apparatus of Fig. l;
Fig. 3A is a graph showing the time relationship of signals to which reference will be made in describing the time interleaving of data;
- Fig. 3B is a graph showing an alternative method of appending a parity code to a set of data signals;
Fig. 4 is a block diagram of an adjacent coder suitable for use in the encoder of Fig. 2;
Fig. 5 is a block diagram of another adjacent coder suitable for use in the encoder of Fig. 2;
Fig. 6 is a block diagram of a decoder suitable for use in the embodiment of Fig. l;
Fig. 7 is a block diagram of a read only memory used as a m~ltiplier;
Fig. 8 is a block diagram showing another multiplier and to which reference will be made in describing the operation of the apparatus in Fig. l; and Fig. 9 is a block diagram of another embodiment of a decoder suitable for use in the apparatus of Fig. 1. i 5 DESCRIPTION OF THE PREFEP~RED EMBODIMENT
Referring now to Fig. 1, a PCM signal processing adapter circuit i8 shown connected to a video input terminal 2i and a video output terminal 20 of a helical scan VTR 1 (video tape recorder). VTR 1 is normally used for recording and reproducing a video signal. With the PCM
signal processing adapter circuit of the present invention, VTR 1 is capable of recording and reproducing a PCM-encoded audio signal of extremely high fidelity.
~5'~
Input terminals 3L and 3R receive left and right channel analog stereo audio signals, respectively, which are supplied through low pass filters 4L and 4R to sample and hold circuits 5L and 5R. Sampled outputs of sample and hold circuits 5L and 5R are supplied to A-D converters 6L and 6R to be PCM encoded into multi-bit digital information words, of which there is one word for each sample. The encoded outputs of A-D converters 6L and 6R
are supplied to an encoder 7. Encoder 7 adds parity signals, compresses the time base and tLme interleaves the resulting PCM signal as will be described. The output of encoder 7 is a serial signal which is applied to a synchronizing signal mixer circuit 8. A reference clock oscillator 9 supplies reference clock signals ~o a pulse generator circuit 10 which produces sampling pulses for control of sample and hold circuits 5L snd 5R, clock pulses for control of A-D conversion in A-D converters 6L and 6R, control signals for encoder 7, and composite synchronizing signal~ for addition to the serial PCM
signal encoder 7 in synchronizing signal mixer circuit 8.
The output from synchronizing signal mixer circuit 8 is fed to video input terminal 2~ of VTR 1 for recording in a conventional matter on a video tape (not shown).
The PCM signal reproduced by VTR 1 is delivered through video output terminal 20 and a clamp circuit 11 ~o a data and synchronizing signal separator circuit 12.
The separated composite synchronizing signal is supplied to a pulse generator circuit 13, and the separated PCM
Eignal is supplied to a decoder 14. Decoder 14 performs time base expansion, error detection and error correction on the PCM signal and applies the resulting digital signals ~1~1363 to D-A conv2r~2rs 15L and l5R. Analog outputs of D-A
converters 15L and 15R are applied through low pass filters 16L and 16R to output terminals 17L and 17R, respectively. Pulse generator circuit 13 pro~ides clamp pulses for clamp circuit 11, control signals for data and synchronizing signal separator circuit 12, control signals for decoder 14 and clock pulses for D-A converters 15L and 15R in response to the composite synchronizing signal applied thereto from data and synchronizing signal separating circuit 12.
Referring to Fig. 2, encoder 7 of Fig. 1 is shown in detail. PCM signal sequences SL and SR (series coded) from A-D converters 6L and 6R are supplied to a distributor circuit 18 wherein the left and right channels are each divided into 3 channels to result in a total of ' 6 channels. For example, the PCM signal sequence or series SL which c~ntinues as L 2~ L 1 Lo~ Ll, L2, L3,----and the PCM signal series SR which continues as R 2~ R 1 Ro~ Rl, R2, R3,---- are distributed into a first channel PCM signal series SLl which contains every third channel from the left source (L 2 Ll, L4,---), a second channel PCM signal series SRl also containing every thi d channel from the right source (R 2 Rl, R4,----), a third channel PCM signal qeries SL2 (L 1~ L2. L5,---), a fourth channel PCM signal series SR2 (R 1~ R2. R5,----~, a fifth channel PCM signal series SL3 (L~, L3, L6, )?
channel PCM signal series SR3 ~Ro~ R3, R6,~
One word in the PCM signal series in each channel is supplied to a modulo 2 adder 19 to produce a first parity signal series SP and, word by word, to an adjacent channel coder 20 to produce a second parity signal seriesS~.
11;~1363 The PCM signal series SRl, SL2, SR2, SL3 and SR3 and first and second parity signal series SP and SQ are respectively supplied to delay circuits 22a, 22b, 22c, 22d, 22e, 22f and 22g. Delay circuits 22a to 22g ~ime interleave the six PCM signal series and the first and second parity signal series by providing delays of d, 2d, 3d, 4d, 5d, 6d and 7d (word time), respectively, when a unit delay amount is taken as d (word time).
Delay circuits 22a to 22g may be any suitable circuits, such as, shift registers or RAM (random access memory).
Delayed PCM signal series SRll, SL12, SR12 SL13 13 and the delayed parity signal series SPl and SQl from delay circuits 22a to 22g, respectively, as well as undelayed signal series SLl, are applied to inputs of a mixer or parallel-two-serial converter 24 and a CRC
(cyclic redundancy code) code generator 23. CRC code generator 23 produces a CRC code SC corresponding to the eight words at its inputs to thereby provide a pointer signal series which is applied to an input of mixer 24.
The CRC code ~s an error detecting code using a cyclic code, and CRC generator 23 is a modulo 2 subtractor which employs a generating polynomial.
Mixer 24 converts its parallel inputs to a serial signal transmitted one bit at a time to a time base compression circuit 25. Time base compression circuit 25 compresses the time base of the serial signal at its input in order to provide a serial signal series having data absent periods properly timed to permit the addition of synchronizing signals. As shown on Fig. 3A, a horizontal period between horizontal sy~chronizing signals HD contains six PCM data wordsj two parity words, and ,~s ~
1~31363 one ~RC or pointer signal word. The six-word PCM signal, two-word parity signal and one-word CRC code are supplied to synchronizing signal mixer circuit 8 (Fig. 1) wherein horizontal synchronizing pulses HD are added in the data absent periods.
- Fig. 3B shows zn alternate format for including the adjacent channel PCM Ql 21d in the serial signal.
In the example of Fig. 3A each word may have 14 bits.
In Fig. 3B, each word contains 16 bits. The 14-bit adjacent-channel code Ql 21d is split into seven 2-bit portions (shown cross hatched~ which arP inserted as the final 2-bits of each of the six data words and the parity word, as shown in Fig. 3B. In this case, the 6ignal comprises six PCM signal words, one parity signal word and one CRC code word. Thus, the signal sequence of Fig. 3B includes seven 16-bit words and one 14-bit word rather than the nine 14-bit words of Fig. 3A.
The following description provides the basis for understanding error correction by encoder 7 and decoder 14 of the present invention. As an example; let it be assumed as follows. When six words Ll, Rl, L2, R2, L3 and R3 are received from distributor circuit 18, first and second parity signals Pl and Ql are ~enerated by modulo 2 adder 19 and ad;acent channel coder 20, as foll~ws: , 1 Ll ~ Rl ~ L2 ~ R2 ~ L3 ~ R3 Ql = T6Ll ~ T5Rl ~ T4L2 ~ T3R2 ~ T2L3 ~ TR3 A generating matrix T is a certain d'th order generating polynomial G(x) which prevents the same value from appearing in T, T2, T3, T4, T5 and T6 of the above ~S ~
13~;3 expression. ~her~ second parity si~nal Ql is required to provide error correction for six words, d > 3 must be satisfied. When d = 3, if the generating polynomial G(x) is a reduced polynomial on GF(2) (Galois Field), (T, T2, T3, T4, T5, T6, T7) do not contain the same value. This reduced polynomial is G(x) = 1 ~ x ~ x3, so that T may be expressed as follows:
T = 1 0 1 ~ 1 0 .
Since (T, T2, T3, T4, T5) are all necessary for the present case, it is not always necessary that the generating polynomial G(x) be a reduced polynomial.
Further, when the second parity signal is provided by multiplication of one word of the respective P~ signal, which is expressed as a vector, by the generating matrix, the bit length of one word should be taken in~o consideration.
As an example, when one word is 14 bits, the following (14 x 14) generating matrix T is used.
o o _________ o g'O ' T ~ 1 0 -~~~~~~~~ gl T"""`.
,0 0 ----~ gl3 where G(x) - gO + glx + g2x + --~~~ gl3x gl4 the 14th generating matrix and (gO - gl4 = 1) as in the above case. Also, when one word is 14 bits, ~ second parity signal of 3 bits may be provided from the result ,3 ~
11~1363 obtained by dividing 14 bits by 3 bits and the generating (3 x 3) matrix. In this case, since 14 bits cannot be evenly divided by 3, a dummy bit of either "0" or "1" is added at the end to make one word containing 15 bits.
The dummy bit need not be transmitted.
As described above, when one word has a certain number of bits and a plurality of channels form one block, the realizability of the encoder and the decoder (the construction of its control circuit, memory capacitor, cost, etc.~ depends upon the form of the generating matrix which is selected. The first parity si~nal series SP can be produced in parallel by adder 19 as in the encoder shown in Fig. 2, or in series by a shift register of one word length and one exclusive OR gate. The syndrome, or error correcting pattern> can be formed by the first parity signal series SP in a similar manner. Thus, simple circuits are sufficient for producing the first parity signal series SP. Formation of ~he second pari~y signal series SQ in adjacent channel coder 20 and error correction thereby in decoder 14 (Fig. 1) are a greater problem. The memory for time base compression (or expan-sion) and interleave ~or de-interleave) depends on the method chosen for producing this signal. Optimization is described for a system in whlch a block is formed of six 14-bit words of PCM data and first and second 14-bit parity signals.
The following table shows the ways in which a system which permits correction of errors in two channels snd one word can be divided into separate blorks.
1~313f~i3 Number of Number of Magnitude of Number of Division ~n) Divided Bits (m) Bits Q
1 14 14x14 (=196) 14 2 7+7 7x7 (=49) 14 3 5+5+5 5x5 (=25~ 15
OBJECTS AND SUMMARY OF THE INVENTION
-Accordingly, an ob~ect of the present invention is to provide a PCM signal transmitting system which converts analog audio signals into digital signals and transmits them as PCM signals.
It is another object of the present invention to provide a PCM signal transmitting syatem which uses a VTR as an apparatus for recording and reproducing the PCM eignals.
According to the present invention, since the data is interleaved before transmission, a burst error resulting from a signal dropout appearing in a transmission system such as, for example, in a VTR, is dispersed over tim~ and thus, when de-interleaved on reception, produces no more than a random error in the de-interleaved signal. Such random error can usually be corrected using error correcting codes appended to information words in the signal. By providing error correction using a parity and a b-ad~acent code, error~ within two words in a de-inter-leaved block can be corrected. A PCM signal transmission system according to the present invention thus provides I li31363 improved error correction capability with less chance of failing to detect an error.
According to the present invention, a PC~. signal transmission system may be used in a signal recording and reproducing apparatus in which7 for example, a 2-channel stereo signal is pulse code modulated and the resulting PCM signal is recorded and reproduced by a VTR.
According to this invention, a block of information words is defined having bits in rows and columns. A
first parity signal consi,sting of vertical parity bits is formed from a plurality of rows of the PCM signal, and a second parity signal is formed by supplying a predetermined bit of the PCM signal to a b-adjacent coder. An adjacent code or b-adjacent code has a symbol on GF (2b) (which is a Galois Field having 2b elements) and is a general name for codes which can correct errors in bit groups.
Examples of b-adjacent codes include the Hamming code and the Reed-Solomon code and so on. In the following example, a matrix code multiplied by a generating matrix T is used as a eode symbol of a b-adjacent signal. A
generating matrix T corresponding to the d'th order of a generating polynomial G (x) is expressed as follows:
G(x) - ~ O gi xi , gO = gd = 1 ~~~~~~ I go ~
`~ I gl T ~ ~ d-l ~ gd-l J ~' of (d x d). 1~ this case, Id 1 is aunit matrix sf (d-l)x~d-l).
If the informatl~n words containin~ error~ can be identified, errors in a second word in a block can be corrected using the b-adjacent signal. To detect the position of errors, an error detecting code produces a pointer whlch is added after interleaving to the trans-mitted signal which contains PC~I interleaved from a plurality of time-separated information words with their first and second error correcting codes.
According to the invention, errors in two infor-mation words can be completely corrected. If an error i8 not identified by a pointer, an error in one word can be corrected in a block. Since the PCM signal is reconstructed by time de-interleaving word by word from each of a plurality of ~ime interleaved blocks to form one block, when the correction of errors is impossible, words in error can be replaced by an average value of correc, words before and after the uncorrectable word.
Further, since the word in which an error exists is indicated by a pointer, a simple encoder and decoder can be used.
More particularly, there is provided:
A method of processing sequentially transferred digital information words, said method comprising the steps of:
forming a block of a plurality of said information words;
forming a parity error correcting word corresponding to said block and adding said parity error correcting word to said block;
forming a b-adjacent error correcting word correspond-ing to said block and adding said b-adjacent error correcting word to said block;
time-interleaving each of said information words and said parity and b-adjacent error correcting words in said block ~1~1363 into time-interleaved ~locks distributed over a predetermined time;
adding an error detecting code to at least one of said time-interlea~ed blocks; and transmitting said at least one time-interleaved block and said error detecting code associated therewith.
There is also provided:
An apparatus for processing digital information words comprising:
means for forming a block of a plurality of said in-formation words;
means for forming and adding a parity error correcting word and a b-adjacent code error correcting word to said block;
means for time-interleaving each of said information words and said error correcting words in said block into time-interleaved blocks distributed over a predetermined time means for adding an error detecting code to at least one of said time-interleaved blocks; and means for transmitting said at least one time-interleaved block and said error detectlng code associated there-with.
There is ~urther provided:
An attachment for r)ermit~inF; a-video tape recorder to record and reproduce at lesst one high quality audio signal on a video tape, comprising:
means for converting 8aid audio signal to a plur~lity of multi-bit diE~ital words, each of said digital words containing a representation of a characteriætic of said audio signal at a discrete point in time;
means for defining a block consisting of a fixed plurality of said digital words;
means for producing a first error correc~in~
word for said block and for adding said first error ~1363 orrecting word to said block;
means for producln~ a second error correcting word for said block and for adding said second error correcting word to said block;
. said first and second error correeting words having a characteristic which permit~ correction of errors in first and second digital words in said block if said irst and second digital words which contain errors are identified and which permits correction of errors in a single digital word in said block if identl-fication of digital words containing errors is not possible;
means for time-in~erleaving each of said digital words and said firs~ and second error correcting word~ from said block each ~nto different time inte-;leaved blocks;
mean~ for produclng an error detecting word for each time-interleaved block and for adding each said error detecting word to its respective time interleaved block;
and means for transmitting said time interleaved block including said error detectin~ code as a serial si~nal including at least horizontal synchronizin~ pulses to a ~Jideo tape recorder for recording therein.
The above, and other objects, features and advantages of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. l~s a signal recording and reproducing apparatus which includes a PCM signal transmitting system according to an embodiment of the present invention;
~ -6b-Fig. 2 is a block diagram showing an encoder suitable for use in the apparatus of Fig. l;
Fig. 3A is a graph showing the time relationship of signals to which reference will be made in describing the time interleaving of data;
- Fig. 3B is a graph showing an alternative method of appending a parity code to a set of data signals;
Fig. 4 is a block diagram of an adjacent coder suitable for use in the encoder of Fig. 2;
Fig. 5 is a block diagram of another adjacent coder suitable for use in the encoder of Fig. 2;
Fig. 6 is a block diagram of a decoder suitable for use in the embodiment of Fig. l;
Fig. 7 is a block diagram of a read only memory used as a m~ltiplier;
Fig. 8 is a block diagram showing another multiplier and to which reference will be made in describing the operation of the apparatus in Fig. l; and Fig. 9 is a block diagram of another embodiment of a decoder suitable for use in the apparatus of Fig. 1. i 5 DESCRIPTION OF THE PREFEP~RED EMBODIMENT
Referring now to Fig. 1, a PCM signal processing adapter circuit i8 shown connected to a video input terminal 2i and a video output terminal 20 of a helical scan VTR 1 (video tape recorder). VTR 1 is normally used for recording and reproducing a video signal. With the PCM
signal processing adapter circuit of the present invention, VTR 1 is capable of recording and reproducing a PCM-encoded audio signal of extremely high fidelity.
~5'~
Input terminals 3L and 3R receive left and right channel analog stereo audio signals, respectively, which are supplied through low pass filters 4L and 4R to sample and hold circuits 5L and 5R. Sampled outputs of sample and hold circuits 5L and 5R are supplied to A-D converters 6L and 6R to be PCM encoded into multi-bit digital information words, of which there is one word for each sample. The encoded outputs of A-D converters 6L and 6R
are supplied to an encoder 7. Encoder 7 adds parity signals, compresses the time base and tLme interleaves the resulting PCM signal as will be described. The output of encoder 7 is a serial signal which is applied to a synchronizing signal mixer circuit 8. A reference clock oscillator 9 supplies reference clock signals ~o a pulse generator circuit 10 which produces sampling pulses for control of sample and hold circuits 5L snd 5R, clock pulses for control of A-D conversion in A-D converters 6L and 6R, control signals for encoder 7, and composite synchronizing signal~ for addition to the serial PCM
signal encoder 7 in synchronizing signal mixer circuit 8.
The output from synchronizing signal mixer circuit 8 is fed to video input terminal 2~ of VTR 1 for recording in a conventional matter on a video tape (not shown).
The PCM signal reproduced by VTR 1 is delivered through video output terminal 20 and a clamp circuit 11 ~o a data and synchronizing signal separator circuit 12.
The separated composite synchronizing signal is supplied to a pulse generator circuit 13, and the separated PCM
Eignal is supplied to a decoder 14. Decoder 14 performs time base expansion, error detection and error correction on the PCM signal and applies the resulting digital signals ~1~1363 to D-A conv2r~2rs 15L and l5R. Analog outputs of D-A
converters 15L and 15R are applied through low pass filters 16L and 16R to output terminals 17L and 17R, respectively. Pulse generator circuit 13 pro~ides clamp pulses for clamp circuit 11, control signals for data and synchronizing signal separator circuit 12, control signals for decoder 14 and clock pulses for D-A converters 15L and 15R in response to the composite synchronizing signal applied thereto from data and synchronizing signal separating circuit 12.
Referring to Fig. 2, encoder 7 of Fig. 1 is shown in detail. PCM signal sequences SL and SR (series coded) from A-D converters 6L and 6R are supplied to a distributor circuit 18 wherein the left and right channels are each divided into 3 channels to result in a total of ' 6 channels. For example, the PCM signal sequence or series SL which c~ntinues as L 2~ L 1 Lo~ Ll, L2, L3,----and the PCM signal series SR which continues as R 2~ R 1 Ro~ Rl, R2, R3,---- are distributed into a first channel PCM signal series SLl which contains every third channel from the left source (L 2 Ll, L4,---), a second channel PCM signal series SRl also containing every thi d channel from the right source (R 2 Rl, R4,----), a third channel PCM signal qeries SL2 (L 1~ L2. L5,---), a fourth channel PCM signal series SR2 (R 1~ R2. R5,----~, a fifth channel PCM signal series SL3 (L~, L3, L6, )?
channel PCM signal series SR3 ~Ro~ R3, R6,~
One word in the PCM signal series in each channel is supplied to a modulo 2 adder 19 to produce a first parity signal series SP and, word by word, to an adjacent channel coder 20 to produce a second parity signal seriesS~.
11;~1363 The PCM signal series SRl, SL2, SR2, SL3 and SR3 and first and second parity signal series SP and SQ are respectively supplied to delay circuits 22a, 22b, 22c, 22d, 22e, 22f and 22g. Delay circuits 22a to 22g ~ime interleave the six PCM signal series and the first and second parity signal series by providing delays of d, 2d, 3d, 4d, 5d, 6d and 7d (word time), respectively, when a unit delay amount is taken as d (word time).
Delay circuits 22a to 22g may be any suitable circuits, such as, shift registers or RAM (random access memory).
Delayed PCM signal series SRll, SL12, SR12 SL13 13 and the delayed parity signal series SPl and SQl from delay circuits 22a to 22g, respectively, as well as undelayed signal series SLl, are applied to inputs of a mixer or parallel-two-serial converter 24 and a CRC
(cyclic redundancy code) code generator 23. CRC code generator 23 produces a CRC code SC corresponding to the eight words at its inputs to thereby provide a pointer signal series which is applied to an input of mixer 24.
The CRC code ~s an error detecting code using a cyclic code, and CRC generator 23 is a modulo 2 subtractor which employs a generating polynomial.
Mixer 24 converts its parallel inputs to a serial signal transmitted one bit at a time to a time base compression circuit 25. Time base compression circuit 25 compresses the time base of the serial signal at its input in order to provide a serial signal series having data absent periods properly timed to permit the addition of synchronizing signals. As shown on Fig. 3A, a horizontal period between horizontal sy~chronizing signals HD contains six PCM data wordsj two parity words, and ,~s ~
1~31363 one ~RC or pointer signal word. The six-word PCM signal, two-word parity signal and one-word CRC code are supplied to synchronizing signal mixer circuit 8 (Fig. 1) wherein horizontal synchronizing pulses HD are added in the data absent periods.
- Fig. 3B shows zn alternate format for including the adjacent channel PCM Ql 21d in the serial signal.
In the example of Fig. 3A each word may have 14 bits.
In Fig. 3B, each word contains 16 bits. The 14-bit adjacent-channel code Ql 21d is split into seven 2-bit portions (shown cross hatched~ which arP inserted as the final 2-bits of each of the six data words and the parity word, as shown in Fig. 3B. In this case, the 6ignal comprises six PCM signal words, one parity signal word and one CRC code word. Thus, the signal sequence of Fig. 3B includes seven 16-bit words and one 14-bit word rather than the nine 14-bit words of Fig. 3A.
The following description provides the basis for understanding error correction by encoder 7 and decoder 14 of the present invention. As an example; let it be assumed as follows. When six words Ll, Rl, L2, R2, L3 and R3 are received from distributor circuit 18, first and second parity signals Pl and Ql are ~enerated by modulo 2 adder 19 and ad;acent channel coder 20, as foll~ws: , 1 Ll ~ Rl ~ L2 ~ R2 ~ L3 ~ R3 Ql = T6Ll ~ T5Rl ~ T4L2 ~ T3R2 ~ T2L3 ~ TR3 A generating matrix T is a certain d'th order generating polynomial G(x) which prevents the same value from appearing in T, T2, T3, T4, T5 and T6 of the above ~S ~
13~;3 expression. ~her~ second parity si~nal Ql is required to provide error correction for six words, d > 3 must be satisfied. When d = 3, if the generating polynomial G(x) is a reduced polynomial on GF(2) (Galois Field), (T, T2, T3, T4, T5, T6, T7) do not contain the same value. This reduced polynomial is G(x) = 1 ~ x ~ x3, so that T may be expressed as follows:
T = 1 0 1 ~ 1 0 .
Since (T, T2, T3, T4, T5) are all necessary for the present case, it is not always necessary that the generating polynomial G(x) be a reduced polynomial.
Further, when the second parity signal is provided by multiplication of one word of the respective P~ signal, which is expressed as a vector, by the generating matrix, the bit length of one word should be taken in~o consideration.
As an example, when one word is 14 bits, the following (14 x 14) generating matrix T is used.
o o _________ o g'O ' T ~ 1 0 -~~~~~~~~ gl T"""`.
,0 0 ----~ gl3 where G(x) - gO + glx + g2x + --~~~ gl3x gl4 the 14th generating matrix and (gO - gl4 = 1) as in the above case. Also, when one word is 14 bits, ~ second parity signal of 3 bits may be provided from the result ,3 ~
11~1363 obtained by dividing 14 bits by 3 bits and the generating (3 x 3) matrix. In this case, since 14 bits cannot be evenly divided by 3, a dummy bit of either "0" or "1" is added at the end to make one word containing 15 bits.
The dummy bit need not be transmitted.
As described above, when one word has a certain number of bits and a plurality of channels form one block, the realizability of the encoder and the decoder (the construction of its control circuit, memory capacitor, cost, etc.~ depends upon the form of the generating matrix which is selected. The first parity si~nal series SP can be produced in parallel by adder 19 as in the encoder shown in Fig. 2, or in series by a shift register of one word length and one exclusive OR gate. The syndrome, or error correcting pattern> can be formed by the first parity signal series SP in a similar manner. Thus, simple circuits are sufficient for producing the first parity signal series SP. Formation of ~he second pari~y signal series SQ in adjacent channel coder 20 and error correction thereby in decoder 14 (Fig. 1) are a greater problem. The memory for time base compression (or expan-sion) and interleave ~or de-interleave) depends on the method chosen for producing this signal. Optimization is described for a system in whlch a block is formed of six 14-bit words of PCM data and first and second 14-bit parity signals.
The following table shows the ways in which a system which permits correction of errors in two channels snd one word can be divided into separate blorks.
1~313f~i3 Number of Number of Magnitude of Number of Division ~n) Divided Bits (m) Bits Q
1 14 14x14 (=196) 14 2 7+7 7x7 (=49) 14 3 5+5+5 5x5 (=25~ 15
4 4+4~4+4 4x4 (=16) ~6 3+3+3+3+3 ,3x3 (=9) 15 Second parity signal Q can be produced using a shift register which has the same number of bits as the number of divided bits (m) in the divided word. Thus, a shift register having as few as three bits can be used (n equals 5).
However, in order to multiply the generating matrix T by the data, the data are read out sequentially from a RAM ~o the shift register (which is necessary for time base compression or interleave). Thus, when the I/O of the RAM is taken into consideration, the divided bit number (m) shsuld be more than 4 and the number of divisions (n~ should be either l or a multiply of 2 so as to easily control the RAM. When n is 1, 2 and 4, the above condition is satisfied.
Further, n = 2 is most preferred since the number of bits in the shift register is small and a useless factor of a dummy bit is not required. From the table, a value n = 2 corresponds to a number of divided bits m c 7.
Next the decoder is discussed. The syndrome S
produced during decoding by the first parity signal is expressed by the following expression when the error pattern of the word in an i'th channel is taken as xi and the error pattern of the word in a ~'th channel as x;.
Sl - x~ ~ x3 f The syndrome S2 produced by the second parity signal is expressed as follows:
S2 ~ T7 ixl ~ T7 ~x;
When i and ~ are detected by the CRC code and identified by pointers, the error patterns for both x and x~ can be obtained from the following simultaneous equations.
S x; = (I ~9 Ti ~ (Sl 63 Ti-7 ~_Xi- Sl~x;
The error can be corrected by adding the error patterns xi and x; to the corresponding error words. If the above process is carried out under the assumption tha~
the words containing errors disappear (all are set to "0"~, correct words can be generated and substituted for the two words containing.
The circuit which provides the syndrome S2 is similar to the circuit which provides the parity signal Q, 80 that (n = 2) and tm - 7) are also suitable for it.
The operational equation for obtaining x;, Ti 7 is also similar to the foregoing. The following describes the manner in which the factor (I ~3 Ti-~ of the oper-ational equation iB generated. Calculation of the factor using a shift register is very complicated. Therefore, it is better that a look-up table corresponding to every possible (i - ;) be memorized in a ROM (read only memory).
Since (i - j) contains only five possibilities, a ROM of (m x m x 5) bits is sufficient for a divided bit number m.
To calculate the matrix, it is convenient to read an output of e~ery row of the (m x m) matrix. Accordingly, with a view to also facilitating control of the ROM, the . . .
ROM may be one of the following:
n ~ 1 m ~ 1416 x 16 x 8 = 2048(bits) n - 2 m - 78 ~ 8 x 8 = 512 (bits) n ~ 3 m - 58 x 8 x R = 512 (bits) n - 4 m ~ 44 x 4 x 8 - 128 (bits) n ~ 5 m ~ 34 x 4 x & = 128 (bits3 Where the calculation of (I ~9 Tl~J) 1 is carried out by the output of the ROM, if the calculation is performed bit by bit, the number of outputs required from the ROM
is m. If m bits are calculated at a time, (m x mj outputs are necessary. Almost all commercially available ROMs provide 4 or 8 outputs, so that, if m is equal to sr less than the number of outputs of the ROM (4 or 8), the calculation c~n be performed bit by bit. If m is larger than the number of outputs of the ROM, a buffer register is needed to store the outputs of the ROM to permit similar calculation bit by bit. However, in this case, the cost of the buffer register is added. In view of the foregoing, it is preferred that m be not more than 7 bits.
The values of (I ~3 Ti ~) 1 and the data (Sl 63 Ti 7S2) may be memorized ln a look-up table in a ROM and then processed at once. If 3 bits are allocated to (i - ;), an input address of 3 bits is required, the total input is (m + 3~ bits and the output is m bits. Even when (m = 14), a ROM of such great capacity is required that it is almost impossible to realize. Thus, m should be not more than 7 bits.
As may be apparent from the foregoing, when one word conta~ns 14 bits, the 14 bits should be divided into two ~ets of 7 bits. Thus, the formation of the second -16- .
r ~;
~1~1363 parity signal SQ, and error correction using the second parity signal and the memory control thereof become easy, and hence the encoder and decoder are simplified.
When the number of divided bits is 7, one example of the-generating matrix T can be expressed as follows:
O O O ~ 1 0 0 ~O O O O 0 1 0 where G(x) = 1 ~ x + x7 is taken as the generating polynomial.
By way of example, when the second parity signal Ql i8 provided for error correction of six words (Ll Rl, L2, R2, L3, R3), the following expressions are obtained:
Qla ~ T6Lla ~9 T5Rla ~9 T L2a ~9 T3R2a ~9 T2L3a ~9 TR3a Qlb ~ T6Llb ~9 T5Rlb ~3 T4L2b ~9 T3R2b ~9 T2L3b ~9 TR3b where Lla is the seven most significant bits and Llb is the seven least significant bits of word Ll, and Rla, Rl~, L2a, L2b~ R2a~ R2b~ L3a~ L3b. R3a and R3b are also seven bit sub-words as above. The first pari~y si~nal Pl is provided with word units similar to ~he above.
Turning to Fig. 4, an adjacent channel encoder 20a (part of ad;acent channel encoder 20) for providing a 7~bit parity signal Qla is shown. Encoder 20a contains a l-bit shift register 27, a 6-bit shift register 28, exclusive OR
gates 29 and 30, and an AND gate 31. The PCM signal is applied to ~n input terminal 32 beginning with the most ~^~
~13~363 æi~nificant bit in the order of Lla, Rla, L2a,--- R3a.
Shift re~isters 27 and 28 are first cleared and the output of AND gate 31 is held at "0" by a gate si~nal applied to its input. PCM signal Lla is shifted into shift registers 27 and 28. Then, the gate signal is set to "1" to shift the stored signal l-bit. The content of shift registers 27 and 28 is changed to (TLl~). The gate signal is then set to "~" and Rla is applied to exclusive OR gate 39 to store ~TLla ~3 Rla) The gate signal is set to "1" to shift thestoredsignal l-bit and thus to store (T2Lla ~9 TRla). The above operation is repeated on the remaining PCM signals to provide the parity si~nal Qla.
Since encoder 20a in Fig. 4 includes only 7-bits for each channel, it cannot be controlled in common with adder 19 from which 14-bits are derived to provide the parity signal Pl. Therefore, the circuit of Fig. 5 may be used which contains coderæ 20a and 20b each similar to that shown in Fig. 4. The seven most significant bits are supplied through a switch 33a to encoder 20a7 and the seven least significant bits are supplied through a switch 33b to encoder 20b.
A T 1 multiplier circuit, which is necessary for decoder 14 (Fig. 1), i8 shown in Fig. 6. Shift registers 27 and 28 are s~ifted in the reverse direction compared to shift registers 27 and 28 in Fig. 4. In the multiplier circuit of Fig. 6, when the PCM signal is supplied to an input terminal 32, the least significant bit is supplied first.
Multiplication of the 7-bit P~ signal by T or T 1 may be carried out by a ROM 34 of (256 x 8) bits, as shown in Fig. 7. Eight input data lines 35 apply the 7-bit PCM
,~ -18-~tl' ~ .
11 31 36~3 signal of 7-bits a~d a l-bit signal which selects T or T l.
The`7-bit result is derived at output data lines 36.
A multiplier circuit for the multiplication of ~ Ti 3) 1 and the operation result (data) of (Sl ~ Ti 7S2), is shown in Fig. 8. The data is stored in a 7-bit data register 37. The stored data and the output from a ROM 40 corresponding to one row of (I 6~ Ti ~) 1 are supplied to AND gates 38a to 38g, respectively. The outputs from AND
gates 38a to 38g are supplied to modulo 2 adders 39a to 39f, whereby one bit of the operation result is obtained. ROM
40 contains (64 x 8) bits and receives a 3-bit row select signal at input data lines 41, which sequentially appoints the first to seventh rows, and a 3-bit select signal at input data lines 42 which appoint (i - j).
Instead of using the multiplier circuit of Fig. 8 which produces the operation result one bit at a time, it may be possible to use a ROM which simultaneously provides all seven bits. By supplying a 3-bit select signal, which appoints seven bits of data (i - j), the seven bits of a predetermined operation result is read out in one step.
A ROM of (1024 x 8) bits is necessary to accomplish this.
An embodiment of decoder 14 (Fig. 1) is schematically shown in Fig. 9. Decoder 14 performs series processing in contrast to encoder 7 (Fig. 2) which performs parallel processing. The PCM signal from data and synchronizing signal separator 12 (Fig. l) is applied through an input terminal 43 to a CRC checker 44. CRC checker 44 detects whether an error exists in the time interleave block of data in each horizontal period. When an error is detected in a horizontal period, a l-bi~ error marker or flag is added to each word in the horizontal period. The PCM
~ 3~3 signal, with or without an error marker, is applied to a time base expansion and de-interleave circuit 45 (which is a RAM). A previous read data signal from RAM 45 is supplied to syndrome forming circuits 46 and 47 and is operated on therein before the ordinary data is supplied to a correction circuit 52. Syndrome forming circuit 46 provides the syndrome Sl and syndrome forming circuit 47 provides the syndrome S2, respectively. The syndrome S2 is supplied to a multiplier 48 by which Ti 7S2 is provided.
This Tl 7S2 is fed to an adder 49 which is also supplied with the syndrome Sl from ~yndrome forming circuit 46, so that adder 49 provides (Sl e~ Ti 7S2) which is then fed to a ROM 50 serving as an opera~ional circuit. ROM 50 produces an error pattern x; which is supplied simultaneously to an adder 51 which is also supplied with syndrome Sl.
Thus, the adder 51 also produces an error pattern xi.
The ordinary data from time base expansion and de-interleave circuit 45 and error patterns xi, x; are supplied to correction circuit 52 which then develops a PCM signal, in which errors are corrected, and delivers the corrected signal to output terminal 53. A compensation circuit (not shown) may be connected to output terminal 53. W~en errors exist in three or more channels and the errors can be corrected, the compensation circuit may substitute, for the uncorrectable PCM signal, the digital mean value of the correct PCM signals which are positioned, in point of time, before and after the uncorrectable PCM
signal.
The si~. channels of PCM signals, time de-interleaved by applyin~ appropriate delays thereto to produce two PCM signals containing the reproduced left and right channels, 11 ~1 3t~
are fed to B-A converters 15L and 15R (Fig. 1), respect-ively, for reconversion into analo~ signals.
As may be understood from the foregoing, according to the present invention, errors in up to two channels in the ~ix channels of PCM signal can be completely corrected.
If the CRC code fails to detect an error in a single one of the 6iX PCM channels, an error can still be detected by syndromes Sl and S2. Therefore, a PCM signal trans-mission system having high error correction capability is achievable by the present invention. Further, in this r invention, six channels of PCM signal and two channels of f parity signal are transmitted time interlea~ed so that a burst error in the transmission path is converted into ~andom bit errors (which most often produces an error within no more than two channels of each time interleaved ~block) and hence the correction capability is improved.
Further, an error detection marker added to the signal permits detection and identification of channels in which an error exists. This improves detection and s~mplifies the construction of a decoder.
Furt~,er, in this invention, one block is formed of a six-word P~ signal and a two-word parity signal with a one-word CRC error detection code added thereto, so that modification can be made in the apparatus for error correction while the code construction is kept the same.
That is, variations in the code construction permit error correction of a single error using a single error correction code when a error is detected by the error detection code. Correction of errors in up to two channels may be formed using the error detection code along with the first and second parity ~ignals.
~ 36~3 Further, the number m of the divided bit6 is deter-mined in consideration of the number of bits in a word and of the number of channels, so that the encoder can be made at low cost.
- Other detectlon codes may be used instead of the CRC code. For example, a parity code may be used.
Having described specific preferred embodiment~ of the invention with reference to the accompanying drawings, it i8 to be understoDd that the invention is not limited to those precise embodiments, and that various changes and modificrcions ~ay be e~fected therein by one skilled in the art without departing rom the scope or spirit of the invention as defined in the appended claims.
However, in order to multiply the generating matrix T by the data, the data are read out sequentially from a RAM ~o the shift register (which is necessary for time base compression or interleave). Thus, when the I/O of the RAM is taken into consideration, the divided bit number (m) shsuld be more than 4 and the number of divisions (n~ should be either l or a multiply of 2 so as to easily control the RAM. When n is 1, 2 and 4, the above condition is satisfied.
Further, n = 2 is most preferred since the number of bits in the shift register is small and a useless factor of a dummy bit is not required. From the table, a value n = 2 corresponds to a number of divided bits m c 7.
Next the decoder is discussed. The syndrome S
produced during decoding by the first parity signal is expressed by the following expression when the error pattern of the word in an i'th channel is taken as xi and the error pattern of the word in a ~'th channel as x;.
Sl - x~ ~ x3 f The syndrome S2 produced by the second parity signal is expressed as follows:
S2 ~ T7 ixl ~ T7 ~x;
When i and ~ are detected by the CRC code and identified by pointers, the error patterns for both x and x~ can be obtained from the following simultaneous equations.
S x; = (I ~9 Ti ~ (Sl 63 Ti-7 ~_Xi- Sl~x;
The error can be corrected by adding the error patterns xi and x; to the corresponding error words. If the above process is carried out under the assumption tha~
the words containing errors disappear (all are set to "0"~, correct words can be generated and substituted for the two words containing.
The circuit which provides the syndrome S2 is similar to the circuit which provides the parity signal Q, 80 that (n = 2) and tm - 7) are also suitable for it.
The operational equation for obtaining x;, Ti 7 is also similar to the foregoing. The following describes the manner in which the factor (I ~3 Ti-~ of the oper-ational equation iB generated. Calculation of the factor using a shift register is very complicated. Therefore, it is better that a look-up table corresponding to every possible (i - ;) be memorized in a ROM (read only memory).
Since (i - j) contains only five possibilities, a ROM of (m x m x 5) bits is sufficient for a divided bit number m.
To calculate the matrix, it is convenient to read an output of e~ery row of the (m x m) matrix. Accordingly, with a view to also facilitating control of the ROM, the . . .
ROM may be one of the following:
n ~ 1 m ~ 1416 x 16 x 8 = 2048(bits) n - 2 m - 78 ~ 8 x 8 = 512 (bits) n ~ 3 m - 58 x 8 x R = 512 (bits) n - 4 m ~ 44 x 4 x 8 - 128 (bits) n ~ 5 m ~ 34 x 4 x & = 128 (bits3 Where the calculation of (I ~9 Tl~J) 1 is carried out by the output of the ROM, if the calculation is performed bit by bit, the number of outputs required from the ROM
is m. If m bits are calculated at a time, (m x mj outputs are necessary. Almost all commercially available ROMs provide 4 or 8 outputs, so that, if m is equal to sr less than the number of outputs of the ROM (4 or 8), the calculation c~n be performed bit by bit. If m is larger than the number of outputs of the ROM, a buffer register is needed to store the outputs of the ROM to permit similar calculation bit by bit. However, in this case, the cost of the buffer register is added. In view of the foregoing, it is preferred that m be not more than 7 bits.
The values of (I ~3 Ti ~) 1 and the data (Sl 63 Ti 7S2) may be memorized ln a look-up table in a ROM and then processed at once. If 3 bits are allocated to (i - ;), an input address of 3 bits is required, the total input is (m + 3~ bits and the output is m bits. Even when (m = 14), a ROM of such great capacity is required that it is almost impossible to realize. Thus, m should be not more than 7 bits.
As may be apparent from the foregoing, when one word conta~ns 14 bits, the 14 bits should be divided into two ~ets of 7 bits. Thus, the formation of the second -16- .
r ~;
~1~1363 parity signal SQ, and error correction using the second parity signal and the memory control thereof become easy, and hence the encoder and decoder are simplified.
When the number of divided bits is 7, one example of the-generating matrix T can be expressed as follows:
O O O ~ 1 0 0 ~O O O O 0 1 0 where G(x) = 1 ~ x + x7 is taken as the generating polynomial.
By way of example, when the second parity signal Ql i8 provided for error correction of six words (Ll Rl, L2, R2, L3, R3), the following expressions are obtained:
Qla ~ T6Lla ~9 T5Rla ~9 T L2a ~9 T3R2a ~9 T2L3a ~9 TR3a Qlb ~ T6Llb ~9 T5Rlb ~3 T4L2b ~9 T3R2b ~9 T2L3b ~9 TR3b where Lla is the seven most significant bits and Llb is the seven least significant bits of word Ll, and Rla, Rl~, L2a, L2b~ R2a~ R2b~ L3a~ L3b. R3a and R3b are also seven bit sub-words as above. The first pari~y si~nal Pl is provided with word units similar to ~he above.
Turning to Fig. 4, an adjacent channel encoder 20a (part of ad;acent channel encoder 20) for providing a 7~bit parity signal Qla is shown. Encoder 20a contains a l-bit shift register 27, a 6-bit shift register 28, exclusive OR
gates 29 and 30, and an AND gate 31. The PCM signal is applied to ~n input terminal 32 beginning with the most ~^~
~13~363 æi~nificant bit in the order of Lla, Rla, L2a,--- R3a.
Shift re~isters 27 and 28 are first cleared and the output of AND gate 31 is held at "0" by a gate si~nal applied to its input. PCM signal Lla is shifted into shift registers 27 and 28. Then, the gate signal is set to "1" to shift the stored signal l-bit. The content of shift registers 27 and 28 is changed to (TLl~). The gate signal is then set to "~" and Rla is applied to exclusive OR gate 39 to store ~TLla ~3 Rla) The gate signal is set to "1" to shift thestoredsignal l-bit and thus to store (T2Lla ~9 TRla). The above operation is repeated on the remaining PCM signals to provide the parity si~nal Qla.
Since encoder 20a in Fig. 4 includes only 7-bits for each channel, it cannot be controlled in common with adder 19 from which 14-bits are derived to provide the parity signal Pl. Therefore, the circuit of Fig. 5 may be used which contains coderæ 20a and 20b each similar to that shown in Fig. 4. The seven most significant bits are supplied through a switch 33a to encoder 20a7 and the seven least significant bits are supplied through a switch 33b to encoder 20b.
A T 1 multiplier circuit, which is necessary for decoder 14 (Fig. 1), i8 shown in Fig. 6. Shift registers 27 and 28 are s~ifted in the reverse direction compared to shift registers 27 and 28 in Fig. 4. In the multiplier circuit of Fig. 6, when the PCM signal is supplied to an input terminal 32, the least significant bit is supplied first.
Multiplication of the 7-bit P~ signal by T or T 1 may be carried out by a ROM 34 of (256 x 8) bits, as shown in Fig. 7. Eight input data lines 35 apply the 7-bit PCM
,~ -18-~tl' ~ .
11 31 36~3 signal of 7-bits a~d a l-bit signal which selects T or T l.
The`7-bit result is derived at output data lines 36.
A multiplier circuit for the multiplication of ~ Ti 3) 1 and the operation result (data) of (Sl ~ Ti 7S2), is shown in Fig. 8. The data is stored in a 7-bit data register 37. The stored data and the output from a ROM 40 corresponding to one row of (I 6~ Ti ~) 1 are supplied to AND gates 38a to 38g, respectively. The outputs from AND
gates 38a to 38g are supplied to modulo 2 adders 39a to 39f, whereby one bit of the operation result is obtained. ROM
40 contains (64 x 8) bits and receives a 3-bit row select signal at input data lines 41, which sequentially appoints the first to seventh rows, and a 3-bit select signal at input data lines 42 which appoint (i - j).
Instead of using the multiplier circuit of Fig. 8 which produces the operation result one bit at a time, it may be possible to use a ROM which simultaneously provides all seven bits. By supplying a 3-bit select signal, which appoints seven bits of data (i - j), the seven bits of a predetermined operation result is read out in one step.
A ROM of (1024 x 8) bits is necessary to accomplish this.
An embodiment of decoder 14 (Fig. 1) is schematically shown in Fig. 9. Decoder 14 performs series processing in contrast to encoder 7 (Fig. 2) which performs parallel processing. The PCM signal from data and synchronizing signal separator 12 (Fig. l) is applied through an input terminal 43 to a CRC checker 44. CRC checker 44 detects whether an error exists in the time interleave block of data in each horizontal period. When an error is detected in a horizontal period, a l-bi~ error marker or flag is added to each word in the horizontal period. The PCM
~ 3~3 signal, with or without an error marker, is applied to a time base expansion and de-interleave circuit 45 (which is a RAM). A previous read data signal from RAM 45 is supplied to syndrome forming circuits 46 and 47 and is operated on therein before the ordinary data is supplied to a correction circuit 52. Syndrome forming circuit 46 provides the syndrome Sl and syndrome forming circuit 47 provides the syndrome S2, respectively. The syndrome S2 is supplied to a multiplier 48 by which Ti 7S2 is provided.
This Tl 7S2 is fed to an adder 49 which is also supplied with the syndrome Sl from ~yndrome forming circuit 46, so that adder 49 provides (Sl e~ Ti 7S2) which is then fed to a ROM 50 serving as an opera~ional circuit. ROM 50 produces an error pattern x; which is supplied simultaneously to an adder 51 which is also supplied with syndrome Sl.
Thus, the adder 51 also produces an error pattern xi.
The ordinary data from time base expansion and de-interleave circuit 45 and error patterns xi, x; are supplied to correction circuit 52 which then develops a PCM signal, in which errors are corrected, and delivers the corrected signal to output terminal 53. A compensation circuit (not shown) may be connected to output terminal 53. W~en errors exist in three or more channels and the errors can be corrected, the compensation circuit may substitute, for the uncorrectable PCM signal, the digital mean value of the correct PCM signals which are positioned, in point of time, before and after the uncorrectable PCM
signal.
The si~. channels of PCM signals, time de-interleaved by applyin~ appropriate delays thereto to produce two PCM signals containing the reproduced left and right channels, 11 ~1 3t~
are fed to B-A converters 15L and 15R (Fig. 1), respect-ively, for reconversion into analo~ signals.
As may be understood from the foregoing, according to the present invention, errors in up to two channels in the ~ix channels of PCM signal can be completely corrected.
If the CRC code fails to detect an error in a single one of the 6iX PCM channels, an error can still be detected by syndromes Sl and S2. Therefore, a PCM signal trans-mission system having high error correction capability is achievable by the present invention. Further, in this r invention, six channels of PCM signal and two channels of f parity signal are transmitted time interlea~ed so that a burst error in the transmission path is converted into ~andom bit errors (which most often produces an error within no more than two channels of each time interleaved ~block) and hence the correction capability is improved.
Further, an error detection marker added to the signal permits detection and identification of channels in which an error exists. This improves detection and s~mplifies the construction of a decoder.
Furt~,er, in this invention, one block is formed of a six-word P~ signal and a two-word parity signal with a one-word CRC error detection code added thereto, so that modification can be made in the apparatus for error correction while the code construction is kept the same.
That is, variations in the code construction permit error correction of a single error using a single error correction code when a error is detected by the error detection code. Correction of errors in up to two channels may be formed using the error detection code along with the first and second parity ~ignals.
~ 36~3 Further, the number m of the divided bit6 is deter-mined in consideration of the number of bits in a word and of the number of channels, so that the encoder can be made at low cost.
- Other detectlon codes may be used instead of the CRC code. For example, a parity code may be used.
Having described specific preferred embodiment~ of the invention with reference to the accompanying drawings, it i8 to be understoDd that the invention is not limited to those precise embodiments, and that various changes and modificrcions ~ay be e~fected therein by one skilled in the art without departing rom the scope or spirit of the invention as defined in the appended claims.
Claims (4)
OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A method of processing sequentially transferred digital information words, said method comprising the steps of:
forming a block of a plurality of said information words;
forming a parity error correcting word corresponding to said block and adding said parity error correcting word to said block;
forming a b-adjacent error correcting word correspond-ing to said block and adding said b-adjacent error correcting word to said block;
time-interleaving each of said information words and said parity and b-adjacent error correcting words in said block into time-interleaved blocks distributed over a predetermined time;
adding an error detecting code to at least one of said time-interleaved blocks; and transmitting said at least one time-interleaved block and said error detecting code associated therewith.
forming a block of a plurality of said information words;
forming a parity error correcting word corresponding to said block and adding said parity error correcting word to said block;
forming a b-adjacent error correcting word correspond-ing to said block and adding said b-adjacent error correcting word to said block;
time-interleaving each of said information words and said parity and b-adjacent error correcting words in said block into time-interleaved blocks distributed over a predetermined time;
adding an error detecting code to at least one of said time-interleaved blocks; and transmitting said at least one time-interleaved block and said error detecting code associated therewith.
2. An apparatus for processing digital information words comprising:
means for forming a block of a plurality of said in-formation words;
means for forming and adding a parity error correcting word and a b-adjacent code error correcting word to said block;
means for time-interleaving each of said information words and said error correcting words in said block into time-interleaved blocks distributed over a predetermined time;
means for adding an error detecting code to at least one of said time-interleaved blocks; and means for transmitting said at least one time-interleaved block and said error detecting code associated there-with.
means for forming a block of a plurality of said in-formation words;
means for forming and adding a parity error correcting word and a b-adjacent code error correcting word to said block;
means for time-interleaving each of said information words and said error correcting words in said block into time-interleaved blocks distributed over a predetermined time;
means for adding an error detecting code to at least one of said time-interleaved blocks; and means for transmitting said at least one time-interleaved block and said error detecting code associated there-with.
3. An attachment for permitting a video tape recorder to record and reproduce at least one high quality audio signal on a video tape, comprising:
means for converting said audio signal to a plurality of multi-bit digital words, each of said digital words containing a representation of a characteristic of said audio signal at a discrete point in time;
means for defining a block consisting of a fixed plurality of said digital words;
means for producing a first error correcting word for said block and for adding said first error correcting word to said block;
means for producing a second error correcting word for said block and for adding said second error correcting word to said block;
said first and second error correcting words having a characteristic which permits correction of errors in first and second digital words in said block if said first and second digital words which contain errors are identified and which permits correction of errors in a single digital word in said block if identi-fication of digital words containing errors is not possible;
means for time-interleaving each of said digital words and said first and second error correcting words from said block each into different time interleaved blocks;
means for producing an error detecting word for each time-interleaved block and for adding each said error detecting word to its respective time interleaved block;
and means for transmitting said time interleaved block including said error detecting code as a serial signal including at least horizontal synchronizing pulses to a video tape recorder for recording therein.
means for converting said audio signal to a plurality of multi-bit digital words, each of said digital words containing a representation of a characteristic of said audio signal at a discrete point in time;
means for defining a block consisting of a fixed plurality of said digital words;
means for producing a first error correcting word for said block and for adding said first error correcting word to said block;
means for producing a second error correcting word for said block and for adding said second error correcting word to said block;
said first and second error correcting words having a characteristic which permits correction of errors in first and second digital words in said block if said first and second digital words which contain errors are identified and which permits correction of errors in a single digital word in said block if identi-fication of digital words containing errors is not possible;
means for time-interleaving each of said digital words and said first and second error correcting words from said block each into different time interleaved blocks;
means for producing an error detecting word for each time-interleaved block and for adding each said error detecting word to its respective time interleaved block;
and means for transmitting said time interleaved block including said error detecting code as a serial signal including at least horizontal synchronizing pulses to a video tape recorder for recording therein.
4. An attachment according to claim 3; further comprising:
means for receiving a serial signal reproduced by the video tape recorder including said time interleaved blocks having said error detecting words and said synchronizing pulses;
means responsive to said error detecting word for detecting an error in at least one of said digital words in said time-interleaved block and for marking all of said digital words in said time-interleaved block with a marker to indicate that an error is detected;
time de-interleaving said digital words and said first and second error correcting words into their original blocks whereby no more than one word from a time interleaved block is time de-interleaved into any one time de-interleaved block;
means for sensing digital words in said time de-interleaved blocks which have markers as a result of their being previously contained in a time interleaved block containing an error;
means for correcting errors in at least two digital words containing markers in said time de-interleaved block; and means for reconverting said digital words into a reproduced audio signal.
means for receiving a serial signal reproduced by the video tape recorder including said time interleaved blocks having said error detecting words and said synchronizing pulses;
means responsive to said error detecting word for detecting an error in at least one of said digital words in said time-interleaved block and for marking all of said digital words in said time-interleaved block with a marker to indicate that an error is detected;
time de-interleaving said digital words and said first and second error correcting words into their original blocks whereby no more than one word from a time interleaved block is time de-interleaved into any one time de-interleaved block;
means for sensing digital words in said time de-interleaved blocks which have markers as a result of their being previously contained in a time interleaved block containing an error;
means for correcting errors in at least two digital words containing markers in said time de-interleaved block; and means for reconverting said digital words into a reproduced audio signal.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13016178A JPS5556744A (en) | 1978-10-23 | 1978-10-23 | Pcm signal transmission device |
| JP130161/78 | 1978-10-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1131363A true CA1131363A (en) | 1982-09-07 |
Family
ID=15027452
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA338,114A Expired CA1131363A (en) | 1978-10-23 | 1979-10-22 | Pcm signal transmitting system |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US4306305A (en) |
| JP (1) | JPS5556744A (en) |
| AT (1) | AT371615B (en) |
| AU (1) | AU530203B2 (en) |
| CA (1) | CA1131363A (en) |
| DE (1) | DE2942825A1 (en) |
| FR (1) | FR2440125B1 (en) |
| GB (1) | GB2038144B (en) |
| NL (1) | NL191724C (en) |
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| CA1170776A (en) * | 1980-07-18 | 1984-07-10 | Yoichiro Sako | Method of error correction of blocks of data |
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| USRE33900E (en) * | 1980-09-11 | 1992-04-28 | At&T Bell Laboratories | Error monitoring in digital transmission systems |
| JPS5753807A (en) * | 1980-09-16 | 1982-03-31 | Toshiba Corp | Processsor of digital signal |
| JPS5753802A (en) * | 1980-09-16 | 1982-03-31 | Toshiba Corp | Processor of digital signal |
| JPS5753806A (en) * | 1980-09-16 | 1982-03-31 | Toshiba Corp | Processor of digital signal |
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| US4394762A (en) * | 1981-01-06 | 1983-07-19 | Tokyo Shibaura Denki Kabushiki Kaisha | Pulse-code modulation signal processing circuit |
| US4380071A (en) * | 1981-02-02 | 1983-04-12 | Sony Corporation | Method and apparatus for preventing errors in PCM signal processing apparatus |
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| WO1982003719A1 (en) * | 1981-04-16 | 1982-10-28 | Odaka Kentaro | Error correction coding method |
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-
1978
- 1978-10-23 JP JP13016178A patent/JPS5556744A/en active Granted
-
1979
- 1979-10-19 US US06/086,677 patent/US4306305A/en not_active Expired - Lifetime
- 1979-10-22 NL NL7907760A patent/NL191724C/en not_active IP Right Cessation
- 1979-10-22 CA CA338,114A patent/CA1131363A/en not_active Expired
- 1979-10-22 AT AT0686479A patent/AT371615B/en not_active IP Right Cessation
- 1979-10-23 AU AU52063/79A patent/AU530203B2/en not_active Expired
- 1979-10-23 GB GB7936687A patent/GB2038144B/en not_active Expired
- 1979-10-23 DE DE19792942825 patent/DE2942825A1/en active Granted
- 1979-10-23 FR FR7926283A patent/FR2440125B1/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| FR2440125A1 (en) | 1980-05-23 |
| NL191724C (en) | 1996-04-02 |
| JPS6150418B2 (en) | 1986-11-04 |
| GB2038144B (en) | 1983-05-11 |
| AT371615B (en) | 1983-07-11 |
| AU5206379A (en) | 1980-05-01 |
| DE2942825C2 (en) | 1990-06-21 |
| ATA686479A (en) | 1982-11-15 |
| AU530203B2 (en) | 1983-07-07 |
| GB2038144A (en) | 1980-07-16 |
| NL7907760A (en) | 1980-04-25 |
| FR2440125B1 (en) | 1988-03-25 |
| US4306305A (en) | 1981-12-15 |
| JPS5556744A (en) | 1980-04-25 |
| DE2942825A1 (en) | 1980-04-30 |
| NL191724B (en) | 1995-12-01 |
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