CA1138071A

CA1138071A - Digital data communication system

Info

Publication number: CA1138071A
Application number: CA000352895A
Authority: CA
Inventors: Randall K.B. Chun; Donn E. Larsen
Original assignee: Boeing Co
Current assignee: Boeing Co
Priority date: 1979-05-31
Filing date: 1980-05-28
Publication date: 1982-12-21
Also published as: WO1980002784A1; EP0019920A1; US4280221A

Abstract

ABSTRACT

In order to accommodate variations in data rate transmissions, a digital data communication system includes a data source (20) and a source interface (22), a digital data bus (18), for transferring encoded information from the data source to one or more receivers (26), each having a receiver interface (24). The source interface (22) is adaptable for controlling the rise and fall times of the signals on the bus at a plurality of frequencies. It is directly coupled to the bus (18) and terminates the bus in its characteristic impedance. The receiver interface (24) operates a plurality of frequencies and is directly coupled to the bus (18).

Description

~3~L~

DIGITAL D,~TA CO~ U~ICATION SYST~M
BACKGROUND OF THE IN~iENT~ON
This invention relates to communication systems and, more particularly, to digital data communication s~stems.
One application of the invention illustrated and described herein is an aircraft avionics system; however, the inven-tion may be used ~n other applications and environmentsO
Commercial aircraft digital avionics systems typically are made up of multiple system elements such as ~nert~al navigation system elements, autopilot s~stem elements or electronic engine control system elements, D~gital data is transferred over a digital data bus from each system element that acts as a source ol data to one or more re-ceiver system elements or data sinks that reauire the data over a digital data bus. Each system element ~s composed of either a data source or a receiver~ as the case ma~ ~e, and an interface acting between it and the dat~,~us~ Ty pically, one data source serves multiple receivers and, since the receivers do not also act as data sources, the, data transfer via th.e data bus is uni-directi.onal from a data source to one or more receivers~
Since the system elements typically o~erate at dlf-ferent data transfer rates, different interfaces are re-quired, depending upon the data rate at which the associ-ated data source or receiver operates. For example, an interface that is designed for use with a data source which operates at a low data rate generally is not suited for use with a data source that operates at a higher data rate. The source interface, or transmitter, controls the rise and fall times of the digital signals applied to the bus in order to minimize the electromagnetic interference radiated from the bus at that data rate. At the 10W data rate, the interface ~rovides a relatively long rise time for the data transmitted on the bus, However, when oper-ating at the higher data rate, the long rise time can mask succeeding bits and cause erroneous data to ~e trans~itted.
Likewise, an interface that is designed for use with a re-ceiver which operates at R low data rate is generally notsuitable for use with a receiver that operates at a hiyher data rate. For example, one of the functions of a re-ceiver interface is to indicate to the receiver ~hen the data transm~ssion begins and ends~ The signal chosen to indicate the presence of transmitted data must so indicate for a period of at least beyond the end of the last bit period received in order to avoid missing a data bit When operating at a lo~ data rate, the interface extends this signal for a predetermined period of time. However, when reception is at a h~gher data rate, the signal extension tends to overlap the start of the first bit period of a subsequent transmission~
The next generation commercial airplane will be re-quired to accommodate new sensors and provide compatible interfacing systems, controls and instruments and may use approximately 100 data transfer busses per ship set. Until this invention, many different digital data transmission standards, using different word labels, formats and elec-trical characteristics have been required~ In addition, previous digital avionics systems did not require data trans-mission frequencies of 100 Kilobits per second (KBPS). Due to the new generation of digital avionics subsystems, a 100 KBPS data transmission fequency will be needed to support new sensors, controls and instruments. Examples of subsystems which require 100 KBPS data rates are new compass displays and electronic attitude direction indica-tors (EADI) which utilize CRT displays.
Therefore, it is an object of this invention to pro-vide a digital data communication system capable of ful-filling the needs of future commercial aircraft avionics 1~ 3~

systems, in which informatlon must be transferred via a digital data bus from a data sollrce to one or more receivers in an economical and e~ficient manner.
Another object oE this invention is to provide a digital data communication system having a source inter-face responsive to digital source data for encoding and transmitting it in digital signals on a digital data bus, and a receiver interface responsive to the encoded digital signals for decoding them ancl providing binary data representative of the digital source data.
~ further related object of this invention is to pro-vide a source interface adaptable for controlling the rise and fall times of the encoded digital signals on the data bus for a plurality of data rates.
Still another related objeet of this invention is to provide a reeeiver interface adaptable for receiving the encoded signals from the bus for a plurality of data rates and decoding the signals into digital data~
Summary of the Inventio_ In accordance with one aspect of the invention there is provided a digital data communication system for transferring digital information from a souree to one or more receivers, comprising: source interface means for receiving digital signals generated by the source and producing encoded digital signals while controlling their rise and fall times on the basis of frequency of the source generated signals; receiver interface means for decoding said encoded diyital signals into digital signals representative of said source generated digital signals for presentation to a receiver; and bus means operatively associated with said source interface means and said receiver interface means for transferring said encoded ~$-~

-3a-digital si~nals from said source inter~ace means to said receiver interfaee means.
In aceordance with another aspect of the inventlon there is provided a source interfaee circuit for presenting information to bus means, comprising: means ~or receiving digital signals generated by a source and producing encoded digital signals; means responsive to said eneoded digital signals for controlling their rise and fall times on the basis of freq~ency of the source generated signals; and means for presenting said eneoded digital signals to the bus means.
In aecordance with yet another aspect of the invention there is provided a receiver interface circuit for reeeiv-ing eneoded digital signals representative of source gener-ated digital signals transmitted via bus means, comprising:means for decoding said encoded digi-tal signals into digital signals representative of the source generated signals for presentation to a receiver.
In preferred forms, the invention provides a digital data communication system which transmits binary informa-tion from a data source to one, two or more receivers along a common bus in an appropriate digital data format.
The format of the transmitted data is preferably differ-ential bipolar return-to-~ero (RZ). The data souree and each receiver include interface eireuits which respeetively eneode and deeode the digital data. The souree interfaee is operable at more than one data rate or frequeney, and is adjustable for eontrolling the rise and fall times of the signals Oll the data bus. I`he souree interEaee prefer-ably is directly eoupled to the bus and terminates thebus in its characteristie impedance. Similarly, the reeeiver interface is operative at more than one data rate or frequency, and is also direetly eoupled to the bus. The range of frequeneies over whieh the interfaces will operate include a high data rate of lOQ kilobits per second and a low data rate of 12 to 14.5 kilobits per second.
With thls construction, the same source interface cir-cuit may be used with all data sources having corxespond-ing output data formats. Likewise, the same recelver in-terface circuit may be used with all receivers having cor-responding input data formats. As a consequence, a single bus may carry the data flow from a given data source to all receivers served there~y~ As will now be appreciated, this invention provides a digital data communication system which afords interchangeability, design efficiency and overall economies which surpass and are unparalleled by~
other digital data communications systems heretofore used in aircraft digital aviontcs systems. ~dditionally~ this invention satisfies or exceeds the m~nl`mum standards for the transfer of digital data between avion~cs s~stems ele-ments set forth in ~R~C Specification 429~ entitled l'Mark 33 Digital Information Transfer S~stem CDITs~i pub~
lished by Aeronautical Radio, Inc, Chereinafter referre~
to as the "ARINC 429 Specification'~l.
The AP~INC 429 Specification enables compatible inter-facing of two different pieces of equipment that may be built by two or more different manufacturers of avionics equipment. Adherence to the standard is voluntary; how- --ever, if the manufacturer wishes to sell products which are plug compatible in the application area encompassed by the standard, it behooves him to comply if at all feasible.
Previous standards have usually adopted the electrical charactistics of a pre-existing interface, especiallv if the usage of such electrical characteristics was wide-spread when the standard was drafted. Similarlv, the ARI~C 429 Specification is a consensus given to one set of interface specifications, rather than an optimal, more general solution to data communications interface problems.

3~

The present invention e~ploys a hybxid source interface ~hich perfox~s the funct~ons of a serial N~Z to ~Z data, clock and sync logic encoder and po~er line driver; and a hybrid~receiver interface which is coupled to t~e data bus and outputs serial NRZ data, clock and sync si~nals, Only the basic transmitting and receiving functions are `
i~plemented in the source interface and recei~er interface hybrids because they are intended for use as universal in-terface components and the utility of extra functions IS
application dependent, As a result r usexs ~ave more flex-ibility to optimize their interface design and the further advantage of reduced cost for a ~asic device usually re-sults in a lo~er system cost.
Two choices of circuit packaging to meet the above re-quirements are possible, They are large scale integration (LSI) or hybrid microcircuits~ The LSI solution yields lower recurring production costs at the expense of higher non-recurrins development costs, less po~er dissipation tolerance, and more troublesome amplifier trimming pros--pects. Here, hybrid packaging is preferred i~n terms o total quantities involved, power dissapation, unit price and technological compatibility. For production ~uantities of less than lO,OOO units, a hybrid IS more econo~ical than an LSI package, One of the advanta~es of a hybrid micxo-circuit design is that, like discrete co~ponent circu~ts,optimum components (in chip form~ can be co~ined to achieve a given circuit design goal. In order to o~t~mize power, speed and versatile interface compatibility, a mix of CMOS (logic) and BIPOL~R Clinear1 technology ~s pre-ferred. Hybrid manufacturing easily lends itself to mix-ing C~50S and bipolar technologies, whereas LSI manufac-turing does not. This flexi~ility does not yet exist with LSI circuits due to various manufacturing processes re-quired for different ty~es of optimum components. ~esi~des miniaturization, other advantages of a hybrid device are gained in reducing printed circuit board ~PCB) area, Xe-ducing cabinet sizes, shipping costs, ~urchasing and ~n-ventory costs Three packaging configurations would ~e desirabler a single source interface package, a sin~le receiver interface package and a dual recei~er ~nterface package.
his invention provides a source interface and a re-ceiver interface which meets or exceeds the recu~rements of the ARrNC 42g Specification. The source and recei~er interfaces are embodied in thick-film hybr~d microelec tronics circuits and pro~ide t~e circuit funct~ons ne~;
cessary to interface a new generation of avioni~cs s~stems or subsystems to a data bus for dia~tal ~nformation trans-fer from one location to another via line drivers, t~i~sted shielded pair transmission lines and line rece~vers~ in ac-cordance with the ARINC 429 Specif~cation~ However, their design is flexible and universal in nature so as not to preclude their usage in similar apPlications~ The hybrid-ized interfaces represent an efficient compromise in mini-mizing cost, power and physical package size while optim~izing speed, reliability and universal utilization as ver-satile interface components. ~ybrid technology has enabled an efficient mix of low power Cr10S and high speed bipolar-FET technology for optimum performance. Further, hybrid microelectronics packaging has reduced the physical pack-age size by 4:1 for the source interface and 6:1 for the receiver interface. Further advantages of these h~br;d~
ized interfaces are: elimination of the manufacturing problems associated with LSI circuits and the mult~tude of com~onentsrequired for discrete componerlt designs as ~eans of interfacing to an A~INC 429 Specification type data bus, andeliminatio~ of the proliferation of similar but incom-patible interface designs.
Accordin~ to further aspects of one preferred e~bodi-ment of this invention, the source interface and rece~ver 3~ ~J~a ~7 interface respectively provide the driving and receiving means ~or a direct cou~led, bIn~ryl sexial d~g;~tal data transmission channel using a shieIded, twisted pair wire cable as the transmission medium. The source interface includes a btnar~ encoder and a three~state d~fferential output trans~Ission line dri~er c~rcuit ~h~ch i~s d~rectly coupled to the transmission line and provtdes a ~al~nced, differential, three-state, r~.seti~e controlled and source terminated output signal~ Non?return to zero (NRZl data, cloc~ and sync si~nals are encoded ~y the sou~ce ~nter-face into a self~clocking three level code known as bi-polar return-to-zero CR~ modulat;~on~ ~ balanced, d~re.ct coupled, diferential input receiver circuit which. detects sa~d 3-state signal is used as the transm~ssion l~ne re-ceiver to receive and convert the bi.~olar return-to~zero ~P~7 ~ modulated signal into a return to zero C~Z) modu lated signal which. is then decoded to regenerate the ori-ginal data, clock and sync signals in an N~Z format~ No transmission line termination is ~rovided b~ the rece;~ver ~nterface; however, the source interace~s output imDed-ance is matched to the transmission line~s characteristic impedance and this ~rovides the means for a source ter~
minated system The data transmiss~on channel operates in a transmission mode defined as a "sim~lex di:str~ution bus" wh~ch affords uni-direct;'onal, non-revers~.~le data flow from a single source interface to the receiverCsi. A
maximum of 20 receivers may be connected to one data bus in an A~IMC 4-~9 S~ecification system? however, source and receiver interfaces may be used in other a~plications with, more than 20 receivers, different data transmission fre-quencies, cable arameters, etc~
An information or data source could be a com~uter, di.gitized transducer output or any other device ~hi~ch emits a seri.al stream of bits at th.e rate of one bit ever~ t~ se-conds, The informat'`on rate of the system is then defined ~1 3~37~ ~

as F = l/tB bits per second. T~le source and receiver in-terfaces described herein are designed ~o operate at a high frequency ~FH~ of lO0,000 bits per second or a low ', frequency (FL) range of 12,000 to 14,500 bits per second.
Although information rates F~ and FL are ARINC 429 Speci-fications characteristics, the interfaces may be used in other applications reauiring different information rates.
In addition to a data signal, the information source should also output a clock and a sync signal. ~hese signals are fed to a logic encoder which performs logic operaticns therein to produce two binarv data streams for control-ling a line driver as internal source log~c sLgnals~ The line drive converts these signals to required transmission line voltages and currents, LO~J impedance outputs of the line drivers are connected to bus term~nat~on resIstors which provide an impedance match between the out~ut im-pedance of the source ~nterface and the transmiss~n line's charaGteristic impedance so as to allow the source ~nter~
face outPuts to absor~ and prevent multiple l~-ne reflec-2a tions~ These differential output signals are transferredby the two differential signal wires of the twisted and shielded pair data bus constituting the transmission line to the inputs of the differential receiver. The receiver includes an input protection circuit which prevents damage to the receiver due to transmission line transients or any overvoltage condition present at the receiver inputs. Sig-nals arriving at the receiver's inputs are sensed by a differential amplifier which has an appropriate input im-pedance to prevent excessive line loading and enable high common mode rejection (CM~) to reject common mode noise signals. The binary output of this amplifier is the volt-age difference between the two input signal wires. Deci-sion is made on the logic state of the detector output by comparing it to h steresis tvpe threshold levels in loaic '1' and logic '0' detectors. Hysteresis type thresholds 3h~7~

improve the receiver's noise immunity bv rejecting trans-mission line noise r A data, clock and sync decoder per-form logic operations on the binary bit streams obtained to decode and reproduce the data, clock and sync ~ignals which appear at the information source. From t~e decoder, the recovered h~nary data ~asses to a receiver which is t~e destination for the information source data, The re-ceiver may be a computer, actuator or any device using the source inlormation, T~e frequenc~ mode of the receiv~
er mav be controlled by selecting a lo~ fre~uenc~ CF
or high frequency tFH~ of operation. Additionally, the rise and fall times of the source interface output sig-nals may be controlled for operation in the FL or F~ modes.
These and other features, objects, and advantages of the present invention will become apparent from the de-tailed description and claims to follow, taken in conjunc-tion with the accompanying drawings in which like parts bear like reference numerals.
Brief Description of the Drawings FIG~ 1 is a block diagram of the digital data communi~
cation system of this invention, FIG. 2 is a timing diagram of the differential bipolar return-to-zero signals in the FIG~ 1 system;
FIG~ 3 is a block diagram of the FIG~ 1 system in greater detail;
FIGo 4 is a timing diagram of the binary signals in the data source system element of FIC-~ 3;
FIG~ 5 is a block diagram of the FIG~ 3 source inter-face;
FIG~ 6 is a ti~ing diagram of the binary signals in the FIG~ 5 source interface;
FIG. 7 is a circuit diagram of the encoding logic of the FIG. 5 source interface;
FIG. 8 is a circuit diagram of the line driver A of the FIG. 5 source interface;

. .

FIG. 9 is a circuit diagram of the line driver B of the FIG. 5 source interface;
FIG. 10 is a ~lock diagram of the FIG, 3 receiver in-terface;
FIG. 11 is a circuit diagram of the differential in-put signal ampli~ier of the FIG. 10 receiver interface;
FIG, 12 is a timing diagram of the binary signals de-veloped in the FIG, 10 receiver interace;
FIG, 13 is a circuit diagram of the FIG. 10 ones de~
`10 tector;
FIG. 14 is a circuit diagram of the FIG. 10 zeroes de~
tector;
FIG. 15 is a circuit diagram of the FIG, 10 data de-coder;
FIG. 16 is a circuit diagram of the FIG. 10 clock de~
coder;
FIG. 17 is a circuit diagram of the FIG. 10 sync de-coder.
Detailed Description of the Drawings Referring to the digital data communication system o this invention as illustrated in FIG. 1, a data source sys-tem element 10 is connected to a plurality of receiver sys-tem elements 12, 14 and 16 by a conventional shielded twis.-ed pair transmission line or data bus 18. Data transfer 25 via line 18 is uni-directional in the direction indicated by the arrow in FIG. 1. In the example illustrated, infor-mation transmitted by the data source system element 10 is presented to line 13 as a differential bipolar return-to-zero (RZ) signal illustrated in FIG. 2. ~his signal a~-30 pears as signal A on one wire of line 18 and signal B on the other wire thereof. Signal A has an amplitude equal to the amplitude of signal B but opposite in polarity. Bi-polar RZ signals involve three dist~nct states, or voltage levels; HIGH, MULL and LO~,~. A logical one data bit is de-fined as a "HI" state during the first half of the bit in-terval returning to the "MULL" state during the second --ll--half of the same bit interval. A logical zero data bit is defined as a ~O" state during the first half of the bit interv~l returning to the "NULL" state durin~ the second half of the bit interval, It is a characteristic of RZ
coding that the signal always returns to the null state during the second half of each transmitted bit period.
The communication system of FIG. 1 is sho~n in more detail in FIG. 3 wherein the data source system element includes data source 20 and source interface 22, The re-ceiver system element includes receiver interface 24 andreceiver 26, Source interface 22 receives ~inary DATA-A, CLOCK-A, and SYNC~A signals, which are of t~e serial bi-nary nonreturn-to-zero (~RZ) type, from the data source.
Source interface 22 encodes and transmits the data in dif-ferential bipolar ~Z format on the transmission line toreceiver interface 24~ The receiver interface decodes the data and provides CLOCX-B, DAT~-B, and SYNC-B signals in an NRZ format to receiver 26~ The source and receiver in-terfaces are directly coupled to transmission line 18 as distinguished from capacitive or transformer coupling.
When information is continuously transmitted in differen-tial bipolar RZ format, a residual voltage can build up on the transmission line if transformer or capacitive coupling is used. This is because the energy in each bit does not always average out to zero and if, for example, a long se-ries of logical ones is transmitted, ~hen the NULL level rises towards the HIGH voltage level. The tendency of the NULL state to float is avoided by directly coupling the interface to the transmission line. However, other coup-ling techniques can be used to achieve the same resultsuch as using optical isolation to couple the interfaces to the bus.
The DATA-A, CLOCK-A, and SYNC-A signals and the sig-nals on line ~ and ~ine B are timed as illustrated in FIG.
4. When binary data is to be transmitted fro~ a data ~1 36~7 $l source system element, SYNC~A goes to a logic~l one state, SYNC~A acts as a transmit enable when it is in the logical one state and a transmit disa~le when it is in the logical zero state. The Line A and Line B waveforms de,icted as graphs A and B respectively, in FIG, 4 represent the sig-nals presented to the transmission line by the source in-terface in response to the signals from the data source.
I~hen the DATA~ signal is a logical one and the CLOCK~A
signal is a logical one, the s;gnal on line A is also a logical one and the signal on line B is a logical zero.
Similarly, when the DAT~-A si,gnal is a logical zero and the CLOCK-~ s~gnal is a'logical one the signal on line A
is a logical zero and the signal on line B is a logical one. The differential hipolar signals on lines A and B
are equal in amplitude but opposite in polarity, Source interface 22 will be described in further detail by reference to FIG. 5. It includes encoding logic 28, line driver A 30, line driver B 32 and line termination impedances 34 and 36. The signals provided to the input ports of the source interface correspond to signals DATA~A, CLOCK-A and SYNC-A of FIG. 4 and the corresponding wave-forms are shown for reference in FIG. 6 respectively. En-coding logic 28 transforms NRZ DATA-A into inverted R~ bi nary data. Encoding logic 28 generates at its output on line 40 a waveform depicted as waveform I in FIG. 6. Wave-form I is a logical zero whenever SYNC-A is a logical one, DATA-A is a logical zero and CLOCT~-A is a logical one.
Similarly, encoding logic 28 generates at its output on line 38 a signal as shown by waveform II in ~IG. 6. Wave-l form II is a logical zero whene~er SY~C-A iS a logical one, DATA-A is a logical one and CLOCK-A goes to a logical one.
The outputs of encoding logic 28 are fed into line driver 30 which procudes at its output line 42 a signal corres-ponding to waveform A for FIG. 6. The output from driver 30 is fed to driver 32 which produces at its output line ~.3~
-1.3-44 a signal corresponding to waveform B of FIGc 6, Output line 42 from driver 30 is finally fed to ~mpedance match-ing resistor 34 which in turn reproduces at its output 46 the pulse pattern corresponding to waveform A of F~G, 6.
Output 44 of driver 3Z is fed into impedance matchtng re-sistor 36 which in turn re~roduces at its output 48 the signal corresponding to ~aveform B of FIG, 6~
Reference is now directed to FIG, 7 ~hich illustrates a preferred circu~t for t~e FIG. 5 encodtng logic 28, In the example tllustrated~ encoding logic 28 co~prises a plurality of non-inverting ~uffers 50, 52 and 54~ The dashed gates 5l and 53 and their associated connections will be described later. In th~s example, the non-invert~
ing buffers are selected C~oS level shifting devices so that the DATA~A, CLOCK~A and SYNC-A s~gnals from the data source can vary in voltage fro~ between 3~S volts to 15 volts in the logicai l state,This level shiftin~ character of CMOS devices pexmits the power supply in the data source to o~erate at any voltage level between 5 and 15 volts. Thus, th.e information source generat;ng the data;
clock and sync may be transistor transistor logic ~TTL) !
Integrated Inject~on Logic ~I2L), C~oS or MMOS logic which allows flexible interfacing to the most standard lo~ic fa-milies~ The implementatIon oE encoding logic 28 has ?ro-visions for receipt of 3 signals from data source 20;DATA-A~ CLOCK-A, and SYNC-A. The DATA-A signal is fed in-to buffer 5Q and its output is connected to NAND gate 58 and inverter 56, The CLOCK-A signal is fed into buffer 52 and its output is connec.ted to NAND gate 58 and ~.ND gate ' 60~ The SYNC-A signal is fed into buffer 54 and ~ts out-put is connected to NAND gate 58 and NAND gate 60, The operation of the ~IG, 5 encoding logic circuit will now be described with reference to the waveforms depicted in FIG. 6~ Assume that the data source has data to trans-mit and the SYNC-A a signal is at a logical one, In the ., ~

~.;38~7~
-:L4-logical one state, the SY~7C-A signal acts as an enahle for gates 58 and 6Q. If the DATA-~ signal i5 at a logical one, then a logical one will ~e presented to gate 58 and in-verter 56. The output of inverter 56 will present a logi-cal zero to gate 60 which will force output line 40 of gate60 to remain in the logical one state~ ~hen CLOCK-.~ goes to a logical one state, a logical one will be presented to both gate 58 and gate 60. Output line 38 of gate 58 will go to a lo~ical zero When CLOCK~A returns to a logical zero, a logical zero will ~e presented to gates 58 and 60, Output 38 of gate 58 will return to the log~cal one state.
Thus, whenever DATAA is a logical one, output 40 will re-main in the logical one state and output 38 ~ill ~ave the same waveform as CLOCR-A but inverted, Assume now that the data source is going to transmit a logical zero. DATA A is a logical zero so the ouput of buffer 50 presents a logical zero to inverter 56 whose output presents a logical one to gate 60. The logical zero on the output of bugger 50 is also presented to gate 58 and forces output 38 to remain in the logical one state.
T~hen CLOCK-A goes to a logical one, buffer 52 presents a logical one to gate 58 and ~ate 60, and output 40 goes to a logical zero in response thereto. Output 38 remains in a logical one state because a logical zero is still pre- -sented to its input fro~ buffer 50. When CLOCK-A goes to a logical zero state, the output of buffer 52 is a logical zero and is presented to gate 58 and gate 60, and output 40 goes to a logical one in response thereto. Thus, when D~TA-A is a logical zero, output 38 will remain in the logical one state and output 40 will have a waveform like CLOCK-A but inverted. The waveforms on outPuts 40 and 38 are shown in FIG. 6 as Graphs I and II, respectively.
Referring now to FI o 8, a preferred circuit for the FIG. 5 line driver A (referenced 30~ has in~uts 38 and 40 and output 42. Input 38 to line driver 30 is the output . ~
'h ~ ' from encoding logic gate 58 and is connected to resistor 62. The output of resistor 62 is connected to capacitor 64, resistor 66, capacitor Ç8 and the inverting input of operational amplifier 70, Input 4Q ~s the output of en-coding logic gate 60 and is connected to resistor 72, The output of resistor 72 is connecte~ to resistor 74, capacitor 76, capacitor 78 and a non-inverting input of ~perati~nal amplifier 70. The output of operational am-plifier 70 is connected to current limiting resistor 80.
The output of resistor 80 is connected to a current boost-er circuit comprising transistors Ql, Q2, resistors 82 and 84 and diodes 86, 88, 90, and 92. Output 42 of the cur-rent booster circuit is connected to resistor 66, capaci-tor 68, and impedance matching resistor 34. Output 46 of resistor 34 is connected to the transmission line.
When a logical zero is applied to line 38 and a logi~
cal one is applied to line 40 then the output of opera-tional amplifier 70 goes to a logical one. Current flows through resistor 80 and into the base of transistor Ql to turn it on. However, the base of Q2 is positi~e with res-pect to its emitter which turns it off. With transistor Ql on, curxent flows from the positive power supply through resistor 82 into resistor 34 to terminal 46 where it is presented to the transmission line. When a logical one is applied to liné 3~ and a logical zero to line 40, the output of operational amplifier 70 is a logical zero.
With a logical zero on the output of operational ampli-fier 70, the base of Ql is at a logical zero causing Ql to be turned off. The base of Q2 is also at a logical zero which tvrns Q2 on. ~ith Q2 turned on, current flows from the transmission line into terminal 46, through re-sistors 34 and 84, through Q2 and into the negative power supply causing the voltage level on the transmission line to be pulled down to the value of the logical zero output state. Resistor 80 acts as a current limiting resistor . .

~ ~.31~

i and prevents oscillations from occurring on the output of operational amplifier 7~ ~esistor 82 limits the amount of current that can be sourced by transistor Ql to the transmission line, Resistor 84 limits the amount of cur- ¦' rent that can be sunk by Q2 from the transmission l;~ne. I
in the event the transmission l~ne'should ~e shorted to ground, resistors 82 and'84 protect transistors Ql and Q2 from conducting excessive currents., Still r~ferring to FIG. 8, the rise time of the pulse generated at output 46 is controlled by two RC networks in order to minimize the electromagnetic interference associ~
ated with pulses havin~ fast rise times. The advantages of controlling rise and fall times on only one amplifier include using less parts, lowering manufacturing labor and parts costs, improved reliabilitY and fewer external pack-age pins and connections for rise time control. The .f irst rise time control circuit is made up of resistor 66 and capacitor 68 and the second circuit is made up of resistor 74 and capacitor 76. In the preferred embodiment, the source interface operates at two data rates, a high data rate of lO0 KBITS/SEC and a low data rate of 12 KBITS/SEC
to 14.5 XBITS/S~C. The normally sharp rising edge of a - pulse at terminal 46 is slowed down by the integrating ef-fect of these two circuits when the source interface is o~-~rating at the high data rate. The circuit is adaptable for operation at the low data rate by jumpering three ter-minals. Terminal 98 is connected to ground which has the effect of paralleling capacitors 76 and 78, and terminal 94 is connected to terminal 96 which has the effect of paralleling capacitors 64 and 68. It is readily apparent that the source interface has universal application at any data rate by choosing the proper values of,capacitors 64, 68, 76 and 78 to acconmodate any rise time rea,uire-ment that a system might have. Additionally, the rise and fall times are user selectable without requiring addi-tional components, d ~:L7~.

Referring no~ to FIG, 9~ a preferred circu~t for the FIG, 5 line dxiver B (referenced 32~ has an ~nPut 42 and output 44O Input 42 ~s driven from l~ne driver 3~ and is connected to res~stor l~a. The output of resistor lOa is connected to resistor 101 and the inverting inpu~ of ope`ra-~ t~onal amplifier lQ2~ The non~;~n~e~ting input of opera~
tional amplifier 102 is connected to resIstor lQ4 which is grounded at its other terminal., The output of opera-tional amplif~er 102 ~s connected to resi~stor 106 w~ich has ~ts output connected to a second current booster cir-cuit. This curre~t booster circuit includes transistors Q3 and Q4, resistors 108 and llQ, and diodes 112, 114, 116, and 118, Line driver 32 is a unity gain inverting amplifier and produces a signal equal in am~litude to that presented to line A but opposite in polarity. If a logical zero sig-nal is applied to input 42, then the output of operation-al amplifier 102 will be a logical one. Current will flow through resistor 106 and into the base of transistor Q3 and cause Q3 to turn on. The logical one presented to the base of transistor Q4 causes 04 to turn off. Current will flow from the positive power supply through Q3, resistor 108 and impedance matching resistor 36 to outPut terminal 48. If a logical one signal is presented to input line 42, the outpu~ of operational amplifier 102 will be a logical zero. The logical zero is presented to the bases of tran-sistors Q4 and Q3 causing transistor Q3 to turn off and Q4 to turn on. With transistor Q4 turned on, current can flow from the,transmission line into terminal 48, through ' resistors 36 and llQ, transistor Q4 and into the negative power supply. Thus, when the signal on line 42 is at a logical one, terminal 48 will be at a logical zero and when the signal on line 42 is at a logical zero terminal 48 will be at a logical one.
FIG. 3 illustrates a receiver system element compris-.

~Jl.3~6 ing receiver interface 24 having input terminal 250 and 252 and output terminals 142, 136 and 146 which convey bi-nary signals CLOCK-~, D~A-~ and syr~c-B to the ~nputs of receiver 26, P~eceiver interface 24 is illustrated in block diagram form in FIG, 10, InPut terminals 250 and 252 are connected to the transmisslon l~ne to receive the d;ffer-ential ~ipolar RZ data transrnitted by the data source sys-tem element. Output 120 of differential input signal am-pli~ier 122 is connected to the inputs of ones detector 124 and zeros detector 126, O~tput 128 of the zeros de-tector is fed into the data decoder 130 and clock decoder 134. Output 132 of the ones detector is fed into data de-coder 130 and clock decoder 134~ The output of the data decoder is connected to terminal 136 and provides a signal designated DATA-B, Output 138 of the clock decoder is fed into sync decoder 14Q and is also connected to terminal 142 and provides a signal designated CL~CR-Be Sync decoder 140 has another input connected to terminal 144 and an out-put connected to terminal 146 which provides a s~anal de-signated SYNC-B.
FIG. 11 depicts the circuit implementation of differ-ential input signal amplifier 122 of FIG, 10, Referring to FIG. 11, the differential input signal amplifier has in-put terminals 250 and 252, which interface with the trans-mission line, connected to resistors 146 and 148 respect-ively, The output of resistor 146 is connected to the anode of diode 150, the cathode of diode 152 and resistor 158. The output of resistor 148 is connected to the ca-thode of diode 154, the anode of diode 156 and resistor 160, The anodes of diodes 152 and 154 are connected to the negative power supply and the cathodes of diodes 150 and 156 are connected to the positive power supply, The output of resistor 160 is fed into the non-inverting input of operational amplifier 162 and also into resistor 164 which has its output terminal connected to ground, The :~1 3~
-:L9-output of resistor 15~ is connected to the inverting input o ope~ational amplifier 162 and feedback resistor 166 which has its output connected to t~e output terminal of operational amplifier 162, The diode bridge operates in conjunction wlth resis-tors 146, 148, 158, 16~, and 164 to protect operational amplifier 162.xom overvoltage transients on the trans-mission line. If a voltage is applied to terminal 252, then the voltage would be divided across resIstor 148 and the comb1nation of resistors 160 and 164~ ~f the voltage level at node 149 is above the voltage level of the posi-tive power supply ~y more than one diode drop, then d;ode 156 would conduct, The input of resistor 160 ~ould there-fore never see a voltage level ~reater than one diode drop above the positive power supply, Similarly, if the voltage applied to terminal 252 is a negative voltage, then the voltage would divide across resistor 14~ and the comhina-tion of resistors 160. and 164~ If the voltage level at node 149 is below th,e voltage level of the negative pow~
er supply by more than one diode drop then diode 154 would conduct~ Therefore, the input to resistor 160 would never see a voltage level more negative than one diode drop be-low the negative power supply, Resistor 146 and 148 also limit the amount of current permitted to flo~ through the diode bridge whenever an o~er-volta~e transient occurs on the transmission line.
Referring again to FIG, 11, operational amplifier 162 detects the differential voltage bet~een term~nals 252 and 250 and provides a bipolar return-to-zero si~nal on line 120, If a logical one is applied to terminal 252 and a logical zero is applied to terminal 250 then the output of operational amplifier 162 on line 120 is a lo~ical one, Similarly, if a logical zero is placed on terminal 252 and a logical one on terminal 250 t~en the output of opera-tional amplifier 162 on line 120 is a logical zero, The 37~

relationship between the in~ut signals present at termi-nals 250 and 252 and the output signal produced on line 120 is depicted FIG~ 12, wherein graph A corres~onds to a waveform presented to terminal 252, graph B corresponds to a ~aveform presented to terminal 250 and graph C cor- -responds to the resulting signal presented to line 120.
F~G, 13 illustrates the c~rcuit implementat~on of ones detector 124 of FIG, lQ. ~ine 120 is the inverti~ng input to voltage comparator 17~ and originates at output 120 of operational amplifter 162 shown in FIG. 11, The non-inverting input of voltage comparator 170 is connected to feedback resistor 172 and bias res~stors 174 and 176~ The other terminal o~ res~stor 174 is connected to the ~ositlve power suppl~ and the ot~er termin~l of resistor 176 ~s con~
nected to ground~ Output 132 of voltage cOm~ar~tQr 170 is connected to the other terminal of feedback resistor 172 and also to pull-up resistor 180, which has its other ter-minal connected to the positive power supply. Resistor 172, 174 and 176 form a resistor network to set the detec-tion threshold for a logical one.
For illustrative purposes, graph C of F~G, 12 illus-trates a waveform applied '~o line 120 which feeds the in-verting input to voltage comparator 170, and graph D il-lustrates the waveform developed by volta~e comparator 170 and applied to line 132. Thus, when a positive 5tgnal ex~
ceeding the logical one threshold is applied to line 12~, the ones detector circuitry provides a logical zero on out.
put line 132. When a negative signal is appli.ed to line 120, output 132 remains in a logical one stateO The out-put o the logic.~ ones detector goes to a logical zero only when line 120 receives a positive signal exceeding the logical one threshold, FIG. 14 illustrates the circuit im~le~entat'~on of zero detector 126 of FIG. 10. Voltage comparator 182 ~s con-nected by line 120 at ItS invertins input to output 120 of ~,, .' ~3~C~7~

operational amplifier 162 shown in FIG. 11. The non-inver-ting input is connected to feedback resistor 184, resistor 186, which has its other terminal connected to ground, and resistor 188, which has its other terminal connected to the negative power supply. Output 190 of vol'cage comparator 182 is connected to the other terminal of feedback resis-tor 184, one side of resistor 192, which has its other side connected to the positive power supply, and invertor 194, which has output terminal 128.
FIG. 12 depicts the relationship between the b,polar RZ
waveform on line 120 of FIG~ 14, which is referenced as graph C, and the resulting waveforms on lines 190 and 128 which are referenc~d as graphs E and F, respectively. If a logical one or a NULL is applied to line 120, output 190 of voltage comparator 182 will remain at its steady state logic zero condition and output 128 of invertor 194 will remain a logical one. When a logical zero is applied to line 120, output 190 goes to a ;ogical one and output 128 goes to a logical zero. Thus, output line 128 is usually in the logical one state and goes to the logical zero state only when the signal on line 120 goes to a logical zero.
The circuit implementation of data decoder 130 of FIG.
10 is shown in FIG. 15~ The data decoder is implemented from two NAND gates in an RS flip-flop configuration with a non-inverting buffer on the output. Normally, inputs 132 and 128 will have logical ones applied to them as depicted by waveforms D and F, respectively, of FIG. 12. Input 132 is the set side o the RS flip-flop and input 128 is the reset side, If a logical zero from the ones detector is applied to line 132, output 196 of the RS flip-flop will go to a logical one as will output 136 of non-inverting buffer 204. The RS flip-flop will maintain this state until a logical zero is applied to line 128 from the zeros detec-tor, causing output 196 of the RS flip-flop to go to a lo-gical zero as does output 136 of non-inverting buffer 204.

0~
~22 .1 No~, the RS flip-flop will ma~ntain thIs state unt~1 a lo-gic zero is applied to line 132 from the ones detector, ~àveform H of FIG, 12 depicts t~e D~TA-B output of the data decoder of FIG, 15~ The output remains a log~cal one when-ever a logical zero occurs in input line 132 (waveform D, FIG 12~, until a logical zero occurs on input line 128 (waveform F, FIG, 12~. Similarly, the output remains a lo-gical zero whenever a logical zero occurs on input line 128, until a logical zero occurs on input line 132.
Referring to FIG. 16, the circuit implementation of clock decoder 134 of FIG. 10 is illustrated. The signal on input 132 to NAND gate 206 is generated ~y the ones detector circuitry and is shown as graph D o-E FIG. 12~ The signal on input 128 is generated by the zeros detector circuitry and is illustrated as graph F of FIG. 12. The logical NAND of these two signals appears on line 208, which is connected to non-inverting ~uffer 210 Output 138 of buf$er 210 is illustrated as graph G in FIGo 12 and is designated the CLOCK-B signal. ~he CLOCR~B. signal that appears at ter-minal 142 is a logical one w~enever the output from tne ones detector on line 132 is a logical zero or ~henever the output from the ZerGS detector on line 128 is a logical zero, otherwise, the CLOCK-B signal is a logical zero.
The circuit implementation of sync decoder 140 of FIG ~ . .
10 is illustrated in FIG~ 17. The sync decoder has input line 209, from the output of NAND gate 206 (FIG. 16), and input terminal 144 and output terminal 146. Input line 209 is connected to the input of invertor 212, which has its output 214 connected to the cathode of diode 216. The anode of diode 216 is connected by line 218 to one side of capacitor 220, which has its other side connected to ground, the input of Schmitt trigger 222, one side of pullup resis-tor 224, which has its other side connected to the posi-tive power supply, and one side of capacitor 226, which has its other side connected to input terminal 144~ Output 228 of Schmitt trigger 222 is connected to the input of non-1~.3E~

inverting buffer 23a, w~ich has its output connected tc output terminal 146, and provides a signal which is desig~
nated SYNC-B.
When the receiver inter~ace is receiving data from the transmission line, the clock decoder continuously gene-rates a clock pulse for each ~it period, depicted by graph G of FIG. 12. These clock pulses are provided on line 209 to invertor 212 of FIG. 17, When the signal on line 209 is a logical one, then output 214 of the invertor goes to a logical zero and causes diode 216 to conduct. With the diode f~rward biased, capacitor 220 is discharged through diode 216 and a logical zero appears on the input to Schmitt trigger 222~ Output 22~ of the Schmitt trigger goes to a logical one, causing the output of buffer 230 to be a logi-cal one also, When the signal on line 209 returns to alogical zero, output 214 of invertor 212 goes to a logical one, causing diode 216 to be reverse biased and.it stops conducting, Capacitor 220 ~egins to charge from the posi-tive power supply through resistor 224. If the receiver in-terface continues to rece~ve data from the transmission linethen another clock pulse will appear on ,line 209 and cause capacitor 220 to be. discharged again through forward biased diode 216, and the input to Schmitt triggér 222 will never reach, a logical one s.tate, Under such a mode or operation, output 228 of the Sc~m~tt trigger will remain in the logi-cal one state,while data is being received as depicted by waveform I of FIG. 12. When data is no longer received, line 209 will normally be at a logical zero, causing output 214 o~ invertor 212 to be a logical one. Diode 216 is re-~
verse biased and capacitor 220 will charge through resistor 224 up to a logical one~ With a logical one applied to the input of Schmitt trigger 222, output 228 will go to a lo-gical zero state and the SYNC-B signal at terminal 146 will also be in a zero state, The RC time constant of resistor 224 and capacitor 220 is such that the voltage level at the input to Schmitt trigger 222 will rise from a logi-cal zero to a logical one if no clock pulses appear for ap-proximately two successive bit periods, When the SYNC-B
signal returns to a logical zero, it signifies the end of the data reception, The receiver interface will operate at ~hatever fre-quency data arrives on the transmlssion line. But it may be desirable to tailor the RC time constant to a fast and a slow data rate. To provide a proper RC time constant ~or a fast data rate terminal 144 is left open and the RC time constant is determined by the combination of resistor 224 and capacitor 220, If receiver operation is desired at a lower data rate, then terminal 144 is connected to ground which effectively parallels capacitor 226 and capacitor 220.
In this configuration, the RC time constant is calculated as the product of the resistance 224 and the parallel com-~ination of capacitors 220 and 226.
Although one preferred em~odiment of the invention has been illustrated and described herein, variations will be-come apparent to one of ord~nary skill in the art. For ,example, it will ~e a~preciated that in its simplest form, the diode circuits of FIG, 8 and FIG, 9 provid~ short cir cuit current protection for the source interface by limit-in the amount of current it can source if the transmis-sion line is shorted to ground. However, in some appli-cations, a solid state active circuit may ~e preferred, Furthermore~ in some applications it may be preferable for the data source to provide only two binary signals in the return-to-zero ~RZ) format; a data ones signal and a data zeros s;gnal. When a logical one occurs in the data ones signal, it indicates that the data source is provid-ing a logical one to t~e source interface. ~hen a logi-cal one occurs on the data zeros signal, it ;ndicates that the data source is providing a logical zero to the source interface, The encod~ng logic of FIG. 7 is readily adapt-37~

able for accepting these RZ data signals~
For example, if the wires shown in ~IG. 7 are cut at points 55 and 57, and gates ~1 and 53, which are similar to gates 50, 52 and 54, are connected as shown by the dotted lines, then the circuitry is configured to accept the ones data and zeros data signals described above, The ones data signal is applied to the input of gate 50, the zeros data signal is applied to the input of gate 53, the input to gate 51 is connected to ground, and the inputs to gates 52 and 54 are connected to the positive power supply of the data source. When a logical one is applied to the input of gate 50, the output of gate 38 will be a logical zero. When a logical one is applied to gate 53 r the out-put of gate 60 will be a logical zero. Thus, the encoding logic is readily adaptable for accepting two binary sig-nals in the return-to-zero format from the data source and transforming them into signals compatible with the cir-cuitry following the encoding logic. Accordingly, the in-vention is not to be limited to the specific embodiment illustrated and described herein, and the true scope and.
spirit of the invention are to be determined by reference to the appended claims,

Claims

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A digital data communication system for transfer-ring digital information from a source to one or more re-ceivers, comprising: source interface means for receiving digital signals generated by the source and producing en coded digital signals while controlling their rise and fall times on the basis of frequency of the source genera-ted signals; receiver interface means for decoding said encoded digital signals into digital signals representa-tive of said source generated digital signals for presen-tation to a receiver; and bus means operatively associated with said source interface means and said receiver inter-face means for transferring said encoded digital signals from said source interface means to said receiver inter-face means.

2. The system of claim 1, wherein said source inter-face means include means for controlling rise and fall times of said encoded digital signals on the basis of two source generated signal frequencies.

3. The system of claim 1, including a plurality of receiver interface means operatively associated with said bus means at spaced apart locations for decoding said en-coded digital signals into signals representative of the source generated signals for presentation to respectively associated receivers.

4. The system of claims 1, 2, or 3, wherein said source interface means include means for shifting voltage level of the source generated signals.

5. The system of claims 1, 2, or 3, wherein said source interface means include impedance matching means for terminating said bus means in its characteristic im-pedance.

6. The system of claims 1, 2, or 3, wherein said source interface means and said receiver interface means are directly coupled to said bus means.

7. The system of claim 1, wherein said source interface means include encoding means for receiving digital signals from the source and encoding said signals, first line driver means for receiving said encoded signals and providing a first encoded digital signal for present-ation to said bus means, second line driver means for receiving said first encoded digital signal and converting it to a second encoded digital signal opposite in polarity to said first signal for presentation to said bus means along with said first signal to produce said encoded digital signals in a differential bipolar return-to-zero format.

8. The system of claim 7, wherein said encoding means include means for receiving and encoding a binary data signal, a binary clock signal and a binary sync signal.

9. The system of claim 8, wherein said receiver inter-face means include differential input signal amplifier means for receiving said encoded digital signals and converting them into encoded bipolar signals indicative of the presence of logical ones and logical zeros, ones de-tector means responsive to said encoded bipolar signals for producing a ones signal indicative of the presence of a logical one, zeros detector means responsive to said encoded bipolar signal for producing a zeros signal indicative of the presence of a logical zero, data de-coder means responsive to said ones signal and said zeros signal for producing a binary data signal for presentation to the receiver, clock decoder means responsive to said ones signal and said zeros signal for producing a binary clock signal for presentation to the receiver, and sync decoder means responsive to said binary clock signal and an external control signal for producing a binary sync sig-nal for presentation to the receiver, whereby said data signal, clock signal and sync signal are representative of the source generated signals.

10. The system of claim 9, wherein said receiver in-terface means further include means for presenting a pre-determined binary information signal to a receiver commenc-ing upon beginning of transfer of said encoded digital sig-nals and persisting for a time period extending beyond the termination of transfer of said encoded digital signals and related to the frequency thereof.

11. The system of claim 10, wherein said receiver interface means include means for selecting said time pe-riod.

12. A system of claim 7, wherein said bus means in-clude a twisted shielded pair of electrical conductors and wherein said first and second encoded digital signals are respectively applied thereto.

13, A source interface circuit for presenting in-formation to bus means, comprising: means for receiving digital signals generated by a source and producing en-coded digital signals; means responsive to said encoded digital signals for controlling their rise and fall times on the basis of frequency of the source generated signals;
and means for presenting said encoded digital signals to the bus means.

14. The circuit of claim 13, wherein said means for controlling rise and fall times include means for control-ling rise and fall times of said encoded digital signals on the basis of two source generated signal frequencies.

15. The circuit of claims 13 or 14, including means for shifting voltage level of the source generated signals.

16. The circuit of claims 13 or 14, including im-pedance matching means for terminating said bus means in its characteristic impedance.

17. The circuit of claims 13 or 14, wherein said interface means is directly coupled to said bus means.

18. The circuit of claim 13, including encoding means for receiving digital signals from the source and encoding said signals, first line driver means for receiving said encoded signals and providing a first encoded digital signal for presentation to said bus means, second line driver means for receiving said first encoded digital signal and converting it to a second encoded digital signal opposite in polarity to said first signal for presentation to said bus means along with said first signal to produce said encoded digital signals in a bipolar return-to-zero format.

19. The source interface means of claim 18 wherein said encoding means include means for receiving and encoding a binary data signal, a binary clock signal, and a binary sync signal.

20. A receiver interface circuit for receiving encoded digital signals representative of source generated digital signals transmitted via bus means, comprising: means for decoding said encoded digital signals into digital signals representative of the source generated signals for presentation to a receiver, differential input signal amplifier means for receiving said encoded digital signals and converting them into encoded bipolar signals indicative of the presence of logical ones and logical zeros, ones detector means responsive to said encoded bipolar signals for producing a ones signal indicative of the presence of a logical one, zeros detector means responsive to said encoded bipolar signal for producing a zeros signal indicative of the presence of a logical zero, data decoder means responsive to said ones signal and said zeros signal for producing a binary data signal for presentation to the receiver, clock decoder means responsive to said ones signal and said zeros signal for producing a binary clock signal for presentation to the receiver, and sync decoder means responsive to said binary clock signal and an external control. signal for producing a binary sync signal for presentation to the receiver, whereby said data signal, clock signal and sync signal are representative of the source generated signals.

21. The circuit of claim 20, wherein said sync decoder means include means for presenting a predetermined binary information signal to a receiver commencing upon termination of transfer of said encoded digital signals and persisting for a time period extending beyond the termination of transfer of said encoded digital signals and related to the frequency thereof.

22. The circuit of claim 21 wherein said sync decoder means include means for selecting said time period.