CA1139860A - Error correction in a digital signal transmission system - Google Patents
Error correction in a digital signal transmission systemInfo
- Publication number
- CA1139860A CA1139860A CA000346490A CA346490A CA1139860A CA 1139860 A CA1139860 A CA 1139860A CA 000346490 A CA000346490 A CA 000346490A CA 346490 A CA346490 A CA 346490A CA 1139860 A CA1139860 A CA 1139860A
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- words
- delay
- error correcting
- signal
- digital
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
- G11B20/1806—Pulse code modulation systems for audio signals
- G11B20/1809—Pulse code modulation systems for audio signals by interleaving
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- Multimedia (AREA)
- Signal Processing (AREA)
- Error Detection And Correction (AREA)
- Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
Abstract
ABSTRACT OF THE DISCLOSURE
In a digital signal transmission system, a predetermined number of words of digital information signals are added bit by bit in a first modulo-two adder to produce a first parity signal.
The information signals and the first parity signal are delayed so as to have different delay times to each other, and the signals thus delayed are again added bit by bit in a second modulo-two adder to produce a second parity signal, which is fed back to the first modulo-two adder to thereby add it with the information signals. The predetermined number of words of information signals and the first and second parity signals are serially transmitted through a transmission line.
In a digital signal transmission system, a predetermined number of words of digital information signals are added bit by bit in a first modulo-two adder to produce a first parity signal.
The information signals and the first parity signal are delayed so as to have different delay times to each other, and the signals thus delayed are again added bit by bit in a second modulo-two adder to produce a second parity signal, which is fed back to the first modulo-two adder to thereby add it with the information signals. The predetermined number of words of information signals and the first and second parity signals are serially transmitted through a transmission line.
Description
BACKGROUND OF THE INVENTION
Field of the Invention The invention relates to a digital signal transmission system, and in particular is direct-ed to a system for transmitting digital information signals through a transmission medium, such as a magnetic tape and microwave line, which is subjected to disturbances causing burst errors, and for enabling corre.ction of the errors which occur in the received digital signal.
Description of the Prior Art Recently, there is proposed to record a digital information signal, such as audio PCN
signal, on a magnetic tape by using a video tape recorder. However, it is well known -
Field of the Invention The invention relates to a digital signal transmission system, and in particular is direct-ed to a system for transmitting digital information signals through a transmission medium, such as a magnetic tape and microwave line, which is subjected to disturbances causing burst errors, and for enabling corre.ction of the errors which occur in the received digital signal.
Description of the Prior Art Recently, there is proposed to record a digital information signal, such as audio PCN
signal, on a magnetic tape by using a video tape recorder. However, it is well known -
- 2 -g ~ , .
" 1139~fà0 that drop-outs causing a burst error frequently occur in the digital signal reproduced from the tape. There are provided several types of transmission systems to correct such a burst error, as appearing in the reproduced PCM signal.
One of the systems is shown in VSP 3409875, in which the PCM signal is transmitted through two lines, one of which includes a predetermined dealy.
In the receiving side, the outputs of the lines are applied to an output device through a switch controlled by an error responsive device, which is responsive to unequal signals at the outputs of the lines, so that upon detection of the unequaI
signals the switch i5 connected to the line having a delay for a predetermined time. Thus, the system can correct the burst errors appearing in the line. However, it is necessary in the above system to provide the two lines for transmission of the same signal. In other words, the capacity of the transmission medium is needed double the usual one.
In order to overcome the above-des-cribed disadvantage, there is proposed the improved digital signal transmitting system, such as that described in Canadian Application No. 329,935 and assigned to the same assignee as the present invention. In the system, a plurality of words of digital information signals are added bit by bit in a modulo-two adder and a first parity signal is generated for the predeter-mined number of words of the digital information 1~39~0 signals. Each word of the information digital signals and the parity signal are respectively delayed so as to have different delay times to each other. The information signals and first .
parity signal thus delayed are added bit by bit in a modulo-two adder to generate a second parity signal for the information and parity signals, and then the predetermined number of words of digital information signals and the first and second parity signals are serially transmitted through a trans-mission line.
According to the system, in case that some errors are introduced in the digital information signals during transmission, it is possible to correct such errors perfectly, unless the errors are contained in more than three words of the information signals. However, lt is impossible to correct the errors included in more than three words of the information signals by the digital signal transmission system of the prior application.
SU~IMARY OF THE INVENTION
An object of the invention is to provide an improved digital signal transmission system in which burst errors contained in the transmitted signal can be corrected at the receiving side.
Another object of the invention is to provide a new system for transmitting digital signals together with parity signals which are composed from the former signals, and for correcting burst errors in the transmitted signal by utilizing the parity signals.
_ - 4 -1139~
A further object of the invention is to provide an improved system for correcting errors contained in the transmitted signal with high correcting ability.
In the system of the invention, a predetermined number of words of digita~ informa-tion signals are added bit by bit in a first modulo -two adder to produce a first parity signal.
The information signals and the first parity signal are delayed so as to have different del'ay times to each other, and the signals thus delayed are again added bit by bit in a second modulo-two adder to produce a second parity signal, which is fed back to the first modulo-two adder to thereby add it with the information signals. The predetermined number of words of'information signals and the first and second p æity signals are serially transmitted through a transmission line.
The other objects, features and advantages of the invention will become apparent from the following description taken in conjunction with the accompanying drawings through which the like references designate the same elements.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. l is a block diagram of the system according to the prior application;
Fig. 2 is a table which is used for the explanation of the system of Fig. l;
Fig. 3 is a block diagram of another system according to the prior application;
Fig. 4 is another table which is used for the explanation of the system of Fig. 3;
Fig. 5 is a block diagram showing an example of the encoder used in the system according~
to this invention;
Fig. 6 is a block diagram showing exam-ples of the encoder and decoder used in another system according to this invention;
Fig. 7 is a table which is used for the explanation of the system of Fig. 6; and Fig. 8, appearing with Fig. 5, is a block diagram showing an example of the encoder used in a further system according to this invention.
_ SCRIPTIO~ OF THE PREFERRED EMBODIMENTS
Before describing the present invention, the system of the prior application will be explained.
Figs. lA and lB show an encoder and a decoder of a system which has been disclosed in the prior application, respectively.
In Fig. lA, la and lb designate input terminals of an encoder which are respectively supplied with a series of words of PCM signals.
In this example, PCM signals (W0, Wl, W2, ..... ) of 1 channel, which are produced by pulse code modulating an audio signal, are distributed into a series of PCM signals SLo consisting of even numbered words (W0, W2, W4, ...... ) and a series of PCM signals SLl consisting of odd numbered words (Wl, W3~ W5, The series of PCM signals SLo and SLl are applied to the input terminals la i~7~
:~39S~O
and lb, respectively. The PCM signals in the series of P~ signals SLo and SLl are supplied to a modulo-two adder 2 word by word. In the modulo-two adder 2~r(Wo (+~ Wl = P0), (W~ ~ W
(~
..... and (W2n ~ W2n+1 P2n) subsequently and thereby a series of first parity signals SP0 ~re f~rmed from the adder 2. The series of the PCM signals SLo are delivered, as they are, to an output terminal 5a while the series of PCM signals SLl and the series of parity signals SP0 are deli-vered through a delay circuit or line 3a of one word delay time and a delay circuit or line 3b of two word delay times to output terminals 5b and 5c, as series of delayed PCM signals SLlo and series of delayed parity signals SPl, respectively.
Each word of the PCM signals from the series of the PCM signals SLo and SLlo is supplied to a modulo-two adder 4, in which adding - ~W2n ~ W2n_2+1) is performed to obtain a series of second parity signals SQo.
The series of the PCM signals SLo and SLlo and the series of the parity signals SPl and SQo which are obtained in the above-described manner are fed to output terminals 5a, 5b, 5c and 5d, respectively.
Fig. lB shows a decoder corresponding to the encoder shown in Fig. lA. In Fig. lB , 6a, 6b, 6c and 6d designate input terminals which are supplied with the series of PCM signals SLo, SLlo and the series of second and first parity li3~
signals SQo ~ SPl, respectively. The series of PCM signals SLo, SLlo and the series of second parity signals SQo are supplied to a Q-decoder 7 in which the error correction by the second parity, signals is carried out. The series of PCM
signals thus corrected by the parity signals are supplied through a delay circuit or line 8a of two woxd delay times and a delay circuit or line 8b of one word delay time to a P-decoder 7, res-pectively. The series of first parity signals-SPl is supplied to the P-decoder 9 so that the error correction by the first parity signal is performed in the P-decoder 9. The series of PCM signals SLo and SLl thus corrected are deliver-ed to output terminals lOa and lOb, respectively.
The above-described encoder and decoder are so formed that the error in each word can be detected independently. Now, the error correction of this case will be explained. In Fig. 2, three woras coupled through the solid lines form first parity signals, and three words coupled through the broken lines orm second parity signals, respectively. It assumes that the decoder is so constructed that the error is corrected firstly by the Q-decoder 7 as sho~Jn in Fig. lB. Under such assumption;
if the error is an error of one word in three words coupled through the broken lines, any errors more than two words can be completely corrected.
Further, even in the case where an error exists 1139~0 in more than two words in the three words coupled by the broken lines, if other two words coupled by the solid line with the erroneous words are correct, the correction becomes possible. If three words, for example, W4, W5 and W6 are erroneous, the two words W5 and W6 can not be corrected by the Q-decoder 7 and remain as they are not corrected, but the word W4 is corrected by a parity signal Q4. Therefore, the errors in words W5 and W6 can be corrected in the P-decoder 9 by parity signals P4 and P6, respectively.
By the way, in such a case where the errors are included in the three words such that PCM signals of two words forming the second parity signals are erroneous and also the first parity signal containing either of the two words of PCM signals is erroneous, the correction thereof becomes impossible. For example, in such a case where three words W5, W6, P4, which are respectively indicated by double circles in Fig. 2, are erroneous, when the Q-decoding is carried out firstly and then the P-decoding is carried, the correction becomes impossible.
In order to avoid that the correction of errors of specific three words becomes impossible, it may be considered that an encoder and a decoder shown in Figs. 3A and 3~
respectively, are employed. That is, during encoding second parity signals Q2n are formed, such that the first parity signals P2n 4 are contained, into the second parity signals Q2n in addition to the PCM signals while the decoder is so formed that the error in the first parity signals can be corrected in the Q-decoder 7. According to the encoding system shown in Fig.
3A, since the first parity signals are also contained so as to form the second parity signals as shown in Fig. 4 by the broken lines, three word errors in any positions can be corrected.
i~3~
However, considering four word errors, the correction becomes impossible, when the specified four words are erroneous. In other words, when the corrected result from the P-decoder 9 is not fed back to the Q-decoder 7, the correction of four word errors is impossible, if the four words errors are corrected by only the first parity signal.
While, even if the decoder is so formed that the corrected result from the P-decoder 9 is fed back to the Q-decoder 7, when the shape formed by connecting four erroneous words in Fig. 4 becomes a parallelogram, the correction of four word errors become impossible. For example, when four words W7, W8, Wg, P6 which are respectively marked with double circles in Fig. 4 are erroneous, these errors can not be corrected by either of the Q-decoder 7 and P-decoder 9, even if the corrected result from the P-decoder 9 is fed back to the Q-decoder 7.
Contrary to the above prior art, according to the transmission system of the present invention, even if four words at any positions are erroneous, their correction is possible, and further even when five words are erroneous, their correction becomes possible dependent upon the construc-tion of a decoder.
An example of the encoding system of the present invention will be described with reference to Fig. 5.
Series of PCM signals SLo to SLn 1 of n's channels are supplied to n's input terminals 1. In this case, series of PCM signals SLo are transmitted as they are to an output terminal 5, and the remaining (n-l)'s series of PCM signals SLl to SLn_l are transmitted through delay circuit or lines to output terminals 5, respectively. The delay amounts or times of ;~'' ` 1139t~0 delay lines 31 to 3n 1 are respectively selected as Dl, D2,..-Dn_ (word times). The n's wor~s derived from the n's respective series of PCM signals SLo to SLn 1 are supplied to the modulo-two adder 2 which produces the series of first parity signals SP0. This series of first perity signals SP0 is delivered through a delay circuit or line 3n with the delay amoun t or time Dn (word timej to an output terminal 5. The (n+l)'s words derived from the series of PCM signals appearing at output terminals 5 and from the series of first parity signals are supplied to the modulo-four parity signals are supplied to the modulo-four adder 4 which produces the series of second parity signals SQo. This series of second parity signals SQo are delivered to an output terminal 5 and also fed back through a delay circuit or line 3n+1 with the delay amount or time Dn+l (word time) to the adder 2.
An error detecting code is added to every one word, or to a set of words consisting of n's PCM signals which appear at the same timing at the output terminals 5.
If the error detecting code is added at every one word, the error in each word can be perfectly detected at the receiving (reproducing) side, but on the other hand redundant degree or density ratio of transmitting signal increases. When an error detecting code is added at every plural words, the redundant degree can be reduced, but if even one word in each set of plural words is erroneous, the other correct words are detected as erroneous words. It is, therefore, effective in the case where the error detecting code is added at every plural words that (n+2)'s series of signals appearing at output terminals 5 are subjected to such interleaving process that they are delayed at different code is added at every ., ., , . . . .. .... , ~ .. .... .. . .. . . . ..
.. . . . .
~139~f~0 plural interleaved words. As the error detecting code, a CRC
(cyclic redundancy check) code or parity code may be used.
Further, as the error correcting code, a full-adder code may be used in place of the parity signal. In this case, the adders 2 and 4 comprise a full adder. Further, in case of forming the parity signals, either of parallel process (exclusive OR gate) or series process (exclusive OR gate and shift register) may be possible.
Now, the manner of determining the delay amounts or times Dl, D2, .... Dn, Dn+l of delay lines 31 to 3n+1 will be described.
First, it is assumed that the delay times Dl, D2, ... Dn are selected to be longer subsequently and the series of PCM signals SLo with no delay are taken as reference.
The delay time Dn+l may be equivalently taken as the delay time Dn+l. The delay times for the respective signals are so selected that as to the series of differences of any adjacent ( n~l' Dl~ D2- Dl~ --- Dn~Dn 1)~ the sum o~ any adjacent difference is not equal to the sum of other adjacent difference. Further, in practice, it is desirable to select the delay time Dn+l as small as possible. This is because it is necessary to reduce the necessary capacity of a shift register and RAM (random access memory) which practically form the delay line. If the delay times are selected as above, four erroneous words at any positions can be corrected. Depending upon the structure of the decoder, five word error can be also corrected.
The above example of the present invention will be now described. Fig. 6A shows an example of the encoder according to the invention, in which series of PCM signals SLo and SLl of two channels are supplied to input terminals la and lb, respectively. In this case, the delay time of a delay ''X~
1139~
line 3a for the series of PCM signal SLl is selected as two words times, the delay time of a delay line 3b for the series of first parity signal SP0 generated from the adder 2 is selected as six word times and the delay time of a delay line 3c inserted in the feedback loop from the adder 4 to the adder 2 is selected as one word time, respectively. In this case, the series of differences of the delay times is (1, 2, 4).
Though not shown, an error detecting code is added to the signals appearing at output terminals 5a, 5b, 5c and 5d of the encoder.
Fig. 6B shows an example of the decoder for the above encoder. At the time when signals are supplied to input terminals 6a, 6b, 6c, 6d of the decoder, the error in the signals is already detected by the error detecting code and the detected result is represented by an error indicating bit added at every word. The series of PCM signals SLo, SLlo and the series of parity signals SQo ~ SPl fed to the input terminals 6a to 6d are firstly supplied to the Q-decoder 7. In this invention, since the second parity signals are pertained or included upon forming the series of first parity signals SPl, the second parity signal is also supplied to the P-decoder 9.
It should be noted that it is necessary to make the timings of four words forming the first parity signal coincide with timing of the first parity signals. Therefore, delay lines 8a, 8b and 8c are provided for the series of PCM signals and the series of second parity signals delivered from the Q-decoder 7. That is, the delay line 8c with the delay time of 7 word times is provided for the series of second parity signals SQo, the delay line 8a with the delay time of 6 word times is provided for the series of PCM signals SLo, and the delay line 8b with the delay time of 2 word times is provided for the series of PCM
.~
signals SLlo.
According to the example of the invention, when words W2n and W2n+l are respectively supplied to the input terminals la and lb of the encoder shown in Fig. 6A, the adder 2 produce the parity signal P2n. Then, three words W2n, W2n+l 4 and P2n 12 are produced at the output terminals 5a, 5b and 5c, respectively. Accordingly, parity signal Q2n is produced at the output terminal 5d by the adding operation of (W2n ~3 W2n+l 4 ~3 P2n 12 = Q2n). This parity signal Q2n is fed back through the delay line 3c to the adder 2 so that the parity signal P2n from the adder 2 is expressed as follows.
P2n W2n ~ W2n+1 6~ Q2n-2 At timing when the parity signal P2n is fed to the input terminal 6d of the decoder shown in Fig. 6B, words (W2n+12' W2n+l+8 and Q2n+12) are respectively fed to the other input terminals 6a to 6c of the decoder. Hence, a first syndrome Sq is generated in the Q-decoder 7 by the following calculation.
P2n ~ W2n+12 ~ W2n+1+8 G3 Q2n+12 ~q In this case, discriminating or error indicating bit added to each word is excepted from the calculation. When no error exists in all the words, all the bits of the syndrome Sq are "0", while when an error is presented in one word, since it becomes ~qual to the erroneous pattern, the error can be corrected by moaulo-two adding the erroneous word with the syndrome Sq.
Due to the provision of the delay lines 8a, 8b and 8c~ the words (W2n' W2n+l~ Q2n-2~ P2n) are fed to the P-decoder 9. Hence, a second syndrome Sp is generated in the P-decoder 9 by the following calculation.
W2n 63 W2n+l 63 Q2n-2 ~3 P2n Sp When no error is presented in all the words, all the bits of syndrome Sp are "0", while when an error exists in one word, since it becomes equal to the erroneous pattern, the error can 1139~;0 be corrected by modulo-two adding the erroneous word with the syndrome Sp.
Fig. 7 is a table showing the relation between the respective words processed by the above example of the present invention. In the table of Fig. 7, the four words coupled by the solid lines in the horizontal direction form the syndrome Sp by the first parity signals, and the four words coupled by the broken lines form the syndrome Sq by the second parity signals.
As clearly understood from the table of Fig. 7, it is possible to correct any four word errors, even if P-and Q-decoders 7 and 9 detect two word errors simultaneously.
For example, in such a case where the PCM signals W2n and W2n+2 (for example, W12 and W14) are erroneous and the parity 2n Q2n+2 (for example, Q12 and Q14) are erroneous two word errors are presented for each of the parity signals Q2n and Q2n+2 and also two word errors are presented for the parity signal P2n+2.
Even in this condition, if the-corrected result from the P-decoder 9 is used,-Q2n or W2n+2 can be corrected.
Accordingly, the correction becomes possible by using P2n+2 and hence the correction of any four word errors becomes possible.
The above correction ability for four word errors can be applied to the correction of five word errors similarly.
Therefore, if the decoding system is constructed in such a manner that the correction by the second parity signal is carried out again by using the corrected result of the P-decoder 9, the correction of any five word errors become possible.
113~
The correction according to the present invention will be impossible for six word errors, which cannot be independently corrected either of first and second parity signals. For example, when six words (P0, Wl, Q4, W6, Q6' Wg) marked with double circles in Fig. 7 are erroneous, the correction thereof becomes impossible.
Fig. 8 is a block diagram showing another example of the encoder of the present invention which is to process the PCM signals of six channels. In this example, series of six channel PCM signals SLo to SL5 are fed to input terminals la to lf, respectively. The series of PCM signals SLo to SL5 are formed by pulse code modulating, for example, the left and right channel signals of a stereophonic audio signal and further distributing the PCM signals of each channel to three channels. In this example, the series of PCM signals SLo is transmitted, as they are, to an output terminal 5a and the other series of PCM signals SLl to SL5 are transmitted through delay circuits or lines 3a to 3e to output terminals Sb to 5f, respectively. The delay amount or times (word times) of the delay lines 3a to 3e are respectively selected as 3, 8, 14, 21 and 31 (word time). The series of parity signals SP0 derived from the adder 2 is delivered through a delay circuit or line 3f with the delay amount or time of 33 (word times) to an output terminal 5g. The series of parity signals SQo derived from the adder 4 is delivered to an output terminal 5h and also to the adder 2 through a delay circuit or line 3g with the delay amount or time of 1 ~word time). In this case, the series of differences of delay times are (1, 3, 5, 6, 7, 10, 2).
Also in the case that the series of six channel PCM signals are encoded as set forth just above, the high correction ability is presented in the same manner as former case.
.,, ~ .
~ 16 -il3~0 Further, it is possible to select the delay times of the delay lines 3a to 3g other than those shown in Fig. 8.
In such case, it is of course desired that the sum of the delay times of the delay lines 3f and 3g, which is the maximum delay time, is selected as small as possible.
It will be apparent that many modifications and variations could be effected by one skilled in the art without departing from the spirits or scope of the novel concepts of the present invention. Therefore, the spirits or scope of the invention should be determined by the appended claims only.
" 1139~fà0 that drop-outs causing a burst error frequently occur in the digital signal reproduced from the tape. There are provided several types of transmission systems to correct such a burst error, as appearing in the reproduced PCM signal.
One of the systems is shown in VSP 3409875, in which the PCM signal is transmitted through two lines, one of which includes a predetermined dealy.
In the receiving side, the outputs of the lines are applied to an output device through a switch controlled by an error responsive device, which is responsive to unequal signals at the outputs of the lines, so that upon detection of the unequaI
signals the switch i5 connected to the line having a delay for a predetermined time. Thus, the system can correct the burst errors appearing in the line. However, it is necessary in the above system to provide the two lines for transmission of the same signal. In other words, the capacity of the transmission medium is needed double the usual one.
In order to overcome the above-des-cribed disadvantage, there is proposed the improved digital signal transmitting system, such as that described in Canadian Application No. 329,935 and assigned to the same assignee as the present invention. In the system, a plurality of words of digital information signals are added bit by bit in a modulo-two adder and a first parity signal is generated for the predeter-mined number of words of the digital information 1~39~0 signals. Each word of the information digital signals and the parity signal are respectively delayed so as to have different delay times to each other. The information signals and first .
parity signal thus delayed are added bit by bit in a modulo-two adder to generate a second parity signal for the information and parity signals, and then the predetermined number of words of digital information signals and the first and second parity signals are serially transmitted through a trans-mission line.
According to the system, in case that some errors are introduced in the digital information signals during transmission, it is possible to correct such errors perfectly, unless the errors are contained in more than three words of the information signals. However, lt is impossible to correct the errors included in more than three words of the information signals by the digital signal transmission system of the prior application.
SU~IMARY OF THE INVENTION
An object of the invention is to provide an improved digital signal transmission system in which burst errors contained in the transmitted signal can be corrected at the receiving side.
Another object of the invention is to provide a new system for transmitting digital signals together with parity signals which are composed from the former signals, and for correcting burst errors in the transmitted signal by utilizing the parity signals.
_ - 4 -1139~
A further object of the invention is to provide an improved system for correcting errors contained in the transmitted signal with high correcting ability.
In the system of the invention, a predetermined number of words of digita~ informa-tion signals are added bit by bit in a first modulo -two adder to produce a first parity signal.
The information signals and the first parity signal are delayed so as to have different del'ay times to each other, and the signals thus delayed are again added bit by bit in a second modulo-two adder to produce a second parity signal, which is fed back to the first modulo-two adder to thereby add it with the information signals. The predetermined number of words of'information signals and the first and second p æity signals are serially transmitted through a transmission line.
The other objects, features and advantages of the invention will become apparent from the following description taken in conjunction with the accompanying drawings through which the like references designate the same elements.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. l is a block diagram of the system according to the prior application;
Fig. 2 is a table which is used for the explanation of the system of Fig. l;
Fig. 3 is a block diagram of another system according to the prior application;
Fig. 4 is another table which is used for the explanation of the system of Fig. 3;
Fig. 5 is a block diagram showing an example of the encoder used in the system according~
to this invention;
Fig. 6 is a block diagram showing exam-ples of the encoder and decoder used in another system according to this invention;
Fig. 7 is a table which is used for the explanation of the system of Fig. 6; and Fig. 8, appearing with Fig. 5, is a block diagram showing an example of the encoder used in a further system according to this invention.
_ SCRIPTIO~ OF THE PREFERRED EMBODIMENTS
Before describing the present invention, the system of the prior application will be explained.
Figs. lA and lB show an encoder and a decoder of a system which has been disclosed in the prior application, respectively.
In Fig. lA, la and lb designate input terminals of an encoder which are respectively supplied with a series of words of PCM signals.
In this example, PCM signals (W0, Wl, W2, ..... ) of 1 channel, which are produced by pulse code modulating an audio signal, are distributed into a series of PCM signals SLo consisting of even numbered words (W0, W2, W4, ...... ) and a series of PCM signals SLl consisting of odd numbered words (Wl, W3~ W5, The series of PCM signals SLo and SLl are applied to the input terminals la i~7~
:~39S~O
and lb, respectively. The PCM signals in the series of P~ signals SLo and SLl are supplied to a modulo-two adder 2 word by word. In the modulo-two adder 2~r(Wo (+~ Wl = P0), (W~ ~ W
(~
..... and (W2n ~ W2n+1 P2n) subsequently and thereby a series of first parity signals SP0 ~re f~rmed from the adder 2. The series of the PCM signals SLo are delivered, as they are, to an output terminal 5a while the series of PCM signals SLl and the series of parity signals SP0 are deli-vered through a delay circuit or line 3a of one word delay time and a delay circuit or line 3b of two word delay times to output terminals 5b and 5c, as series of delayed PCM signals SLlo and series of delayed parity signals SPl, respectively.
Each word of the PCM signals from the series of the PCM signals SLo and SLlo is supplied to a modulo-two adder 4, in which adding - ~W2n ~ W2n_2+1) is performed to obtain a series of second parity signals SQo.
The series of the PCM signals SLo and SLlo and the series of the parity signals SPl and SQo which are obtained in the above-described manner are fed to output terminals 5a, 5b, 5c and 5d, respectively.
Fig. lB shows a decoder corresponding to the encoder shown in Fig. lA. In Fig. lB , 6a, 6b, 6c and 6d designate input terminals which are supplied with the series of PCM signals SLo, SLlo and the series of second and first parity li3~
signals SQo ~ SPl, respectively. The series of PCM signals SLo, SLlo and the series of second parity signals SQo are supplied to a Q-decoder 7 in which the error correction by the second parity, signals is carried out. The series of PCM
signals thus corrected by the parity signals are supplied through a delay circuit or line 8a of two woxd delay times and a delay circuit or line 8b of one word delay time to a P-decoder 7, res-pectively. The series of first parity signals-SPl is supplied to the P-decoder 9 so that the error correction by the first parity signal is performed in the P-decoder 9. The series of PCM signals SLo and SLl thus corrected are deliver-ed to output terminals lOa and lOb, respectively.
The above-described encoder and decoder are so formed that the error in each word can be detected independently. Now, the error correction of this case will be explained. In Fig. 2, three woras coupled through the solid lines form first parity signals, and three words coupled through the broken lines orm second parity signals, respectively. It assumes that the decoder is so constructed that the error is corrected firstly by the Q-decoder 7 as sho~Jn in Fig. lB. Under such assumption;
if the error is an error of one word in three words coupled through the broken lines, any errors more than two words can be completely corrected.
Further, even in the case where an error exists 1139~0 in more than two words in the three words coupled by the broken lines, if other two words coupled by the solid line with the erroneous words are correct, the correction becomes possible. If three words, for example, W4, W5 and W6 are erroneous, the two words W5 and W6 can not be corrected by the Q-decoder 7 and remain as they are not corrected, but the word W4 is corrected by a parity signal Q4. Therefore, the errors in words W5 and W6 can be corrected in the P-decoder 9 by parity signals P4 and P6, respectively.
By the way, in such a case where the errors are included in the three words such that PCM signals of two words forming the second parity signals are erroneous and also the first parity signal containing either of the two words of PCM signals is erroneous, the correction thereof becomes impossible. For example, in such a case where three words W5, W6, P4, which are respectively indicated by double circles in Fig. 2, are erroneous, when the Q-decoding is carried out firstly and then the P-decoding is carried, the correction becomes impossible.
In order to avoid that the correction of errors of specific three words becomes impossible, it may be considered that an encoder and a decoder shown in Figs. 3A and 3~
respectively, are employed. That is, during encoding second parity signals Q2n are formed, such that the first parity signals P2n 4 are contained, into the second parity signals Q2n in addition to the PCM signals while the decoder is so formed that the error in the first parity signals can be corrected in the Q-decoder 7. According to the encoding system shown in Fig.
3A, since the first parity signals are also contained so as to form the second parity signals as shown in Fig. 4 by the broken lines, three word errors in any positions can be corrected.
i~3~
However, considering four word errors, the correction becomes impossible, when the specified four words are erroneous. In other words, when the corrected result from the P-decoder 9 is not fed back to the Q-decoder 7, the correction of four word errors is impossible, if the four words errors are corrected by only the first parity signal.
While, even if the decoder is so formed that the corrected result from the P-decoder 9 is fed back to the Q-decoder 7, when the shape formed by connecting four erroneous words in Fig. 4 becomes a parallelogram, the correction of four word errors become impossible. For example, when four words W7, W8, Wg, P6 which are respectively marked with double circles in Fig. 4 are erroneous, these errors can not be corrected by either of the Q-decoder 7 and P-decoder 9, even if the corrected result from the P-decoder 9 is fed back to the Q-decoder 7.
Contrary to the above prior art, according to the transmission system of the present invention, even if four words at any positions are erroneous, their correction is possible, and further even when five words are erroneous, their correction becomes possible dependent upon the construc-tion of a decoder.
An example of the encoding system of the present invention will be described with reference to Fig. 5.
Series of PCM signals SLo to SLn 1 of n's channels are supplied to n's input terminals 1. In this case, series of PCM signals SLo are transmitted as they are to an output terminal 5, and the remaining (n-l)'s series of PCM signals SLl to SLn_l are transmitted through delay circuit or lines to output terminals 5, respectively. The delay amounts or times of ;~'' ` 1139t~0 delay lines 31 to 3n 1 are respectively selected as Dl, D2,..-Dn_ (word times). The n's wor~s derived from the n's respective series of PCM signals SLo to SLn 1 are supplied to the modulo-two adder 2 which produces the series of first parity signals SP0. This series of first perity signals SP0 is delivered through a delay circuit or line 3n with the delay amoun t or time Dn (word timej to an output terminal 5. The (n+l)'s words derived from the series of PCM signals appearing at output terminals 5 and from the series of first parity signals are supplied to the modulo-four parity signals are supplied to the modulo-four adder 4 which produces the series of second parity signals SQo. This series of second parity signals SQo are delivered to an output terminal 5 and also fed back through a delay circuit or line 3n+1 with the delay amount or time Dn+l (word time) to the adder 2.
An error detecting code is added to every one word, or to a set of words consisting of n's PCM signals which appear at the same timing at the output terminals 5.
If the error detecting code is added at every one word, the error in each word can be perfectly detected at the receiving (reproducing) side, but on the other hand redundant degree or density ratio of transmitting signal increases. When an error detecting code is added at every plural words, the redundant degree can be reduced, but if even one word in each set of plural words is erroneous, the other correct words are detected as erroneous words. It is, therefore, effective in the case where the error detecting code is added at every plural words that (n+2)'s series of signals appearing at output terminals 5 are subjected to such interleaving process that they are delayed at different code is added at every ., ., , . . . .. .... , ~ .. .... .. . .. . . . ..
.. . . . .
~139~f~0 plural interleaved words. As the error detecting code, a CRC
(cyclic redundancy check) code or parity code may be used.
Further, as the error correcting code, a full-adder code may be used in place of the parity signal. In this case, the adders 2 and 4 comprise a full adder. Further, in case of forming the parity signals, either of parallel process (exclusive OR gate) or series process (exclusive OR gate and shift register) may be possible.
Now, the manner of determining the delay amounts or times Dl, D2, .... Dn, Dn+l of delay lines 31 to 3n+1 will be described.
First, it is assumed that the delay times Dl, D2, ... Dn are selected to be longer subsequently and the series of PCM signals SLo with no delay are taken as reference.
The delay time Dn+l may be equivalently taken as the delay time Dn+l. The delay times for the respective signals are so selected that as to the series of differences of any adjacent ( n~l' Dl~ D2- Dl~ --- Dn~Dn 1)~ the sum o~ any adjacent difference is not equal to the sum of other adjacent difference. Further, in practice, it is desirable to select the delay time Dn+l as small as possible. This is because it is necessary to reduce the necessary capacity of a shift register and RAM (random access memory) which practically form the delay line. If the delay times are selected as above, four erroneous words at any positions can be corrected. Depending upon the structure of the decoder, five word error can be also corrected.
The above example of the present invention will be now described. Fig. 6A shows an example of the encoder according to the invention, in which series of PCM signals SLo and SLl of two channels are supplied to input terminals la and lb, respectively. In this case, the delay time of a delay ''X~
1139~
line 3a for the series of PCM signal SLl is selected as two words times, the delay time of a delay line 3b for the series of first parity signal SP0 generated from the adder 2 is selected as six word times and the delay time of a delay line 3c inserted in the feedback loop from the adder 4 to the adder 2 is selected as one word time, respectively. In this case, the series of differences of the delay times is (1, 2, 4).
Though not shown, an error detecting code is added to the signals appearing at output terminals 5a, 5b, 5c and 5d of the encoder.
Fig. 6B shows an example of the decoder for the above encoder. At the time when signals are supplied to input terminals 6a, 6b, 6c, 6d of the decoder, the error in the signals is already detected by the error detecting code and the detected result is represented by an error indicating bit added at every word. The series of PCM signals SLo, SLlo and the series of parity signals SQo ~ SPl fed to the input terminals 6a to 6d are firstly supplied to the Q-decoder 7. In this invention, since the second parity signals are pertained or included upon forming the series of first parity signals SPl, the second parity signal is also supplied to the P-decoder 9.
It should be noted that it is necessary to make the timings of four words forming the first parity signal coincide with timing of the first parity signals. Therefore, delay lines 8a, 8b and 8c are provided for the series of PCM signals and the series of second parity signals delivered from the Q-decoder 7. That is, the delay line 8c with the delay time of 7 word times is provided for the series of second parity signals SQo, the delay line 8a with the delay time of 6 word times is provided for the series of PCM signals SLo, and the delay line 8b with the delay time of 2 word times is provided for the series of PCM
.~
signals SLlo.
According to the example of the invention, when words W2n and W2n+l are respectively supplied to the input terminals la and lb of the encoder shown in Fig. 6A, the adder 2 produce the parity signal P2n. Then, three words W2n, W2n+l 4 and P2n 12 are produced at the output terminals 5a, 5b and 5c, respectively. Accordingly, parity signal Q2n is produced at the output terminal 5d by the adding operation of (W2n ~3 W2n+l 4 ~3 P2n 12 = Q2n). This parity signal Q2n is fed back through the delay line 3c to the adder 2 so that the parity signal P2n from the adder 2 is expressed as follows.
P2n W2n ~ W2n+1 6~ Q2n-2 At timing when the parity signal P2n is fed to the input terminal 6d of the decoder shown in Fig. 6B, words (W2n+12' W2n+l+8 and Q2n+12) are respectively fed to the other input terminals 6a to 6c of the decoder. Hence, a first syndrome Sq is generated in the Q-decoder 7 by the following calculation.
P2n ~ W2n+12 ~ W2n+1+8 G3 Q2n+12 ~q In this case, discriminating or error indicating bit added to each word is excepted from the calculation. When no error exists in all the words, all the bits of the syndrome Sq are "0", while when an error is presented in one word, since it becomes ~qual to the erroneous pattern, the error can be corrected by moaulo-two adding the erroneous word with the syndrome Sq.
Due to the provision of the delay lines 8a, 8b and 8c~ the words (W2n' W2n+l~ Q2n-2~ P2n) are fed to the P-decoder 9. Hence, a second syndrome Sp is generated in the P-decoder 9 by the following calculation.
W2n 63 W2n+l 63 Q2n-2 ~3 P2n Sp When no error is presented in all the words, all the bits of syndrome Sp are "0", while when an error exists in one word, since it becomes equal to the erroneous pattern, the error can 1139~;0 be corrected by modulo-two adding the erroneous word with the syndrome Sp.
Fig. 7 is a table showing the relation between the respective words processed by the above example of the present invention. In the table of Fig. 7, the four words coupled by the solid lines in the horizontal direction form the syndrome Sp by the first parity signals, and the four words coupled by the broken lines form the syndrome Sq by the second parity signals.
As clearly understood from the table of Fig. 7, it is possible to correct any four word errors, even if P-and Q-decoders 7 and 9 detect two word errors simultaneously.
For example, in such a case where the PCM signals W2n and W2n+2 (for example, W12 and W14) are erroneous and the parity 2n Q2n+2 (for example, Q12 and Q14) are erroneous two word errors are presented for each of the parity signals Q2n and Q2n+2 and also two word errors are presented for the parity signal P2n+2.
Even in this condition, if the-corrected result from the P-decoder 9 is used,-Q2n or W2n+2 can be corrected.
Accordingly, the correction becomes possible by using P2n+2 and hence the correction of any four word errors becomes possible.
The above correction ability for four word errors can be applied to the correction of five word errors similarly.
Therefore, if the decoding system is constructed in such a manner that the correction by the second parity signal is carried out again by using the corrected result of the P-decoder 9, the correction of any five word errors become possible.
113~
The correction according to the present invention will be impossible for six word errors, which cannot be independently corrected either of first and second parity signals. For example, when six words (P0, Wl, Q4, W6, Q6' Wg) marked with double circles in Fig. 7 are erroneous, the correction thereof becomes impossible.
Fig. 8 is a block diagram showing another example of the encoder of the present invention which is to process the PCM signals of six channels. In this example, series of six channel PCM signals SLo to SL5 are fed to input terminals la to lf, respectively. The series of PCM signals SLo to SL5 are formed by pulse code modulating, for example, the left and right channel signals of a stereophonic audio signal and further distributing the PCM signals of each channel to three channels. In this example, the series of PCM signals SLo is transmitted, as they are, to an output terminal 5a and the other series of PCM signals SLl to SL5 are transmitted through delay circuits or lines 3a to 3e to output terminals Sb to 5f, respectively. The delay amount or times (word times) of the delay lines 3a to 3e are respectively selected as 3, 8, 14, 21 and 31 (word time). The series of parity signals SP0 derived from the adder 2 is delivered through a delay circuit or line 3f with the delay amount or time of 33 (word times) to an output terminal 5g. The series of parity signals SQo derived from the adder 4 is delivered to an output terminal 5h and also to the adder 2 through a delay circuit or line 3g with the delay amount or time of 1 ~word time). In this case, the series of differences of delay times are (1, 3, 5, 6, 7, 10, 2).
Also in the case that the series of six channel PCM signals are encoded as set forth just above, the high correction ability is presented in the same manner as former case.
.,, ~ .
~ 16 -il3~0 Further, it is possible to select the delay times of the delay lines 3a to 3g other than those shown in Fig. 8.
In such case, it is of course desired that the sum of the delay times of the delay lines 3f and 3g, which is the maximum delay time, is selected as small as possible.
It will be apparent that many modifications and variations could be effected by one skilled in the art without departing from the spirits or scope of the novel concepts of the present invention. Therefore, the spirits or scope of the invention should be determined by the appended claims only.
Claims (14)
OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A digital signal transmission system comprising:
a) first means for modulo-two-adding a plurality of words of a digital signal to produce a first error correcting signal;
b) delay means for delaying said plurality of words of the digital signal and said first error correcting signal so as to have different delay times to each other; and c) second means for modulo-two-adding at least one of delayed words of the digital signal and delayed first error correcting signal to produce a second error correcting signal whereby a group of digital signals comprising said plurality of words of the digital signal and said first and second error correcting signals are transmitted;
said system being characterized by means for feeding said second error correcting signal back to said first modulo-two-adding means to modulo-two-add said second error correct-ing signal with said plurality of words of the digital signal, said transmission system being characterized by second delay means connected in said feedback means for delaying said second error correcting signal.
a) first means for modulo-two-adding a plurality of words of a digital signal to produce a first error correcting signal;
b) delay means for delaying said plurality of words of the digital signal and said first error correcting signal so as to have different delay times to each other; and c) second means for modulo-two-adding at least one of delayed words of the digital signal and delayed first error correcting signal to produce a second error correcting signal whereby a group of digital signals comprising said plurality of words of the digital signal and said first and second error correcting signals are transmitted;
said system being characterized by means for feeding said second error correcting signal back to said first modulo-two-adding means to modulo-two-add said second error correct-ing signal with said plurality of words of the digital signal, said transmission system being characterized by second delay means connected in said feedback means for delaying said second error correcting signal.
2. A digital signal transmission system comprising:
a) first means for modulo-two-adding a plurality of words of a digital signal to produce a first error correcting signal;
b) delay means for delaying said plurality of words of the digital signal and said first error correcting signal so as to have different delay times to each other; and c) second means for modulo-two-adding at least one of delayed words of the digital signal and delayed first error correcting signal to produce a second error correcting signal whereby a group of digital signals comprising said plurality of words of the digital signal and said first and second error correcting signals are transmitted said system being characterized by means for feeding said second error correcting signal back to said first modulo-two-adding means to modulo-two-add said second error correct-ing signal with said plurality of words of the digital signal, said transmission system being characterized by that each of said digital signals and said error correcting signals have respective error detecting codes to be transmitted therewith.
a) first means for modulo-two-adding a plurality of words of a digital signal to produce a first error correcting signal;
b) delay means for delaying said plurality of words of the digital signal and said first error correcting signal so as to have different delay times to each other; and c) second means for modulo-two-adding at least one of delayed words of the digital signal and delayed first error correcting signal to produce a second error correcting signal whereby a group of digital signals comprising said plurality of words of the digital signal and said first and second error correcting signals are transmitted said system being characterized by means for feeding said second error correcting signal back to said first modulo-two-adding means to modulo-two-add said second error correct-ing signal with said plurality of words of the digital signal, said transmission system being characterized by that each of said digital signals and said error correcting signals have respective error detecting codes to be transmitted therewith.
3. A digital signal transmission system according to claim 1 being characterized by that delay amounts in said first and second delay means are selected such that difference (Dn - Dn-1) between the delay amounts in adjacent digital words is different from difference (Dn+1 - Dn) between the delay amounts in subsequent adjacent digital words.
4. A digital signal transmission system according to claim 1 further comprising, first means receiving said digital words for recording said digital words in response to said second error correcting signal, when said errors are detected by said error detecting code; and second means receiving said digital words from said first decoding means for decoding said digital words in response to said first error correcting signal to thereby correct said errors included in said plurality of digital signals;
said system being characterized by third delay means connected between said first and second decoder means for delaying said digital words so as to compensate the delay amounts in said first and second delay means.
said system being characterized by third delay means connected between said first and second decoder means for delaying said digital words so as to compensate the delay amounts in said first and second delay means.
5. A digital signal transmission system according to claim 4 being characterized by that delay amount for said second error correcting signal in sand third delay means is equal to summation of delay amount of said second delay means and delay amount for said first error correcting signal in said first delay means.
6. In a digital transmission system in which a digital signal is transmitted in the form of digital words and in which at least first and second error correcting signals are included in the digital signal so transmitted, an encoding section comprising:
means for applying a sequence of selected ones of said words of the digital signal to a first channel and the remaining words to at least one further channel;
first adder means for adding a plurality of said words of the digital signal together with said second error correcting signal to produce said first error correcting signal:
delay means for delaying said remaining words of the digital signal by one amount of delay and for delaying said first error correcting signal by another amount of delay;
second adder means for adding at least one of the delayed words and the delayed first error correcting signal to produce said second error correcting signal, wherein said first and second adder means include a modulo-N adder and a modulo-M
adder, respectively, with N and M being whole numbers;
feedback means for feeding said second error correcting signal back to said first adder means so that the latter adds said second error correcting signal together with-said plurality of words of the digital signal to produce said first error correcting signal; and output means for providing said words of the digital signal, said delayed first error correcting signal and said second error correcting signal as the output of said encoding section to be transmitted.
means for applying a sequence of selected ones of said words of the digital signal to a first channel and the remaining words to at least one further channel;
first adder means for adding a plurality of said words of the digital signal together with said second error correcting signal to produce said first error correcting signal:
delay means for delaying said remaining words of the digital signal by one amount of delay and for delaying said first error correcting signal by another amount of delay;
second adder means for adding at least one of the delayed words and the delayed first error correcting signal to produce said second error correcting signal, wherein said first and second adder means include a modulo-N adder and a modulo-M
adder, respectively, with N and M being whole numbers;
feedback means for feeding said second error correcting signal back to said first adder means so that the latter adds said second error correcting signal together with-said plurality of words of the digital signal to produce said first error correcting signal; and output means for providing said words of the digital signal, said delayed first error correcting signal and said second error correcting signal as the output of said encoding section to be transmitted.
7. A digital signal transmission system according to claim 6, wherein each of said first and second adder means includes a modulo-two adder.
8. A digital signal transmission system according to claim 6, wherein said digital words and said first and second error correcting signals have respective error-detecting codes associated therewith.
9. A digital signal transmission system according to claim 6, further comprising means for interleaving said selected words of the digital signal, said delayed remaining words of the digital signal, said delayed first error correcting signal and said second error correcting signal with one another to form a signal group of interleaved digital words, and for associating with each said group a single error detecting code.
10. A digital signal transmission system according to claim 6, wherein said feedback means includes another delay means for delaying said second error correcting signal by a pre-determined amount.
11. A digital signal transmission system according to claim 10, wherein the first-mentioned delay means and said other delay means impart amount of delay such that the difference between the amount of delay imparted to successive digital words (Wn-1, Wn) is unequal to the amount of delay imparted to immediately subsequent successive digital words (Wn, Wn+1).
12. A digital signal transmission system according to claim 10, wherein said encoding section further includes means for associating at least one error detecting code with said selected and delayed remaining words of the digital signal, said delayed first error correcting signal and said second error correcting signal in said output of the encoding section, said system further comprising a decoding section which includes first decoding means for receiving said output of the encoding section and decoding said selected and delayed remaining words of the digital signal by means of said delayed first error correcting signal and said second error correcting signal, whenever errors are indicated by said error detecting code;
second decoding means for receiving the decoded digital words from said first decoding means, and decoding said decoded digital words by means of said delayed first error correcting signal and receive delay means coupled between said first and second decoding means for imparting an amount of delay to said decoded digital words to compensate for the amount of delay imparted by the first-mentioned delay means and said other delay means.
second decoding means for receiving the decoded digital words from said first decoding means, and decoding said decoded digital words by means of said delayed first error correcting signal and receive delay means coupled between said first and second decoding means for imparting an amount of delay to said decoded digital words to compensate for the amount of delay imparted by the first-mentioned delay means and said other delay means.
13. A digital signal transmission system according to claim 12, wherein said receive delay means imparts an amount of delay to said second error correcting signal equal to the sum of the amount of delay imparted to said first error correcting signal by said first-mentioned delay means and the amount of delay imparted to said second error correcting signal by said other delay means.
14. A digital signal transmission system according to claim 6, wherein the transmitted digital signals have at least one error detecting code associated therewith, said system further comprising first decoding means for receiving said digital words and decoding the same by means of said first and second error correcting signals whenever errors are indicated by said error detecting code;
second decoding means for receiving, from the first decoding means, the decoded digital words and decoding the same by means of said first and second error correcting signals when-ever errors are indicated by said error detecting code; and receive delay means coupled between said first and said second decoding means for imparting an amount of delay to said decoded digital words to compensate for the amount of delay imparted by the first-mentioned delay means.
second decoding means for receiving, from the first decoding means, the decoded digital words and decoding the same by means of said first and second error correcting signals when-ever errors are indicated by said error detecting code; and receive delay means coupled between said first and said second decoding means for imparting an amount of delay to said decoded digital words to compensate for the amount of delay imparted by the first-mentioned delay means.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22460/79 | 1979-02-27 | ||
| JP2246079A JPS55115753A (en) | 1979-02-27 | 1979-02-27 | Pcm signal transmission method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1139860A true CA1139860A (en) | 1983-01-18 |
Family
ID=12083312
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000346490A Expired CA1139860A (en) | 1979-02-27 | 1980-02-26 | Error correction in a digital signal transmission system |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US4356564A (en) |
| JP (1) | JPS55115753A (en) |
| AT (1) | AT373704B (en) |
| CA (1) | CA1139860A (en) |
| DE (1) | DE3006958A1 (en) |
| FR (1) | FR2450540B1 (en) |
| GB (1) | GB2045036B (en) |
| NL (1) | NL188726C (en) |
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| JPS54137204A (en) * | 1978-04-17 | 1979-10-24 | Sony Corp | Digital signal transmission method |
| JPS54139406A (en) * | 1978-04-21 | 1979-10-29 | Sony Corp | Digital signal transmission method |
| US4211997A (en) * | 1978-11-03 | 1980-07-08 | Ampex Corporation | Method and apparatus employing an improved format for recording and reproducing digital audio |
-
1979
- 1979-02-27 JP JP2246079A patent/JPS55115753A/en active Granted
-
1980
- 1980-02-22 US US06/123,721 patent/US4356564A/en not_active Expired - Lifetime
- 1980-02-25 DE DE19803006958 patent/DE3006958A1/en not_active Withdrawn
- 1980-02-25 AT AT0102280A patent/AT373704B/en not_active IP Right Cessation
- 1980-02-26 CA CA000346490A patent/CA1139860A/en not_active Expired
- 1980-02-27 GB GB8006644A patent/GB2045036B/en not_active Expired
- 1980-02-27 FR FR8004374A patent/FR2450540B1/en not_active Expired
- 1980-02-27 NL NLAANVRAGE8001187,A patent/NL188726C/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| GB2045036A (en) | 1980-10-22 |
| DE3006958A1 (en) | 1980-09-11 |
| JPS55115753A (en) | 1980-09-05 |
| NL188726B (en) | 1992-04-01 |
| AT373704B (en) | 1984-02-10 |
| NL8001187A (en) | 1980-08-29 |
| FR2450540A1 (en) | 1980-09-26 |
| FR2450540B1 (en) | 1988-07-29 |
| JPS6151814B2 (en) | 1986-11-11 |
| GB2045036B (en) | 1983-05-05 |
| ATA102280A (en) | 1983-06-15 |
| NL188726C (en) | 1992-09-01 |
| US4356564A (en) | 1982-10-26 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |