CA1149031A - Adaptive filter including a delay circuit - Google Patents
Adaptive filter including a delay circuitInfo
- Publication number
- CA1149031A CA1149031A CA000347102A CA347102A CA1149031A CA 1149031 A CA1149031 A CA 1149031A CA 000347102 A CA000347102 A CA 000347102A CA 347102 A CA347102 A CA 347102A CA 1149031 A CA1149031 A CA 1149031A
- Authority
- CA
- Canada
- Prior art keywords
- circuit
- signal
- output
- input
- filter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/025—Systems for the transmission of digital non-picture data, e.g. of text during the active part of a television frame
- H04N7/035—Circuits for the digital non-picture data signal, e.g. for slicing of the data signal, for regeneration of the data-clock signal, for error detection or correction of the data signal
- H04N7/0355—Circuits for the digital non-picture data signal, e.g. for slicing of the data signal, for regeneration of the data-clock signal, for error detection or correction of the data signal for discrimination of the binary level of the digital data, e.g. amplitude slicers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H15/00—Transversal filters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H21/00—Adaptive networks
- H03H21/0012—Digital adaptive filters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/08—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/06—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
- H04L25/061—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset
Abstract
ABSTRACT:
"adaptive filter including a delay circuit".
An adaptive filter having a delay circuit, taps of which comprise amplitude control circuits controlled by means of an error signal which indicates the difference between the output signal of the filter and a reference signal, includes a further control circuit which controls the amplitude of the reference signal such that an unwanted stable state for the filter is prevented from occurring.
"adaptive filter including a delay circuit".
An adaptive filter having a delay circuit, taps of which comprise amplitude control circuits controlled by means of an error signal which indicates the difference between the output signal of the filter and a reference signal, includes a further control circuit which controls the amplitude of the reference signal such that an unwanted stable state for the filter is prevented from occurring.
Description
3 ~9(331 r ~. .
"Adaptive filter including a delay circuit".
The invention relates to an adaptive filter in-cluding a delay circuit taps of which comprise amplitude control circuits, also including a difference-determining circuit forming an error signal of a signal corrected by the filter with respect to a reference signal which has a waveform l~hich substantially corresponds to the desired waveform of the signal corrected by the filter, circuits for obtaining control signals for the amplitude control cir~uits being controlled by means of this error signal and including a further control circuit.
Nachrichten Technische Zeitschrift 1971, Vol. 1 pages 18-24, page 20 in particular, discloses anadaptive filter of the above-~entioned kind. The further control circuit there has ~or its function to keep the amplitude at the center of main tap of the delay circuit of the filter constant and it is arranged outside the filter, that is to say before the input of the filter, as the filter utilizes the error signal. In certain cases it appears that such a controI may result in an unwanted stable state where- -in the amplitude of the filter output signal becomes zero.
It is an object of the invention to provide the further control circuit in such a place that the above~
mentioned drawbac~ is obviated~
According to the invention anadaptive filter of the type mentioned in the opening paragraph is therefore characterized in that the further control circuit is provided at an input of the difference determining circuit, whereas the control signal for this further control circuit is obtained from an integrator at an output of a multiplying circuit to which the reference signal and the error signal are applied.
It appeared that by the action of the further con-trol circuit on the amplitude of the reference signal or on ,, ~.
27 11-1979 -2 P~ 9388 the amplitude of the corrected signal and the error signal a blocked state which may particularly occur on actuation is prevented from occurring. In addition, a stable final state with a zero amplitude of the output signal of the fllter ~
does not occur anymore if there is a d7c. voltage component in the signal to be corrected by the filter. Namely, a control before the filter would tend to control this d.c.
~oltage component to zero if the reference signal does not contain this d.c. voltage component and in general this : lO cannot be the case because it usually has an unknown value whichis influenced by, for example, unwanted contributions of circuits.
A further embodiment of an adaptive filter according to the invention is characterized in that the further control circuit is a multiplying circuit. Owing to this measure an influence exercised by unwanted direct~
currents on the amplitude control systems is substantially eliminated.
An adapti~e filter according to the invention is very suitable for suppressing echoes in data signals which are present at a certain level in a video signal~ such as teletext signals or digital audio signals. A television re-ceiver having such a filter gives a very good echo sup-pression which cannot only be effective on the data signal - 25 but also on the remaining portion of the signal~ so that the quality of a television picture displayed by the re-ceiver can improve.
The invention will now be further explained with reference to the drawing:
In the drawing:
Fig. 1 illustrates an adaptive filter according to the in~ention by means of a block diagram~
Fig. 2 illustrates by means of a circuit diagram ~ a possible construction of a dslay element of a delay cir--~ 35 cuit for an adaptive filter shown in Fig. 1, Fig. 3 shows a possible constru~ion of an amplitu-de control circuit for an adaptive filter shown in ~ig. 1, ~ ig. 4 shows a construction of a clamping circuit ,~
3~
,, ~ . . ....
in accordance with a further embodiment of the invention for an adaptive filter shown in Fig. 1 and Fig. 5 shows a possible construction of a threshold circuit and ancdditional control circuit for an adaptive filter shown in Fig~ 1, In Fig. 1 a signal which is to be corrected by the filter is applied to an input 1 of an adaptive filter. For the construction of the filter as it will be described here-inafter this is a video signal of a television signal~ In certain periods of time this video signal comprises data information such as, for example, teletext information or digital video inf~ormation. Generally, this information is present in the video signal at a level which deviates from the zero level of that video signal.
In the description of ~ig. 1 only the operation of the adaptive filter during the occurrence of the data signal will be described. The subsequent Figures show what gate circuits can be used to make the adaptive action of the filter operable during the occurrence of the data signal and ~ to maintain the corrective action of the filter also for the remaining portion of the video signal.
The input 1 of the filter is at the same time the input of a delay circuit 3 having a number of taps 5, 7, 9, 11 and 12. The taps 5~ 7~ 9 and 11 are connected to an adding circuit 21 via amplitude control circuits 13 and 15, 17~ 19, respectively~ and the tap 12~via a circuit 22 hav-ing a fixed transfer fac-tor equal to unit~.
A signal which is applied to an input 25 of a clamping circuit 27 is obtained from an output 23 of the adding circuit 21. The clamping circuit 27 corrects the d.c.
voltage level of the data signal such that a signal obtained from an output 29 thereof is suitable to be processed b~ a threshold circuit 31 to which it is applied~
An output signal of the threshold circuit 31 is applied to an input 32 of an au-tomatic gain control circuit 33, an output 34 of which is connected to an input 35 of a difference-determining circuit 37, a second input 39 of which receives the signal coming from the output 29 of the .
~9~3~
27~ 1979 -4- PHN 9388 clarnping circuit 27.
- The signal obtained at the input 35 of the differ-ence-determining circuit via the threshold circuit 31 and the automatic gain control circuit 33 is called the referenoe signal. Because of the action of the threshold circuit 31 it has a wave form which substantially corresponds to the wave form the corrected signal at the second input 39, which is at the ~ame time the output of the filter, should have. A
signal called error signal and which controls a plurality lO of automatic settings is obtained from an OlltpUt 41 of the difference-determining circuit 37.
The error signal at the output 41 of the difference-determining circuit 37 is applied to four circuits 43, 45, 47, 49, which apply control signals to the amplitude con-15 trol circuits 13 and 153 17, 19, respectively, via an in-tegrator 51 and 53, 55, 57, respectively, and which are formed by an amplifier another input of which is connected to the taps 5 and 7, 9, 11, respectively. The amplifiers 43, 45, 47, 49 forrm, together with the integrators 51, 53, 20 55, 57, so-called correlation circuits which ensure, via the arnplitude control circuits 137 15, 17, 19, that -the corrected signal at the second input 39 of the difference-determining circuit 37 becomes substantially equal to that of the reference signal at the input 35 thereof.
The error signal coming fram the output 41 of the difference-determining circuit 37 is also applied to an input 59 of the au-tomatic gain control circuit 33. Connected ~ to this input 59 there is an input of an arnplifier 61 another input of which is connected to an input of a further 30 control circuit 63, which is connected to the input 32 of the automatic control circuit 33. Via an integrating cir-cuit 65 an output of the multiplier 61 is connected to a further input of the further control circuit 63, an output of which is connected to the output 34 of the automatic gain 35 control circuit 33. The fur-ther control circuit 63 is con-stituted by a multiplier.
The automatic gain control circuit 33 now controls the arnplitude of the reference signal to such a value that /
33~
.~ .
27~ 1979 -5- P~ 9388 the error signal at the output 41 of the difference-determining circuit assumes a value which approaches the value of the desired corrected signal as closely as pos-sible. The place where the automatic gain control is now active ensures that no unwanted stable state can occur anymore and any direct current component in the corrected signal cannot provoke the control to zero of the output signal of the filter.
The influence of the direct current component lQ in the corrected signal on the amplitude control circuits 13, 15, 17, 19 is reduced by the clamping circuit 27 to an input 67 of which the error signal is applied, this error signal also being applied via an integrating circuit 69 to an input of a multiplier 71, a further input of which is connected to a constant direct current source 72. An output of the multiplier 71 then applies such a direct current signal to an input of a subtracting circuit 73iji another input of which is con~lected to the input 25 of the clamping circuit 27~ that, in the signal at an output of the subtracting circuit 73 which is connected to the out-- put 29 of the clamping circuit 27 a level between two data levels equals a threshold level of the threshold circuit 31.
The clamping circuit 27 therefore causes a reduced adaptation time of the filter. Furthermore, it does not only compensate for a possible level in the input signal of the filter but also for any unwanted direc-t current component or a possible asymmetry in the threshold circuit 31 which were~ for example~ cauced by direct current coupl-ings in the filter. This makes the filter circuit very ` 30 suitable for implemen-tation as integrated circuit.
It will be clear that the clamping circuit 27 can be omitted when no direct curren-t component in the cor-rected signal or asymmetry in the threshold circuit are ; expected.
Should -the f`ilter be suitable for processing a multi-level data signal instead of processing a by-level signal for which the above-mentioned circuit of the filter is intended, the reference signal generation and, 27~ 1979 - 6 - P~ 9388 consequently, the threshold circuit and the additional control circuit must be adapted thereto.
Instead of a reference signal generated by means of a threshold circuit it is, alternatively, possible to use a reference signal which was generated in a different man-ner. The automatic gain control can then be used in an analogous manner~
In this example the error signal for the amplitude control circui-ts is processed in accordance with the method Of minimising the mean square. It will be obvious that this can also be done in a different, suitable manner.
If so desired it is, for example, alternatively possible to use a signal at the output 23 of the adding circuit 21~ a~ the output 22 of the threshold circuit 31 or at the output 34 of the automatic gain control circuit 33 as the output signal of ~e filter. If the output signal of the filter is obtained from the output 29 of the clamp-in~ circuit 27 the amplitude thereof can be keptconstant by a control circuit which also uses the output signal of the integrator 65 as its control signal, but which controls into a sense opposite to ihe sense of the multiplying circuit 63, which may be effected hy means of a dividing circui-t.
It is further possible -to apply the output signal of the last-mentioned control circuit to the input 39 of the difference-determining circuit 37 when the mul-tiplying cir-cuit 63 is provided at the output 41 of the difference-determining circuit 37 instead of at the input 35 thereof.
In that case, if so desired~ the output signal can alter-natively be derived from other points in the circuit.
The above-described construc-tion of the amplifying control circuit 33 has the advantage that it is insensitive to noise and yet controls in a rapid manner. Other construct-ions, for example using peak detection to obtain the con-trol signal, are possible.
A filter according to the invention is suitable for processing synchronous and asynchronous data signals and analog pulse-modulated signals such as, for example, pulse width~ pulse duration and pulse pOSitiO}l modulated ~9~3~
signals. The filter is, for example, also very suitable for asynchronous processing in repeaters, as a circuit for recovering a clock signal is not necessary.
In a filter according to the invention the taps of the delay circuit can be used as inputs thereof if so desired.
The tap of the delay circuit in which no control is effected can alternatively be located in a different location then in the centre, as in the embodiment, and may, if so desired, alternatively be provided with some degree of control.
An advantageous construction of the delay circuit which is very suitable for implementation as integrated circuit is one in which the different delay elements are constructed as Laguerre sections: Fig. 2 describes one section of this delay circuit. It is, of course, alter-natively possible to use other types of delay circuits.
The multiplying circuits used need not be linear provided the amplitude of the output signal increases or decreases monotonously versus the amplitude of each of their input signals.
In Fig. 2 a signal applied to an input 75 is applied, vla a resistor 77, to a Darlington emitter-follower pair 79, 81 which is coupled by means of their emitters to a transistor 83, the collector of which is connected to an output 85 from which an input signal for the following section is obtained.
The input 75 is further connected to a transis-tor 88 via a capacitor 87, the collector of this transis-tor controlling the emitter of a transistor 89. The -~ collector of the transistor 89 is connected to the col-lector of the transistor 83.
Three transistors 91, 93, 95 form direct current sources for the base-emitter junction, which is bridged by a diode 97 of the transistor 88, for the collector of the transistor 81, which is connected to the base of the transistor 79 and for the collectors of the transistors 83 and 89, respectively. To that end, the bases of the tran-,~
~9~3~
, .
sis$ors 91, 93 and 95 are connected to the emitter, which is connected to the base of a transistor 97, of a tran-sistor 99~ the base of which, which is connected to the oollector of the transistor 97, is supplied with a direct current via a resistor 101. This direct current comes from the base, which is connected to the collector of a transis-tor 103, of a transistor 105, the emitter of ~hich is connected to the base o~ the transistor 103 and also to the bases of three transistors 107, 109 and 111, which ser~e as a direct current source for, in this order, the emitter~
which is connected to the base of the transistor 81, of the transistor 79, the interconnected emitters of the transis-tors 81, 85 and the emitter which is connected to the bases of the transistors 83 and 89 of a transistor 112, the base of which is connected to zero potential.
A signal A which is applied to an output 113 which constitutes a tap of the delay circu~t, ~s obtained from the emitter of the transistox 79. The signal path from the input 75 to this output 113 has a low-pass characteristic the cut-o~f frequency of which is chosen near the highest frequency of the fre~uency band of the signal to be passed through the delay oircuit. An output 1 15 has a ref`erence potential B obtained from the emitter of the transistor 11 1 .
An output 117, which caters for direct currents in other portions of the filter is connected to the emitter of the transistor 105.
The circuit has a circuit delaying transfer between ~he input 75 and the output 85. The product of the ~alues of the resistor 77 and the capacitor 87 determines the time delay.;
The terminals 113, 115 and 117 are also terminals of the amplitude control circuit shown schematically in Fig. 30 In this Fig. 3 the terminal 11 7 is connected to the bases o~ 2 current source transistors 119, 121, which each supply the direct current for a multiplying circuit.
A ~irst multiplying circuit is formed by si~
transistors 123, 125, 127, 129, 131 and 135. The transis-tors 123, 125 and 127, 129 and 131, 135,respectively, are coupled together by means of their emitters. A control signal is applied in anti-phase ti the bases of the tran-sistors 123 and 125~ Later in this description it will bedescribed how this control signal is obtainedO
The bases of the transistors 127 and 131 are con-nected to the terminal l13 and are supplied with the signal A from a tap of the delay circuit. The bases of the transis-l tors 129 and 135 are connected to the terminal 115 and aresupplied with the reference potential B. The collectors of the transistors 127 and 135 are connected to an output 137 and the collectors of the transistors 129 and 131 are con-nected to an output 139. The outputs 137 and 139 carry in anti-phase the signals P and Q whose amplitude is controlled by the first multiplying circuit.
The second multiplying circuit is formed by six transistors 141, 143, 145, 147, 149 and 151. The transis-tors 141, 143 and 145, 147, and 149, 151, respectively, are coupled togeth0r by means of their emitters. The signal A
originating from the terminal 113 is applied to the base of the transistor 141. The hase of the transistor 143 is connected to *he reference potential B of the terminal 115.
The bases of the transistors 147 and 151 are oonnected to an input 153 to which the error signal ~ ~ is applied and the bases of the transistors 145 and 149 are connected to an input 155 ~o which the error signal - ~ is applied in anti-phase. rhe collectors of the transistors 147 and 149 are interconnected and are connected via a current mirror circuit, comprising three transistors 157, 159 and 161, to the interconnected collectors of the transistors 145 and 151, which supply a current to a capacitor 163 whioh functions as an integrator, this curren-t being a measure of the product of the error signal and the signal A coming ~rom the relevant tap of the delay circuit.
In response thereto a control signal is produced across -the capacitor 163, which control signal is applied to the base of the transistor 125 Via a complementary pair ~9(33~
of transistors 165~ 167 which are arranged as an artificial transistor, this pair of transistors having an emitter resistor 168, the control signal also being applied in anti-phase to the base of the transistor 123 via a pair of complementary transistors 169, 171, which are arranged as an artificial transistor, a resistor 173 and a -transistor 175. A circuit comprising a number of diodes 177, 179, 181 and 183 at the bases of the transistors 123, 125 converts the currents supplied by the pairs of transistors 165, 167 and 169, 171 into voltages of a suitable level.
The ar;tificial transistors 165, 167 and 169, 171 are complementary and their base currents are equal and opposite when the voltage at the capacitor 163 is at a -certain value, which is determined by the resistors 168 and 173, which value adjusts itself if no control current is supplied by the multiplier 145, 147, 149, 151, as is the case at the beginning of the control. The current gains of the artificial transistors 165~ 167 and 169~ 171 are equal so that ~t the beginning of a control action the voltages at the bases of -the transistors 123 and 12~ have the same value and the gain of the first multiplying circuit 123, 125, 127, 131, 135 is zero.
By temporarily cutting off the transistors 141, 143 the second multiplying circuit 141, 143, 145, 147, 149, ~, 25 151 can be made inac-tive, if so desired, by means of a gating signal T to be applied to an input 185, this gating signal also being to the emitters of the transistors 141, 143 via a diode 187. This does not affect the control voltage at the capacitor 163 so that an amplitude setting of the ~irst multiplier resulting from the control, is retained ~or some time.
In Fig. 4 the signals P and Q coming from the terminals 137 and 139 of the amplitude control circuits are added by an adding circuit 185 and applied to inputs 187 and 189 Or a subtracting circuit comprising eight transis-tors 191, 193, 195, 197, 199, 201, 203 and 205. The other inputs o~ the subtracting circuits are the collectors of an emitter-coupled pair of transistors 207, 209. The 9~3~.
27-11-1979 _11- PHN 9388 outputs of the subraoting circuit, which are formed by the interconneoted collectors of the transistors 191, 195 and 193, 201, respectively~ apply clamped output signals in anti-phase to two outputs 215, 217, via two emitter follow-ers 211, 213. A circuit having three resistors 219, 221, 223and a diode 225 connected to the zero potential, to which also the bases of -the transistors 191~ 193 are connected, -constitutes the output circuit of the subtracting circuit.
Clamping is effected in response to the fact that in the subtracting circuit the direct current component of the ` signal at the inputs 187, 189 is corrected by the direct currents which are applied via the emitter-coupled pair of transistors 207, 209 to the transistors 199, 197, 195 and 205, 203, 201, respectively, which are arranged to form 15 current mirror circuits~
These direct currents are derived from the error signals + ~ and - ~ applied in anti-phase to two inputs 227, 229, which error signal controls the bases of an emitter-coupled pair of transistors 231, 233. The collector 20 of the transistor 233 is connected to the collector of the transis$or 231 via a current mirror circuit having three transistors 235, 2377 239, so that a difference current which is a measure of the average difference in voltage at the inputs 227, 229 is applied in this collector circuit 25 to a capacitor 241, which functions as an integrator. In response to this difference current there is produced across the capacitor 2L~1 a control voltage which controls the base of the transistor 209 via a pair of complementary transistors 243, 245, arranged as an artificial transistor 30 and having an emitter resistor 246, and which so controls the base of the transistor 207 via a pair of complementary transistors 247, 249, arranged as an artifical transistor and having a resistor 251, that variations occur in anti-phase at the bases of the transistors 207, 209.
Connected to the bases of the transistors 207, 209 is a further diode circuit 259, 261, 263, 265 which is ~ed by two resis-tors 255, 257, whereby the currents supplied by the artificial transistors 243, 245 and 247, 249 are con-~9~3~
27~ 1979 - 12- PHN 9388 verted into voltages of a suitable level for controlling the bases of the pair of transistors 207, 209. The resis-tors 255 and 257 have for their function to adapt the con-trol range of the clamping circuit.
The pair of transistors 207, 209 contains its direct current from a current source transistor 267 the base of which is connected to the terminal 11 7. There is a current source transistor, as shown by means of a dotted line in Fig. 4, for each Laguerre section as shown schematically in Fig. 2~ The~ compensate for the direct currents which are applied to the inputs 187 and 18~ via the signals P and Q.
The base of the transistor 253 is connected to zero potential via an emitter follower 269. The emitter current for the emitter follower 269 is supplied by a current source transistor 271.
The direct current for the pair of transistors 231, 233 is supplied by a current source transistor 273.
The bases of the current source transistors 271 and 273 20 are controlled by a resistor 275 and two transistors 277, 279.
Ganeration of the control voltage can be temporari-ly made inactive by cutting off the transistors 231, 233 by means of a gating signal T, applied to the emitters 25 thereof via a diode 281, the gating signal coming from an input 283. The voltage across the capacitor 2l~1 is then not influenced.
The outputs 215 and 217 of the clamping circuit of Fig. ~ constitute outputs of the filter circuit and are 30 also inputs of the circuit of Fig. 5.
In Fig. ~ the clamped signal at the inputs 215, 217 is applied in anti-phase to the bases of two transis-tors 285, 287, which form the further control circuit in combination with a transistor included in the emitter cir-35 cuits of these transistors, the control signal beingapplied to the base of the transistor 289. The manner of obtaining this control signal will be described hereinafter.
A flip-flop circuit comprising two transistors 291, 293 .
27~ 1979 - 13 - PHN 9388 and a resistor 295 is arranged between the collector of the transistor 289 and the emitters of the transistors 285, 287, causing the further control circuit to operate also as a threshold circuit for the signal at the bases 5 of the transistors 285, 287, so that a two-level signal occurs at the collectors of the transistors, the amplitude of this signal being determined by the control voltage at the base of the transistor 289. When the base of the transistor 285 is positive with respect to that of the .~ 10 transistor 287 the transistor 291 is cutoff and the transis-: tor 293 conducts, so that the current of the current source-transistor 289 flows via the transistor 287, and when the base of the transistor 285 is negative with respect to the base of the transistor 287 this current flows via the transistor 285.
The signals at the inputs 215, 217 are also ap-plied to the bases of two transistors 297, 299 the emitters of which are connected to the collector of a direct current , transistor 305 via resistors 301, 303, the collectors : : 20 being connected to the collectors of the transistors 285 and 287, respectively. As a result thereof the collector circuit of these four transistors 285, 287, 297S 299 forms a difference-determining circuit wherein the output signal of the filter, applied via the transistors 297, 299, and a : ~ 25 reference signal supplied by the transistors 285, 287 and having an amplitude which is controlled by a control signal at the base of the transistor 289 are subtracted from one another so that the error signal is supplied in antiphase I ~ and - ~ at two outputs 307, 309.
This error signal is further applied to the bases of two transistors 311, 313 and 315, 317, respectively.
The emit~ers of the transistors 313 and 317 are connected to the collector of a transistor 319 and the emitters of the transistors 311 and 315 are connected to -the collector of a transistor 321 the bases of which are controlled by the signal at the inputs 215, 217 and the emitters of which are connec-ted to the collector of a direct current source transistor 329 via a flip-flop circuit which comprises two 3~
transistors 323, 325 and a resistor 327 and which serves as threshold circuit. The interconnected collectors of the transistors 311 and 317 are connected to the interconnected collectors of the transistors 313 and 315 via a current mirror circuit comprising three transistors 331, 333 and 335 and a resistor 336, so that the collectors of the transistors 313 and 315 apply a difference currerlt~ which produces a voltage across that capacitor, this voltage being a measure of the value of the error signal multiplied 3 10 by the sign of the output signal of the filter, to a capa-citor 337 l~hich serves as an integrator.
Via thrée emitter followers 339, 341, 343 and a resistor 345 the voltage at the capacitor 337 is applied to the emitter of a transistor 347, the base of which is l~ connected to-zero potential and whose collector applies a control signal to two transistors 349, 351, which form a current mirror circuit together with the transistor 289.
The transistors 3O5 and 329 form in combination with two transistors 353, 355 and a resistor 357 a current 20 mirror circuit, which is controlled by a resistor 35g from the zero potential.
The direct currents to the collectors of the transistors 285~ 287, 297 and 299 are applied via resis-tors 3617 363 and emitter followers 365, 367,the bases 25 of these emitter followers having been connected to the zero potential at a sui-table level via a resistance-diode networX 369, 371, 373. The resistors 361 and 363 are low-value resistors and compensate for any inequalities in the transistors 365~ 367.
The transistors 319 and 321 can be temporarily cutoff by a gating signal T, which can be applied to an input 375 and which can take over the collector current of the transistor 329 via a diode 377, This does not affect the voltage at the capacitor 337.
For clarity, two threshold circuits 2g1~ 293, 295, and 323, 325, 327 are shown in the construction of Fig. 5 instead of the sole threshold circuit denoted in Fi~. 1 by reference nu-neral 31.
3~
27-11-1979 -15~ PHN 9388 .
It is possible to derive, for example from a cir-cuit as shown in Fig. 3, a non-controlled circuit 22 of Fig. 1 by arranging in parallel with the emitter-collector path of the transistor 125, the emitter-collector path of a transistor, the base of which is connected to such a voltage that the transistors 123 and 125 are non-conducting.
-Jt 25
"Adaptive filter including a delay circuit".
The invention relates to an adaptive filter in-cluding a delay circuit taps of which comprise amplitude control circuits, also including a difference-determining circuit forming an error signal of a signal corrected by the filter with respect to a reference signal which has a waveform l~hich substantially corresponds to the desired waveform of the signal corrected by the filter, circuits for obtaining control signals for the amplitude control cir~uits being controlled by means of this error signal and including a further control circuit.
Nachrichten Technische Zeitschrift 1971, Vol. 1 pages 18-24, page 20 in particular, discloses anadaptive filter of the above-~entioned kind. The further control circuit there has ~or its function to keep the amplitude at the center of main tap of the delay circuit of the filter constant and it is arranged outside the filter, that is to say before the input of the filter, as the filter utilizes the error signal. In certain cases it appears that such a controI may result in an unwanted stable state where- -in the amplitude of the filter output signal becomes zero.
It is an object of the invention to provide the further control circuit in such a place that the above~
mentioned drawbac~ is obviated~
According to the invention anadaptive filter of the type mentioned in the opening paragraph is therefore characterized in that the further control circuit is provided at an input of the difference determining circuit, whereas the control signal for this further control circuit is obtained from an integrator at an output of a multiplying circuit to which the reference signal and the error signal are applied.
It appeared that by the action of the further con-trol circuit on the amplitude of the reference signal or on ,, ~.
27 11-1979 -2 P~ 9388 the amplitude of the corrected signal and the error signal a blocked state which may particularly occur on actuation is prevented from occurring. In addition, a stable final state with a zero amplitude of the output signal of the fllter ~
does not occur anymore if there is a d7c. voltage component in the signal to be corrected by the filter. Namely, a control before the filter would tend to control this d.c.
~oltage component to zero if the reference signal does not contain this d.c. voltage component and in general this : lO cannot be the case because it usually has an unknown value whichis influenced by, for example, unwanted contributions of circuits.
A further embodiment of an adaptive filter according to the invention is characterized in that the further control circuit is a multiplying circuit. Owing to this measure an influence exercised by unwanted direct~
currents on the amplitude control systems is substantially eliminated.
An adapti~e filter according to the invention is very suitable for suppressing echoes in data signals which are present at a certain level in a video signal~ such as teletext signals or digital audio signals. A television re-ceiver having such a filter gives a very good echo sup-pression which cannot only be effective on the data signal - 25 but also on the remaining portion of the signal~ so that the quality of a television picture displayed by the re-ceiver can improve.
The invention will now be further explained with reference to the drawing:
In the drawing:
Fig. 1 illustrates an adaptive filter according to the in~ention by means of a block diagram~
Fig. 2 illustrates by means of a circuit diagram ~ a possible construction of a dslay element of a delay cir--~ 35 cuit for an adaptive filter shown in Fig. 1, Fig. 3 shows a possible constru~ion of an amplitu-de control circuit for an adaptive filter shown in ~ig. 1, ~ ig. 4 shows a construction of a clamping circuit ,~
3~
,, ~ . . ....
in accordance with a further embodiment of the invention for an adaptive filter shown in Fig. 1 and Fig. 5 shows a possible construction of a threshold circuit and ancdditional control circuit for an adaptive filter shown in Fig~ 1, In Fig. 1 a signal which is to be corrected by the filter is applied to an input 1 of an adaptive filter. For the construction of the filter as it will be described here-inafter this is a video signal of a television signal~ In certain periods of time this video signal comprises data information such as, for example, teletext information or digital video inf~ormation. Generally, this information is present in the video signal at a level which deviates from the zero level of that video signal.
In the description of ~ig. 1 only the operation of the adaptive filter during the occurrence of the data signal will be described. The subsequent Figures show what gate circuits can be used to make the adaptive action of the filter operable during the occurrence of the data signal and ~ to maintain the corrective action of the filter also for the remaining portion of the video signal.
The input 1 of the filter is at the same time the input of a delay circuit 3 having a number of taps 5, 7, 9, 11 and 12. The taps 5~ 7~ 9 and 11 are connected to an adding circuit 21 via amplitude control circuits 13 and 15, 17~ 19, respectively~ and the tap 12~via a circuit 22 hav-ing a fixed transfer fac-tor equal to unit~.
A signal which is applied to an input 25 of a clamping circuit 27 is obtained from an output 23 of the adding circuit 21. The clamping circuit 27 corrects the d.c.
voltage level of the data signal such that a signal obtained from an output 29 thereof is suitable to be processed b~ a threshold circuit 31 to which it is applied~
An output signal of the threshold circuit 31 is applied to an input 32 of an au-tomatic gain control circuit 33, an output 34 of which is connected to an input 35 of a difference-determining circuit 37, a second input 39 of which receives the signal coming from the output 29 of the .
~9~3~
27~ 1979 -4- PHN 9388 clarnping circuit 27.
- The signal obtained at the input 35 of the differ-ence-determining circuit via the threshold circuit 31 and the automatic gain control circuit 33 is called the referenoe signal. Because of the action of the threshold circuit 31 it has a wave form which substantially corresponds to the wave form the corrected signal at the second input 39, which is at the ~ame time the output of the filter, should have. A
signal called error signal and which controls a plurality lO of automatic settings is obtained from an OlltpUt 41 of the difference-determining circuit 37.
The error signal at the output 41 of the difference-determining circuit 37 is applied to four circuits 43, 45, 47, 49, which apply control signals to the amplitude con-15 trol circuits 13 and 153 17, 19, respectively, via an in-tegrator 51 and 53, 55, 57, respectively, and which are formed by an amplifier another input of which is connected to the taps 5 and 7, 9, 11, respectively. The amplifiers 43, 45, 47, 49 forrm, together with the integrators 51, 53, 20 55, 57, so-called correlation circuits which ensure, via the arnplitude control circuits 137 15, 17, 19, that -the corrected signal at the second input 39 of the difference-determining circuit 37 becomes substantially equal to that of the reference signal at the input 35 thereof.
The error signal coming fram the output 41 of the difference-determining circuit 37 is also applied to an input 59 of the au-tomatic gain control circuit 33. Connected ~ to this input 59 there is an input of an arnplifier 61 another input of which is connected to an input of a further 30 control circuit 63, which is connected to the input 32 of the automatic control circuit 33. Via an integrating cir-cuit 65 an output of the multiplier 61 is connected to a further input of the further control circuit 63, an output of which is connected to the output 34 of the automatic gain 35 control circuit 33. The fur-ther control circuit 63 is con-stituted by a multiplier.
The automatic gain control circuit 33 now controls the arnplitude of the reference signal to such a value that /
33~
.~ .
27~ 1979 -5- P~ 9388 the error signal at the output 41 of the difference-determining circuit assumes a value which approaches the value of the desired corrected signal as closely as pos-sible. The place where the automatic gain control is now active ensures that no unwanted stable state can occur anymore and any direct current component in the corrected signal cannot provoke the control to zero of the output signal of the filter.
The influence of the direct current component lQ in the corrected signal on the amplitude control circuits 13, 15, 17, 19 is reduced by the clamping circuit 27 to an input 67 of which the error signal is applied, this error signal also being applied via an integrating circuit 69 to an input of a multiplier 71, a further input of which is connected to a constant direct current source 72. An output of the multiplier 71 then applies such a direct current signal to an input of a subtracting circuit 73iji another input of which is con~lected to the input 25 of the clamping circuit 27~ that, in the signal at an output of the subtracting circuit 73 which is connected to the out-- put 29 of the clamping circuit 27 a level between two data levels equals a threshold level of the threshold circuit 31.
The clamping circuit 27 therefore causes a reduced adaptation time of the filter. Furthermore, it does not only compensate for a possible level in the input signal of the filter but also for any unwanted direc-t current component or a possible asymmetry in the threshold circuit 31 which were~ for example~ cauced by direct current coupl-ings in the filter. This makes the filter circuit very ` 30 suitable for implemen-tation as integrated circuit.
It will be clear that the clamping circuit 27 can be omitted when no direct curren-t component in the cor-rected signal or asymmetry in the threshold circuit are ; expected.
Should -the f`ilter be suitable for processing a multi-level data signal instead of processing a by-level signal for which the above-mentioned circuit of the filter is intended, the reference signal generation and, 27~ 1979 - 6 - P~ 9388 consequently, the threshold circuit and the additional control circuit must be adapted thereto.
Instead of a reference signal generated by means of a threshold circuit it is, alternatively, possible to use a reference signal which was generated in a different man-ner. The automatic gain control can then be used in an analogous manner~
In this example the error signal for the amplitude control circui-ts is processed in accordance with the method Of minimising the mean square. It will be obvious that this can also be done in a different, suitable manner.
If so desired it is, for example, alternatively possible to use a signal at the output 23 of the adding circuit 21~ a~ the output 22 of the threshold circuit 31 or at the output 34 of the automatic gain control circuit 33 as the output signal of ~e filter. If the output signal of the filter is obtained from the output 29 of the clamp-in~ circuit 27 the amplitude thereof can be keptconstant by a control circuit which also uses the output signal of the integrator 65 as its control signal, but which controls into a sense opposite to ihe sense of the multiplying circuit 63, which may be effected hy means of a dividing circui-t.
It is further possible -to apply the output signal of the last-mentioned control circuit to the input 39 of the difference-determining circuit 37 when the mul-tiplying cir-cuit 63 is provided at the output 41 of the difference-determining circuit 37 instead of at the input 35 thereof.
In that case, if so desired~ the output signal can alter-natively be derived from other points in the circuit.
The above-described construc-tion of the amplifying control circuit 33 has the advantage that it is insensitive to noise and yet controls in a rapid manner. Other construct-ions, for example using peak detection to obtain the con-trol signal, are possible.
A filter according to the invention is suitable for processing synchronous and asynchronous data signals and analog pulse-modulated signals such as, for example, pulse width~ pulse duration and pulse pOSitiO}l modulated ~9~3~
signals. The filter is, for example, also very suitable for asynchronous processing in repeaters, as a circuit for recovering a clock signal is not necessary.
In a filter according to the invention the taps of the delay circuit can be used as inputs thereof if so desired.
The tap of the delay circuit in which no control is effected can alternatively be located in a different location then in the centre, as in the embodiment, and may, if so desired, alternatively be provided with some degree of control.
An advantageous construction of the delay circuit which is very suitable for implementation as integrated circuit is one in which the different delay elements are constructed as Laguerre sections: Fig. 2 describes one section of this delay circuit. It is, of course, alter-natively possible to use other types of delay circuits.
The multiplying circuits used need not be linear provided the amplitude of the output signal increases or decreases monotonously versus the amplitude of each of their input signals.
In Fig. 2 a signal applied to an input 75 is applied, vla a resistor 77, to a Darlington emitter-follower pair 79, 81 which is coupled by means of their emitters to a transistor 83, the collector of which is connected to an output 85 from which an input signal for the following section is obtained.
The input 75 is further connected to a transis-tor 88 via a capacitor 87, the collector of this transis-tor controlling the emitter of a transistor 89. The -~ collector of the transistor 89 is connected to the col-lector of the transistor 83.
Three transistors 91, 93, 95 form direct current sources for the base-emitter junction, which is bridged by a diode 97 of the transistor 88, for the collector of the transistor 81, which is connected to the base of the transistor 79 and for the collectors of the transistors 83 and 89, respectively. To that end, the bases of the tran-,~
~9~3~
, .
sis$ors 91, 93 and 95 are connected to the emitter, which is connected to the base of a transistor 97, of a tran-sistor 99~ the base of which, which is connected to the oollector of the transistor 97, is supplied with a direct current via a resistor 101. This direct current comes from the base, which is connected to the collector of a transis-tor 103, of a transistor 105, the emitter of ~hich is connected to the base o~ the transistor 103 and also to the bases of three transistors 107, 109 and 111, which ser~e as a direct current source for, in this order, the emitter~
which is connected to the base of the transistor 81, of the transistor 79, the interconnected emitters of the transis-tors 81, 85 and the emitter which is connected to the bases of the transistors 83 and 89 of a transistor 112, the base of which is connected to zero potential.
A signal A which is applied to an output 113 which constitutes a tap of the delay circu~t, ~s obtained from the emitter of the transistox 79. The signal path from the input 75 to this output 113 has a low-pass characteristic the cut-o~f frequency of which is chosen near the highest frequency of the fre~uency band of the signal to be passed through the delay oircuit. An output 1 15 has a ref`erence potential B obtained from the emitter of the transistor 11 1 .
An output 117, which caters for direct currents in other portions of the filter is connected to the emitter of the transistor 105.
The circuit has a circuit delaying transfer between ~he input 75 and the output 85. The product of the ~alues of the resistor 77 and the capacitor 87 determines the time delay.;
The terminals 113, 115 and 117 are also terminals of the amplitude control circuit shown schematically in Fig. 30 In this Fig. 3 the terminal 11 7 is connected to the bases o~ 2 current source transistors 119, 121, which each supply the direct current for a multiplying circuit.
A ~irst multiplying circuit is formed by si~
transistors 123, 125, 127, 129, 131 and 135. The transis-tors 123, 125 and 127, 129 and 131, 135,respectively, are coupled together by means of their emitters. A control signal is applied in anti-phase ti the bases of the tran-sistors 123 and 125~ Later in this description it will bedescribed how this control signal is obtainedO
The bases of the transistors 127 and 131 are con-nected to the terminal l13 and are supplied with the signal A from a tap of the delay circuit. The bases of the transis-l tors 129 and 135 are connected to the terminal 115 and aresupplied with the reference potential B. The collectors of the transistors 127 and 135 are connected to an output 137 and the collectors of the transistors 129 and 131 are con-nected to an output 139. The outputs 137 and 139 carry in anti-phase the signals P and Q whose amplitude is controlled by the first multiplying circuit.
The second multiplying circuit is formed by six transistors 141, 143, 145, 147, 149 and 151. The transis-tors 141, 143 and 145, 147, and 149, 151, respectively, are coupled togeth0r by means of their emitters. The signal A
originating from the terminal 113 is applied to the base of the transistor 141. The hase of the transistor 143 is connected to *he reference potential B of the terminal 115.
The bases of the transistors 147 and 151 are oonnected to an input 153 to which the error signal ~ ~ is applied and the bases of the transistors 145 and 149 are connected to an input 155 ~o which the error signal - ~ is applied in anti-phase. rhe collectors of the transistors 147 and 149 are interconnected and are connected via a current mirror circuit, comprising three transistors 157, 159 and 161, to the interconnected collectors of the transistors 145 and 151, which supply a current to a capacitor 163 whioh functions as an integrator, this curren-t being a measure of the product of the error signal and the signal A coming ~rom the relevant tap of the delay circuit.
In response thereto a control signal is produced across -the capacitor 163, which control signal is applied to the base of the transistor 125 Via a complementary pair ~9(33~
of transistors 165~ 167 which are arranged as an artificial transistor, this pair of transistors having an emitter resistor 168, the control signal also being applied in anti-phase to the base of the transistor 123 via a pair of complementary transistors 169, 171, which are arranged as an artificial transistor, a resistor 173 and a -transistor 175. A circuit comprising a number of diodes 177, 179, 181 and 183 at the bases of the transistors 123, 125 converts the currents supplied by the pairs of transistors 165, 167 and 169, 171 into voltages of a suitable level.
The ar;tificial transistors 165, 167 and 169, 171 are complementary and their base currents are equal and opposite when the voltage at the capacitor 163 is at a -certain value, which is determined by the resistors 168 and 173, which value adjusts itself if no control current is supplied by the multiplier 145, 147, 149, 151, as is the case at the beginning of the control. The current gains of the artificial transistors 165~ 167 and 169~ 171 are equal so that ~t the beginning of a control action the voltages at the bases of -the transistors 123 and 12~ have the same value and the gain of the first multiplying circuit 123, 125, 127, 131, 135 is zero.
By temporarily cutting off the transistors 141, 143 the second multiplying circuit 141, 143, 145, 147, 149, ~, 25 151 can be made inac-tive, if so desired, by means of a gating signal T to be applied to an input 185, this gating signal also being to the emitters of the transistors 141, 143 via a diode 187. This does not affect the control voltage at the capacitor 163 so that an amplitude setting of the ~irst multiplier resulting from the control, is retained ~or some time.
In Fig. 4 the signals P and Q coming from the terminals 137 and 139 of the amplitude control circuits are added by an adding circuit 185 and applied to inputs 187 and 189 Or a subtracting circuit comprising eight transis-tors 191, 193, 195, 197, 199, 201, 203 and 205. The other inputs o~ the subtracting circuits are the collectors of an emitter-coupled pair of transistors 207, 209. The 9~3~.
27-11-1979 _11- PHN 9388 outputs of the subraoting circuit, which are formed by the interconneoted collectors of the transistors 191, 195 and 193, 201, respectively~ apply clamped output signals in anti-phase to two outputs 215, 217, via two emitter follow-ers 211, 213. A circuit having three resistors 219, 221, 223and a diode 225 connected to the zero potential, to which also the bases of -the transistors 191~ 193 are connected, -constitutes the output circuit of the subtracting circuit.
Clamping is effected in response to the fact that in the subtracting circuit the direct current component of the ` signal at the inputs 187, 189 is corrected by the direct currents which are applied via the emitter-coupled pair of transistors 207, 209 to the transistors 199, 197, 195 and 205, 203, 201, respectively, which are arranged to form 15 current mirror circuits~
These direct currents are derived from the error signals + ~ and - ~ applied in anti-phase to two inputs 227, 229, which error signal controls the bases of an emitter-coupled pair of transistors 231, 233. The collector 20 of the transistor 233 is connected to the collector of the transis$or 231 via a current mirror circuit having three transistors 235, 2377 239, so that a difference current which is a measure of the average difference in voltage at the inputs 227, 229 is applied in this collector circuit 25 to a capacitor 241, which functions as an integrator. In response to this difference current there is produced across the capacitor 2L~1 a control voltage which controls the base of the transistor 209 via a pair of complementary transistors 243, 245, arranged as an artificial transistor 30 and having an emitter resistor 246, and which so controls the base of the transistor 207 via a pair of complementary transistors 247, 249, arranged as an artifical transistor and having a resistor 251, that variations occur in anti-phase at the bases of the transistors 207, 209.
Connected to the bases of the transistors 207, 209 is a further diode circuit 259, 261, 263, 265 which is ~ed by two resis-tors 255, 257, whereby the currents supplied by the artificial transistors 243, 245 and 247, 249 are con-~9~3~
27~ 1979 - 12- PHN 9388 verted into voltages of a suitable level for controlling the bases of the pair of transistors 207, 209. The resis-tors 255 and 257 have for their function to adapt the con-trol range of the clamping circuit.
The pair of transistors 207, 209 contains its direct current from a current source transistor 267 the base of which is connected to the terminal 11 7. There is a current source transistor, as shown by means of a dotted line in Fig. 4, for each Laguerre section as shown schematically in Fig. 2~ The~ compensate for the direct currents which are applied to the inputs 187 and 18~ via the signals P and Q.
The base of the transistor 253 is connected to zero potential via an emitter follower 269. The emitter current for the emitter follower 269 is supplied by a current source transistor 271.
The direct current for the pair of transistors 231, 233 is supplied by a current source transistor 273.
The bases of the current source transistors 271 and 273 20 are controlled by a resistor 275 and two transistors 277, 279.
Ganeration of the control voltage can be temporari-ly made inactive by cutting off the transistors 231, 233 by means of a gating signal T, applied to the emitters 25 thereof via a diode 281, the gating signal coming from an input 283. The voltage across the capacitor 2l~1 is then not influenced.
The outputs 215 and 217 of the clamping circuit of Fig. ~ constitute outputs of the filter circuit and are 30 also inputs of the circuit of Fig. 5.
In Fig. ~ the clamped signal at the inputs 215, 217 is applied in anti-phase to the bases of two transis-tors 285, 287, which form the further control circuit in combination with a transistor included in the emitter cir-35 cuits of these transistors, the control signal beingapplied to the base of the transistor 289. The manner of obtaining this control signal will be described hereinafter.
A flip-flop circuit comprising two transistors 291, 293 .
27~ 1979 - 13 - PHN 9388 and a resistor 295 is arranged between the collector of the transistor 289 and the emitters of the transistors 285, 287, causing the further control circuit to operate also as a threshold circuit for the signal at the bases 5 of the transistors 285, 287, so that a two-level signal occurs at the collectors of the transistors, the amplitude of this signal being determined by the control voltage at the base of the transistor 289. When the base of the transistor 285 is positive with respect to that of the .~ 10 transistor 287 the transistor 291 is cutoff and the transis-: tor 293 conducts, so that the current of the current source-transistor 289 flows via the transistor 287, and when the base of the transistor 285 is negative with respect to the base of the transistor 287 this current flows via the transistor 285.
The signals at the inputs 215, 217 are also ap-plied to the bases of two transistors 297, 299 the emitters of which are connected to the collector of a direct current , transistor 305 via resistors 301, 303, the collectors : : 20 being connected to the collectors of the transistors 285 and 287, respectively. As a result thereof the collector circuit of these four transistors 285, 287, 297S 299 forms a difference-determining circuit wherein the output signal of the filter, applied via the transistors 297, 299, and a : ~ 25 reference signal supplied by the transistors 285, 287 and having an amplitude which is controlled by a control signal at the base of the transistor 289 are subtracted from one another so that the error signal is supplied in antiphase I ~ and - ~ at two outputs 307, 309.
This error signal is further applied to the bases of two transistors 311, 313 and 315, 317, respectively.
The emit~ers of the transistors 313 and 317 are connected to the collector of a transistor 319 and the emitters of the transistors 311 and 315 are connected to -the collector of a transistor 321 the bases of which are controlled by the signal at the inputs 215, 217 and the emitters of which are connec-ted to the collector of a direct current source transistor 329 via a flip-flop circuit which comprises two 3~
transistors 323, 325 and a resistor 327 and which serves as threshold circuit. The interconnected collectors of the transistors 311 and 317 are connected to the interconnected collectors of the transistors 313 and 315 via a current mirror circuit comprising three transistors 331, 333 and 335 and a resistor 336, so that the collectors of the transistors 313 and 315 apply a difference currerlt~ which produces a voltage across that capacitor, this voltage being a measure of the value of the error signal multiplied 3 10 by the sign of the output signal of the filter, to a capa-citor 337 l~hich serves as an integrator.
Via thrée emitter followers 339, 341, 343 and a resistor 345 the voltage at the capacitor 337 is applied to the emitter of a transistor 347, the base of which is l~ connected to-zero potential and whose collector applies a control signal to two transistors 349, 351, which form a current mirror circuit together with the transistor 289.
The transistors 3O5 and 329 form in combination with two transistors 353, 355 and a resistor 357 a current 20 mirror circuit, which is controlled by a resistor 35g from the zero potential.
The direct currents to the collectors of the transistors 285~ 287, 297 and 299 are applied via resis-tors 3617 363 and emitter followers 365, 367,the bases 25 of these emitter followers having been connected to the zero potential at a sui-table level via a resistance-diode networX 369, 371, 373. The resistors 361 and 363 are low-value resistors and compensate for any inequalities in the transistors 365~ 367.
The transistors 319 and 321 can be temporarily cutoff by a gating signal T, which can be applied to an input 375 and which can take over the collector current of the transistor 329 via a diode 377, This does not affect the voltage at the capacitor 337.
For clarity, two threshold circuits 2g1~ 293, 295, and 323, 325, 327 are shown in the construction of Fig. 5 instead of the sole threshold circuit denoted in Fi~. 1 by reference nu-neral 31.
3~
27-11-1979 -15~ PHN 9388 .
It is possible to derive, for example from a cir-cuit as shown in Fig. 3, a non-controlled circuit 22 of Fig. 1 by arranging in parallel with the emitter-collector path of the transistor 125, the emitter-collector path of a transistor, the base of which is connected to such a voltage that the transistors 123 and 125 are non-conducting.
-Jt 25
Claims (3)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. An automatic gain control circuit for an adapt-ive filter, said filter including a delay circuit having a plurality of taps thereto, a plurality of amplitude con-trol circuits coupled respectively to said plurality of taps, correlation circuits for respectively providing control signals for said amplitude control circuits, means for combining the outputs from said amplitude control cir-cuits for forming a corrected output signal of said filter, and a difference determining circuit having an input coupled to the corrected signal output of the filter and an output for providing an error signal which, in turn, is applied to said correlation circuits, characterized in that said automatic gain control circuit is coupled to another input of said difference determining circuit and to the corrected signal output of the filter for deriving a reference signal from the corrected output signal of the filter, said reference signal having a waveform which sub-stantially corresponds to the desired waveform of the cor-rected output signal, said automatic gain control circuit comprising a further control circuit having a first input and an output coupled respectively to the input and the output of the automatic gain control circuit, an inte-grator coupled to a second input of said further control circuit for providing a control signal therefor, and a multiplying circuit having inputs coupled respectively to the input of said automatic gain control circuit and the output of said difference determining circuit and an out-put coupled to said integrator.
2. An automatic gain control circuit as claimed in Claim 1, characterized in that the further control circuit is a multiplying circuit.
3. An automatic gain control circuit as claimed in Claim 1 or 2, characterized in that the input signal thereto is first applied to a threshold circuit.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| NL7902093A NL7902093A (en) | 1979-03-16 | 1979-03-16 | SELF-ADJUSTING FILTER WITH A DELAY CIRCUIT. |
| NL7902093 | 1979-03-16 | ||
| GB7915682A GB2048618B (en) | 1979-03-16 | 1979-05-04 | Data pulse slicing |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1149031A true CA1149031A (en) | 1983-06-28 |
Family
ID=26271416
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000347102A Expired CA1149031A (en) | 1979-03-16 | 1980-03-06 | Adaptive filter including a delay circuit |
| CA000347636A Expired CA1134461A (en) | 1979-03-16 | 1980-03-13 | Waveform correction circuit |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000347636A Expired CA1134461A (en) | 1979-03-16 | 1980-03-13 | Waveform correction circuit |
Country Status (12)
| Country | Link |
|---|---|
| US (2) | US4333158A (en) |
| EP (1) | EP0016503B1 (en) |
| JP (2) | JPS55125717A (en) |
| AU (2) | AU537411B2 (en) |
| BE (1) | BE882246A (en) |
| BR (1) | BR8001498A (en) |
| CA (2) | CA1149031A (en) |
| DE (2) | DE3009264C2 (en) |
| ES (1) | ES489554A1 (en) |
| FR (1) | FR2451667A1 (en) |
| GB (2) | GB2048618B (en) |
| NL (1) | NL7902093A (en) |
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| US6826279B1 (en) | 2000-05-25 | 2004-11-30 | 3Com Corporation | Base band echo cancellation using laguerre echo estimation |
| JP2002300542A (en) * | 2001-04-03 | 2002-10-11 | Mitsubishi Electric Corp | Data slicer circuit |
| JP2008508770A (en) | 2004-07-29 | 2008-03-21 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Data extraction from television signals using adaptable slice levels |
| US10855951B2 (en) * | 2018-07-13 | 2020-12-01 | Analog Devices Global Unlimited Company | Methods and devices for compensating sag effect |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2049578A5 (en) * | 1969-06-13 | 1971-03-26 | Thomson Csf | |
| US3632905A (en) * | 1969-12-19 | 1972-01-04 | Bell Telephone Labor Inc | Method for improving the settling time of a transversal filter adaptive echo canceller |
| US3715670A (en) * | 1971-12-20 | 1973-02-06 | Bell Telephone Labor Inc | Adaptive dc restoration in single-sideband data systems |
| US4013980A (en) * | 1973-01-05 | 1977-03-22 | Siemens Aktiengesellschaft | Equalizer for partial response signals |
| JPS5182548A (en) * | 1974-12-27 | 1976-07-20 | Fujitsu Ltd | Jidotokaki |
| US4087654A (en) * | 1975-11-28 | 1978-05-02 | Bell Telephone Laboratories, Incorporated | Echo canceller for two-wire full duplex data transmission |
| JPS5270707A (en) * | 1975-12-09 | 1977-06-13 | Nec Corp | Automatic phase control system |
| FR2354003A1 (en) * | 1976-06-04 | 1977-12-30 | Anvar | IMPROVEMENTS TO DATA TRANSMISSION SYSTEMS |
| NL7709663A (en) * | 1977-09-02 | 1979-03-06 | Philips Nv | DELAY NETWORK WITH A CHAIN OF ALL-PASS SECTIONS. |
| US4222073A (en) * | 1977-10-19 | 1980-09-09 | Matsushita Electric Industrial Co., Ltd. | Multiplexed information signal receiving system |
-
1979
- 1979-03-16 NL NL7902093A patent/NL7902093A/en not_active Application Discontinuation
- 1979-05-04 GB GB7915682A patent/GB2048618B/en not_active Expired
-
1980
- 1980-03-06 CA CA000347102A patent/CA1149031A/en not_active Expired
- 1980-03-10 US US06/129,050 patent/US4333158A/en not_active Expired - Lifetime
- 1980-03-11 DE DE3009264A patent/DE3009264C2/en not_active Expired
- 1980-03-12 FR FR8005545A patent/FR2451667A1/en active Granted
- 1980-03-13 BR BR8001498A patent/BR8001498A/en unknown
- 1980-03-13 GB GB8008509A patent/GB2045039B/en not_active Expired
- 1980-03-13 CA CA000347636A patent/CA1134461A/en not_active Expired
- 1980-03-14 BE BE0/199815A patent/BE882246A/en not_active IP Right Cessation
- 1980-03-14 EP EP80200239A patent/EP0016503B1/en not_active Expired
- 1980-03-14 AU AU56443/80A patent/AU537411B2/en not_active Ceased
- 1980-03-14 ES ES489554A patent/ES489554A1/en not_active Expired
- 1980-03-14 DE DE8080200239T patent/DE3064560D1/en not_active Expired
- 1980-03-15 JP JP3330680A patent/JPS55125717A/en active Granted
- 1980-03-17 JP JP3466380A patent/JPS56107629A/en active Granted
- 1980-03-18 AU AU56541/80A patent/AU530895B2/en not_active Ceased
- 1980-04-18 US US06/141,517 patent/US4358790A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| EP0016503A1 (en) | 1980-10-01 |
| ES489554A1 (en) | 1980-09-16 |
| GB2045039A (en) | 1980-10-22 |
| JPS56107629A (en) | 1981-08-26 |
| US4358790A (en) | 1982-11-09 |
| CA1134461A (en) | 1982-10-26 |
| AU530895B2 (en) | 1983-08-04 |
| AU5654180A (en) | 1980-09-18 |
| US4333158A (en) | 1982-06-01 |
| DE3009264C2 (en) | 1982-09-09 |
| JPS6318894B2 (en) | 1988-04-20 |
| AU5644380A (en) | 1980-09-18 |
| GB2048618B (en) | 1983-11-02 |
| BR8001498A (en) | 1980-11-11 |
| JPH0586088B2 (en) | 1993-12-09 |
| DE3064560D1 (en) | 1983-09-22 |
| JPS55125717A (en) | 1980-09-27 |
| NL7902093A (en) | 1980-09-18 |
| FR2451667B1 (en) | 1982-12-10 |
| BE882246A (en) | 1980-09-15 |
| EP0016503B1 (en) | 1983-08-17 |
| AU537411B2 (en) | 1984-06-21 |
| DE3009264A1 (en) | 1980-09-18 |
| GB2045039B (en) | 1983-09-28 |
| GB2048618A (en) | 1980-12-10 |
| FR2451667A1 (en) | 1980-10-10 |
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