CA1149919A - Circuit interrupter with multiple display and parameter entry means - Google Patents

Abstract

49,013 ABSTRACT OF THE DISCLOSURE
A circuit interrupter includes a microcomputer-based trip unit, and a display and control panel compris-ing a numeric display device and a plurality of legends associated with light-emitting diodes. The trip unit pre-sents a sequential display of numeric values of associated circuit electrical parameters and time-current trip char-acteristic setting values, with the. currently visible numeric quantity being identified by an energized light emitting diode and associated legend. The control panel also includes a test switch for initiating a test opera-tion and a potentiometer for selecting a desired simulated fault current value for the test operation. The test capability is provided simultaneously with normal circuit breaker operation which maintains full protection of the associated circuit. A short-delay feature is provided having a selectable i2t characteristic with adjustment of both pick-up and time parameters.

Description

1~4~9i9 1 49,013 CIRCUIT INTERRUPTER WITH MULTIPLE
DISPLAY AND PARAMETER ENTRY MEANS
CROSS-REFERENCE TO RELATED CANADIAN APPLICATIONS
m~ present invention i8 related to material disclosed in the following Canadian patent applications9 all of which are assigned to the sam~ a~signee of the present application.
Canadian Serial No. 374,787, "Circuit Interrupter With Solld State Digital Trip Unit" filed April 6, 1981 by J. C. Engel;
Canadian Serial No. 374,755, "Circuit Interrupter With Front Panel Numeric Dlsplay" filed April 6, 1981 by J. C. Engel, R. T. Elms. and G. F. Saletta;
Canadian 5erlal No. 374,764, "Clrcuit Interrupter Wlth Solld State Digltal Trlp Unit And Posltlve Power-up Feature" flled Aprll 6, 1981 by R. T. Elms, G. F. Saletta, and B, J. Mercler;
Canadlan 5erial No. 374,776, "Circuit Interrupter Wlth Dlgital Trlp Unit And Optlcally-C:oupled Data Input/Output System" iiled April 6, 1981 by J. C. Engel, J. A. Wafer, J. T. Wllson, and R. T. Elms;
Canadian Serlal No. 374,716, "Clrcult Interrupter With Energy Management Functions" flled April 6, 1981 by J. T. Wilson, J. A. Wafer, and J. C. Engel;
Canadlan Serlal No. 374,735, "Circult Interrupter With Dlgltal Trip Unit And Style Deslgnator Clrouit" ~iled April 6, 1981 by J. J. Matsko, E. W. Lange, J. C. Engel, and B. J. Mercier;
Canadian Serlal No. 374,742, "Circuit Interrupter With i4~919

2 49,013 Overtemperature Trip Device" filed April 6, 1981 by J. J. Matsko, and J. A. Wafer;
Canadian Serial No. 374,754, "Circuit Interrupter With Digital Trip Unit And Means To Enter Trip Settings"
filed APril 6, 1981 by R. T. Elms, J. C. Engel, B. J.
Mercier, G. F. Saletta, and J. T. Wil~on;
Canadian Serial No. 374,792, 1Circuit Interrupter With Digital Trip Unit And Power Supply" filed April 6, 1981 by J. C. Engel, J. A. Wafer, R. T. Elms, and G. F. Saletta;
Canadian Serial No. 374,771, "Circuit Interrupter With Remote Indicator And Power Supply~' filed April 6, 1981 by J. C. Engel, J. A. Wafer, ~. J. Mercier, and J. J. Matsko;
Canadian Serial No. 374,724, "Circuit Interrupter With Digital Trip Unit And Automatic Reset" filed April 6, 1981 by B. J. Mercier and J. C. Engel; and Canadian Serial No. 374,748, "Circuit Interrupter With Digltal Trip Unit And Potentiometers For Parameter Entry" filed April 6, 1981 by J. C. Engel, B. J. Mer-cier, and R. T. Elms.
BACKGROUND OF THE INVENTION
Field of the Invention:
The in~ention relates to circuit interrupters having means for electronlcally analyzlng the electrical condltlons on the clrcuit belng protected and for auto-matlcally opening to interrupt the current flow whenever electrical conditions exceed predetermined limits.
Descrlption of the Prior Art:
Clrcuit breakers are widely used ln industrial and commercial applications ~or protecting electrical conductor~ and apparatus connected thereto from damage due : to excessive current flow. Although initially used as direct replacements for fuses, circuit breakers were gradually called upon to provide more sophisticated types of protection other than merely interruptlng the circuit when the current flow exceeded a certain level. More elaborate time-current trip characteristics were required such that ~ 49~9

3 49,013 a circuit breaker would rapidly open upon very high over-load conditions but would delay interruption upon detec-tion of lower overload currents, the delay time being roughly inversely proportional to the degree of overload.
Additionally, circuit breakers were called upon to inter-rupt upon the detection of ground fault currents. As the complexity of electrical distribution circuits increased, the control portions of circuit breakers were intercon-nected to provide selectivity and coordination. This allowed the designer to specify the order in which the various circuit breakers would interrupt under specified fault conditions.
During the late 1960's, solid state electronic control circuits were developed for use in high power low voltage circuit breakers. Thes~ control circuits per-formed functions such as instantaneous and delayed trip-ping which were traditionally achieved by magnetic and thermal means. The improved accuracy and flexibility of the solid state electronic contro~s resulted in their wide-spread acceptance, even though the electronic control circuits were more expensive than their mechanical coun-terparts.
The earliest electronic control circuit designs utilized discrete components such as transistors, resist-Z5 ors, and capacitors. More recent designs have includedintegrated circuits which have provided improved product performance at a slightly reduced cost.
As the cost of energy continues its rapid rise, there is increasing interest in effectively controlling 3o the usage of electrical energy through the design of more sophisticated electrical distribution circuits. There-fore, there is required a circuit breaker providing a more complex analysis of electrical conditions on the circuit being protected and even greater capability for coordina-tion with other breakers As always, it is extremelydesirable to provide this capability at the sa~e or lower cost.
In addition, it would be desirable to provide a

4 49,013 real-time sequentlal display of the numeric value of electrical conditions on the circuit being protected and the limit value settings which define the tlme current trip characteristics of the breaker. Another desired feature would be the ability to test circuit breaker with any desired value of simulated phaæe or ground current while ~imultaneously providing protection for the associ-ated circuit.
SUMMARY OF THE INVENTION
In accordance with the principles of the present invention, there is pro~ided a circuit interrupter having interrupter mean3 for conducting current flow through an associated electrical circuit and ~or operating to inter-rupt current flow therethrough upon command, sensing means for sensing current flow through the interrupting means, display means for displaying numeric quantities, a plur-ality of light emitting indicator members, and a trip unit connected between the interrupter means and the sensing means. The trip unit operates the interrupter means when current flow through the interrupter means exceeds a predetermined time-current trip characteristic. The trip unit also generates numeric quantities representing elec-trical parameters of the associated clrcuit and limit value parameters deflning the time-current trip character-istic, sequentially presents a series o~ numeric quanti-ties to the display device, and individually energizes the light emittlng lndicator members in a sequence corresponding to the ~equence of the numeric quantity presentatlon, thereby identifylng the parameter whose numerlc value is being displayed.
The apparatu~ also includes means for initiating a slmulated fault current and mean~ for specifying the value of the simulated ~ault current. me trip unit then compares the simulated fault current value to the time-~5 current trip characteristic and simulates a tripping oper-ation according to the time-current trip characteristic.
m e test ~unction can proceed ~imultaneously wlth normal limit value checks on the electrical conditions of the circuit being protected, thereby insuring that the protec-i .. . .
, ~

~4~9 49,013 tive function of the apparatus remains operable during thetest.
The apparatus also lncludes a display device to provide a real time display of the operator selected ~alue of simulated fault current. Also provided is a switch to selectively disable the interrupting means, when desired, to permit an indication of a simulated tripping operation without resulting in an actual operation of the interrupter means.

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~ : , 49,001; 49,0~2; 49,004; 49,006; 49,009; 49,010; 49,013;
49,048; 49,049; 49,050 BRIEF DESCRIPTION OF THE_D~AWINGS
Figure 1 is a perspective view of a circuit breaker embodying the principles of the present invention;
Fig. 2 is a functional block diagram of the circuit breaker of Fig. l;
Fig. 3 is a block diagram of a typical electri-cal distribution system utilizing circuit breakers of the type shown in Fig. l;
Fig. 4 is a graph of the time-current tripping characteristic of the circuit breaker shown in Fig. 1, plotted on a log-log scale;
Fig. 5 is a detailed frontal view of the trip unit panel of the circuit breaker of Figs. 1 and 2;
Fig. 5A is a block diagram of the microcomputer shown in Fig. 2;
Fig. 6 is a detailed schematic diagram of the panel display system of Fig. 5; and Fig. 7 is a detailed schematic diagram of the parameter input system of Fig. 2;
Fig. 8 is a detailed schematic diagram of the A Style Number ~ e~r System of Fig. 2;
Fig. 9 is a schematic diagram of the Remote Indicator and Power Supply of Fig. 2;
Fig. 10 is a diagram of the waveforms present at various locations in the Remote Indicator and Power Supply of Fig. 9;
Fig. 11 is a block diagram of the System Power Supply shown in Fig. ~ ;
Fig. 12 is a schematic diagram of the System Power Supply shown in Fig. ll;
Fig. 13 is a diagram of the switching levels occurring at various locations in the System Power Supply of Figs. 11 and 12;
Fig. 14 is a schematic diagram of the Data Input Output System and Power Supply of Fig. 2;
Fig. 15 is a diagram of the waveforms present at , , 49,001; 49,002; 49,004; 49,006; 49,009; 49,010; 49,013;
49,048; 49,049i 49,050 various locations in the system of Fig. 14;
Fig. 16 is a schematic diagram of a power-on hardware initialization and automatic reset circuit;
Fig. 17 is a flowchart of the main instruction loop stored in read-only memory of the microcomputer shown in Fig. 2;
Fig. 18 is a flowchart of the first function of the main instruction loop shown in Fig. 17;
Fig. 19 is a flowchart of the second function of the main instruction loop shown in Fig. 17;
Fig. 20 is a flowchart of the third function of the main instruction loop shown in Fig. 17;
Fig. 21 is a flowchart of the fourth function of the main instruction loop shown in Fig. 17;
15Fig. 22 is a flowchart of the fifth function of the main instruction loop shown in Fig. 17;
Fig. 23 is a flowchart of the sixth function of the main instruction loop shown in Fig. 17;
Fig. 24 is a flowchart of the seventh function 2~ of the main instruction loop shown in Fig. 17;
Fig. 25 is a flowchart of the eighth function of the main instruction loop shown in Fig. 17;
Fig. 26 is a flowchart of the common display subroutine of Fig. 17;
25Fig. 27 is a flowchart of the trip subroutine of Fig. 17; and Fig. 28 is a flowchart of the subroutine to obtain setting values from the potentiometers of Fig. 5.
DESCRIPTION OF THE PREFERRED EMBODIMENT
I. INTRODUCTION
A. Use of a Circuit Breaker in an Electrical Power Distribut~i~on System Before explaining the operation of the present invention, it will be helpful to describe in greater detail the function of a circuit breaker in an electrical power distribution circuit. Fig. 3 shows a typical elec-.

,. . .

49,001; 49,002; 4g,004; 49,006; 49,009; 49,010; 49,013;
49,048; 49,049; 49,050 trical distribution system. A plurality of electricalloads 48 are supplied through circuit breakers 50, 52 and 54 from either of two sources of electrical energy 56 and 58. The sources 56 and 58 could be transformers connected to a high voltage electrical feeder line, a diesel-powered emergency generator, or a combination of the two. Power from the first source 56 is supplied through a first main circuit breaker 50 to a plurality of branch circuit break-ers 60-66. Similarly, power from the second source 58 may be supplied through a second main circuit breaker 52 to a second plurality of branch circuit breakers 68-74. Al-ternatively, power from either source 56 or 58 may be supplied through the tie circuit breaker 54 to the branch circuit breakers on the opposite side. Generally, the main and tie circuit breakers 50, 52 and 54 are coordin-ated so that no branch circuit is simultaneously supplied by both sources. The capacity of the main and tie circuit breakers 50, 52 and 54 is usually greater than that of any branch circuit breaker.
If a fault (abnormally large current flow) should occur at, for example, the point 76, it is desira-ble that this condition be detected by the branch circuit breaker 62 and that this breaker rapidly trip, or open, to isolate the fault from any source of electrical power.
The fault at the point 76 may be a large over-current condition caused, for example, by a short circuit between two of the phase conductors of the circuit, or an overload only slightly above the rating of the breaker caused by a stalled motor. Alternatively, it might be a ground fault caused by a breakdown of insulation on one of the conduc-tors, allowing a relatively small amount of current flow to an object at ground potential. In any case, the fault would also be detected by the main or tie breakers 50, 52 or 54 through which the load fed by branch breaker 62 is supplied at the time of the fault. However, it is desir-able that only the branch circuit breaker 62 operate to i9 49,001; 49,002; 49,004; 49,006; 49,009; 49,010; 49,013;
49,048; 49,049; 49,050 isolate the fault from the source of electrical power rather than the main or tie breakers. The reason for this is that if the main or tie circuit breaker should trip, electrical power would be lost to more than just the load attached in the branch circuit on which the fault oc-curred. It is therefore desi~able that the main and tie circuit 50, 52 and 54 breakers should have a longer delay period following detection of a fault before they initiate a tripping operation. The coordination of delay times among the main, tie and branch circuit breakers for vari-ous types of faults is a major reason for the need to provide sophisticated control in a trip unit.
B. Time-Current Tripping Characteristics:
In order to achieve the coordination between circuit breakers as described above, the time vs. current tripping characteristics of each circuit breaker must be specified. Circuit breakers have traditionally exhibited characteristics similar to that shown in Fig. 4, where both axes are plotted on a logarithmic scale. When cur-rent below the maximum continuous current rating of thebreaker is flowing, the breaker will, of course, remain closed. As current increases, however, it is desirable that at some point, for example the point 300 of Fig. 4, the breaker should trip if this overload current persists 2'i for an extended period of time. Should a current flow equal to the maximum continuous current rating as speci-fied by point 300 persist, it can be seen from Fig. 4 that the breaker will trip in approximately 60 seconds.
At slightly higher values of current, the time 3o required for the breaker to trip will be shorter. For example at 1.6 times maximum continuous current as speci-fied by point 302, the breaker will trip in about 20 seconds. The portion of the curve between the points 300 and 304 is known as the long delay, or thermal, character-3- istic of the breaker, since this characteristic was pro-vided by a bimetal element in traditional breakers. It is 49,001; 49,002; 49,004; 49,006; 49,009; 49,010; 49,013;
49,048; 49,049; 49,050 desirable that both the current level at which the long delay portion begins and the trip time required for any point on that portion be adjustable. These parameters are known as long delay pick-up and long delay time, respec-A 5 tively, and are indicated by the arrows 306 and 3~.3~9, At very high ov~rcurrent levels, for example 12 times the maximum continuous current and above, it is desirable that the circuit breaker trip as rapidly as possible. This point 312 on the curve is known as the "instantaneous'~ or magnetic, trip level~ since traditional breakers employed an electromagnet in series with the contacts to provide the most rapid response. The instan-taneous pick-up level is usually adjustable, as indicated by the arrow 314.
To aid in coordinating breakers within a dis-tribution system, modern circuit breakers have added a short delay trip characteristic 316 between the long delay and instantaneous portions. The present invention allows adjustment of both the short delay pick-up level and the 2~ short delay trip time as indicated by the arrows 318 and 320.
Under certain conditions it is desirable that the trip time over the short delay portion also vary inversely with the square of the current. This is known as an I2t characteristic and is indicated in Fig. 4 by the broken line 310.
II. PHYSICAL AND OPERATIONAL DESCRIPTION
A. Circuit Breaker Reference may now be had to the drawings, in 3~ which like reference characters refer to corresponding components. A perspective view and a functional block diagram of a molded case circuit breaker 10 employing the principles of the present invention is shown in Figs. 1 and 2, respectively. Although the circuit interrupter 10 is a three-pole circuit breaker for use on a three-phase electrical circuit, the invention is, of course, not so 11 49,013 limited and could be used on a single-phase circuit or another type Or multiphase clrcuit. A power ~ource such as a transformer or switchboard bus is connected to input terminals 12 and an electrical load is connected to output terminals 14. Intern~l conductors 16 connected to the terminals 12 and 14 are al~o connected to interrupt$ng contacts 18 which serve to selectively open and clo~e an electrical circuit through the clrcuit breaker. The contacts 18 are mechanically operated by a mechanism 20 whlch regponds to manually or automatically-initiated command~ to open or close the contacts 18.
Current transformers 24 surround each of the inte~nal phase conductors 16 to detect the level of cur-rent nOw through the conductors 16. me output signal ~rom the current transformers 24 18 supplied to a trip unit 26, along with the output signal rrom a current transiormer 28 which detects the level of ground fault current n owing ln the clrcuit. The trlp unit 26 con-stantly monitors the le~el of phase and ground fault currents flowing in the clrcult to which the breaker 10 is connected and initlates a command signal to a trlp coll 22 which actuates the mechanlsm 20 to open the contacts 18 whene~er electrlcal conditlons on the clrcuit belng pro-tected exceed predetermlned lim~ts stored ln the trlp t~n~t 26. Durlng normal cond~tions, the mechanism 20 can be commanded to open and closo the contacts ~8 through man-ually-initiated commands applled through the manual con-trols 32, Re~erring to Fig. 1, lt,can be seen that the clrcult breaker 10 lnclude~ a molded in~ulatlng houslng 34. The te d nals 12 and 14 are on the rear o~ the hous-lng 34 and are thus not shown ln Fig. 1. A handle 36 ls mounted on the ~,ight-hand side o~ the housing 34 to allow an operator to manually charge a spring (not shown) in the mechanlsm 20. The manual controls 32 are positioned in :
, ~ , , , $ ~ 19 49,001; 49,002; 49,004; 49,006; 49,009; 49,010; 49,013;
49,048; 49,049; 49,050 the center of the housing 34. Windows 38 and 40 indicate the state of charge of the spring and the position of the contacts 18, respectively. A push-button 42 allows an operator to cause an internal electric motor to mechanic-ally charge the spring in the same manner as the manualcharging operation which can be performed by the handle 36. A pushbutton 44 allows an operator to cause the spring to operate the mechanism 20 to close the contacts 18. Similarly, a pushbutton 46 allows an operator to cause the spring and mechanism 20 to open the contacts 18.
B. Trip Unit 1. Front Panel The panel of the trip unit 26 is positioned on the left side of the housing 34 as can be seen in Fig. 1.
This panel, shown in more detail in Fig. 5, includes a plurality of indicator lights, potentiometers, numeric display devices, and switches, to permit an operator to observe the electrical parameters on the circuit being ~ protected~ the limit values ~hi~h-ere presently e~t ~ din the trip unit, and to enter new limit values if so de-sired.
A rating plug 78 is inserted into the front panel of the trip unit 26 to specify the maxlmum contin-uous current to be allowed in the circuit being protected by the circuit breaker. This may be less than the actual capacity of the circuit breaker, which is known as the frame size. For example, the frame size for the circuit breaker may be 1,600 amperes; however, when the breaker is initially installed the circuit being protected may need 3 to supply only 1,000 amperes of electrical current.
Therefore, a rating plug may be inserted in the trip unit to ensure that the maximum continuous current allowed by the circuit breaker will be only 1,000 amperes even though the circuit breaker itself is capable of safely carrying 1,600 amperes.
An auxiliary AC power receptacle 132 is located -~ 114~ 19 49,001; 49,002; 49,0~4; 49,006; 49,009; 49,010; 49,013;
49,048; 49,049; 49,050 at the upper right of the trip unit panel, as seen in Fig.

5. This socket is used to supply auxiliary alternating current operating power (separate from the electrical circuit being protected) to the circuitry of the trip unit. The operation of t:his auxiliary AC power supply will be described more completely in section III.E.
2. Block Diagram Referring to Fig. 2, it can be seen that the trip coil 22 is supplied with power through a conductor 136 from the power supply 144. The flow of current through the trip coil is controlled by a non-latching switching device such as a switching field effect tran-sistor 192 actuated by the main trip unit circuitry. The use of a non-latching switch device instead of an SCR or A ,5 other type of latching device as used/the prior art pro-vides greater noise immunity.
In addition, the circuit breaker 10 includes three parallel-connected normally-open thermally activated switches 141 connected in parallel with FET 192. These switches are physically mounted on the conductors 16 in proximity to the contacts 18, with one switch mounted on each phase conductor 16./~/
Each switch Jcomprises a bimetal element which closes the switch contacts when the temperature of the associated conductor rises to 150C and resets when the conductor temperature falls below 130C. Although a bimetallic switch is employed in the disclosed embodimen~, other types of thermally activated switches such as ther-mistors could be mounted on the conductor. Alternatively, radiation sensors could be used. Infrared detectors could monitor the heat generated on the contacts or~onductors, while ultraviolet or RF detectors could sense radiation generated by arcing contacts or terminals.
The switches 141 serve to directly energize the trip coil 22 upon high temperature~c~ornditions. In addi-tion, the hardware interrupt line/of the microcomputer is 4~919 14 49,013 connected throu~h the tr~p coil 22 to the high side of the sw1tches 141 to signal the microcomputer 154 that a trip operation has occurred. mis causes execution of appropriate ln~tructions in internal read-only memory (ROM) of the micro-computer 154 to generate output data to a remote indicator 145. Since the mechanism 20 requires somewhat more than 30 ms. to open the contacts following a trip command, power 18 available for trip un~t 26 to execute 2 complete operation cycles of the main loop program even if no external power i~
supplied. Alternatively, the switcheg 141 could be wired solely to the microcomputer 154 to allow it to initiate the trip operation and genera~e output data in the same manner as an o~ercurrent trip.
Informatlon concernlng electrical parameters on the circult is provided by the three phase current trans-formers 24, each oi which monitors current flow through the individual phase conductors of the circuit. me transformer 28 surrounds the three phase conductors of the clrcult and detects currents whlch n ow outward from a source through the phase conductors and then return through unauthor1zed paths through ground, commonly known a~ ground fault currents.
The slgnals from the current transformers 24 are ~upplied to a rectifier and auctloneering clrcuit 142 whlch provldes a DC current proportlonal to the hlghe~t instantaneous AC current on any of the three phases. me clrcuit 142 provide~ normal operating power for the trip unit through a power supply 144. me transformers 24 and 28 act as current source~ and are limited to supply power to the circuit 142 at approxlmately 40 ~olts. This ls converted by the power supply 144 to three operatlng ~oltage~: a 1.67 ~olt reference voltage labelled VREF, a 5 ~olt operating ~oltage for the microcomputer and as~o-ciated circultry of the trlp unit, and a 40 volt supply which operates the trip coll 22. Information from the rectifler and auctloneering circult 142 which is propor-tional to the present value of phase current i~ also ., 4<~919 15 49,013 supplled to the peak detector 160 of the main trip unit circuitry as indicated in Flg. 2.
The ælgnal ~rom the ground transformer 28 ls supplied to a rectlfier clrcult 146 which provldes an alternate source o~ operating power for the trlp unlt through the power supply 144, and also supplles informa-tlon proportional to the present value of ground current to the peak detector 162 of the trip unlt circultry. An external DC source 148 of operatlng power on the order of about 40 volts may also be supplled to the power supply 144, as may be an external AC source 150 of operating power ~upplied through the trip unlt front panel socket 132 to a rectirier 152 and then to the power supply 144.
The main trlp unit circuitry includes an lnform-atlon processor and sequence controller 154 which may be, ~or example, a type 8048 mlcrocomputer obtainable ln commerc~al quantitles ~rom the Intel Corporation. A block diagram of the controller 154 i5 shown in Fig. 5A; however, a detalled descrlption o~ the 8048 microcomputer may be obtalned from the MCS-48 Microcomputer User's Manual, published by the Intel Corporatlon.
An analog-to-digltal converter 156 such as the type ADC3084 obtainable ln commerclal quantitles from the National Semiconductor Corporatlon is connected ~ the data bus 172 of the microcomputer 154. Any o~ eight ln-puts to the analog-to-dlgital ¢onverter (ADC) 156 are ~e-lected through a multiplexer 158 such as the type CD4051B
according to an addres~ supplled by the microcomputer vla port 1 to the multlplexer 158. These inputs include peak detectors 160 and 162 for phase and ground current values, an averaglng c1rcult 164 for average phase current, a palr of mlltlplexers 166 and 168 for readlng panel swltches and potentiometers addressed and selected by the mlcrocomputer via port 2, and four llnes from a Style Number Deslgnator clrcult 170. me designator clrcult 170 allows manufac-turlng personnel to provlde the microcomputer 154 wlth ;.
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1:~49919 49,001; 49,002; 49,004; 49,006; 49,009; 49,010; 49,013;
49,048; 49,049; 49,050 information concerning the optional features and modes, such as ground fault detection and serial I/O capability, with which the specific trip unit will be supplied. Use of such a designator circuit allows a single microcomputer configuration to ~e provided for a plurality of different models of the trip unit 26.
Also connected to the microcomputer data bus 172 is an external read-only memory (~OM) 151 and a data in-put/output system 174 which allows the trip unit to inter-act with other components and circuit breakers of theelectrical distribution system. Power for the data input/
output system is provided by a separate power supply 176 derived from the five-volt bus of the power supply 144.
As will be more completely described in a later section, the data input/output power supply 176 is a pulse-type power supply activated by a line 178 connected to port 1 of the microcomputer 154.
Input to the microcomputer 154 from the limit value potentiometers and switches of the trip unit panel, shown in Fig. 2, is supplied through multiplexers 166 and 168 to multiplexer 158. Output information to the panel display system/including the LED's 84-100 and numeric dis-play indicators 80 and 82 is supplied from the micropro-cessor 154 through port 2. Port 2 also supplies address and SELECT information to the multiplexers 166 and 168.
Port 1 of the microcomputer 154 provides a plurality of functions. Control of the ADC 156 is pro-vided by a line 180 from port 1 to a switchin~ ~ ansistor 182 which varies the reference voltage/to the ADC. Input 3~ to the ADC 156 from the multiplexer 158 is controlled through a line 184 from port l to a switching transistor 186 to selectively ground the multiplexer output to the ADC 156 under control of the program of the microcomputer 154 as will be described hereinafter. Grounding of the 3, multiplexer 158 output while either of the peak detectors 160 and 162 are selected causes a reset of the peak detec-49,001; 4~,002; 49,00l~ 9 006; 49,009; 49,010; 49,013;
49,04~; 49,049; ~9,050 tors.
~ ddress in~ormation allo~ing the mu~-tiplexer 158 to select from its various inpl~t sources 160, 162, 164, 166, 168 or 170 is provided from port 1 of the micro-computer through address lines 1~8.
Control of the trip coil 22 is provided from the microcomputer 154 through port 1 and a TRIP line 190.
Thus, when it is deter~ined that a tripping operation is called for the rnicrocomputer 154 sends, through port 1, a signal on the trip line 190 cau~sing the switching tran-sistor 192 to energize the tr~p coil 2Z, activate the rnechanism ~0 and separate the contacts 18.
3. erational Modes J~lode 1: Lo~ Power This mode is performed under conditions of ~ery low current flow throu~h the hreaker (less than 25% of frame rating), "hen external power is not being supplied to the trip unit. Unf~er these conditions sufficlent operating power cannot be con~inuously supplied to the trip unit~ ~nd ,ome of its noImal fImctions canno-t be rellably performetl. Therefore, the power supply generates a pulse of o~frating pol~rer t~ thc trip unit circuitry sufficient to e~t?cute the norInlll oper~ting c~cle of the trip unit ~)ut to (lis~lc1y only tht? present phase current through t~le breiIke~r on the numerlc 1isp]ay 80. This value i-. flash~?d hy the display at a ratt~ which increases as load currerIt increasf?s. At; ]oad urrent values above 25%
of frame rating, I~Iode 2 operation is performed. Fractions of ratin~r values ~lill hereinafttr be infdicated by ~er unit notation; e.g. ~59' ~ .25 PU.
~ode ~
1'~1iS MOdf' of operation is per~orrned when load current is greater than .25 PU of fraMe rating but less than 1.0 PU of the rating plug value, or when e~ternal power is being supplied to the trip unit.
As can be seen ln Fig. 5, the t;rip unit panel contains a n~mber of ad~ustment potentiorneters, light-emitting diode indicators (L~D's), pushbutton switches, ,, ~ 9 49,001; 49,002; 49,004; 49,006; 49,009; 49,010; 49,013;
49,048; 49,049; 49,050 and two-position switches. The panel also includes a pair of numeric display indicators 80 and 82. The electronic circuitry internal to the trip unit causes the numeric display indicators 80 and 82 to sequentially display the present value of electrical conditions on the circuit being protected and the various limit se~tings defining the time-current trip curve of the breaker as currently set. The LED's, when lighted, indicate by the legends associated with each indicator, what value is being dis-played at any time by the numeric displays 80 and 82. Ifso desired, the numeric values displayed on the numeric indicators 80 and 82 may also be sent to a remote locati~ofn, via the SERIAL OUT terminal of the Data I/O System 174 Beginning at the top of the trip unit panel as shown in Fig. 5, the LED indicator 84 is labeled PHASE
CURRENT on the left and GROUND CURRENT on the right. When this LED is lighted, it indicates that the present per unit value of current flowing in the three-phase circuit being protected is displayed in the left-hand numeric dis-play indicator 80, and the present per unit value ofground current on the circuit bein8 protected is indicated in the right-hand digital display indicator 82. In a similar manner, the LED 86 is labeled PEAK KW SETTING and PEAK KW SINCE LAST RESET. When this LED is lighted, the value appearing in the left-hand numeric display 80 is that value of kilowatts delivered by the circuit being protected which will cause a DEMAND signal to be generated by the data input/output system. The peak value of kilo-watts drawn through the breaker since the display was last reset (by the pushbutton ~ immediately to the right) is presented on the numeric display indicator 82. The LED's 88 and -~ correspondingly indicate PRESENT KW and MW x HOURS, and power factor multiplied by line voltage as follows:

~i4~919 19 49,013 PRESENT KW = presentphase cu~rent x (powerfactor x line voltage) aæ entered by operator on ~ront panel actual megawatt-houræ = (MW x HOURS) x frame rating In this manner, a user can more readlly perform energy management for his ~ystem. Not only is a continu-OU8 display of present demand, peak demand, and total energy usage provided, but in add~tlon, alarming or auto-matic load sheddlng may be initiated by the output signal provided through the data I/O system in response to the PEAK KW monitoring function.
If desired, a potential transformer could be added to the circuit breaker 10 to monitor line voltage and eliminate the need for manual operator entry of a value f line voltage Furthermore, a hlgh-spaed A/D aonverter could be added to sample line voltage and phase current at a high enough rate to permit direct calculation of power factor and eliminate the need for an operator to enter the power ~actor.
Below the rating plug 78 in Flg. 5 can be seen a number of LED's labelled INSTANTANEOUS, LONG DELAY, SHORT DELAY, and GROUND FAULT. To the left of this series o~ LED's is the legend CURRENT PICK-UP and to the right i8 the legend TIME
IN. When the LED 92 labelled INSTANTANEOUS i8 lighted, thl~ indicates that the value of current which wlll re~ult in an instantaneous trip 18 pre~ently being dlsplayed in the left-hand dlgital dlsplay indicator 80. By deflni-tlon, the in3tantaneous trip will occur immedlately, thus there 18 no correspondlng tlme to be dlsplayed, and the display 82 18 blank. When the LED 94 labelled LONG DELAY
is l~ghted, this indlcate~ that the left-hand numeric dlsplay indlcator 80 18 pre~ently showing the current value at which a long-delay trlpping operation will be lnitiated, while the right-hand numeric display indicator 82 is show ng the time parameter in seconds of a long delay tripping operatlon. These tlme and current values .

49,001; 49,002; 49,004; 49,006; 49,009; 49,010; 49,013;
49,048; 49,049; 49,050 correspond to the long delay tripping operation discussed above with regard to the time-current tripping curve of the circuit breaker.
When the LED 96 labeled SHORT DELAY is lighted, 5 the left-hand numeric display indicator 80 is showing the current value which will cause a short delay tripping operation to be initiated, while the right-hand numeric display indicator 82 is showing the duration, in cycles, of a short delay tripping operation. Similarly, when the LED g8 labeled GROUND FAULT is lighted, the left-hand numeric display 80 will show the value of ground current which will cause a ground fault tripping operation and the right-hand digital display 82 will show the number of cycles between the detection of the ground fault current and the command to cause the circuit breaker to trip.
As can be seen in Fig. 5, some of the legends have a solid circular symbol associated therewith, while other legends are associated with a solid square symbol.
The circular symbols indicate that the parameter desig-nated by the associated legend will be displayed as a /muftiple of frame rating. Similarly, those parametersassociated with a square symbol will be displayed afil mPul t-iples of ~ rating. For example, assume the displays 80 and 82 were presenting values of 0.61 and 0.003, respec-tively, and the LED indicator 84 is lighted. This repre-sents a present phase current of 976 amperes (0.61 x frame rating = 0.61 x 1600 amps = 976) and a present ground current of 3.6 amperes (0.003 x plug rating = 0.003 x 1200 amps = 3.6 amps).
3~ A pair of miniature switches 102 and 104 labeled I2T RESPONSE are used to vary the shape of the time-current tripping curve in the short delay and ground fault areas, respectively. When the switches 102 and 104 are in the lower position, this indicates the Ground Fault and Short Delay portions of the curve will not exhibit an I2T
slope, but will instead be horizontal. When the switches l9 49,001; 49,002; 49,004; 49,006; 49,009; 49,010; 49,013;
49,048; 49,049; 49,050 102 and 104 are in the upper position, the I2T character-istic will be employed, and the characteristic for the Short Delay tripping operation will have the shape as shown in Fig. 4.
A potential transformer connected to the asso-ciated circuit could be used to otain line voltage data, and rapid sampling and direct multiplication o~ the in-stantaneous values of phase current and line voltage used to calculate real power. However, the disclosed method provides a convenient and cost-effective method which avoids isolation problems associated with potential trans-formers.
Summarizing, in normal operation, the following ~ operations will be ~r~ ~ ~ sequentially, with the entire /sequencé repeated 60 times per second: peak KW, MW-HR
integration, instantaneous trip, long delay trip, short delay trip, and ground fault trip.
In addition the following values will be ~
~ye~ sequentially in pairs, with each dise~y lasting 4 seconds: PRESENT PHASE CURRENT - PRESENT GROUND CURRENT, PEAK KW setting (demand) - PEAK KW SINCE RESET, PRESENT
KW - MWHR, POWER FACTOR x LINE VOLTAGE, INSTANTANEOUS
PICKUP - TIME, LONG DELAY PICKUP - TIME, SHORT DELAY
PICKUP - TIME, AND GROUND FAULT PICKUP - TIME.
Mode 3: Overcurrent and Trip Mode Ihis mode is performed when either phase current is above the Long Delay Pickup value or ground current is above the Ground Current Plckup value. Sequencing of display values and LED indication thereof continues as in Mode 2 even though the breaker is overloaded. In addi-tion, the Long Delay Pickup LED 9~l will be lighted.
If the overcurrent or ground fault condition persists, the trip unit will initiate a tripping operation according to the time-current trip characteristic loaded therein by the user. When tripping occurs, the function which initiated the trip (long delay, short delay, instan-~9 49,001; 49,()02; 49,004; 49to06; 49,009; 49,010; 49,013;
49,048; 49,049; 49,050 taneous, or ground fault) will be indicated on the frontpanel by energization of the appropriate LED 92, 94, 96, or 98. The cause-of-trip info~nation will be sent out by the data I/0 system to the remote indlcator 145, In addi-tion, the per unit phase or ground ~ault current thatcaused the trip will be dlsplayed and frozen on the numer-ic display 80.
In addition to the rnicrocomputer trip capabili-ty, the trip circuit breaker includes the thermal switches 141 as a back-up system. Shou~d this system initiate a trip operation, the lnstantaneous LED 92 will be lighted, a value of 15.93 PU current value will be displayed on the numeric display 80, and an INSTANTANEOUS signal sent by the data I/0 system.
Mode 4: Parameter Ad,iustment AS can ~e seen in Fig~ 5, the trip unit panel also include,s a plurality of limit value potentiometers associated ~ith the various legends on the trip unit panel. These potentiometers are provided to allow an ?0 operator to adjust the circuitry of the trip unit to vary the shape of the ~ime-current trip curve and produce the type ol tripping characteristics required by the design of the entire electrical distribution system. ~en an op~rator atl,justs one of the potentioTneters, (for example, ~5 the INsrr~iTAN~OUS C~RENl' PICK-UP potentiometer 112) thls adjustm-nt is d~tected by the -trip unit circuitry and the sequential display o~ values ls 1nterrupted. The parameter value beirlg adjusted is immediately displayed in the correspon(ling n-lmeric di~play indicator, and the correspond-ing LED indicator is lighted, ~`or e~.alnple, lf it ls desiredto ~dJust the inst.~taneou~ current pick-up value, an operator in~eIts a screwdriver or other -tool into the potentlometer 112 and beglns to turn it. Irnmedlately, the INSTA~T~IOI)S LED indicator 92 llghts ~ld the prescnt value of the inst.~ntaneous current pick-up i~ displ~yed in the numeric display indicator ~0. This number is in pcr unit format, tha-t is, a rnultiplier , j ,, .
49,001; 49,002; 49,004; 49,006; 49,009; 49,010; 49,013;
49,048; 4g,049; 4g,050 times the frame rating, as specified by the solid round symbol. Thus, as the potentiometer 112 is rotated, the value displayed in the indicator 80 would begin to slowl~
increase in discrete steps from, for example, 1.00 up to the maximum allowable value as stored internally in the trip unit, which is 10Ø When the desired value is achieved, adjustment of the potentiometer is ceased and the trip unit resumes its sequential scan and display of present values and settings. In a similar manner, any of 1~ the potentiometers on the trip unit front panel may be ad-justed to achieve the desired parameter setting.
In the past, adjustment of parameter values using potentiometers in conjunction with digital circuitry has presented problems. There was a tendency, for exam-ple, for each minute change in the value of a potentio-meter~to produce a different value which would be immedi-ately displayed. This produced an annoyingly rapid varia-tion of the display which rendered adjustment difficult.
Furthermore, temperature variations and other minor per-turbations in the circuitry would cause variation in the display and value of the potentiometer even when no ad-justment was being made. In addition, failure of the potentiometer in the past would sometimes prevent the designated parameter from being read at all.
ln order to avoid these problems, the present invention employs the potentiometers to select one of eight predetermined parameter values stored within ROM of the trip unit microcomputer. Thus, the potentiometer acts as a discrete multiposition switch rather than a continu-ously variable adjustment device. In the event of a potentiometer failure, the trip unit selects the most conservative value of the parameter associated with the malfunctioning potentiometer for use in its monitoring functions.
To add further convenience to an adjustment operation, the trip unit includes a hysteresis feature ~ ~ ~$ ~19 49,001; 49,002; 49,00~; 4~,006; 49,009; 49,010; 49,013;
4~,048; 49,049; 49,0S0 which is describ~d in detail in Section III.C.
Parameters may also be entered by an external ,~ circuit over the SERIAL IN terminal~of ~hé Jdata I/O system '~ 174.
Mode 5: Test Mode A TEST mode is also provided in the trip unit herein disclosed. By pressing either of the\pushbutYton switches 128 or 130, an overcurrent condition or ground-fault condition, respectively, may be simulated. If the switch 106 is in the NO TRIP position~ the fault current value to be simulated is determined by the adjustment of the potentiometer 120 while either of the switches 128 or 130 are depressed. With the switch 106 in the TRIP posi-tion, fixed values of fault current are simulated. This simulated overcurrent or ground-fault condition will or will not result in actual opening of the contacts/o~ the circuit breaker, as determined by the setting of the TRIP/NO TRIP switch 106. In either case, the test is initiated upon release of the pushbuttons 128 or 130, causing the TEST MODE LED 100 to be lighted~ ~hen the delay period expires, the appropriate LED 92, ~, or 96 will light, thus indicating the successful completion of the test. If the switch 106 has been set to the TRIP //
position, the contacts of the circuit breaker will al~e Y
open.
Through the use of the TEST mode with the switch 106 in the NO TRIP position, an operator can check any desired point on the time-current tripping characteristic.
He does this by pressing the desired test button 128 or 130, and dialing in, on the TEST potentiometer 120, any desired multiple of the maximum continuous current. He then releases the desired phase or ground fault test button 128 or 130. The trip unit will simulate a fault at that level of the multiple of maximum continuous current which was entered via TEST potentiometer 120, and will simulate a tripping operation without actually opening the ,~ ~14g9~9 25 49,0~3 contact~.
At the completion of the test, LED 92, 94, 96 or 98 will be lighted to indicate whether the breaker tripped under instantaneous, long delay, short delay, or ground iault modes. me display 80 will show the per unit cur-rent value at which the breaker tripped (whlch will be the same as the value entered via potentiometer 120) and display 82 will ~how the number of seconds or cycles (whlch i8 spèci~ied by LED'~ 92, 94, 96 or 98) iollowing initlatlon of the test in which the breaker tripped.
Durlng execution Or a test, a determination is made as to which is larger: actual phase (or ground) current or ~imulated phase (or ground) current, and the larger o~ the two compared to the varlous setting values, mus, a test can take place with no loss or protection.
Furthermore, ii simulated current is larger than actual current, but both are larger than Long Delay Pick-Up, a trlp operatlon will be performed at the end oi the test, regardless o~ the positlon oi the TRIP/NO TRIP swltch 106.
The operator can then plot the tlme-current value dl~played to see li thls polnt lle~ on the deslred tlme-current trlpplng characterl~tlc curve. Any number of polnto can be ~o te~ted, allowlng complete verl~lcatlon of the trlpplng characterlstlc as entered ln the trlp unlt.
C. Remote Indlcator And Power SUD~1Y
A remote lndlcator and power supply 145 may also be connected to the trlp unlt 26. Thls devlce, shown schematlcally in Flg. 9, provldes the capablllty of in-dlcating at a locatlon remote ~rom the clrcuit breaker 10 when the breaker has trlpped and what caused the trlp.
In additlon, the devlce 145 can lndlcate when peak power demand ha~ exceeded a pre~et llmlt. mese indlcatlons are provlded by four LEnl~ correspondlng to PEAK KW DEMAND
EXCEEDED, OVERCURRENT TRIP (long delay), SHORT CIRCUIT TRIP
(lnstantaneou~, short delay, or thermal), and aROUND FAULT
TRIP.
Two relays are also provided ln the remote lndl-,:, ~ .

:: :

49,001; 49,0Q2; 49,004; 49,006; 49,009; 49,010; 49,013;
4~,048; 49,049; 49,050 cator 145. One relay is actuated on receipt of a peak KW
demand indication, to provide the capability of automatic load shedding. The other relay is actuated on receipt of any type of trip indication to trigger an alar~ bell, 5 light, or other desired function.
The device 145 also includes a power supply energized from the AC line which provides 32 volts DC.
The output of this power supply is connected to the EXTER-NAL DC terminal 148 of Fig. 2.
A detailed description of the circuitry of the remote indicator and power supply is contained in Section III.E.
III. ELECTRICAL DESCRIPTION
A. Arithmetic, Logic, and Control Processor The arithmetic, logic, and control processor 154 is a type 8048 microcomputer manufactured by the INTEL
Corporation. As seen in Fig. 5A, the single 40-pin pack-age includes the following functions: an eight-bit arith-metic logic unit~, a3 control unit, a lX x eight-bit ROM
2n program memory ~5~,' 64 x eight-bit RAM data memory 157, an eight-bit bi-directional data bus 172, and two quasi bi-directional eight-bit ports Port 1 and Port 2. Addi-tional control lines are also provided. A more detailed description may be obtained from the previously referenced 2~, MCS-4~ Microcomputer Users Manual. Referring to the figures, and especially Figure 2, the interconnections to the microcomputer 154 will now be described.
The eight-line data bus 172 is connected to the eight output terminals of the ADC 156. The eight-bit digital values supplied by the ADC are thus read by the microcomputer 154 by the following sequence: a pulse is sent out on the WR line of the microcomputer 154 to the ADC 156, commanding the ADC to convert the analog quantity appearing at its input terminals into an eight-bit digital quantity. Upon completion of the conversion process, the ADC 156 generates a pulse over the line connected to the -` 114~919 27 49,013 T1 teæt terminal of the microcomputer. The mlcrocomputer then generates a pulse on the RD line, whlch transfers the blt pattern produeed by the ADC to the accumulator o~ the mlcrocomputer 154.
me data bus 172 i8 also connected to the data lnput/output system 174, to allow the trip unit 26 to communicate with other circ~lt breakers and with the remote indicator/power ~upply 145. me data input/output system will be more completely descrlbed in Sectlon IIIG.
Port 1 and port 2 of the microcomputer provide the eapabllity to communicate and eontrol the other compo-nentR of the trip ~t 26. me speeifie connection~ will now be de~cribed. Line numbers eorre~pond to the notation used ln the MCS-48 Microeomputer Users Manual.
Port 1:
Llne 0, line 1, llne 2--These llnes provlde the ehannel address in~ormatlon ~rom the mieroeomputer 154 to the multlplexer 158, as indieated at 188 on Flgure 2.
Llne 3--This llne, lndlea~ed at 180 in Figure 2, aetuates the FET 182 to ehange the re~erenee voltage de-ll~erod to the ADC 156, thereby inereaslng the resolution ~or the Long Delay phase eurrent measurement.
Llne 4-- mis line aetivates the tran~istor 192 to energize the trip eoll 22 and eause the meehanism 20 to open the eontaets 18 to the br~aker. Llne 4 is indieated at 190 ln Flgure 2.
Line 5--Thls line aetuates the FET 186 to ground the output o~ the multlplexer 158, whleh also grounds the lndlvld1~Al input to the multiplexer 158 whieh happen~ to be seleeted at that time. mus, aetlvating llne 5, (lndleated at 184 ln F~gure 2) ean reset the peak deteetors 160 and 162, when these are seleeted by the multlplexer 158.
Llne 6--This llne aet~vates the Chlp Seleet termlnal on the external ROM when performing a read opera-tlon.
Line 7--This line~ indicated at 178 in Figure 2, periodically energizes the power supply 176 of the data '.

,~ .

ll4c3gl9 49,001; 49,002; 49,004; 49,006; 4g,009; 49,~10; 49,013;
49,048; 49,049; 49,050 input/output system 174.
Port 2:
Line 0, Line 1, Line 2, Line 3--These lines car-ry the data sent from the microcomputer 154 to the panel display system 155. As can be seen in Figure 6, the digit values are supplied over these lines to the latch decoder 194 for display on the numeric indicators 80 and 82. Line 0, line 1, and line 2 (indicated as 207 in Figure 6 and Figure 7) also supply channel address information to multiplexers 206, 166 and 168. Line 3 (indicated as 216 in Figure 7) is connected to the INHIBIT te~minals of the multiplexers 166 and 168 and serves to toggle or selec-tively activate the multiplexers 166 and 168.
4--This line ~actuates the transistor 198 to light the decimal point on the numeric indicators 80 and 82.
Line 5--This line is connected to the Latch En-able terminal of the latch decoder 194 and serves to latch the data values appearing on lines 0 through 3 in the 2~ latch decoder 194.
Line 6--This line energizes the transistor 208 which, in conjunction with the output lines of the latch decoder 194 serves to energize the LED indicators 84 through 98.
Line 7--This line is connected to the INHIBIT
terminal of multiplexer 206 and is indicated at 212 in Figure 6. ~ ~7 The Interrupt terminal ~4~ of the microcomputer is connected to the high voltage side of the thermal 3~ switches 141. Activation of these switches thus causes the Interrupt terminal 143 to ~o LO and initiate the Interrupt instructions in ROM/whlch processes the thermal trip operation, and indicates an instantaneous display trip.
B. Panel Display System A detailed schematic diagram of the panel dis-, , 1~9919 49,001; 49,002; 49 J 004; 49,006; 49,009; 49,010; 49,013;49,048; 49,049; 49,050 play system of Fig. 2 is shown in Fig. 6. As can be seen, a seven-segment latch decoder circuit 194 such as a type CD4511B is provided. A four-bit input signal is provided by lines 0-3 of port 2 of the microcomputer 154. The de-coder circuit 194 provides a seven-line output signal through a load resistor array 196 to the pair of four digit seven-segment LED digital display indicators 80 and 82. An eighth line for activating the decimal point of the digital display indicators 80 and 82 is also provided through a transistor 198 which is actuated by a line 200 also connected to port 2 of the microcomputer 154. A
driver circuit 202 and transistor 204 are provided under control of a multiplexer circuit 206, which may be for example, a type CD4051B. A three-bit SELECT signal, also driven by three lines 207 from port 2 of the microproces-sor is supplied as input to the multiplexer circuit 206.
The LED indicators 84, 86, 88, 90, 92, 94, 96, 98 and 100 are actuated through the transistor 208 by a line from port 2 of the microcomputer 154 in conjunction with the ~o digital display indicators 80 an2d 82. The TEST LED 100 is also driven by the transistor i~ and an additional tran-sistor Z10 in conjunction with an INHIBIT line 212 also supplied to the multiplexer 206 from port 2 of the micro-computer.
C. Parameter Input Limit values for the trip unit 26 are provided by the potentiometers 108-120, as shown in Figs. 2, 5, and 7. Each of the potentiometers has one end of its resis-tance element connected to the VREF supply, and the other end of the resistance element grounded. The wiper of each potentiometer is connected to an input terminal of one of the multiplexers 166 and 168 which may be, for example, a type CD4051B. Thus, each of the potentiometers provides an analog voltage signal to its appropriate multiplexer input terminal. These input terminals are selected by a three-bit address line ~ plus an INHIBIT line 216 con-., .-' , '- ~ ', ' ' :

.' ' ~

, 49,001; 49,002; 49,004; 49,00~; 4g,009; 49,010; 49,013;
49,~48; 49,049; 49,050 nected to port 2 of the microprocessor.
The two-position switches 102, 104 and 106 correspond respectively to I T IN/OUT switches for phase current and ground current, and a TRIP/NO TRIP function for the test mode. As can be seen, these switches serve to construct a variable voltage divider between VREF and ground which provides any of six analog voltage values to a terminal of the multiplexer 168. In a similar manner, the pushbutton switches 107, 105, 128 and 130 correspond-ing respectively to DISPLAY RESET, DEMAND RESET, PHASETEST, and GROUND TEST, serve to place any of eight analog voltage signals on another terminal of the multiplexer 168.
D. Style Number Designator Figure 8 shows in detail the style number desig-nator circuit 170 shown in Fig. 8. Each four-digit deci-mal style number ee~r~p~ ~ing to a particular option combination. As can be seen in Fig. 8, the style desig-nator circuit provides input to four terminals of multi-plexer 158. Each of these terminals represents one digit of the decimal style number and may be connected to any of four positions on a voltage divider formed by the resist-ors 218, 220, and 222 connected between ground and VREF.
These connections are selected and made by jumper connec-tions wired at the factory to provide each of the termin-als of multiple~er 158 with any of four possible analog voltage signal values. The multiplexer 158, on command, then supplies these values to the ADC 156 which converts them to the 8-bit digital code which is read by the micro-computer and interpreted as the style number, allowing the microcomputer to determine which of the many option com-binations for the trip unit 26 are actually present in that particular trip unit.
E. Remote Indicator And Power Suppl~
The data input/output system 174 supplies pulse coded output signals, over a single optically coupled pair ....

14~9~9 31 49,013 of wires~ to the Remote Indicator 145 shown in Fig. 9 provlding a remote indication that the load being supplied through the clrcuit breaker has exceeded a predetermined power limit. In addition, cause-of-trip indications of o~ercurrent, short circult, or ground ~ault are provided. me circuit to be described decodes the correspondine four input slgnals to provide both LED indications and relay closures.
In additlon, the circuit provides a remote source of power, irom both the AC line and from batteries, ~-to the power supply 144. This capab$1ity is needed in those applications which require continuous retention of data such as cause-o~-trip indicators and energy functions including megawatt-hours and peak demand power.
A~ can be seen in Figure 9, lnput power i~ 9Up-plled through a transformer 602, rectifier circuit 604, and fllter capacltor 606 at a level o~ approximately 32 volts. A current limiting resl~tor 608 is provided to protect against accidental shorting of the output terminal 610. Terminal 610 is connected to the EXTERNAL DC INPUT
148 (Flgure 2) and terminal 612 is connected to the digi-tal ground terminal of the trlp unlt 26. If a ~umper 18 connected between terminal 610 and termlnal 614, the three lnternal 8-volt nlckei-cadmium batteries 616 can be acti-vated to support the output voltage at 24 volts/ should the AC input voltage be lnterrupted. A 10 K "trickle charge" re~lstor 618 i8 provided for battery charging.
An 8.2 volt power 8Upply i8 provided by resistor 620, Zener diode 622, and capacitor 624 for the decodlng and alarm circuit.
The data I/O output terminal 508 of Figure 14 labelled Remote Indlcator Out 18 connected to terminal 626 of Fl~ure 9, and the I/O COMMON terminal 500 of Figure 14 is connected to terminal 628 of Flgure 9. The 100 mlcro-second, 4 volt output pulse~ applled to terminals 626 and 628 produce an 8 mllliampere current n ow through the ~5 optical coupler 6~0. Thi8 current turns on the coupler ~ ;, , ' ' " ' ' : -, ,.. . , ~ .- ...................... .

9i9 \
49,001; 49,002; 49,004; 49,006; 49,009; 49,010; 49,013;
49,048; 49,049; 49,050 transistor which produces an 8 volt pulse across resistor 632.
The microcomputer 154 can produce one 100 micro-second pulse every two milliseconds, or a maximum of eight pulses per cycle of AC power. A coding technique is used, with one pulse out of eight denoting a DEMAND alarm. If a trip has occurred, two consecutive pulses out of eight denote a ground fault trip, three consecutive pulses out of eight denote overcurrent (long delay) trip, and five consecutive pulses out of èight denote a short circuit (either instantaneous or short delay) trip condition. The pulse coding scheme is shownlin Figure ~0. ~5 ~
The input pulses provide trigger inputs for a retriggerable 3 millisecond monostable flip-flop output Ql of integrated circuit 634 which may be, for example, an RCA CD4098 device. The retriggerable feature means that any pulse which occurs during the 3 millisecond timing interval will cause a new 3 millisecond interval to start.
Waveforms B of Figure 10 show the resulting Ql output for one, two, three, and four consecutive input pulses, corre-sponding to a DEMAND ALARM, a ground fault trip, a long delay trip, and a short circuit trip, respectively. The amplitude ~f the Ql pulses is equal to the supply voltage supplied to the integrated circuit 634. When the Ql output is averaged by resistor 636 and capacitors 638, a DC voltage C is produced whose value is the following fraction of the supply voltage:either 3/16 volts, 5/16 volts, 7/16 volts, or 11/16 volts, respectively. This value is fed to the inverting input terminals of quad f 30 comparator 640 which compare the filtered value C to fixed fractions of the supply voltage of 1/8 volts, 1/4 volts, 3/8 volts, and 9/16 volts, which are developed by the ; divider network including resistors 642, 644, 646, 648, and 650. The comparator then provides outputs which 35 indicate which of four possible pulse patterns were ap-. plied at input terminals 626 and 628. If, for example, a .
'' .: ' ' ~' ~ ~4~9i9 49,~01; 49,002; 49,004; 49,006; 49,009; 49,010; 49,013;
4g,048; 49,049; 49,050 DEMAND condition exists, producing a pulse pattern of one out of eight pulses, the DC voltage at the inverting terminal of comparator A of 640 will be 3/16 of the supply volts, which is greater than 1/8 of the supply volts but smaller than 1/4 of the supply volts. As a result, the output termi~al of comparator A will be LO while other inputs will/HIGH. Transistor 652 and relay 654 will be turned on by current flow through resistor 656 which also lights the demand LED 658.
An overcurrent trip condition will cause three consecutive pulses to appear at the input terminals 626 and 628, and an averaged value of 7/16 of the supply will appear at the inverting terminals of the comparators of 640. This value is greater than 3/8 of the supply volts but less than 5/8 of the supply volts. In this case, the output terminals of comparators A, B, and C will be LO. Transistor 660 and relay 662 will be on, because of current flow through the overcurrent LED 664 and re-sistor 666. Transistor 652 and the DEMAND LED will be off 2~ because of the shorting effect of transistor 668. The GROUND LE~ 670 is also off because of the shorting effect of the OVERCUR~ENT LED 664. In this way, the highest level comparison always dominates. A function of inte-grated circuit 672 (which may be, for example, an RCA type ~5 CD040)and Ql is to provide a 1/2 second ON delay for the comparators, which is required to allow the voltage on capacitor 638 to stabilize. The Ql pulses occur every 1/60 seconds. These are counted by counter 672 until thirty-two pulses occur and output Q6 goes HlGH. At this 3CI time, output Ql is turned on, and additional pulse inputs are inhibited by diode 674.
Approximately 30 milliseconds after the last pulse is received by optical isolator 630, the Q2 terminal of the retriggerable monostable flip-flop 634 will go HIGH. This resets the output Q6 of 672 and turns Ql off.
The function of counter 672 and Ql is to provide positive ~4g919 49,001; 499002; 49 004~ 49 oo6; 4~,009; 49 010; 49 013;
49,04~; 49,049; ~9,050 3~1 on/off operation of the LED indicators and the ALA~/LOCK-OUT and DE~ND RELAYS 662 and 654.
F. Data In~ut/Output System and Associa-ted Power Supply As hereinbefore explained, it is contemplated that a circuit breaker employing the principle~ of the present invention will be employed in an electrical dis-tribution system in coordination ~ith a nt~b~ of other c~rcuit brea~ers. It is sometimes desired that various cornmands and inforrnation be sent from this circuit breaker and that various parameters sent by other associated breakers be sensed by this breaker. This inforraation is used to construct the desired interlocking scheme as specified by the system architect or designer The Data I/O Systerrl, sho~n in detail in Fig. 14, includes four output lines: Short Delay Interlock Out 502, Ground Interloc~ Ou-t 504, Serial Out 506 and Remote Indicator Out 50~.
Three input terminals are also provided: Short Del~y Interlock In 510, Ground Interlock In 512, ~Ind Serial In 51l-~. The Serial Out and Serial In terminals are used to cornmunicate di~ltal data between the microcomputer 154 and a remo-te digital clrcuit. The Remote Indicator Out terminal provides a one~of-f`our coded pulse output for cause~of-trip indication (overcurrent, short circuit, or ground ), ~n(l peak power demand alarm indication to the Remote Indicator as describe(l ln Section III F. lhe input and output interlock terminals allow direct interlock connec-tlons be~ween breakers without any addltional cornponents.
If t~pical optical coupling circultry ~/ere used, 400 mllliwatts of power would bc required (12 mllliamperes at 5 V~ for each of' seven lines). The po~rer which the current transforrner~ 2~ are capable of supplying ls only about 500 [nilliwatts (100 rnillia~peres at 5 ~X), rnost of which is re~uired by the microcoraputer 15L-. Conventional optical couplirlg circuitry thus cannot be us~d.
The po~er supply for the data in~ut/output sys tem 174 incluAes a pulse transforraer 501 cor~ected through a translst;or 22~ -to line 7 of port 1, indicated as 17~ in 35 49,013 Figures 2 and 14. The microcomputer provides a 100 micro-second pul~e every 2000 microseconds, a~ commanded in the common display subroutine, thereby reducing the power supply requlrement of the data input/ou~put system 174 by a factor of nearly 20 to 1, or about 20 milliwatts (4 mllliamperes average at 5 VDC). Thls ls small enough to be easlly supplled from the power supply 144.
The waveforms appearing in the power supply 176 are shown ln Flgure 15. Waveform A 18 that generated on line 7 oi port 1 by the microcomputer 154. For approxi-mately 100 mlcroseconds out of about every 2000 microsec-onds (actually 1/8 x 1/60 seconds) llne 7 of port 1 i8 held low at mlcrocomputer circuit ground. This turns on transistor 228, thereby applying ~5 volts to the input of transformer 501, as seen in waverorm E~ Or Figure 15. A
corresponding waveform is produced on the output terminal Or transformer 501 relative to the system common termlnal of the data input/output system 174.
If an output 18 desired from, for example, the Remote Indlcator Out terminal 508, the corresponding microcomputer output line, line 3 o~ the data bus 172 18 held at clrcult ground, as ~hown ln waveform C in Figure 15. LED 516 i8 turned on by current $10w through transls-tor 228. The phototransistor 517 then turn~ translstor 518 on, producing output voltage ~averorm D. I$ llne 3 oî
data bus 172 (wsveform C) 18 HIGH, then the correspondlng output $rom translstor 518 i~ zero, as shown by wa~reform D.
The lnput clrcultry 18 deslgned to work wlth both a dlrectly coupled DC si~nal from an older clrcuit breaker, or a pulse lnput such as that previously described ln this section. An lnput slgnal at, $or example, the Serlal Input terminal 514 as shown in wave$orm E, wlll al~o appear at the gate o$ FET 236, a~ ~hown ln waveform F. When the pulse voltage appears at the output of pul~e transformer 501, current will nOw in L~ 238, and then through FET 236 whlch has been turned on by the lnput ' . ':

49,001; 49,002; 49,004; 49,006; 49,009; 49,010; 49,013;
49,048; 49,049; 49,050 signal at the Serial Input terminal 514. The FET 236 has a turn-on gate voltage of 2.5 volts and internal gate-to-source 15 volt Zener diode protection. This range is required to meet the 4 volt pulse input provided by a microcomputer type circuit and a 12 volt DC signal pro-vided by the older type of solid state trip unit.
- FE~ 236 provides two functions. First, it pro-vides a memory element when the input signal is a pulse.
It does this in connection with the capacitor 232 which is charged through resistor 230 by the 100 microsecond input pulse. The values of capacitor 232 and resistor 230 are chosen so as to give a 15 microsecond time constant.
Capacitor 232 discharges through resistor 234, sized to give a 10 millisecond time constant. The capacitor 232 cannot discharge through 230, since the input signal is provided by the emitter of an NPN transistor. Thus, the gate of transistor 236 is held high as long as input pulses occur every two milliseconds. Approximately lO
milliseconds after the input pulses disappear, transistor 236 will be turned off.
The second purpose of transistor 236 is current gain. The optical coupler 226 requires nearly 10 milli-amperes to turn the associated phototransistor on. This current is provided by transistor 236. The high DC input impedance at the input terminal is required, since the older trip unit control circuits can provide only a small DC input current. a~ f~ 'h~,/
j The presence or lack of an input signal~is read by the microcomputer at line 0 of the data bus, waveform G, which is high during the 100 microsecond pulse period if, and only if, an input signal is present at the termi-nal 514. A pull-down resistor ~ is provided to maintain the data bus lines connected to the data input terminals ; at circuit ground when no input signal is present at the terminal 514. In this manner, a signal from a circuit breaker, emergency power generator, or other associated -~ . -- ~''`.

1-14~919 49,001; 49,002; 4g,004; 49,006; 49,009; 49,010; 49,013;
49,048; 49,049; 4~,050 component of the electrical power distribution system can be sensed by the microcomputer 154 and the circuit breaker 10 can be commanded to perform appropriate action. Fur-thermore, parameter values can also be supplied, through the SERIAL IN terminal 514, from a remote location. Ap-propriate instructions in ROM then decode the incoming information and store it in RAM for use by the limit checking functions.
G. System Power Supply lo l. Block Diagram Description The power supply 144 of Fig. 2 is shown in block diagram form in Fig. 11. It can be powered by one of four sources: external AC or DC voltage, the Remote Indicator 145 of Fig. 2, current input from a ground current detec-tion transformer 28, or current input from the three phasecurrent measuring transformers 24.
The rectified output of the external AC source is compared to the DC voltage from the Remote Indicator and the largest instantaneous value is supplied by the auctioneer circuit 702 to the power supply's energy stor-age capacitor 704 for use by the DC-to-DC converter 706 and the trip coil 22. A voltage sensing circuit 708 monitors the output of the voltage auctioneering circuit 702. Whenever this voltage is greater thanb22 VDC the A 25 DC-to-DC converter 706 is turned ON. A/current switch 710 is thrown to position (2) when the voltage exceeds 24 VDC.
The converter 706 provides the 5 VDC supply (at 100 mA) for the microcomputer circuit, a reference voltage VREF
(1.64 VDC) and a power ON reset control signal RS.
The unit can also be powered by either the rectified output of the ground current transformer or the current auctioneered, rectified output, of the three phase current transformers 24. The two currents are summed at ~c~O~ b~v i 712 and fed to the ~e~ 710 which passes the current either into the energy storage capacitor 704 or a current cr~*~P" 714. Current flows into the capaci-. .~

~14~ 9 49,001; 49,002; 49,004; 49,006; 49,009; 49,010; 49,013;
49,048; 49,049; 49,050 i,~
tor 704 un-til the-capacitor voltage reaches about 39 V~C, at ~Ihich point the "crowbar" 710 transfers the current to the by-pass circuit 714. Current by-passing continues until the vo-tage on the capacitor 704 drops to about 34 VDC and the s~itch 710 again c~uses the current to flow into the capacitor 2. Circuit Description The power supply 144 is sho~rn in greater detail.
in Fig. 12. The external AC input is rectified by BR201 and compared to the external r~ input. The result is fed through D101 to energy storage capacitors C105 and C112.
The sensed voltage is also fed to the crowbar circult formed by the power field effect transistor Q101 and gates A c~n~i B (connected ~s inverters) of quad NAND circuit IC101. The quad NANI) circuit ls powerecl by current flow through f2103, D107, D108 and n109, which produces a ternpera-ture stabilized voltage of about 10 V~C for pin 14 of IC101D.
The quad N~D has input hysteresis ~Ihich causes the output to go ~0~l when the inputs e~ceed about 70~ of the supply X0 voltage (7 V~)C)~ The output then stays low until the inputs drop to ~~0 of the supply voltage (3 V~C). I~us the crowbar is tu~ned or~ ~rhen 7 Vr)C appears across ~105 w}lich corresponds to 24 V~)~ at the e~ternal r)C input (7 VDC plus drop across R104, R10, .-ln(l D10~). It will be noted that the cro~tbar can also ~e turn~?d ~N if thc voltage across the energy storAge capacitor 70l~ exceeds 39 ~II)C.
If e~ter~al F~ower is available~ then the on-off status of t~e converter 706 is controlled b~ the external power supply voltage, rather than the storage capacitor ~,0 volta~.
The 24 vr,c ~itching point for the external DC
lnput corresponds to the minimum r~ voltage require~ for the trip coil 22 to opcrate. The 39 VDC limit on the voltage ~cross the ener W stora~e capacltor is a compro-., 5 ~' --- 114~919 49,001; 49,002; 49,004; 49,006; 49,009; 49,010; 49,013;
49,048; 49,0~9; 49,050 mise between the 50 VDC maximum limit of the capacitor and the 30 VDC minimum input to the converter required to produce 5 VDC output at 100 mA DC with a minimum current transformer output 32 mA RMS.
Current shunts R100 and R101 are used ~o sense A phase and ground current ~ . ~t will be noted that current flow through the resistors is through either Q101 (crowbar ON) or C105 and C112 (crowbar OFF) and IC102.
The required 15 millisecond turn-off delay of the ~5 VDC supply is achieved by means of diode D110, resistor R107, and capacitor C102. When the voltage at pinc8 and 9 of IC101 drops below 3 VDC the output pin 10 goes high. A 15 millisecond delay exists before pin 12 and 13 reaches 7 VDC. At this time pin ~ goes low caus-ing the +5 VDC reference to go to zero.
The voltage sensor 708 also provides an ON/OFF
control to the DC-to-DC converter 706. The converter 706 is turned ON when the capacitor voltage reaches 37 VDC and ~0 OFF when it drops to 33 VDC. A 15 millisecond delay in the OFF signal is used to insure that the microcomputer 154 is ON long enough to display the present value of phase and ground current, even when the output current from transformers 24 is too small to maintain the opera-tion of converter 706, and to ensure the maintenance of aTRIP signal long enough to effect generation of the trip coil 22. Note that the trip coil is controlled by non-latching FET 192, rather than a latching device such as the SCR's used in the prior art. This provides immunity from nuisance trips due to electrical transients, and prevents undue drain on the power supply when operating power is supplied by a battery.
Ther/s/w~itching points of the ON/OFF control 708 and crow bar ~ are shown in Fig. 13.
~J p The converter 706 is a chopper type consisting ~J dQ~ nr f~r~
of/switching trlnsistor IC102, inductor L101, "free wheel-~:149919 40 49,013 ing" diode D112, and a voltage ieedback reference formed by transistors Q103 and Q104. me voltage at the base of Q103 ls ad~usted to be +5 VDC by means of R109. This voltage ls approximately 1/2 the temperature stablllzed +10 VDC produced by D107, D108 and D109.
me circuit operates as follows. If the output voltage 18 below +5 VDC, Q103 will be ON and Q104 OFF.
The collector current of Q103 is the base current for the PNP darlington transi~tor IC102 which i8 then turned ON.
With approximately +35 VDC applled to L101 the current will rise linearly. The current will n ow into C106 and the connected load. When the output voltage exceeds ~5 VDC, Q103 will be turned OFF and Q104 will be turned ON.
me collector current of Q104 turn~ on Q102 which clamps the ba~e of IC102 causing lt to be tu~ned OFF rapidly. At this tlme, the current in L101 will ~witch from IC102 to diode D112. me output voltage will begin to decrease until Q103 turns ON, Q104 turns OFF, and the process re-peats itselr. Hystere~ls in the ON/OFF switching results from natural over and under shoot as~oclated with the L101 and C106 resonant network~ Positl~e switching ~eedback i~
provlded by C103 and R110. The ~witching points of the power ~upply 144 are shown in Flg. 13.
In addltlon to the ~5 VDC le~el, the power supply 144 also provldes a reference voltage VREF whlch i8 used by the microcomputor 154, An addition~l slgn~l, a power-on re~et sienal for the microcomputer l~ provided by IC1~3 ln combination R114, R115, R116 and C106. When the converter turns ON and ~5 VDC 18 produced, the ~ line remain~ at circuit ground for about 5 milliseconds. Thls ~ignal 1~ applied to the microprocessor which i~ then reset. Diodo D111 provides an immediate power-down reset as soon as the 5 VDC rererence goes to zero, thereby assurlng both a safe power-up and power-down tran~ltlon.
H. Read-OnlY Memorv The lnternal microcomputer ROM 155 18 ~upplled with .

49,001; 49,002; 49,004; 49,006; 49,009; 49,010; 49,013;
49,048; 49,049; 49,050 instructions defining a series of eight major functions which are execute(q,every dcycle of AC current, that is, A every 16.667 milis~n~s. Each function is responsible for retrieving one or more parameter values from outside the microcomputer. These parameters include values ob-tained from the electrical circuit being protected, such as phase current and ground current, as well as values specified by the front panel potentiometers and switches.
The function then loads the parameter value into a speci-fied location in RAM. In addition, most of the functionsare also responsible for performing one or more limit checks; for example, comparing present phase current to the instantaneous trip pick-up value. Since the entire loop of eight functions is executed every 16.67 ~ c-onds, each of the limit checks is performed at that rate.
In addition to the scanning and limit checkduties, each function is responsible for two operations relating to the front panel numeric displays 80 and 82.
Every four seconds, one function reads a display parameter value from its assigned location in RAM. It then formats this parameter value into four digit values. For example, if the present phase current is equal to 2.14 per unit, the appropriate function would produce four digit values~
a blank, a two, a one, and a four. These digit values would then be placed into assigned locations in RAM, each location corresponding to one digit of the numeric display indicator 80. Generally, each function will so format two parameter values, thus loading a total of eight digit values into corresponding RAM locations. These digit 3C values remain in RAM for four seconds until the next function performs its digit value loading duty.
At this point, the digit values are residing in RAM; they must now be sent to the appropriate digit of the numeric displays 80 and 82, the second operation performed by the eight main functions. Each function is responsi-ble, at each time it is executed, for retrieving one of ..

49,001; 49,002; 49,004; 49,006; 49,009; 49,010; 49,013;
49,048; 49,049; 49,050 the digit values from RAM and sending this digit value out on port 2 of the microcomputer 154 to the numeric displays 80 or 82. The digit value then appears lighted in its appropriate location in the numeric displays. Since a new function is executed approximately every 2 milliseconds (16.667/8 ms), the digit value will appear for this length of time on the numeric display before it is extinguished and the next digit value sent to a different digit loca-~ tion on the numeric display. At any given time,/on~y one10 digit ~ ~ on the~ numeric displays 80 and 82.
However, the digits flash so rapidly that they appear to an observer to be simultaneously lighted.
The external ROM 151 is optional and may be used to store instructions to implement additional features such as other functions related to the data I/O system.
Also, the look-up table for potentiometer settings may be stored in external ROM to facilitate changes in the table values.
The organization of the main instruction loop in ROM of the microcomputer can be seen in Fig. 17. The eight main functions are named FUNCTx, where x equals l through 8. The major subroutines called from these func-tions are the common display routine CMDIS, the analog to digital conversion routine ADCVl, the subroutine to toggle between the two display panel multiplexers 166 and 168 and perform the analog to digital conversion TADCV, and the subroutine to obtain discrete values from the potentio-meter settings READ, The main functions, and the corre-sponding subroutines will now be described in greater detail.
CMDIS - Figure 26 This subroutine is called by each major function and thus is executed every 2 milliseconds. It displays one digit value, as addressed by register Rl~and performs an analog to digital conversion on one of the eight input lines of the multiplexer 158, as specified by register R6.

, ' : ' '" 114~919 49,001; 49,002; 49,004; 49,006; 49,009; 49,010; 49,013;
4g,048; 49,049; 49,050 CMDIS outputs one pulse of 100 microsecond duration on line 7 of port 1, to energize the data input/output power supply 176. A portion of CMDIS, called TADCV, switches between multiplexer 166 and 168 to read a potentiometer rom the other side of the panel. In addition, CMDIS
completes a time delay to ensure that each major function executes in exactly 16.667/8 milliseconds.
Reference may now be made to Fig. 26 for a more detailed description of CMDIS. An internal counter is first checked to determine if the 16.667 ms/8 execution time window has expired. If not, the subroutine loops until the window does expire. The counter is then reset.
Next, line 7 of port 1 is activated to perform two functions. The analog-to-digital converter Chip Select terminal is deactivated by this line. This line is also connected to transistor 228 of the data input/output power supply. Thus, activation of line 7 of port 1 con-stitutes the leading edge of an approximately 100 micro-second pulse for the data I/0 power supply.
Pre-existing alarm conditions are now checked to determine if a pulse should be sent out on the serial output terminal of the optically coupled data input/output circuitry 174. As previously described, the serial output feature provides a pulse coded signal over a 16.667 milli-second time window to inform the remote indicator of possible alarm or trip conditions.
Register 6 is now incremented to obtain the channel address for the next input line of the multiplexer 158 to be accessed. Register 1 is now decremented to 3~ obtain the address of the next digit value for display.
Using register Rl as an address pointer, one of the eight digit values is now retrieved from RAM and prepared for dispatching to the numeric display indicat-ors. Since the digit value only requires four bits, the upper four bits are used to properly set up the Latch Enable line 5 of port 2 and the inhibit line 7 of port 2 , 49,001; 49,002; 49,004; 49,006; 49,009; 49,010; 49,013;
49,048; 49,049; 49,050 212. The LED indicator 84, 86, 88, 90, 92, 94, 96, 98 or 100 corresponding to the parameter now being displayed is controlled by bit 6 of port 2. The corresponding bit in the digit value being displayed is set or reset by the SRACE subroutine in FUNCTl. This control information and the digit value are then sent out on port 2 to the latch decoder 194 of the display system 155. ~6 ~t` ~G~
The channel address for the multiplexer ~5& as contained in register 6 is now sent out on port 2. The analog to digital conversion routine ADCVl is executed, and the digital value of the input to the multiplexer 158 is stored in register 3 and in the accumulator.
FUNCTl - Figure 18 This function first initializes register R1 with an address one greater than the address of DIGITl, the digit value which will be displayed in the rightmost position of the numeric displays 80 and 82 (which will be decremented by CMDIS before used). It also initializes register R6 with the first channel address to be accessed by the multiplexer 158.
Subroutine SRACE is entered next. This subrou-tine increments a four second counter. If this counter overflows from a hex value of FF to zero, this indicates that the four-second display period has elapsed, and it is time~ to command a new pair of values to appear on the numeric indicators 80 and 82. This is done by shifting the register R7. Next, SRACE sets bit 6 in one of the eight digit value RAM locations so that the appropriate LED indicator corresponding to the parameters being dis-3~ played will be lighted.
The common display routine CMDIS is now called.Upon completion, DIGIT1, the rightmost digit of the numer-ic display 82, will be lighted and the present phase current will have been read and processed by the ADC 156.
The present phase current value is now stored in RAM.
Index register R7 is now checked to determine if 9i9 it is t~me to display the present phase current value on the front panel numeric display indicator 80. If ~o, the value of pre~ent pha3e current is formatted into four diglt value~, and each of these digit values stored in the memory locations DIGIT8, DIGIT6, AND DIGIT5 in RAM
corresponding to the leftmost display digits, that ls, the digits of the numerlc indicator 80. The pre~ent ground current is also formatted into four digit values. mese diglt values are stored in the RAM locations DIGIT4, DI¢IT3, DIGIT2, and M GIT1 corresponding to the values of the rightmost digits, that is, the four digits of the numeric display 82.
Next, serial data I/0 operations are performed, if called for, and the value of phase current used for the long delay iunction is read. In order to obtain a value haYlng twice the resolutlon of the ætandard value of pre-sent phase current, the reference voltage supplied to the ADC 156 18 ad~usted via line 6 of port 1. The ADC i8 now commanded to again convert the value o~ the peak detector 160 as supplied through the multlplexer 158. Following the completlon oi the analog-to-digltal conversion, the capacitor of the phaso current peak detector 160 is re~et by groundlng the output of the multiplexer 158 through FET
186, as commanded by line 5 of port 1. The value of long delay phase current i8 now stored in RAM.
FUNCT1 now sends a channel address to the multi-plexer 158 via port 1 to select the ground current peak detector 162. me analog to digltal conversion routlne ADCV 1 ls called to read the ground current and convert it to a digital value. me ground current peak detector capacitor is now reset, At higher levels Or pha~e current, the ground current transformer 28 can generate iictitlous ~alues o~
ground current when no such value, in fact, exl~ts. mis eriect is more noticeable as phase current increases.
mere~ore, the iictitious ground current is accounted for by reducing the value of ground current to be ~tored in .

11499:~9 , 49,001; 49,002; 49,004; 49,006; 49,009; 49,010j 49,013;
49,048; 49,049; 49,050 RAM by a factor of 1/8 of the phase current whenever the phase current is between 1.5 per unit and 9 per unit. If the present value of phase current is greater than 9 per unit, the ground curren_ is neglected, by zeroing. the A 5 present ground current, ~ appropriate value of ground current is now stored in RAM.
FUNCT2- Figure 19 This function determines the average phase cur-rent, performs energy calculations, and determines the style number of the trip unit 126. First, the multiplexer 158 is supplied an address via port 1, as indexed by register R6 to cause the averaging circuit 164 to supply an analog value to the ADC 156. The common display rou-tine is now called, causing DIGIT2, the second digit from the right on the numeric display indicator 82, to be lighted~ and a digital value for the average phase current to be supplied. The value of average phase current is next multiplied by the product of power factor times line voltage, as specified by the front panel potentiometer 110. The result is the Present Kilowatt value, PRKW.
This value is temporarily stored and is also added to the megawatthour tally. A check is next made to determine if PRKW is greater than the peak kilowatt value registered since the las~ actuation of the Kilowatt Reset pushbutton 105~ If PR ~ is greater, the peak accumulated kilowatt value is set equal to PRKW, and both values stored in RAM.
A check is next made on register R7 to determine if it is time to display the present kilowatt and mega-watthour values on the numeric displays 80 and 82. If so, these quantities are formatted into four digit values apiece and loaded into the digit value storage locations in RAM.
An address is now generated to the multiplexer 158 to select the style number designator 170 to be sup-plied to the ADC 156. An A to D conversion is now made onthe style number and this value stored in RAM, to desig-: . .'.' 9i9 49,001; 49,002; 49,004; 49,006; 49,009; 49,010; 49,013;
49,048; 49,049; 49,050 nate which of several optional features are included in the present trip unit and to select execution of the appropriate instructions farther down in ROM.
FUNCT3 - Figure 20 The first task of this function is to reset the number of pulses to be sent out over the serial output terminal. This information will later be used by the common display program to produce the proper pulse code on serial output. The common display routine is now exe-cuted, to light DIGIT3, the third digit from the right on the numeric displays and return a digital value from the Peak Kilowatt setting potentiometer 108.
Next, a flag is set to prevent an extraneous pulse from being sent on the serial output terminal. The READ routine is then executed to obtain one of eight discrete values for the Peak Kilowatt setting as specified by the corresponding potentiometer 108. This routine will be later described in greater detail.
A check is now made to determine if it is time to display the Peak Kilowatt setting on the numeric indi-cator 80. If so, the value of Peak Kilowatt setting as determined by the READ routine is formatted into four digit values and stored in the digit value locations in RAM corresponding to the digits of the numeric display 80.
A running tally of kilowatts is maintained in RAM. This tally is incremented by the present kilowatt value on every execution of FUNCT3, thus integrating the kilowatt values over time, producing a value corresponding to kilowatt hours. A check is now made of this location in RAM to determine if a value corresponding to 10 kilo-watthours has been reached. If so, a megawatthour tally in RAM is incremented and the kilowatthour tally reset retaining the remainder. A check is made to determine if it is time to display the contents of the megawatthour tally on the display. If so, this quantity is formatted into four digit values and stored in the digit value li4~919 49,001; 49,002; 49,004; 49,006; 49,009; 49,010; 49,013;
49,048; 49,049; 49,050 locations in RAM corresponding to the numeric display 82. :
Line 3 of port 2 is now activated to select multiplexer 166 and deselect multiplexer 168 as an input to multiplexer 158. An analog to digital conversion is now made on the panel switches 102, 104, and 106, and a digital value unique to each combination of switch set-tings stored in RAM.
FUNCT4 - Figure 21 The first task of FUNCT4 is to call the common display routine to light DIGIT4, the fourth digit from the right on the numeric display indicator 82, and read the PFxLV potentiometer 110 and return a digital value there-from. The READ routine is now called to obtain the look-up table value corresponding to the digital value of the PFxLV potentiometer 110. If it is time to display the PFxLV value, it is formatted into four digit values and ; stored in the RAM locations corresponding to numeric display indicator 80.
Line 3 of port 2 now selects multiplexer 166 as input through multiplexer 158 to the ADC 156, and an analog to digital conversion is ordered on the voltage divider network which includes the pushbutton switches 105, 107, 128, and 130. A unique digital value corre-sponding to the pattern of pushbuttons now depressed is stored in RAM. This quantity is also checked to determine if any pushbuttons have indeed been pressed. If none, then FUNCT5 is entered. Otherwise, a ^heck is made to : determine if the kilowatt reset pushbutton 105 has been pressed. If so, the value of peak kilowatts in RAM is 3o cleared. Next, a check is made to determine if the system reset pushbutton 107 has been pressed. If so, all trip indicators are cleared, the serial output pulse codes are zeroed, the display sequence is reset, and the interrupt is enabled. If the system reset button is not being pressed, then one of the test pushbuttons 128 and 130 is.
The digital value of the pushbutton read through the ,. ....
, :

, 49,001; 49,002; 49,004; 49,006; 49,009; ~9,010; 49,013;
49,048; 49,049; 49,050 m~ltiplexers 166 and 15~ is ~w sto~ n ~1 ~es~ ~ld~, FUNC~5 - Figure 22 The common display routine is called to l~ght DIGIT5, the fifth digit from the right, and to read the instantaneous current pick-up potentiometer 112. The READ
routine takes the digital value of the potentiometer set-ting supplied by the common display routine and obtains the actual setting from the look-up table in ROM. A check is now made to determine if it is time to display the in-stantaneous current pick-up setting on the numeric indi-cator 80. If so, the instantaneous pick-up value is for-matted into four digit values and stored in RAM locations corresponding to the digits of the numeric indicator ~0.
The TEST potentiometer 120 is now read through the multiplexers 168 and 158 and a digital value obtained.
The digital value previously obtained from scanning the front panel switches is now checked to determine if the switch 106 is in the TRIP position. If so, a fixed value is loaded into the RAM location where the value of the TEST potentiometer 120 would normally be stored. This A fixed value is interpreted as either ~i~ per unit for phase current or 1.5 per unit for ground current, at a later point in the execution of the test. If the switch 106 is in the NO TRIP position, a check is next made to determine if more than one pushbutton is pressed. This is an illegal condition, and no test will be performed. lf it is determined that only one pushbutton is pressed, a check is made to see which one it is. If the GROUND TEST
pushbutton 130 is pressed, a check is made to determine if the value of the TEST potentiometer 120 as stored in RAM
is greater than or equal to the present value of ground current. If it is not, this means that the actual value of ground current now being detected by the system is greater than the value of ground current simulated by the potentiometer 120. Thus, no test wil] be performed and the trip unit will execute the standard ground current 49,001; 49,002; 49,004; 49,006; 49,009; 49,010; 49,013;
49,048; 49,049; 49,050 limit checks. If the value of the TEST potentiometer 120 as stored in RAM is greater than the present value of - 7~s, A ground current, then indexes are set to turn on the ~
LED 100, the value of the TEST potentiometer 120 is for-matted into four digit values and stored in the RAM loca-tions corresponding to the digits of the numeric indicator 82, and the display of the numeric indicator 82 frozen.
If the PHASE TEST pushbutton 128 is pressed, a check is made to determine if the value of the TEST poten-tiometer 120 as stored in RAM is greater than the presentphase current. If it is not, then the actual value of phase current is more critical than the simulated test value, and no test will be performed. Instead, the normal limit checks on the present phase current will be executed by the system. If the simulated test value of phase current is greater than the present value of phase cur-rent, then an index is set to turn on the TEST LED 100, the value of the TEST potentiometer 120 is formatted into four digit values and stored in RAM locations correspond-ing to the digits of the numeric indicator 80, and anindex set to freeze the numeric indicator 80.
A check is now made to determine if the test flag is equal to the bit pattern produced by scanning the pushbuttons. If it is, this indicates that the TEST push-button is still being depressed. Since a test is not tobe initiated until the button is released, no test will be performed at this time. If the test flag value is differ-ent from the pushbutton value, a check is made to deter-mine if the PHASE TEST pushbutton 128 had been pressed.
If so, the value of the TEST potentiometer 120 is stored in the RAM locations corresponding to present phase cur-rent and long delay phase current. If the GROUND TEST
button had been pressed, then the value of the TEST po-tentiometer 120 is stored in the RAM location correspond-ing to the present ground current value. This completesthe portion of the testing function incorporated in func-,.,.

. .,, ;

~14a919 49,001; 49,002; 49,004; 49,006; 49,009; 49,010; 49,013;
49,048; 49,049; 49,050 tion 5.
Next, the present value of phase current is com-pared to the instantaneous current pick-up as specified by the potentiometer 112. If the present value of phase current is below this value, then function 6 is immediate-ly entered. If the present value of phase curren~ is grea~er than the instantaneous current pick-up level, an index is set to cause the common display subroutine to put out a pattern of pulses on the serial output terminal to indicate that an instantaneous trip has occurred and the TRIP subroutine is called, as will be explained in a later section.
FUNCT6 - Figure 23 The common display routine is executed to light DIGIT6, and read and convert the long delay pick-up poten-tiometer 114. The digital value of this potentiometer is now acted upon by the READ routine to obtain the table look-up value. If it is time to display the long delay pick-up value on the numeric indicators, the long delay pick up value is formatted into four digit values and stored in the RAM locations corresponding to the digits of the numeric indicator 80. Next, the long delay time potentiometer 122 is scanned and converted to a digital value, and acted on by the READ routine to obtain the table look-up value for the long delay time function.
The Long delay limit check is now made, by first comparing the long delay phase current to the long delay pick-up value. If the long delay phase current is not greater than the long delay pick-up, then the long delay tally is reduced by the square of the difference beween the long delay pick-up setting and the long delay phase current. FUNCT7 is then entered.
If the long delay phase current is greater than the long delay pick-up value, then the long delay tally is incremented by the square of the long delay phase current.
A check is now made to determine if the long delay tally 3~ ~9~
49,001; 49,002; 49,004; 49,006; 49,009; 49,010; 49,013;
49,048; 49,049; 49,050 is greater than the value of long delay tally specified for a long delay trip. If not, FUNCT7 is then entered.
If the current value of the tally is greater than the trip level, a code is stored in RAM to cause the common display program to generate the proper pulse code over the serial output terminal to indicate a long delay trip. Next, the TRIP subroutine is called, and the long delay tally clear-ed. FUNCT7 is then entered.
FUNCT7 - Figure 24 The common display program is called to light DIGIT7 and obtain a digital value for the setting of the short delay pick-up potentiometer 116. The READ routine is then called to obtain the proper table look-up value for short delay pick-up corresponding to the digital value scanned from the potentiometer. A check is made to deter-mine if it is time to display the short delay pick-up function. If so, the short delay pick-up value is for-matted into four digit values and stored in the RAM loca-tions corresponding to the digits of numeric display indicator 80.
Line 3 of port 2 is now activated to select multiplexer 166, scan the short delay time potentiometer 124, and obtain a digital value therefrom. The table look-up value for short delay time is then obtained through the READ routine. If it is now time to display the short delay time value, the short delay ti~e value is formatted into four digit values and stored in the RAM
locations for display as digits 1 through 4 in numeric display 82.
The short delay limit value check is now per-formed, by first comparing the present phase current to the short delay pick-up setting. If the pick-up setting is not exceeded, then the short delay tally is cleared and FUNCT8 entered.
If the present phase current is greater than the short delay pick-up value, the RAM location corresponding ~ 9 49,001; 49,002; 49,004; 49,006; 4g,009, 49,010; 49,013;
49,048; 49,049; 49,050 to the pattern of switches 102, 104 and 106 is checked to deter~ine if the short delay I2T function is called for, via the switch 102. If so, the square of the present phase current is added to the short delay tally, and the new value of the short delay tally compared to the short delay tally trip level. If the trip level is exceeded, pulse code for serial out and remote indicator is s~ored and the TRIP subroutine is called. If the tally trip level is not exceeded, then FUNCT8 is entered.
If the I2T function was not specified for the short delay test, then the present phase current value is added to the short delay tally and a comparison made to determine if the new value of the short delay tally now exceeds the short delay tally trip level. If not, FUNCT8 is immediately entered. If the tally trip level is ex-ceeded, the pulse code for serial out and remote indicat-ors is stored and TRIP routine is called before entering FUNCT8.
FUNCT8 - Figure 25 2') The common display routine is called to light DIGIT8, the leftmost digit in numeric display indicator 80 and to scan and convert the ground fault pick-up potentio-meter 118. The look-up table value for ground fault pick-up corresponding to the digital value of the poten-tiometer 118 is then determined by the READ routine and stored in RAM. If it is now time to display the ground fault pick-up value, this quantity is formatted into four digit values and stored in the RAM locations corresponding to the four digits of the numeric indicator 80.
The ground fault time potentiometer 126 is now scanned and a digital value obtained therefor. The ~EAD
routine then determines the look-up table value corre-sponding to the digital value for the potentiometer 126.
If it is time to display the ground fault time value, this quantity is formatted into four digit values and stored in the RAM locations corresponding to the four digits of the 49,001; 49,002; 49,004; 49,0~6; 49,009; 49,010; 49,013;
49,048; 49,049; 49,050 numeric indicator 82.
A test is now made to determine if the present value of ground fault current is greater than the ground fault pick-up level. If not, an additional test is made to determine if the present value of ground fault current is greater than one-half of the ground fault pick-up level. If so, the ground fault interlock flag is set in RAM. The ground fault tally is then decremented and the loop returns to FUNCTl.
If the present value of ground fault current is ~o-t greater than the ground fault pick-up level, the location in RAM specifying the front panel switch pattern is then checked. If the ground fault I2T switch 104 is set, a quantity equal to 1.5 times the present value of ground fault current is added to the ground fault tally.
If the I2T switch 104 is not set, then the ground fault tally is merely incremented.
Next, a check is made to determine if the ground fault tally is greater than the ground fault time limit value. If not, the main loop is entered once again at FUNCTl. If the tally is greater than the ground fault time, then a pulse code is stored to allow the proper pulse pattern to be transmitted on the serial output terminal, and the TRIP routine i5 called prior to return-ing to the top of the main loop at FUNCTl.TRIP - Figure 27 This subroutine is executed whenever electrical conditions on the circuit breaker exceed the time-current characteristic limit values as entered through the front panel of the trip unit 26. The out-of-limit conditions are detected by the calling functions of the main loop instructions stored in the ROM.
The TRIP subroutine first checks the trip flag to determine if this trip condition was detected on a pre-~5 vious execution of the main loop. If so, the next step isto set register R7 to freeze the numeric display. If this , .
.
:
... , . .. :

~ ~ ~9 9~9 49,001; 49,002; 4g,004; 49,006; 49,009; 49,010; 4g,013;
49,048; 49,049; 49,050 is the first time the trip condition has been detected, then the trip flag is reset and the present value of phase current is loaded into the digit value locations in RAM
corresponding to the digits of numeric display 80. Next, bit 6 of the appropriate digit value location in RAM is set, to cause the proper LED to be lighted on the front panel to display that function which caused the trip oper-ation. Note that when bit 6 of a digit value is sent out on port 2, line 6 of port 2 will be actuated when and only when the digit connected to the proper LED is lighted.
This will turn on the transistor 208, lighting the proper LED.
Register R7 is then set to freeze the numeric display and prevent any of the functions of the main loop from attempting to display a different quantity. The interrupt is now disabled and a check is made to determine if this call to the TRIP routine was the result of a test being performed; that is, as a result of the operator having pressed either the PHASE TEST button 128 or the GROUND TEST button 130. If so, a check is next made to determine if the switch 106 is in the NO TRlP position.
If so, the routine resets the test flag and four second timer and returns to the calling location.
If the switch 106 is in the TRIP position, or if ~5 the call to the TRIP subroutine was not caused by a test, then line 4 of port 1 is actuated. This sends a signal over the line 190 of Fig. 2 to the transistor 192, actuat-ing the trip coil 22 and causing the contacts 18 to open.
The test flag and four second timer are reset and the subroutine returns to the calling location.
R AD - Figure 28 This subroutine performs a table look-up func-tion to allow the limit value setting potentiometers on the front panel of the trip unit 26 to select any of eight discrete values rather than a continuously variable out-~,. put. In addition, the subroutine provides a hysteresis ~ 499i9 56 49,013 effect when ad~u~ting the potentlometers to ellminate the unde~lrable variatlon oi potentlometer values on amblent temperature and provlde greater ease and convenience ln ad~ustment.
Upon entry to the READ routine, reglster RO
contains the address in RAM o~ the location where the parameter value being read will be stored, register R2 contalns the beginning address of the table of eight values which can be selected by the potentiometer, and the accumulator and register R~ both contain the dlgital value of the voltage settlng produced by the potentlometer, a~
supplled by the ADC 156.
- A check i8 ilrst made to determlne ii a tripplng operatlo~ has already occurred. If 80, the subroutlne is lmmediately exited. Otherwlse, the eight-bit digital value oi the potentiometer voltage settlng has lts lower iive blts stripped oif and the three most signlilcant dlglts rotated to become the least slgnliticant blts. me accumulator thus contains a binary number havlng a decimal value from O to 7. This qu-ntity is then added to the address oi the beginning oi the table, as stored in regis-ter R2, yielding the address ln RAM Or the table value selected by this particular adJustment oi the potentlo-meter. The value thus obtained may or may not be used to update the ~peciilc parameter being ad~usted, dependlng on the pre~lous value of this potentlometer.
Ii the old ~ettlng 18 equal to zero, then a ~tart-up conditlon exists. The new ~etting 18 immediately loaded into the appropriate RAM location and the subroutine READ
i~ exlted, Ii the new setting a~ obtalned irom the lookup table is equal to the old ~ettlng, then the old ~ettlng i~
reloaded lnto RAM at the address speclfied by register RO.
Ii the new settlng i~ unequal to the old settlng then the hysteresls te~t i~ periormed.

, ~ . .

g~
49,001; 49,002; 49,004; 49,006; 49,009; 49,010; 49,01~;
--- 49, 048; 49, 049; 49, o50 56a Essentially, the hysteresis test examines the entire eight-bit output of the ADC 156, as scanned from the potentiometer. If bits 1 and 2 are equal, that is, if they are either 00 or 11, then the new setting is ignored and the old setting is reloaded into RAM, The purpose of ``` ~14~9i9 49,001; 49,002; 49,004; 49,006; 49,009; 49,010; 49,013;
49,048; 49,049; 49,050 this action can be understood by reference to TABLE I, wherein eight values out of thel28 possible combinations of ADC output are shown. As has already been explained, the most significant bits, that is bits 5, 6 and 7, deter-mine the setpoint of the potentiometer. As can be seen inTABLE I, the potentiometer setting in binary notation will increase from 100 to 101 as the analog-to-digital con-verter output moves from value D to value E. By ignoring a change in potentiometer setting wherein bits 1 and 2 are 1~ either 11 or 00, a hysteresis effect is obtained.

TABLE I

Bit Number: 7 6 5 4 3 2 1 0 Value Remembering that the hysteresis test is only performed if there is a change in the upper three bits of the ADC output, it can be seen that an increase in ADC
output from value B to value C will not result in a new value being stored, since the upper three bits of B and C
are the same. An increase from value B to value G J how-ever, would clearly result in a new value being stored, since bit 5 of the output changed from a zero to a one.
Without the hysteresis test being performed, an increase in ADC output from value C to value F would simi-~ , 35 larly result in a new potentiometer value being stored.

., ' ~

9'~9 49,001; 49,002; 49,004; 49,006; 49,009; 49,010; 49,013;
49,048; 49,049; 49,050 However, this represents a change in value of about 3/256 of the maximum potentiometer, or less than 1.2%. Such variation can easily occur due to changes in ambient temperature.
Through the use of the hysteresis test, wherein ADC outputs having equal values of bits 1 and 2 are ig-nored, it can be seen that a change in ADC output from value C to value F would result in the new potentiometer setting being ignored and the old potentiometer setting being reloaded into RAM, since bits 1 and 2 of value F are both zero. Similarly, if the operator were reducing the value of the potentiometer, causing an ADC output to change from value G to value C the new value would also be ignored and the old value retained, since bits 1 and 2 of value C are both one, and the hysteresis test would reject the new setting. It can therefore be seen that the hys-teresis test insures that the potentiometer setting must be changed by more than 4/256 of its total possible ad-justment before a new setting will be accepted. It can be argued that the hysteresis test just described is not suf-ficiently precise, in that a valid setting change may possibly be ignored. This might occur, for example, if the,old potentiometer setting produced an ADC output much larger than value H, for example 10110101, and the new potentiometer setting produced an ADC output equal to value D. It can be seen that this represents a very large excursion in the rotation of the potentiometer, and yet the final position producing a value equal to value D
would be ignored, since bits 1 and 2 are both ONE's. It must be remembered, however, that an interactive operation is being performed, and that the parameter value selected by the READ routine is, from the point of view of a human operator, instantaneously presented on the numeric dis-plays 80 or 82. In the example just cited, the operator would see that a fairly large excursion of the potentiome-ter produced no change in value, and he would naturally ~ 991g 49,001; 49,002; 49,004; 49,006; 49,009; 49,010; 49,013;
49,048; 49,049; 49,050 make an even further adjustment. At some point, his further adjustments would result in a new value being selected by the READ routine and presented under numeric display. If the change produced were larger than desired, the operator would then readjust in the opposite direc-tion, the entire operation taking much less time to per-form than to explain. This represents an extremely cost-effective and convenient method of entering parameter changes for the time current tripping characteristic into a circuit breaker. Adjustment of the potentiometer to the extreme upper and lower limits will cause the most con-servative value to be displayed.
In the event that bit 2 is not equal to bit 3, that is the hysteresis test does not cause the setting to be ignored, a bit pattern is loaded in register R7 to cause display of this setting value on the numeric dis-plays 80 or 82. The four-second timer is then reset and the new setting value is stored in the RAM location corre-sponding to thls particular parameter. The subroutine then returns to the calling function.
If an ADC output of all zero's or all one's is obtained, the READ routine interprets this as a poten-tiometer failure. The most conservative parameter value is then selected from the look-up table, displayed on the numeric display 80 or 82, and stored in RAM.
I Hardware Initialization After Power-On F ~
~I
The microcomputer 154 must be initialized fol-lowing power-up. In the case of the Intel 8048 device this is accomplished by means of a RS pin which if held low causes the program to '1jump" to address 0 which by convention is the starting address of the power-on start-up subroutine. The RS pin is held low by the power supp].y by means of D900 for about 5 ms, after the +5 VDC is applied.
However, the RS pin does not affect the I/O
lines from the microcomputer and thus during the power ON

'`` il4g919 49,001; 49,002; 49,004; 49,006; 49,009; 49,010; 49,013;
49,048; 49,049; 49,050 transient these may assume either a high or low output state which, in the case of four particular lines of Port 1 and Port 2, can cause excessive power supply drain or even accidental tripping of the circuit breaker 10 or other interconnected breakers. These lines are as fol-1ows:
1. LED (line 6 of Port 2--should be low to ensure all LED indicators on front panel are OFF).
2. INHIBIT 212 (line 7 of Port 2--should be tristated, that is, held in a high-imped-ance state to ensure that all 8 digits of the 7-segment LED displays 80 and 82 are OFF).
3. PULSE 178 (line 7 of Port l--should be tristated to ensure that pulse transformer 501 is OFF).
4. TRIP 190 (line 4 of Port l--should be tristated to ensure that no false trip 2~ occurs on power-on).
The desired tristating is achieved by means of hex buffer U900. When ~ of the microcomputer 154 is low, the DISABLE (A) of U900 is low (removed) which causes DISABLE (B) to be high (active). In this way the four critical leads from the microcomputer 154 are switched to the high impedance state, except for LED which is held low as desired by the pull-down resistor R905.
A second function of U900 is to reset counter U901 as shown in Fig. 16.
J. Automatic Reset Ç,~f~r~ !~
Once a successful power-up transition is made, the microcomputer 154 continues to execute a logical and sequential series of instructions indefinitely. Under unusual conditions, such as those produced by electrical systern transients, it is possible for an instruction to be improperly executed. The only way to restore the micro-1~9919 49,001; 49,002; 49,004; 49,006; 49,009; 49,010; 49,013;49,048; 49,049; 49,050 computer 154 to its orderly program execution is to per-form another reset operation. In unattended applications, this reset must be automatic.
This is accomplished by means of counter U901 which utilizes a 400 kHz clock output (ALE) from the microcomputer 154 to provide a fixed time delay between the last U901 RS pulse and a high on Q11 (RS for the~ C).
If the RS pulse of U901 occurs soon enough, Q11 will remain low and the ~C will not be reset.
The U901 RS pulses are derived from the col-lector of transistor 228. Normally these pulses are 100~s wide and occur approximately every 2 ms. The circuit is designed so that 5.46 ms is required for Qll to time out (go high) and thus Qll is always low.
If improper instruction execution sequence occurs, the following possible conditions would cause an automatic reset of the microcomputer (Qll would time out).

If this condition should exist for more than 300,~s, pulse transformer 501 will saturate and V901 RS
will remain low.
_~8-o~'F
If this condition should exist, U901 RS will remain low.
228-Pulse R_te Too Slowly If transistor 228 turn-on pulses occur less than every 5.46 ms, the U901 RS will be low long enough for a,~C reset to occur.
228-Pulsed Too Fast 3~ Rapid pulsing of transistor 228 will be filtered by~R9~00 and C900 (39,~s time constant).
~44-ON/OFF Duty Cycle ~ 1/10 Transformer T501 is pulsed on for 100 ~ s, to a voltage of 5 volts, by transistor 228. When 228 is turned OFF, the transformer's magnetizing current will flow through diode D901 which will result in a voltage of about 4~,001; 49,002; 49,004; 49,006; 49,009; 49,010; ~9,013;
49,048; 49,049; 49,050 -.5 volts being applied to the transformer 501. The average voltage of the transformer must be zero and thus 1000~ s x 100 ~s) will be required to "reset" the transformer's magnetizing current to zero. A l-to-10 or less ON-to-OFF ratio must be maintained for the transformer 501 to function or the transformer's core will ultimately saturate. If trans-former 501 i5 saturated, the RS pulses will not be applied to U901 and Qll will time out and reset the microcomputer.

Claims (13)

63 49,013 What we claim is:

1. Circuit interrupter apparatus, comprising:
interrupter means for conducting current flow through an associated electrical circuit and for operating to interrupt current flow therethrough upon command;
sensing means for sensing current flow through said interrupter means;
display means for displaying numeric quantities;
a plurality of designating means for identifying a parameter;
a plurality of light-emitting indicator members positionally associated with said designating means; and trip unit means connected between said interrupter means and said sensing means for operating said interrupter means when current flow therethrough exceeds a predetermined time-current trip characteristic defined by limit value parameters, for generating numeric quantities representing electrical parameters of an associated circuit and limit value parameters defining said time-current trip character-istic, for sequentially presenting a series of said numeric quantities to said display device, and for individually energizing said light-emitting indicator members in a sequence corresponding to the sequence of said numeric quantity presentations, whereby each numeric quantity so displayed is identified as a value of a specific parameter.

2. Apparatus as recited in claim 1 wherein said designating comprise printed legends and said indicator members comprises light emitting diodes.

3. Apparatus as recited in claim 2 wherein said 64 49,013 delay means comprises a pair of numeric display devices, said designating means comprises a plurality of pairs of printed legends, each of said light emitting diodes being associated with one of said legend pairs, and one member of each legend pair is associated with each of said dis-play devices; whereby energization of one of said light emitting diodes is operable to identify a pair of numeric quantities displayed in said display devices.

4. Apparatus as recited in claim 2 wherein said trip unit means comprises means for generating numeric quantities based on any of a plurality of per-unit bases, and each of said printed legends comprises a symbol asso-ciated with one of said per-unit bases, whereby each nu-meric quantity appearing on said display means is identi-fied as a per unit quantity based on a specified one of said per unit bases.

5. Self-contained circuit interrupter appara-tus, comprising:
interrupter means for conducting current flow through associated electrical circuit and for operating to interrupt current flow therethrough upon command;
sensing means for sensing current flow through said interrupting means;
trip unit means connected between said inter-rupter means and said sensing means for operating said interrupter means when current flow through said inter-rupter means exceeds a multi-function time-current trip characteristic and for performing a test operation compar-ing a simulated fault current value to said multi-function time-current trip characteristic;
input means for receiving an operator-selected value of simulated fault current;
initiating means for commanding said trip unit means to perform a test operation;
result-indicating means for indicating to an operator the result of said test operation comparison; and a housing enclosing said apparatus.

6. Apparatus as recited in claim 5 wherein said 49,013 initiating means comprises a momentary contact switch, and said trip unit means comprises means for activating said input means when and only when said momentary contact switch is actuated, and said initiating means initiates a test operation only upon release of said momentary contact switch.

7. Apparatus as recited in claim 5 comprising a display device connected to said trip unit and wherein said input means comprises a potentiometer connected to said trip unit means, and said trip unit means comprises means for causing said operator-selected value to be pre-sented in substantially real time upon said display de-vice.

8. Apparatus as recited in claim 5 wherein said result-indicating means comprises a plurality of light emitting indicator members each associated with one func-tion of said multi-function time-current trip characteris-tic; said trip unit means comprising means for energizing a selected one of said indicator members when said simu-lated fault current value exceeds said multi-function time-current trip characteristic, whereby the function of said multi-function time-current trip characteristic which was exceeded by said simulated fault current value is indicated by said energized indicator member.

9. Apparatus as recited in claim 8 comprising a test indicator member energized by said trip unit means upon initiation of a test operation and deenergized by said trip unit means when said selected one of said light emitting indicators is energized.

10, Circuit interrupter apparatus, comprising:
interrupter means for conducting current flow through an associated electrical circuit and for operating to interrupt current flow therethrough on command;
sensing means for sensing current flaw through said interrupter means;
trip unit means connected to said interrupter means and said sensing means for operating said interrup-ter means when current flow therethrough exceeds a time-66 49,013 current trip characteristic and for performing a test operation comparing a simulated fault current value to said time-current trip characteristic, said trip unit means comprising means for indicating the results of said comparison and switch means for selecting operation or non-operation of said interrupter means when said simu-lated fault current value exceeds said time-current trip characteristic.

11. Apparatus as recited in claim 10 wherein said trip unit means comprises means for establishing a non-adjustable simulated fault current when said switch means selects non-operation of said interrupter means as a result of said comparison.

12. Apparatus as recited in claim 10 wherein said trip unit means comprises safety means for operating said interrupter means when current flow therethrough exceeds the time-current trip characteristic, regardless of the status of said switch means.

13. Apparatus as recited in claim 10 wherein said time-current trip characteristic comprises a long delay function and said trip unit comprises means for immediately operating said interrupter means upon comple-tion of a test operation if current flow through said interrupter means exceeds the long delay function of said time-trip characteristic at the time of completion oil the test, regardless of the status of said switch means.