CA1159170A - Display device - Google Patents
Display deviceInfo
- Publication number
- CA1159170A CA1159170A CA000371944A CA371944A CA1159170A CA 1159170 A CA1159170 A CA 1159170A CA 000371944 A CA000371944 A CA 000371944A CA 371944 A CA371944 A CA 371944A CA 1159170 A CA1159170 A CA 1159170A
- Authority
- CA
- Canada
- Prior art keywords
- display
- signal
- memory elements
- row
- module selection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2085—Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
- G09F9/35—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being liquid crystals
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/02—Composition of display devices
- G09G2300/026—Video wall, i.e. juxtaposition of a plurality of screens to create a display screen of bigger dimensions
Abstract
ABSTRACT OF THE DISCLOSURE
A flat panel display device is formed by combining many individual solid state display modules each of which is capable of displaying only one or two characters. Each module includes a semiconductor chip on which is integrated circuit elements for driving and circuits for addressing, and a memory element for a selection signal for obtaining access to each module. The chip is incorporated in a package comprising also an insulating substrate carrying connector pins, transparent electrodes formed on the underside of the cover, the whole package forming the module.
A flat panel display device is formed by combining many individual solid state display modules each of which is capable of displaying only one or two characters. Each module includes a semiconductor chip on which is integrated circuit elements for driving and circuits for addressing, and a memory element for a selection signal for obtaining access to each module. The chip is incorporated in a package comprising also an insulating substrate carrying connector pins, transparent electrodes formed on the underside of the cover, the whole package forming the module.
Description
~ ~5~17~) l~c pl~sellt inveiltioll relates ti) a flat pcLllel display device, part-icularly ~hose involving lalgc scale intcgratioll combining the integrated active elemellts for dl iving conresponding to picture element with the display medi~ull.
lhere has bcen plol)osed recently a display unit having a structure in wllicll arl in~egrated dl ive circuit is combined with a flat panel type matrix disi)lay device utilL- ing e~ectro-lumlnescence (EL) or liquid crystals.
rlhe drive c ircuit consists of active elements corresponding to picture ele-ments integrated onto a silicon wafer, thus controlling partially and select-ively the optical functions of display mediums layered on the upper side of the silicon wafer. In addition, from the point of view of forming a display unit which is as wide as possible, attempts have been made to integrate active elements corresponding to the picture elements utilizing the SOS~Silicon On Sapphire3 technique or the thin film transistor (TFT) technique in place of the silicon wafer. One such solid state flat panel displays is described, for example, in the United States Patent Specification No. 3,866,209 "CHARGE-TRANSFER DISPLAY SYSTEM" by P.K. Weimer. In addition, a flat panel display using the TFT technique is proposed, for example, in the paper by F.C. Luo et al. entitled "Design and Fabrication of Large-Area Thin-Film Transistor Matrix Circuits for Flat-Display Panels" introduced in the IEEE Transactions, Vol.
ED-27, No. 1, January 1980, PP 223-230.
However, it is extremely difficult to realize a large size flat panel matrix display device combining active elements explained above with the existing techniques. In particular, in the case of the structure integrating active elements corresponding to picture elements using a silicon wafer, the size of display screen is limited according to the size of the wafer and more-over it is very difficult from the point of view of yield to form as many as '~., ~ 1S917(~
lhere has bcen plol)osed recently a display unit having a structure in wllicll arl in~egrated dl ive circuit is combined with a flat panel type matrix disi)lay device utilL- ing e~ectro-lumlnescence (EL) or liquid crystals.
rlhe drive c ircuit consists of active elements corresponding to picture ele-ments integrated onto a silicon wafer, thus controlling partially and select-ively the optical functions of display mediums layered on the upper side of the silicon wafer. In addition, from the point of view of forming a display unit which is as wide as possible, attempts have been made to integrate active elements corresponding to the picture elements utilizing the SOS~Silicon On Sapphire3 technique or the thin film transistor (TFT) technique in place of the silicon wafer. One such solid state flat panel displays is described, for example, in the United States Patent Specification No. 3,866,209 "CHARGE-TRANSFER DISPLAY SYSTEM" by P.K. Weimer. In addition, a flat panel display using the TFT technique is proposed, for example, in the paper by F.C. Luo et al. entitled "Design and Fabrication of Large-Area Thin-Film Transistor Matrix Circuits for Flat-Display Panels" introduced in the IEEE Transactions, Vol.
ED-27, No. 1, January 1980, PP 223-230.
However, it is extremely difficult to realize a large size flat panel matrix display device combining active elements explained above with the existing techniques. In particular, in the case of the structure integrating active elements corresponding to picture elements using a silicon wafer, the size of display screen is limited according to the size of the wafer and more-over it is very difficult from the point of view of yield to form as many as '~., ~ 1S917(~
2~lU x 2-~() active elelllellti all(l LighL emittillg areas without any fault on an or~ina!y 3-ialch w.lfe~ ultller, Lt is also di:Eficult to form the ~ctive ele-lllellts ~or dl`iVillg and lignL elllLtt.illg areas .in such a number corresponding to the required pic~ure elemel~ts with satisfactory yield even when the SOS struc-ture or the l`l:l` structure .is employed, and after all it is the principal aim ln this type of display device to economically obtain a large size display screen.
It is an object of this LnventiOn to provide a new structure of flat panel display which can be manufactured economically with a high yield and overcome the abovementioiled problems.
It is another object of this invention to provide a modular type solid state display device whi.ch easily allows realization of a large size display structure and simple maintenance.
It is further object of this invention to provide a modular type large scale flat panel display device.
Briefly, the present invention is based on obtaining firstly basic elements by forming small size display modules each including a plurality of picture elements and the display screen of the required area is then obtained by using one mode or by combining a plurality of such display modules. The display modules should be of a size which permits easy manufacture of the cir-cuit function elements to be integrated without any defects and desirably should be determined to a scale, which permits for example, 16 x 16 picture elements or more to be obtained which is required for dot matrix display of one character. In addition, according to a preferred embodiment of the pre-sent invention, the display module is basically composed of IC chips each of which integrates the picture element electrodes which face the display medium and determine the picture elements arranged in the form of a matrix, the 1 15~17() activc clcmcnts ~for sclect~;vc clriving correspollding individually to each pic-turc elemcnt electrode and in addition the address circuit which receives scr;ally on timing the information signals (data signals) corresponding to the patterns to be displayecl ancl clistributes these signals to said active elements.
Morcover, that the complication of connecting lead wires when a plurality of d;splay modules are comhined and moullted is avoided as much as possible.
According to a speci~ic aspect of the invention, the memory element which stores module selection signals for display module of the relevant dis-play block is provided for each said display block arranged in units of one or plural display modules whicl~ form a large scale display screen, and it is enabled to selectively drive the corresponding display modules with an output of said memory element. Particularly when, in this case, the memory elements for plural display blocks are connected in series in order to sequentially transfer the module selection signals, the access to the display modules can be sequentially and adequately controlled in accordance with the display con-tents such as sequential access and high speed skip access etc. only by cont-rolling the module selection signal transfer mode between the memory elements.
Broadly stated, the present invention provides a display device having a structure combining a plurality of display modules comprising a plurality of display picture elements and semiconductor active elementseach operatively connected to one of said display picture elements, wherein each display module further comprises a semiconductor substrate, as the basic material, cut in such a size as to contain semiconductor active elements cor-responding to a picture element required for display of a character or a plurality of characters.
According to another aspect, the invention provides a display device, operatively connectable to receive a module selection signal and an address I 1~9~
signal, coml-risi~ a r)luralitv of displ.ly modules each of which comprise a disl-lay mCd;UIII; a pl.urality of l-;.cturc clcment electrodes arranged facing said display mcdi~ ; and activc clelllcnts, each operatively connected to one of sai.d picture elcmeTIts, for selcctivc driving corresponding to said picture element clectrodes; wllerci.n cach display module furtller comprises: a first input tcrmi~ l for receiving thc module sclection signal; a second input terminal for receiving the address signal; and an address circuit, operatively connected to said second input terminal and to said active elements, distributing said address signal to said active elements, wherein sai.d display device further includes a memory element, operatively connected to said first input terminal, for receiving said module selection signal for each display block which comprises at least a unit of one display module, and wherein sequential control of a storing condition of said memory elements selectively enables driving of dis-play modules for the corresponding display block.
The invention will now be described in greater detail with reference to the accompanying drawings~ in which:
Figure 1 is the sectional view of a display module which is the main component of the present invention;
Figure 2 is a plan view to a larger scale explaining a method of for-ming an IC chip to be used in the display module;
Figure 3 is a schematic view indicating an example of the structure of the dri.ve circuit to be integrated;
Figure 4 is a diagrammatic perspective view indicating an example of -3a-
It is an object of this LnventiOn to provide a new structure of flat panel display which can be manufactured economically with a high yield and overcome the abovementioiled problems.
It is another object of this invention to provide a modular type solid state display device whi.ch easily allows realization of a large size display structure and simple maintenance.
It is further object of this invention to provide a modular type large scale flat panel display device.
Briefly, the present invention is based on obtaining firstly basic elements by forming small size display modules each including a plurality of picture elements and the display screen of the required area is then obtained by using one mode or by combining a plurality of such display modules. The display modules should be of a size which permits easy manufacture of the cir-cuit function elements to be integrated without any defects and desirably should be determined to a scale, which permits for example, 16 x 16 picture elements or more to be obtained which is required for dot matrix display of one character. In addition, according to a preferred embodiment of the pre-sent invention, the display module is basically composed of IC chips each of which integrates the picture element electrodes which face the display medium and determine the picture elements arranged in the form of a matrix, the 1 15~17() activc clcmcnts ~for sclect~;vc clriving correspollding individually to each pic-turc elemcnt electrode and in addition the address circuit which receives scr;ally on timing the information signals (data signals) corresponding to the patterns to be displayecl ancl clistributes these signals to said active elements.
Morcover, that the complication of connecting lead wires when a plurality of d;splay modules are comhined and moullted is avoided as much as possible.
According to a speci~ic aspect of the invention, the memory element which stores module selection signals for display module of the relevant dis-play block is provided for each said display block arranged in units of one or plural display modules whicl~ form a large scale display screen, and it is enabled to selectively drive the corresponding display modules with an output of said memory element. Particularly when, in this case, the memory elements for plural display blocks are connected in series in order to sequentially transfer the module selection signals, the access to the display modules can be sequentially and adequately controlled in accordance with the display con-tents such as sequential access and high speed skip access etc. only by cont-rolling the module selection signal transfer mode between the memory elements.
Broadly stated, the present invention provides a display device having a structure combining a plurality of display modules comprising a plurality of display picture elements and semiconductor active elementseach operatively connected to one of said display picture elements, wherein each display module further comprises a semiconductor substrate, as the basic material, cut in such a size as to contain semiconductor active elements cor-responding to a picture element required for display of a character or a plurality of characters.
According to another aspect, the invention provides a display device, operatively connectable to receive a module selection signal and an address I 1~9~
signal, coml-risi~ a r)luralitv of displ.ly modules each of which comprise a disl-lay mCd;UIII; a pl.urality of l-;.cturc clcment electrodes arranged facing said display mcdi~ ; and activc clelllcnts, each operatively connected to one of sai.d picture elcmeTIts, for selcctivc driving corresponding to said picture element clectrodes; wllerci.n cach display module furtller comprises: a first input tcrmi~ l for receiving thc module sclection signal; a second input terminal for receiving the address signal; and an address circuit, operatively connected to said second input terminal and to said active elements, distributing said address signal to said active elements, wherein sai.d display device further includes a memory element, operatively connected to said first input terminal, for receiving said module selection signal for each display block which comprises at least a unit of one display module, and wherein sequential control of a storing condition of said memory elements selectively enables driving of dis-play modules for the corresponding display block.
The invention will now be described in greater detail with reference to the accompanying drawings~ in which:
Figure 1 is the sectional view of a display module which is the main component of the present invention;
Figure 2 is a plan view to a larger scale explaining a method of for-ming an IC chip to be used in the display module;
Figure 3 is a schematic view indicating an example of the structure of the dri.ve circuit to be integrated;
Figure 4 is a diagrammatic perspective view indicating an example of -3a-
3 1~7il tlle structur~ o~ .- la~ c.~ displ.ly device;
I:igures Sa alld 5b sllo~ two other cxamples of the address circuit integrated on a ch~
ligu-e 6 is the partlally cut-away perspective view indicating an-other exalllple of thc structure of a large scale display device;
I:igure 7 is the schelllatic view of another integrated circuit struc-ture of an IC chip wllich is used as the basic element of the display module;
I:igure 8 shows the circuit s-tructure of a modular display device using a plurality of clisplay modules;
Figure 9 and Figure 10 are timing charts for explaining the opera-tions of the moclular display device shown in Figure 8;
Figure 11 shows the circuit structure of another type of modular display device according to the invention;
Figure 12 is a timing chart for explaining the operation of the modular display device shown in Figure 11.
Figure 1 indicates schematically the structure of a display module which is used as the basic unit of the display device of the present invention.
~'he module 1 as a whole is structured as a stacked element comprising an insulating substrate 4 in which are mounted connecting pins 2 and 3; a semi-conductor IC chip 6 integrating required corresponding driving circuit elementswhich provide picture element electrodes 5 arranged in the form of a matrix as will be described later; a display medium 7, for example liquid crystal; and a glass cover 9 providing a transparent electrode 8 on its underside. Such a stacking structure itself is substantially equivalent to the conventional dis-play device of this type comprising active elements but the structure dis-closed by the present invention is different from the conventional one in that the relevant stacking element itself is formed as a small scale display module 1 1 5 t~
ccll)a~lc of` d.isp~aying a sill~Lc CharaCter~ or several characters a,nd the add-ress functioT~ ,is aJso incor])oratcd in it.
,\s an e~a~ )1c, the I(: chil) 6 has a size as large as 5.3mm square which is obtained by dividing l~ngituciillally and laterally a 3 inch character siLicon wa~er 10 as showll in ligllre 2 into l/lOths. This chip provides the circuit functions l~e~lu,i,re(l t'or controlling the display of one character. The dot matrix type clla~acter fon~ usually emp10ys a 7 x 9 dot picture element for the alpllarlumerics ancl also a 16 x 16 dot picture element which is sufficient even for Chinese characters. 'I`herefore, it is enough to integrate the selective driving functions oL 24 x 24 picture elements per chip for the dis-play of characters even including the cursor di,splay and the space between characters and such integration can be realiæed with comparative ease. In addition, according to such element structure, the whole wafer or sheet is divided up and is not used as a unitary structure since any defective chips can be discarded thus minimizing the loss.
Figure 3 shows an example of the structure of the driving circuit integrated onto IC chip 6 for a 5 x 7 dot picture element structure. In Figure 3, Pll, P12, ...., P75 are picture element electrodes which are mutually insulated and formed on the silicon substrate and having a small area corresponding to the arrangement of 5 x 7 matrix picture elements and these are respectively connected to the drain electrodes of field effect transistors (FET) Qll' Q12' ------J Q75 used as the active elements for selective driving.
The source electrodes of these FETs are connected to the common source ele-trode terminal V5s and the gate electrodes are connected to the outputs of respective stages of a shift register SR for address via the common control gate electrode CG. In this case, the shift register SR as the address circuit has the structure of a series of static shift registers which are arranged in i 1~'317t~
a nleandcr folm l3cLi~cell thc lillc~; of the piCtUT`L` element electrode. ln addition t.he information -~ign.~ t.l) in~ t ter~ l and the clock signal input tcrlll.LIlal Cl., are l~rovl~ed first stage "~hile the end terminal En is provided at th~ f.inal ~ta~re.
I`he IC chip 6 con~l)ris:ing such Cil`CUit function can easi.ly be pro-duced by making nse Or the cur:rent sem:iconcluctor technology, particularly MOS
process teclmology. Ihus, a displ~.Ly moclule 1 as shown in Figure 1 can be com-yleted by hermetically sea:ling the display medium, for example, the liquid crystal laye:r, with the glass covc-:r 9. Portions of the module other than the picture element electrodes Pll ...., P75 is covered with the insula-ting film.
The various terminal from the IC chip 6 can be connected easily with the lead pins 2, 3 the chip i.s mounted on the supporting substrate 4.
Thus, a 5 x 7 dot matrix picture element using liquid crystal as the display medlum is defined on the area opposed to the transparent electrode 8 inside the glass cover 9 and the picture element electrodes Pll to P75 on the IC chip 6. When the specified driving voltage is applied between the trans-parent electrode 8 and the common source electrode terminal Vss of the IC chip 6, and when the information signal being set to each stage of the shift register SR by giving the transfer signal to the control gate electrode CG is 0 applied to the respective gate electrodes of the corresponding FETs: Qll to after the information signal corresponding to the character pattern to be displayed is input in series from the input terminal In of the shift register SR, the selected F~Ts become ON and the corresponding picture element elec-trodes are driven, and as a result, the desired character pattern is displayed.
The embodiment explained above is the display module which is the basic element of the present invention, but a large scale flat panel display device can be formed easily by combining a plurality of such display modules.
l 15'317i~
I:igl11e ~ is a perspec~ive view showi1lg the structure of such a large scale d1s~ y dev1cc, whcrei11 Lhe disp1ay area, 30 times that of a single dis-ylay moduie, ca1~ be obtaille(1 by n1ounti1lg a total of 30 display modules (5 x 6) D~!ll, 1)MI " ...., 1)~15( on t1~e commo11 mounti1lg substrate ll. Although not limited, eac11 individua1 disL~MLy IllC)dUie has, for example, the structure explai1led previously in rcg~1d to 1igure l and provides selectable matrix pic-ture eleme1lt arrangem~11t in u11its of one character or more for one block. On the mounting substrate ]l, connecting holes or sockets ~not illustrated) are provided for receiving the connectlng pins 2, 3 of respective display modules and moreover on the substrate ll, the wiring conductors for connecting and distributing the required signals and power sources are laid in the form of matrix by means of the well known multi-layer printed wiring technology, corresponding to the mounting locations of respective display modules DMll to DM65. In addition, on the mounting substrate ll, the chip select circuit or decoder circuit (not illustrated) may be mounted in order to selectively drive respective display modules. As a connecting structure for mounting each dis-play module on the substrate ll, a variety of connecting structures may be emyloyed in addition to the use of connecting pins.
In case of employing the abovementioned module combination structure, when the address circuit accommodated on the IC chip of each module is the shift register having the one meander line as indicated in Figure 3, it is very convenient for simplifying the circuits mounted. In particular, the dis-play data signal for the total display screen can be applied from the single input terminal and data distribution to individual display modules becomes very easy by connecting in series the input/output terminals In and E of the shift registers included in the adjacent display modules. 11owever, when the display screen further increases in size, requiring an increased number of 3 1 7 ~
~is~ y modulc~ to l)e moullted, eollnectiolls can also be made by dividing the irlput Ulllt 0~ i.isl)l.ly ~lclta Into each l,ine Ol~ bi,ock (plural modules). At any ate, sillce each displ.ly mo~ulc comprises the acldress circuit of the time series .inpul, format, tlle connect.ing work for mounting the display modules in orcler to ~orm a large scale clisplay screen can be done easily.
~ lus, accorcl.i.ng to the struc-ture combining di,splay modules as shown in F:igure ~, a display panel of the desired size can be obtained in accordance with the number of modules to be combined~ Even when a display fault or func-tion deterioration may be generated, the total quality can be maintained and economical maintenallce work can be assured only by replacing the relevant defective display module.
The IC chip of each display module is not limited only to the integration of required circuit function elements on the abovementioned silicon substrate and can be structured as an SOS structure utilizing a sapphire substrate or TFT structure using other insulating substrate. In addi-tion, the address circuit which is integrated together with the active ele-ments for driving corresponding to picture elements is capable of employing a variety of structures in addition to that shown in Figure 3.
Figure 5(a) and (b) are block diagrams indicating modifications of such an address circuit. In Figure 5(a), the gate electrodes of active ele-ments Q arranged corresponding to the picture element electrodes are connected in the row (lateral) direction while the source electrodes are connected in the column(longitudinal) direction, and thereby the shift register SR 1 for data input in the row side and the shift register SR 2 for scanning in the column direction are provided. Figure 5(b) shows an example of the structure of the address circuit providing the shift register SRl for serial-to-parallel conversion and branching registers SR2 to SRn which are connected in parallel ~15'~7~i to eacll stage ~ d e~telld Ml tlle longitudinal dlrectiom 50 that addressing is pelforlDed ~on each col.umn ol` the active elements corresponding to the picture element elect:rodec.
.~ p:ract.i.ca.l c.ircul t structure of the shift register for addressing is not illustrated, I)ut :it call be formed as the well known single phase static shift reglster or 2-phase dyllalll.ic shift register. Moreover, it can be inte-grated as the shiXt register having the structure of charge transfer type CCD, BBD or PCD~ In case such shift register as the address circuit occupies a large area on the IC chip and thereby the size of picture element electrode and the space for mounting are limited, it is recommended to dispose the pic-ture element electrode via an insulating film on the circuit function element surface using the multilayered wiring technique.
~ s the display medium, an EL, ECD or LED may be used in addition to the liqui.d crystal indicated previously. Moreover, simple modification allows formation of a gas discharge type or fluorescent display tube type display device.
When the display module is formed of a fluorescent display tube type, the fluorescent substance has to he coated on each picture element elec-trode to be used as the anode and sealed under vacuum condition together with the common filament for the emissi.on of electrons.
~ he display modules of the present invention, can be used to obtain easily a large scale display device by combining a plurality of modules as ex-plained previously. In such a case, all of the required modules can be mounted on the single mounting substrate 11 as shown in Figure 4. In addition to this technique, a sub-unit may be formed by firstly mounting the modules in the required numbers on a supporting substrate by a similar method and then expanding the display screen gradually by mounting a plurality of such sub-g_ 1 15917~
Ullits on all~hel` ~;ubstratc. I~'hCII ~Isin~ SUC]I .3 sub-unit or interim unit struc-ture, it i; reco~ c!ll(led t:o coll~`igllr<lte only the lC chips in Ullits of character or l~lock alld thell asscmblc the structure of tlle clisplay medium and glass cover provided therco]l by st;lckillg them in common for each sub-unit.
i jgUI~e 6 jS thc par~:ialLy cut-.lway perspective view of an embodiment indicatillg a disp1ay ~levice employino the sub-un:it structure. In this figure, On the sub-ullit substl~ate 21, a plur<llity of IC chips 22 in-tegrating picture element electrodes, active e1erllents corresponding to them and the address cir-cuits as e~plained above arc bonded and thereafter a sub-unit SU is structured by providing thereoll the comrnon disp1ay medium layer 23 and the glass cover 24 providing hermetical sealing. The connecting leads for the IC chips are con-centrated on the sub-unit substra-te 21 and are then led out to the connecting pin 25~ and moreover tllese lead wires are connected to a bus (not illustrated) on the master substrate 26 together with plurality of sub-units. Of course, a display module or sub-unit can be formed in the desired size and shape and the desired display can be obtained by combining different shapes and sizes of therrl.
As explained above, the primary feature of the present invention is found in economically offering a large scale display device employing compara-tively small scale display modules which can easily be produced without de-fects as the basic unit of construction. An embodiment of a circuit structure which may to advantage be obtained using a combination of plural display modules is explained hereunder.
Figure 7 shows basically the module circuit structure where the ele-ments for giving the module selection function are added to the IC chip com-prising the row and column shift registers as shown in Figure 5 (a).
In Figure 7, P11~ P12J .... ~ P75 are the picture element electrodes ~ 15~7(~
WhiCIl .IL`C lilUtllal l\' illsUIat:cd .311d fOrllled 011 the silicon substrate 30 of the specjfied size in 5uc}l a mallller as correspondiilg to the 5 x 7 dot matrix pic-ture elemellt arrangelll~nt and these are connected to the drain electrodes of the field effect transistoL~s (1:l.l`) Qll~ Ql2~ ~ Q75 respectively as the active elements for sclective driving. The source electrodes of these FETs for drivillg are conilected to the character clata shift register 31 via the com-moll X conductor in each column in the longitudinal direction. This character data shift register 31 has an input terminal 32 for character data signal CS, an input terminal 33 for character data signal catch timing signal (CTS) and an output terminal 34. The gate electrodes of FETs for driving are connected to the outputs of respective A~D ga-te circuits 35 via the common Y conductor in each row in the lateral direction. One input of each AND gate circuit 35 is connected with the scan shift register 38 providing an input terminal 36 for scan signal SS and an input terminal 37 for scan signal catch timing signal STS, while the other input of each gate 35 is led out to the input ter-minal 39 of the modulc selection signal MAS.
Figure 8 outlines an embodiment of a modular display device wherein a plurality of single character modules as explained above are arranged long-itudinally and laterally. In this case, a total of 256 display modules DMl to DM256 is arranged in the form of a matrix of 32 columns and 8 rows in order to form the display screen of 32 characters x 8 rows. The 32 display modules DMl-DM32,...., DM225-DM256 of each row are respectively moùnted on the common sub-unit substrate, thus forming the display blocks DBl to DB8 in respective rows, and the terminals 33, 36, 37 and 39 of display modules included in each block are connected in common in each row. In addition, the character data shift register 31 in each display module is connected in series to the input terminal 32 of the adjacent register via the output terminal 34.
1 ~ t) ~
~ cll oL` disl~la~ l)locks r~BI to l)B8 Is provi.ded rcspectively wlth a mellloly elelllellt ~ Il. to M~ modul.c selectioll which is a feature of -the ~lescnt invclltioll. In -thc c~lse of tile em~od.iment shown in the :Eigure, th:is memory element .i.s strllctul-e(l wi.th a so-cal.lecl J-K fL:ip-flop (E:l~ ci-rcuit, having an input ter~ la~ OI tile sclectioll signal, an :input terminal CL for the tim.ing signal whicll .in~stlucts the catcll of the relevant selecti.on signal, an input termillal K for the .i.nverted signal ancl an output terminal Q for the selection signal. I`he termina.l J of the memory element MAM 1 associated with the display block DM l of the 1st row is connected with the terminal 40 for inputt:ing -the module selection i.nstruction signal MSS, while said MSS term:inal 40 is also connected the terminal K via the invertor IN. Moreover, the output terminals Q of the memory elements are connected in common to the module selection signal input terminal 39 of the display modules included in the corresponding row block and simultaneously is cascade-connected to the J input terminal of the memory element MAM 2 in the ne~ct row. Therefore, eight memory elements MAM 1 to MAM 8 as a whole have the structure of eight stages of a shift register and the module selection instruction signal to be input to the J terminal of the 1st memory element MAM 1 from the MSS terminal 40 can be transferred sequentially by the timing signal TTS for catching a signal which is applied in common to the CL terminal of each element from the terminal 41 In the device of Figure 8, the input terminals 32 of the character data for the display module of the 1st column of each row are connected in parallel to the input terminal 42 of the character data signal CS, and more-over the terminals 33, 36 and 37 of the display modules connected in common on the sub-unit substrate in row units are also connected in common as a whole and then led out to the terminal 43 for the character data catch timing signal CTS, terminal 44 for the scan signal SS and the terminal 45 for the scan 7 ~-~
sigIuLl c~ItcIl tim.iIIg siIlai ~ hUS, the disI)lay device shown in Figure 8 h~s, a total vf six sign~-I in~ut term:inals.
Ihe operation o~ su(II a moclular rlisplay device will now be explained w.ith refereIlce to ~igure 9 ~hi.cII shows the ti.ming chart relating to the line sec~uential acccss method. TIIe signal wavefo:rms are indicated with labels cornespondiIlg to the signal labcLs given to the signal input terminals of the device shown in I:iguIe 8.
When the modllle selectiolI instruction signal MSS is input from the external interface circu:it at term:inal 40, this signal is then applied to the J terminal of the memory element MAM 1 having the FF circuit structure con-nected to the display block DB 1 of the 1st row and kept in the storing condi.--tion at the falling edge of the timing signal TrS. Thus, the memory element ~1 1 outputs the module selection signal MAS 1 as logic "1" from the terminal Q. This selection signal MAS 1 is applied in common to the module selection signal input terminal 39 of the 32 display modules included in the display block of the 1st row, thus opening the A~D gate 35 for allowing the scan signal to pass and enabling the supply of scan signal to the driving elements.
The character data signal CS is input to the terminal 42 from the external interface circuit and then applied to the input terminal 32 of the character data shift register 31 included in the display module of the 1st row. At this time, the character data signal CS is sequentially caught by the shift registers which are cascade-connected for each row by the data catch timing signal CTS which is given to the terminal 33 from the terminal 43.
Thus, the character data signal train stored first corresponds to the information to be displayed on the heading display line of the display block of the 1st row.
On the other hand, the scan signal SS sent from the terminal 44 is 5~17~1 pliecl ~o the ini;ut ~orminill 3C of the scarl silift register 3c~ and this sigrlal CaUg~lt ~y the ~ illg c~dge 0~ the catch timing signal SlS se~t from the tcrlllincll 4~i. Ihcleat~tel~ this scan signal is sequentially transferred by the sc~n timillg sigllal Sl( (th.` sigllai line is not illustrated) and sequentially scans the ~ conductor ot` t llC -~even ~ines in synchronization with the address oper.ltioll by the cllaractel clat:a signal. In other words) the scan address signal SAS 1 is a~plied througll the ~ND gate circuit 35 so -that the gate ele-ctrodes of lETs for clriving oi the 1st line of the display modules DMl to DM32 of the 1st row are controlled to the ON state by the heading pulse of the scan timing signal STC~ and simultaneously the FETs selected in accordance with the data address signal applied from the character data shift register 31 select-ively drive the picture element electrodes of the heading line. Succeedingly, in order to selectively clrive the 2nd display line of the display block DB 1 of the 1st row, the new character data signal CS is controlled by the catch timing signal CTS and input to the character data shift register 31 in series.
Meanwhile, the scan signal in -the scan shift register is shifted for one bit by the scan timing signal STC, outputting the signal SAS 2 and the picture element electrodes of the 2nd line are selectively driven by these address signals. Thereafter, in the same way, the picture element electrodes of the seven lines of the 1st row are sequentially driven and the character informa-tion of the 1st row is displayed.
As e~plained above, while the display block DB 1 of the 1st row is driven by the module selection signal MAS 1, the character data signal CS, scan signal SS and signal catch timing signal CTS, STS are applied in common to the display blocks of the 2nd and succeeding rows. However, in the display blocks of these 2nd and succeeding rows, an output of the corresponding memory elements for module selectiorl is logic "0", and thereby the AND gate circuit ~ 1S917~) 35 lnserted to the output si~ of the scall shift register of the ~isplay modu1es is closed. 5`or this reaso]~, the scan address signal is not allowed to pass thl~ougll the gate el~ctrodcs of IEIs for clriving, disabling the actual d~ g operation.
When tlle drivillg operation t`or the 1st row is completed, the timing signal l`'l`S for catc~ lg the module selection signal is generated and thereby the module selection signal MAS ] for the ls-t row is caught by the memory ele-ment ~IAM 2 corresponding to the display blocks of the 2nd row. Thus the MAM 2 generates the module selection signal MAS 2 of the 2nd row from its terminal Q. This module selection signal MAS 2 enables the driving of display blocks of the 2nd row. Thus, these blocks are sequentially addressed from the head-ing line as in the case of the 1st row. As explained above, the module selec-tiOI1 signals are sequentially transferred between the memory elements corres-ponding to the rows and the display blocks in unit of row are selectively driven on time series. Thereby the display of a single display screen is completed.
Meanwhile, in case there are spaces in displays in the line sequen-tial access method as mentioned above, speed-up of display can be realized by skipping the address operation at the relevant space line. Figure 10 shows the timing chart for explaining such skip access operation, wherein the signal waveforms for skipping the scan address of the 3rd and 4th rows are indicated particularly.
In Figure 10, after the display blocks of the 1st and 2nd rows are sequentially driven by the module selection signals MAS 1 and MAS 2, the con-trol is carried out in such a way that the succeeding scan signal catch timing signals STSs are suppressed by the signal catch timing signal TTS (the 3rd pulse) for shifting the signal MAS 2 in the preceding stage to the 3rd memory 1 15917n elelllell~ M,~l 3. I`hereattel, ~Ifter the tLming signal ITS (the 4th pulse) is applied in order to tlallsfel tllc mod~lle selection signal ~S 3 to the memory elemc~llt ~M ~l of ~he llext ro~, the control is carried out in such a way that the next scall sigrlal catcll timLng signal LS suppressed by the relevant signal.
W}lell the time interval of ~lle timing signal Eor storing the module selection signals to the melllory elelllellt is curtailed and simultaneously the scan signal catch timing sigllcLl SlS durillg such period is suppressed, the skip operation call be after all realized because the module selection signals MAS 3 and MAS 4 are generated but an Outpllt of the scan shift register does not become effec-tive.
In the above explanation, the sequential access and skip access in row units are realized by providing the memory elements of module selection signals corresponding to rows and executing the logic operations with the module selection signal sent from said memory elements and an output signal of the scan shift registers; however, a variety of access systems can be employed by adequately setting the inter-relation between the display modules and dis-ylay blocks and adding the memory elements for required blocks.
Figure 11 shows an embodiment of a display device using the character sequential access method. In this figure, nine display modules DMll to DM33 are arranged in the form of a 3 x 3 matrix for simplification. The display modules are structured such that the FF memory elements MAMll to MAM33 are integrated on the IC chip for driving and these are connected in series for each row on the sub-unit which is not illustrated. In addition, as in the case of the embodiment shown in Figure 8, the FF memory elements MAMl to MAM3 for row block selection are provided corresponding to each row, and the Q ter-minal outputs of these memory elements are colmected to the 1st J input ter-minals of said memory elements corresponding to modules connected in series ~ 1S9~7t~
~01 CL1CII rOW~ 1e OtllOr II.LII~ t:hcy ~ e a~so connected to the J terminalsof thc row selectioll 111el110rY clements correspollding to the next row, thus ena~ling sigllaL ~rallsfel. Tn additiorl, the fetch and transfer of signal for tlle row selcctioll Inelllory elemerlts ~Ml to MAM3 are controlled by the timing signal IlS serlt from the terlllillal 41 alld the fetch and transfer of signal for the module selection memory e~ements M.~lll to MAM33 are controlled by the timing signal MTS sent trom the terminal 46. The signal lines for data and scan sides are not illustrated for simpl fication, but they are the same as those of an em~odiment sllowll in Figure 8. Therefore, as the display device of Figure 11, only one input terminal 46 of the timing signal MTS is added.
According to the structure of Figure 11, the sequential access and high speed skip access for each character (module) are possible and the optimum operation mode can be set in accordance with display contents.
Figure 12 shows the timing chart for explaining such operations. In this case, the display modules DM11, 12,23,31,32 indicated as the hatched portions of Figure 11 are selectively driven and the remaining modules are skipped.
Thus, after the module DMl2 is selectively driven by the module selection signal ~S12, the timing signal MTS for sending the relevant selec-tion signal to the next molule DM13 is thinned and the row selection signal ~Sl is proceeded to the next row by the other timing signal TTS, and moreover the selection signal MAS 2 of the 2nd row is transferred up to the memory ele-ment M~M23 of the module M23 by the timing signal MTS which is controlled at a high speed, thus selectively driving the relevant module. In this case, although not indicated in the figure, the character data is input character by character in common for all modules in accordance with the scanning sequence and only the modules for which the logic gates in the scan address or data address side are opened by the said module selection signal are driven effect-ively. -17-1 159~
I`he pLillci~)al cml)odilllcllt~ o~ tlle prescnt :invcntion are explained al)ovc, hut a val.iety o.t`lllodificat~ s and expa.nsions are possible for those s~i.ll.ed ill this :t.ie kl. I:or c~alllplc, thc disc)lay module structure may include tile piCtUL'e Clf`lllerlt ill Ull:i t'; of.` one or more characters. In add:ition, as for t:hc selection of` displ.ly moduLcs, it is na-turaily possible to select the block arr.lngcd in rows but it .is aLso possil)le to emp.l.oy other freely determined bloch forlllats. Of coursc i t :is possible to select module by module. Further-more the circult structurc integrclted on the semiconductor substrate of each module i.s capable of .introducing a memory driving system where a capacitor for accumulating the signa.L is provided to the active elements for driving, :in addition -to the ref:resh system as indicated above.
A solid state flat panel display having a large display screen can be configu:rated very easily using the present invention.
In addition, a display device as a whole can be configura-ted very economically because wiring and interface of control can be made very easily, and excellent functions such as sequential access and high speed skip access etc. assure the setting of optimum operation mode in accordance with display contents. Thus, the present invention is very effective for adopting a dis-play device comprising driving circuits into the character display device for computer terminals.
I:igures Sa alld 5b sllo~ two other cxamples of the address circuit integrated on a ch~
ligu-e 6 is the partlally cut-away perspective view indicating an-other exalllple of thc structure of a large scale display device;
I:igure 7 is the schelllatic view of another integrated circuit struc-ture of an IC chip wllich is used as the basic element of the display module;
I:igure 8 shows the circuit s-tructure of a modular display device using a plurality of clisplay modules;
Figure 9 and Figure 10 are timing charts for explaining the opera-tions of the moclular display device shown in Figure 8;
Figure 11 shows the circuit structure of another type of modular display device according to the invention;
Figure 12 is a timing chart for explaining the operation of the modular display device shown in Figure 11.
Figure 1 indicates schematically the structure of a display module which is used as the basic unit of the display device of the present invention.
~'he module 1 as a whole is structured as a stacked element comprising an insulating substrate 4 in which are mounted connecting pins 2 and 3; a semi-conductor IC chip 6 integrating required corresponding driving circuit elementswhich provide picture element electrodes 5 arranged in the form of a matrix as will be described later; a display medium 7, for example liquid crystal; and a glass cover 9 providing a transparent electrode 8 on its underside. Such a stacking structure itself is substantially equivalent to the conventional dis-play device of this type comprising active elements but the structure dis-closed by the present invention is different from the conventional one in that the relevant stacking element itself is formed as a small scale display module 1 1 5 t~
ccll)a~lc of` d.isp~aying a sill~Lc CharaCter~ or several characters a,nd the add-ress functioT~ ,is aJso incor])oratcd in it.
,\s an e~a~ )1c, the I(: chil) 6 has a size as large as 5.3mm square which is obtained by dividing l~ngituciillally and laterally a 3 inch character siLicon wa~er 10 as showll in ligllre 2 into l/lOths. This chip provides the circuit functions l~e~lu,i,re(l t'or controlling the display of one character. The dot matrix type clla~acter fon~ usually emp10ys a 7 x 9 dot picture element for the alpllarlumerics ancl also a 16 x 16 dot picture element which is sufficient even for Chinese characters. 'I`herefore, it is enough to integrate the selective driving functions oL 24 x 24 picture elements per chip for the dis-play of characters even including the cursor di,splay and the space between characters and such integration can be realiæed with comparative ease. In addition, according to such element structure, the whole wafer or sheet is divided up and is not used as a unitary structure since any defective chips can be discarded thus minimizing the loss.
Figure 3 shows an example of the structure of the driving circuit integrated onto IC chip 6 for a 5 x 7 dot picture element structure. In Figure 3, Pll, P12, ...., P75 are picture element electrodes which are mutually insulated and formed on the silicon substrate and having a small area corresponding to the arrangement of 5 x 7 matrix picture elements and these are respectively connected to the drain electrodes of field effect transistors (FET) Qll' Q12' ------J Q75 used as the active elements for selective driving.
The source electrodes of these FETs are connected to the common source ele-trode terminal V5s and the gate electrodes are connected to the outputs of respective stages of a shift register SR for address via the common control gate electrode CG. In this case, the shift register SR as the address circuit has the structure of a series of static shift registers which are arranged in i 1~'317t~
a nleandcr folm l3cLi~cell thc lillc~; of the piCtUT`L` element electrode. ln addition t.he information -~ign.~ t.l) in~ t ter~ l and the clock signal input tcrlll.LIlal Cl., are l~rovl~ed first stage "~hile the end terminal En is provided at th~ f.inal ~ta~re.
I`he IC chip 6 con~l)ris:ing such Cil`CUit function can easi.ly be pro-duced by making nse Or the cur:rent sem:iconcluctor technology, particularly MOS
process teclmology. Ihus, a displ~.Ly moclule 1 as shown in Figure 1 can be com-yleted by hermetically sea:ling the display medium, for example, the liquid crystal laye:r, with the glass covc-:r 9. Portions of the module other than the picture element electrodes Pll ...., P75 is covered with the insula-ting film.
The various terminal from the IC chip 6 can be connected easily with the lead pins 2, 3 the chip i.s mounted on the supporting substrate 4.
Thus, a 5 x 7 dot matrix picture element using liquid crystal as the display medlum is defined on the area opposed to the transparent electrode 8 inside the glass cover 9 and the picture element electrodes Pll to P75 on the IC chip 6. When the specified driving voltage is applied between the trans-parent electrode 8 and the common source electrode terminal Vss of the IC chip 6, and when the information signal being set to each stage of the shift register SR by giving the transfer signal to the control gate electrode CG is 0 applied to the respective gate electrodes of the corresponding FETs: Qll to after the information signal corresponding to the character pattern to be displayed is input in series from the input terminal In of the shift register SR, the selected F~Ts become ON and the corresponding picture element elec-trodes are driven, and as a result, the desired character pattern is displayed.
The embodiment explained above is the display module which is the basic element of the present invention, but a large scale flat panel display device can be formed easily by combining a plurality of such display modules.
l 15'317i~
I:igl11e ~ is a perspec~ive view showi1lg the structure of such a large scale d1s~ y dev1cc, whcrei11 Lhe disp1ay area, 30 times that of a single dis-ylay moduie, ca1~ be obtaille(1 by n1ounti1lg a total of 30 display modules (5 x 6) D~!ll, 1)MI " ...., 1)~15( on t1~e commo11 mounti1lg substrate ll. Although not limited, eac11 individua1 disL~MLy IllC)dUie has, for example, the structure explai1led previously in rcg~1d to 1igure l and provides selectable matrix pic-ture eleme1lt arrangem~11t in u11its of one character or more for one block. On the mounting substrate ]l, connecting holes or sockets ~not illustrated) are provided for receiving the connectlng pins 2, 3 of respective display modules and moreover on the substrate ll, the wiring conductors for connecting and distributing the required signals and power sources are laid in the form of matrix by means of the well known multi-layer printed wiring technology, corresponding to the mounting locations of respective display modules DMll to DM65. In addition, on the mounting substrate ll, the chip select circuit or decoder circuit (not illustrated) may be mounted in order to selectively drive respective display modules. As a connecting structure for mounting each dis-play module on the substrate ll, a variety of connecting structures may be emyloyed in addition to the use of connecting pins.
In case of employing the abovementioned module combination structure, when the address circuit accommodated on the IC chip of each module is the shift register having the one meander line as indicated in Figure 3, it is very convenient for simplifying the circuits mounted. In particular, the dis-play data signal for the total display screen can be applied from the single input terminal and data distribution to individual display modules becomes very easy by connecting in series the input/output terminals In and E of the shift registers included in the adjacent display modules. 11owever, when the display screen further increases in size, requiring an increased number of 3 1 7 ~
~is~ y modulc~ to l)e moullted, eollnectiolls can also be made by dividing the irlput Ulllt 0~ i.isl)l.ly ~lclta Into each l,ine Ol~ bi,ock (plural modules). At any ate, sillce each displ.ly mo~ulc comprises the acldress circuit of the time series .inpul, format, tlle connect.ing work for mounting the display modules in orcler to ~orm a large scale clisplay screen can be done easily.
~ lus, accorcl.i.ng to the struc-ture combining di,splay modules as shown in F:igure ~, a display panel of the desired size can be obtained in accordance with the number of modules to be combined~ Even when a display fault or func-tion deterioration may be generated, the total quality can be maintained and economical maintenallce work can be assured only by replacing the relevant defective display module.
The IC chip of each display module is not limited only to the integration of required circuit function elements on the abovementioned silicon substrate and can be structured as an SOS structure utilizing a sapphire substrate or TFT structure using other insulating substrate. In addi-tion, the address circuit which is integrated together with the active ele-ments for driving corresponding to picture elements is capable of employing a variety of structures in addition to that shown in Figure 3.
Figure 5(a) and (b) are block diagrams indicating modifications of such an address circuit. In Figure 5(a), the gate electrodes of active ele-ments Q arranged corresponding to the picture element electrodes are connected in the row (lateral) direction while the source electrodes are connected in the column(longitudinal) direction, and thereby the shift register SR 1 for data input in the row side and the shift register SR 2 for scanning in the column direction are provided. Figure 5(b) shows an example of the structure of the address circuit providing the shift register SRl for serial-to-parallel conversion and branching registers SR2 to SRn which are connected in parallel ~15'~7~i to eacll stage ~ d e~telld Ml tlle longitudinal dlrectiom 50 that addressing is pelforlDed ~on each col.umn ol` the active elements corresponding to the picture element elect:rodec.
.~ p:ract.i.ca.l c.ircul t structure of the shift register for addressing is not illustrated, I)ut :it call be formed as the well known single phase static shift reglster or 2-phase dyllalll.ic shift register. Moreover, it can be inte-grated as the shiXt register having the structure of charge transfer type CCD, BBD or PCD~ In case such shift register as the address circuit occupies a large area on the IC chip and thereby the size of picture element electrode and the space for mounting are limited, it is recommended to dispose the pic-ture element electrode via an insulating film on the circuit function element surface using the multilayered wiring technique.
~ s the display medium, an EL, ECD or LED may be used in addition to the liqui.d crystal indicated previously. Moreover, simple modification allows formation of a gas discharge type or fluorescent display tube type display device.
When the display module is formed of a fluorescent display tube type, the fluorescent substance has to he coated on each picture element elec-trode to be used as the anode and sealed under vacuum condition together with the common filament for the emissi.on of electrons.
~ he display modules of the present invention, can be used to obtain easily a large scale display device by combining a plurality of modules as ex-plained previously. In such a case, all of the required modules can be mounted on the single mounting substrate 11 as shown in Figure 4. In addition to this technique, a sub-unit may be formed by firstly mounting the modules in the required numbers on a supporting substrate by a similar method and then expanding the display screen gradually by mounting a plurality of such sub-g_ 1 15917~
Ullits on all~hel` ~;ubstratc. I~'hCII ~Isin~ SUC]I .3 sub-unit or interim unit struc-ture, it i; reco~ c!ll(led t:o coll~`igllr<lte only the lC chips in Ullits of character or l~lock alld thell asscmblc the structure of tlle clisplay medium and glass cover provided therco]l by st;lckillg them in common for each sub-unit.
i jgUI~e 6 jS thc par~:ialLy cut-.lway perspective view of an embodiment indicatillg a disp1ay ~levice employino the sub-un:it structure. In this figure, On the sub-ullit substl~ate 21, a plur<llity of IC chips 22 in-tegrating picture element electrodes, active e1erllents corresponding to them and the address cir-cuits as e~plained above arc bonded and thereafter a sub-unit SU is structured by providing thereoll the comrnon disp1ay medium layer 23 and the glass cover 24 providing hermetical sealing. The connecting leads for the IC chips are con-centrated on the sub-unit substra-te 21 and are then led out to the connecting pin 25~ and moreover tllese lead wires are connected to a bus (not illustrated) on the master substrate 26 together with plurality of sub-units. Of course, a display module or sub-unit can be formed in the desired size and shape and the desired display can be obtained by combining different shapes and sizes of therrl.
As explained above, the primary feature of the present invention is found in economically offering a large scale display device employing compara-tively small scale display modules which can easily be produced without de-fects as the basic unit of construction. An embodiment of a circuit structure which may to advantage be obtained using a combination of plural display modules is explained hereunder.
Figure 7 shows basically the module circuit structure where the ele-ments for giving the module selection function are added to the IC chip com-prising the row and column shift registers as shown in Figure 5 (a).
In Figure 7, P11~ P12J .... ~ P75 are the picture element electrodes ~ 15~7(~
WhiCIl .IL`C lilUtllal l\' illsUIat:cd .311d fOrllled 011 the silicon substrate 30 of the specjfied size in 5uc}l a mallller as correspondiilg to the 5 x 7 dot matrix pic-ture elemellt arrangelll~nt and these are connected to the drain electrodes of the field effect transistoL~s (1:l.l`) Qll~ Ql2~ ~ Q75 respectively as the active elements for sclective driving. The source electrodes of these FETs for drivillg are conilected to the character clata shift register 31 via the com-moll X conductor in each column in the longitudinal direction. This character data shift register 31 has an input terminal 32 for character data signal CS, an input terminal 33 for character data signal catch timing signal (CTS) and an output terminal 34. The gate electrodes of FETs for driving are connected to the outputs of respective A~D ga-te circuits 35 via the common Y conductor in each row in the lateral direction. One input of each AND gate circuit 35 is connected with the scan shift register 38 providing an input terminal 36 for scan signal SS and an input terminal 37 for scan signal catch timing signal STS, while the other input of each gate 35 is led out to the input ter-minal 39 of the modulc selection signal MAS.
Figure 8 outlines an embodiment of a modular display device wherein a plurality of single character modules as explained above are arranged long-itudinally and laterally. In this case, a total of 256 display modules DMl to DM256 is arranged in the form of a matrix of 32 columns and 8 rows in order to form the display screen of 32 characters x 8 rows. The 32 display modules DMl-DM32,...., DM225-DM256 of each row are respectively moùnted on the common sub-unit substrate, thus forming the display blocks DBl to DB8 in respective rows, and the terminals 33, 36, 37 and 39 of display modules included in each block are connected in common in each row. In addition, the character data shift register 31 in each display module is connected in series to the input terminal 32 of the adjacent register via the output terminal 34.
1 ~ t) ~
~ cll oL` disl~la~ l)locks r~BI to l)B8 Is provi.ded rcspectively wlth a mellloly elelllellt ~ Il. to M~ modul.c selectioll which is a feature of -the ~lescnt invclltioll. In -thc c~lse of tile em~od.iment shown in the :Eigure, th:is memory element .i.s strllctul-e(l wi.th a so-cal.lecl J-K fL:ip-flop (E:l~ ci-rcuit, having an input ter~ la~ OI tile sclectioll signal, an :input terminal CL for the tim.ing signal whicll .in~stlucts the catcll of the relevant selecti.on signal, an input termillal K for the .i.nverted signal ancl an output terminal Q for the selection signal. I`he termina.l J of the memory element MAM 1 associated with the display block DM l of the 1st row is connected with the terminal 40 for inputt:ing -the module selection i.nstruction signal MSS, while said MSS term:inal 40 is also connected the terminal K via the invertor IN. Moreover, the output terminals Q of the memory elements are connected in common to the module selection signal input terminal 39 of the display modules included in the corresponding row block and simultaneously is cascade-connected to the J input terminal of the memory element MAM 2 in the ne~ct row. Therefore, eight memory elements MAM 1 to MAM 8 as a whole have the structure of eight stages of a shift register and the module selection instruction signal to be input to the J terminal of the 1st memory element MAM 1 from the MSS terminal 40 can be transferred sequentially by the timing signal TTS for catching a signal which is applied in common to the CL terminal of each element from the terminal 41 In the device of Figure 8, the input terminals 32 of the character data for the display module of the 1st column of each row are connected in parallel to the input terminal 42 of the character data signal CS, and more-over the terminals 33, 36 and 37 of the display modules connected in common on the sub-unit substrate in row units are also connected in common as a whole and then led out to the terminal 43 for the character data catch timing signal CTS, terminal 44 for the scan signal SS and the terminal 45 for the scan 7 ~-~
sigIuLl c~ItcIl tim.iIIg siIlai ~ hUS, the disI)lay device shown in Figure 8 h~s, a total vf six sign~-I in~ut term:inals.
Ihe operation o~ su(II a moclular rlisplay device will now be explained w.ith refereIlce to ~igure 9 ~hi.cII shows the ti.ming chart relating to the line sec~uential acccss method. TIIe signal wavefo:rms are indicated with labels cornespondiIlg to the signal labcLs given to the signal input terminals of the device shown in I:iguIe 8.
When the modllle selectiolI instruction signal MSS is input from the external interface circu:it at term:inal 40, this signal is then applied to the J terminal of the memory element MAM 1 having the FF circuit structure con-nected to the display block DB 1 of the 1st row and kept in the storing condi.--tion at the falling edge of the timing signal TrS. Thus, the memory element ~1 1 outputs the module selection signal MAS 1 as logic "1" from the terminal Q. This selection signal MAS 1 is applied in common to the module selection signal input terminal 39 of the 32 display modules included in the display block of the 1st row, thus opening the A~D gate 35 for allowing the scan signal to pass and enabling the supply of scan signal to the driving elements.
The character data signal CS is input to the terminal 42 from the external interface circuit and then applied to the input terminal 32 of the character data shift register 31 included in the display module of the 1st row. At this time, the character data signal CS is sequentially caught by the shift registers which are cascade-connected for each row by the data catch timing signal CTS which is given to the terminal 33 from the terminal 43.
Thus, the character data signal train stored first corresponds to the information to be displayed on the heading display line of the display block of the 1st row.
On the other hand, the scan signal SS sent from the terminal 44 is 5~17~1 pliecl ~o the ini;ut ~orminill 3C of the scarl silift register 3c~ and this sigrlal CaUg~lt ~y the ~ illg c~dge 0~ the catch timing signal SlS se~t from the tcrlllincll 4~i. Ihcleat~tel~ this scan signal is sequentially transferred by the sc~n timillg sigllal Sl( (th.` sigllai line is not illustrated) and sequentially scans the ~ conductor ot` t llC -~even ~ines in synchronization with the address oper.ltioll by the cllaractel clat:a signal. In other words) the scan address signal SAS 1 is a~plied througll the ~ND gate circuit 35 so -that the gate ele-ctrodes of lETs for clriving oi the 1st line of the display modules DMl to DM32 of the 1st row are controlled to the ON state by the heading pulse of the scan timing signal STC~ and simultaneously the FETs selected in accordance with the data address signal applied from the character data shift register 31 select-ively drive the picture element electrodes of the heading line. Succeedingly, in order to selectively clrive the 2nd display line of the display block DB 1 of the 1st row, the new character data signal CS is controlled by the catch timing signal CTS and input to the character data shift register 31 in series.
Meanwhile, the scan signal in -the scan shift register is shifted for one bit by the scan timing signal STC, outputting the signal SAS 2 and the picture element electrodes of the 2nd line are selectively driven by these address signals. Thereafter, in the same way, the picture element electrodes of the seven lines of the 1st row are sequentially driven and the character informa-tion of the 1st row is displayed.
As e~plained above, while the display block DB 1 of the 1st row is driven by the module selection signal MAS 1, the character data signal CS, scan signal SS and signal catch timing signal CTS, STS are applied in common to the display blocks of the 2nd and succeeding rows. However, in the display blocks of these 2nd and succeeding rows, an output of the corresponding memory elements for module selectiorl is logic "0", and thereby the AND gate circuit ~ 1S917~) 35 lnserted to the output si~ of the scall shift register of the ~isplay modu1es is closed. 5`or this reaso]~, the scan address signal is not allowed to pass thl~ougll the gate el~ctrodcs of IEIs for clriving, disabling the actual d~ g operation.
When tlle drivillg operation t`or the 1st row is completed, the timing signal l`'l`S for catc~ lg the module selection signal is generated and thereby the module selection signal MAS ] for the ls-t row is caught by the memory ele-ment ~IAM 2 corresponding to the display blocks of the 2nd row. Thus the MAM 2 generates the module selection signal MAS 2 of the 2nd row from its terminal Q. This module selection signal MAS 2 enables the driving of display blocks of the 2nd row. Thus, these blocks are sequentially addressed from the head-ing line as in the case of the 1st row. As explained above, the module selec-tiOI1 signals are sequentially transferred between the memory elements corres-ponding to the rows and the display blocks in unit of row are selectively driven on time series. Thereby the display of a single display screen is completed.
Meanwhile, in case there are spaces in displays in the line sequen-tial access method as mentioned above, speed-up of display can be realized by skipping the address operation at the relevant space line. Figure 10 shows the timing chart for explaining such skip access operation, wherein the signal waveforms for skipping the scan address of the 3rd and 4th rows are indicated particularly.
In Figure 10, after the display blocks of the 1st and 2nd rows are sequentially driven by the module selection signals MAS 1 and MAS 2, the con-trol is carried out in such a way that the succeeding scan signal catch timing signals STSs are suppressed by the signal catch timing signal TTS (the 3rd pulse) for shifting the signal MAS 2 in the preceding stage to the 3rd memory 1 15917n elelllell~ M,~l 3. I`hereattel, ~Ifter the tLming signal ITS (the 4th pulse) is applied in order to tlallsfel tllc mod~lle selection signal ~S 3 to the memory elemc~llt ~M ~l of ~he llext ro~, the control is carried out in such a way that the next scall sigrlal catcll timLng signal LS suppressed by the relevant signal.
W}lell the time interval of ~lle timing signal Eor storing the module selection signals to the melllory elelllellt is curtailed and simultaneously the scan signal catch timing sigllcLl SlS durillg such period is suppressed, the skip operation call be after all realized because the module selection signals MAS 3 and MAS 4 are generated but an Outpllt of the scan shift register does not become effec-tive.
In the above explanation, the sequential access and skip access in row units are realized by providing the memory elements of module selection signals corresponding to rows and executing the logic operations with the module selection signal sent from said memory elements and an output signal of the scan shift registers; however, a variety of access systems can be employed by adequately setting the inter-relation between the display modules and dis-ylay blocks and adding the memory elements for required blocks.
Figure 11 shows an embodiment of a display device using the character sequential access method. In this figure, nine display modules DMll to DM33 are arranged in the form of a 3 x 3 matrix for simplification. The display modules are structured such that the FF memory elements MAMll to MAM33 are integrated on the IC chip for driving and these are connected in series for each row on the sub-unit which is not illustrated. In addition, as in the case of the embodiment shown in Figure 8, the FF memory elements MAMl to MAM3 for row block selection are provided corresponding to each row, and the Q ter-minal outputs of these memory elements are colmected to the 1st J input ter-minals of said memory elements corresponding to modules connected in series ~ 1S9~7t~
~01 CL1CII rOW~ 1e OtllOr II.LII~ t:hcy ~ e a~so connected to the J terminalsof thc row selectioll 111el110rY clements correspollding to the next row, thus ena~ling sigllaL ~rallsfel. Tn additiorl, the fetch and transfer of signal for tlle row selcctioll Inelllory elemerlts ~Ml to MAM3 are controlled by the timing signal IlS serlt from the terlllillal 41 alld the fetch and transfer of signal for the module selection memory e~ements M.~lll to MAM33 are controlled by the timing signal MTS sent trom the terminal 46. The signal lines for data and scan sides are not illustrated for simpl fication, but they are the same as those of an em~odiment sllowll in Figure 8. Therefore, as the display device of Figure 11, only one input terminal 46 of the timing signal MTS is added.
According to the structure of Figure 11, the sequential access and high speed skip access for each character (module) are possible and the optimum operation mode can be set in accordance with display contents.
Figure 12 shows the timing chart for explaining such operations. In this case, the display modules DM11, 12,23,31,32 indicated as the hatched portions of Figure 11 are selectively driven and the remaining modules are skipped.
Thus, after the module DMl2 is selectively driven by the module selection signal ~S12, the timing signal MTS for sending the relevant selec-tion signal to the next molule DM13 is thinned and the row selection signal ~Sl is proceeded to the next row by the other timing signal TTS, and moreover the selection signal MAS 2 of the 2nd row is transferred up to the memory ele-ment M~M23 of the module M23 by the timing signal MTS which is controlled at a high speed, thus selectively driving the relevant module. In this case, although not indicated in the figure, the character data is input character by character in common for all modules in accordance with the scanning sequence and only the modules for which the logic gates in the scan address or data address side are opened by the said module selection signal are driven effect-ively. -17-1 159~
I`he pLillci~)al cml)odilllcllt~ o~ tlle prescnt :invcntion are explained al)ovc, hut a val.iety o.t`lllodificat~ s and expa.nsions are possible for those s~i.ll.ed ill this :t.ie kl. I:or c~alllplc, thc disc)lay module structure may include tile piCtUL'e Clf`lllerlt ill Ull:i t'; of.` one or more characters. In add:ition, as for t:hc selection of` displ.ly moduLcs, it is na-turaily possible to select the block arr.lngcd in rows but it .is aLso possil)le to emp.l.oy other freely determined bloch forlllats. Of coursc i t :is possible to select module by module. Further-more the circult structurc integrclted on the semiconductor substrate of each module i.s capable of .introducing a memory driving system where a capacitor for accumulating the signa.L is provided to the active elements for driving, :in addition -to the ref:resh system as indicated above.
A solid state flat panel display having a large display screen can be configu:rated very easily using the present invention.
In addition, a display device as a whole can be configura-ted very economically because wiring and interface of control can be made very easily, and excellent functions such as sequential access and high speed skip access etc. assure the setting of optimum operation mode in accordance with display contents. Thus, the present invention is very effective for adopting a dis-play device comprising driving circuits into the character display device for computer terminals.
Claims (12)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A display device having a structure combining a plurality of display modules comprising a plurality of display picture elements and semiconductor active elements each operatively connected to one of said display picture elements, wherein each display module further comprises a semiconductor sub-strate, as the basic material, cut in such a size as to contain semiconductor active elements corresponding to a picture element required for display of a character or a plurality of characters.
2 A display device as claimed in claim 1, wherein said plurality of display modules are mounted in common on a mounting substrate.
3. A display device as claimed in claim 2, wherein said common mounting substrate includes conductors for connecting the plurality of display modules.
4. A display device as claimed in claim 1, having the structure that;
the semiconductor substrates providing the plurality of picture elements are arranged on a common subunit substrate on which is provided a common dis-play medium thereby forming a plurality of subunits, said plurality of sub-units being mounted on another substrate.
the semiconductor substrates providing the plurality of picture elements are arranged on a common subunit substrate on which is provided a common dis-play medium thereby forming a plurality of subunits, said plurality of sub-units being mounted on another substrate.
5. A display device, operatively connectable to receive a module selec-tion signal and an address signal, comprising: a plurality of display modules each of which comprise a display medium; a plurality of picture element electrodes arranged facing said display medium; and active elements, each operatively connected to one of said picture elements, for selective driving corresponding to said picture element electrodes; wherein each display module further comprises: a first input terminal for receiving the module selection signal; a second input terminal for receiving the address signal; and an address circuit, operatively connected to said second input terminal and to said active elements, distributing said address signal to said active elements, wherein said display device further includes a memory element, operatively connected to said first input terminal, for receiving said module selection signal for each display block which comprises at least a unit of one display module, and wherein sequential control of a storing condition of said memory elements selectively enables driving of display modules for the corresponding display block.
6. A display device as claimed in claim 5, wherein each of said plurality of display modules further comprises a semiconductor substrate integrating said active elements for selective driving and said memory elements for storing said module selection signal.
7. A display device as claimed in claim 5, wherein said memory elements each have input/output terminals and said input/out-put terminals of said memory elements are operatively connected so that said memory elements are connected in series and the module selection signal can be transferred sequentially between respective ones of said memory elements.
8. A display device as claimed in claim 5, further compris-ing logic gate circuits which open or close in response to the module selection signal sent from said memory elements and are operatively connected between the output of said address circuit included in each of said plurality of display modules and said active elements for selective driving, whereby said logic gate circuits enable selective driving of said plurality of display modules.
9. A display device as claimed in claim 5, wherein a display block in a unit of a row is configured by arranging a plurality of said display modules laterally, wherein a display screen for multi-row display is configured by arranging in parallel said display blocks in a plurality of rows longitudinally, and wherein said display modules of each row are selected in common by arranging said memory elements for module selection corresponding to the display blocks in units of row.
10. A display device as claimed in claim 5, wherein display blocks in units of row are formed by laterally arranging a plurality of said display modules, wherein a multi-row display screen is formed by longitudinally arranging in parallel said display blocks in a plurality of rows, wherein said memory elements include memory elements for module selection which correspond to said dis-play modules and which are operatively connected in series for each row, wherein said memory elements include memory elements for row selection which correspond to said display blocks arranged in units of row and are operatively connected in series, wherein outputs of said memory elements for row selection are connected to the inputs of the first of said memory elements for module selection of the corresponding row, thereby the module selection signals can be transferred sequentially between the memory elements for row selection and between the memory elements for module selection of each row.
11. A display device as claimed in claim 5, 6 or 7 wherein said display device is operatively connectable to receive a timing signal and an inverted module selection signal, wherein said memory elements for module selection which store the module selection signals comprise flip-flop circuits respectively including: a third input terminal for receiving the timing signal for initiating storage of the module selection signal in said memory elements, a fourth input terminal for receiving the inverted module selection signal and a signal output terminal.
12. A display device as claimed in claim 8, 9 or 10, wherein said display device is operatively connectable to receive a timing signal and an inverted module selection signal, wherein said memory elements for module selection which store the module selection signals comprise flip-flop circuits respectively including: a third input terminal for receiving the timing signal for initiating storage of the module selection signal in said memory elements, a fourth input terminal for receiving the inverted module selection signal and a signal output terminal.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2584480A JPS56122089A (en) | 1980-02-29 | 1980-02-29 | Display unit |
| JP25844/80 | 1980-02-29 | ||
| JP15400380A JPS5778093A (en) | 1980-10-31 | 1980-10-31 | Display unit |
| JP154003/80 | 1980-10-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1159170A true CA1159170A (en) | 1983-12-20 |
Family
ID=26363537
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000371944A Expired CA1159170A (en) | 1980-02-29 | 1981-02-27 | Display device |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US4368467A (en) |
| EP (1) | EP0035382B1 (en) |
| CA (1) | CA1159170A (en) |
| DE (1) | DE3174755D1 (en) |
Families Citing this family (54)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4523189A (en) * | 1981-05-25 | 1985-06-11 | Fujitsu Limited | El display device |
| WO1983001332A1 (en) * | 1981-09-30 | 1983-04-14 | OOTA, Makoto; | Colored liquid crystal display unit |
| JPS58137892A (en) * | 1982-02-10 | 1983-08-16 | 株式会社東芝 | Display unit |
| US4574280A (en) * | 1983-01-28 | 1986-03-04 | The Board Of Trustees Of The University Of Illinois | Gas discharge logic device for use with AC plasma panels |
| CH666560A5 (en) * | 1983-03-01 | 1988-07-29 | Tadeusz Bobak | DISPLAY DEVICE. |
| JPS6048090A (en) * | 1983-08-26 | 1985-03-15 | 伊勢電子工業株式会社 | Fluorescent display unit |
| GB8402654D0 (en) * | 1984-02-01 | 1984-03-07 | Secr Defence | Flatpanel display |
| FR2563649B1 (en) * | 1984-04-28 | 1991-01-18 | Canon Kk | LIQUID CRYSTAL DEVICE AND CORRESPONDING ATTACK METHOD |
| JPS6132093A (en) * | 1984-07-23 | 1986-02-14 | シャープ株式会社 | Liquid crystal display driving circuit |
| US4682162A (en) * | 1984-09-14 | 1987-07-21 | Trans-Lux Corporation | Electronic display unit |
| JPS61223878A (en) * | 1985-03-29 | 1986-10-04 | 三菱電機株式会社 | Display unit |
| US5691608A (en) * | 1986-06-16 | 1997-11-25 | Canon Kabushiki Kaisha | Image display apparatus |
| WO1989006416A1 (en) * | 1987-12-25 | 1989-07-13 | Hosiden Electronics Co., Ltd. | Method of erasing liquid crystal display and an erasing circuit |
| US5248963A (en) * | 1987-12-25 | 1993-09-28 | Hosiden Electronics Co., Ltd. | Method and circuit for erasing a liquid crystal display |
| US4960719A (en) * | 1988-02-04 | 1990-10-02 | Seikosha Co., Ltd. | Method for producing amorphous silicon thin film transistor array substrate |
| JPH01217421A (en) * | 1988-02-26 | 1989-08-31 | Seikosha Co Ltd | Amorphous silicon thin film transistor array substrate and its production |
| US5079636A (en) | 1988-07-21 | 1992-01-07 | Magnascreen Corporation | Modular flat-screen television displays and modules and circuit drives therefor |
| US5067021A (en) * | 1988-07-21 | 1991-11-19 | Brody Thomas P | Modular flat-screen television displays and modules and circuit drives therefor |
| FR2652185A1 (en) * | 1989-09-15 | 1991-03-22 | Thomson Csf | Interactive visual display screen |
| GB8926647D0 (en) * | 1989-11-24 | 1990-01-17 | Hillen Sean | Video display |
| US6311419B1 (en) | 1989-12-31 | 2001-11-06 | Smartlight Ltd. | Dedicated mammogram viewer |
| IL92936A (en) | 1989-12-31 | 1998-02-08 | Smartlight Ltd | Self-masking transparency viewing apparatus |
| WO1993011452A1 (en) * | 1991-11-25 | 1993-06-10 | Magnascreen Corporation | Microprojection display system with fiber-optic illuminator, and method of display and illumination |
| JPH0651250A (en) * | 1992-05-20 | 1994-02-25 | Texas Instr Inc <Ti> | Monolithic space optical modulator and memory package |
| DE4244584A1 (en) * | 1992-12-28 | 1994-07-07 | Krone Ag | Method and arrangement for networking electro-optical screen modules |
| JPH10503030A (en) * | 1993-11-28 | 1998-03-17 | スマートライト・リミテッド | Fluoroscopy device with passive matrix LCD |
| US5557436A (en) * | 1994-05-12 | 1996-09-17 | Magnascreen Corporation | Thin seal liquid crystal display and method of making same |
| US5805117A (en) * | 1994-05-12 | 1998-09-08 | Samsung Electronics Co., Ltd. | Large area tiled modular display system |
| DE4424138C1 (en) * | 1994-07-08 | 1995-09-07 | Siemens Ag | Modular expandable electronic work surface |
| US5767818A (en) * | 1994-09-27 | 1998-06-16 | Nishida; Shinsuke | Display device |
| JPH08129360A (en) * | 1994-10-31 | 1996-05-21 | Tdk Corp | Electroluminescence display device |
| US5748164A (en) * | 1994-12-22 | 1998-05-05 | Displaytech, Inc. | Active matrix liquid crystal image generator |
| US6853083B1 (en) | 1995-03-24 | 2005-02-08 | Semiconductor Energy Laboratory Co., Ltd. | Thin film transfer, organic electroluminescence display device and manufacturing method of the same |
| US5644327A (en) * | 1995-06-07 | 1997-07-01 | David Sarnoff Research Center, Inc. | Tessellated electroluminescent display having a multilayer ceramic substrate |
| ES2116234B1 (en) * | 1996-09-04 | 1999-04-01 | Colom Oller Y Asociados S A | SYSTEM OF REPRESENTATION AND WALL DISPLAY OF IMAGES AND INFORMATION AND SCREEN IMPLEMENTING THE SAME. |
| US5963276A (en) * | 1997-01-09 | 1999-10-05 | Smartlight Ltd. | Back projection transparency viewer with overlapping pixels |
| EP1012659A4 (en) * | 1997-03-25 | 2002-10-02 | Sixeye Ltd | Modular front-lit display panel |
| JPH11272209A (en) * | 1998-01-30 | 1999-10-08 | Hewlett Packard Co <Hp> | Integrated circuit video tile for display |
| US6897855B1 (en) | 1998-02-17 | 2005-05-24 | Sarnoff Corporation | Tiled electronic display structure |
| US6492973B1 (en) * | 1998-09-28 | 2002-12-10 | Sharp Kabushiki Kaisha | Method of driving a flat display capable of wireless connection and device for driving the same |
| US6498592B1 (en) | 1999-02-16 | 2002-12-24 | Sarnoff Corp. | Display tile structure using organic light emitting materials |
| US6690337B1 (en) | 1999-06-09 | 2004-02-10 | Panoram Technologies, Inc. | Multi-panel video display |
| AU5974300A (en) * | 1999-06-14 | 2001-01-02 | Carlos J.R.P. Augusto | Active matrix for flat panel display |
| US6980184B1 (en) | 2000-09-27 | 2005-12-27 | Alien Technology Corporation | Display devices and integrated circuits |
| GB0130600D0 (en) * | 2001-12-21 | 2002-02-06 | Koninkl Philips Electronics Nv | Active matrix electroluminescent display device |
| US6999045B2 (en) * | 2002-07-10 | 2006-02-14 | Eastman Kodak Company | Electronic system for tiled displays |
| KR100625981B1 (en) * | 2003-10-30 | 2006-09-20 | 삼성에스디아이 주식회사 | Panel driving method and apparatus |
| JP5687495B2 (en) * | 2008-01-21 | 2015-03-18 | シーリアル テクノロジーズ ソシエテ アノニムＳｅｅｒｅａｌ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ｓ．Ａ． | Device for controlling pixel and electronic display device |
| US8497821B2 (en) * | 2009-02-16 | 2013-07-30 | Global Oled Technology Llc | Chiplet display device with serial control |
| KR101236940B1 (en) * | 2010-09-30 | 2013-02-25 | 삼성중공업 주식회사 | Ship for installing a wind power generator |
| KR102050511B1 (en) * | 2012-07-24 | 2019-12-02 | 삼성디스플레이 주식회사 | Display device |
| CN105139806B (en) * | 2015-10-21 | 2018-05-01 | 京东方科技集团股份有限公司 | Array base palte, display panel and display device |
| CN106098698B (en) * | 2016-06-21 | 2019-06-04 | 京东方科技集团股份有限公司 | Array substrate and preparation method thereof, display device |
| WO2020131894A1 (en) * | 2018-12-21 | 2020-06-25 | Lumiode, Inc. | Addressing for emissive displays |
Family Cites Families (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR1584198A (en) * | 1968-09-12 | 1969-12-12 | ||
| US3493933A (en) * | 1969-02-04 | 1970-02-03 | William Brooks | Shift register control circuit for variable message displays |
| BE754223A (en) * | 1969-08-04 | 1970-12-31 | Ncr Co | ELECTROLUMINESCENT DISPLAY DEVICE |
| US3701123A (en) * | 1969-10-29 | 1972-10-24 | Hewlett Packard Co | Hybrid integrated circuit module |
| GB1430468A (en) * | 1972-08-10 | 1976-03-31 | Ise Electronics Corp | Display modules |
| GB1437328A (en) * | 1972-09-25 | 1976-05-26 | Rca Corp | Sensors having recycling means |
| US3885196A (en) * | 1972-11-30 | 1975-05-20 | Us Army | Pocketable direct current electroluminescent display device addressed by MOS or MNOS circuitry |
| US3913090A (en) * | 1972-11-30 | 1975-10-14 | Us Army | Direct current electroluminescent panel using amorphous semiconductors for digitally addressing alpha-numeric displays |
| US3787834A (en) * | 1972-12-29 | 1974-01-22 | Ibm | Liquid crystal display system |
| US3832034A (en) * | 1973-04-06 | 1974-08-27 | Ibm | Liquid crystal display assembly |
| JPS5749912B2 (en) * | 1973-10-29 | 1982-10-25 | ||
| US4039890A (en) * | 1974-08-16 | 1977-08-02 | Monsanto Company | Integrated semiconductor light-emitting display array |
| US3976906A (en) * | 1975-06-09 | 1976-08-24 | Litton Systems, Inc. | Programmable character display module |
| US4107662A (en) * | 1976-02-17 | 1978-08-15 | Hitachi, Ltd. | Character generator for visual display devices |
| CA1082378A (en) * | 1976-08-05 | 1980-07-22 | Thomas A. Brown | Abuttable light-emitting device modules for graphic display assemblies |
-
1981
- 1981-02-20 US US06/236,621 patent/US4368467A/en not_active Expired - Fee Related
- 1981-02-27 CA CA000371944A patent/CA1159170A/en not_active Expired
- 1981-02-27 DE DE8181300817T patent/DE3174755D1/en not_active Expired
- 1981-02-27 EP EP81300817A patent/EP0035382B1/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| EP0035382A1 (en) | 1981-09-09 |
| DE3174755D1 (en) | 1986-07-10 |
| US4368467A (en) | 1983-01-11 |
| EP0035382B1 (en) | 1986-06-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CA1159170A (en) | Display device | |
| US20230316998A1 (en) | Local passive matrix display | |
| US8040293B2 (en) | Shift register and organic light emitting display using the same | |
| KR100432554B1 (en) | organic light emitting device display driving apparatus and the method thereof | |
| US5818412A (en) | Horizontal driver circuit with fixed pattern eliminating function | |
| US7522145B2 (en) | Liquid crystal display apparatus | |
| US6380919B1 (en) | Electro-optical devices | |
| US8018402B2 (en) | Organic light emitting display device and testing method thereof | |
| US11341893B2 (en) | Hybrid architecture for zero border display | |
| KR100468562B1 (en) | High definition liquid crystal display | |
| US20060267911A1 (en) | Shift register and display device using the same and driving method thereof | |
| JPS6180226A (en) | Active matrix driving device | |
| KR19980081100A (en) | Active matrix devices | |
| US11783743B2 (en) | Shifting register, driving method thereof, driving circuit and display device | |
| US11120746B2 (en) | Shift register unit, gate driving circuit, display device and driving method | |
| CN107331348A (en) | Shift register cell and its driving method, array base palte and display device | |
| JPH02708B2 (en) | ||
| US6133750A (en) | Combination of global clock and localized clocks | |
| JPS6364793B2 (en) | ||
| JPS5958479A (en) | Ic board for active matrix display body | |
| JPS61292127A (en) | Integrated circuit for driving liquid crystal | |
| JPH0752333B2 (en) | Active matrix liquid crystal display device and manufacturing method thereof | |
| Cooperman et al. | A single chip 64* 16 broadband switch | |
| KR20230087168A (en) | Gate driving circuit and display device comprising the same | |
| JPS6365957B2 (en) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |