CA1159554A - Digital signal processing apparatus - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE
In a digital video signal processing apparatus having error correcting and concealing capabilities, a video signal is converted to a digital signal and transmitted or recorded with error detecting and error correcting signals. Upon receiving or reproducing the transmitted signal, an error in the digitized video signal is detected by means of the error detecting signal, and corrected, if possible, by means of the error correcting signal. If the error is so extensive that its correction by the error correction signal is not possible, the erroneous signal is concealed by its replacement with a substantially corresponding signal of the previous field which has been stored in a suitable memory.

Description

BACKGROUND ()F THE IN~rENTIoN
_ Field of the Invention This invention rela~ces generally to an error correcting ~nd concealing 8y5tel~1, nd more particularly ~ directed to an error correcting and concealing ~ystem which ~8 applied to a digi~cal signal proces~ing sp~aratus, sueh as, a d~gital vldeo tape recorder.
Descri tion of ~he Prior :Art ~ In recordirlg and reproducing a digital video signal by a rotary head type video tape recorder (VTR), random errors may result from head no~se, tape noi~e or amplifier noise or a bur~e error may be caused by a ~i~nal dropou~c. It is a recognized advantage c~f di'gital signal processing that erroneous data san be mathematically corrected by the ~nclusio~ in the recorded or ~ransmitted data of redundant Sits. For example, a well known ~cheme for correct~ng digital data ~n~rolve6 dividing the latter , .. .. .
~' ' ' ~

,, _,. . .. ... .

. .
. .

into blocks, each of which i~ recorded ~r tran6mi~ted alon~ with ~ p~rity ob~alned by modul~ 2 ~ddition for ~ach block QO that, upon reproduction ~r rRcepti~n, ~n error in any such block c~n be corrected on the ba~iæ
of the respective parity. R~wever, ~he addition t~
the recorded information dat~ of ~he redund~nt b~ts representing ~he p~ri~y for the purpo~e of protectlng the information d~ta from errors necessarily lncrease~
ehe recording bi~ rate wh~ch i8 l~mited by ~he necessity of minimlzing the consump~ion of ~ape.
Therefore, even if the code ~rrange~ent of the digital video signal is designed to be capable ~f error correction, the exten~ of the error may somet~me~
exceed ~he error correcting abillty wh~ch i~ limlted by the ~cceptable redundancy.
It has further been proposed to conceal ~n error in a transm~tted or recorded video 8ignal 80 ~ha~
6uch error will not be noticed in the displayed picture.
One error concealing method that has already been proposed involves in~erpolation of the erroneous data with data of the immediately preceding line of the ~ame field, and such method relie~ on the strong correlation of a televisio~ picture in the vertical direction. Another conventional error concealîng method involves replacement of ~he erroneous da~a with a mean value of data from the lines immediately preceding ~nd following the line containing the error.
The above error concealing methods bo~h obr~in a signal for interpolation or substitutlon for the erroneous data from the data of the 8a~e field.
Incidentally, since the television pirture is formed by interlaced scanning, ~t will be appreciated that adjacent l~nes in the ~me field are s~aced apart by a

-2-di~tance that 1~ twice the dls~nce between ~d~acen~
line~ in the pictorial repre~entation of the co~ple~e frame made up of ~wo interl~ced flelds. Therefore, the data ln ~mmedi~tely ~d~acent line~ ~ re3pec~vely, of ~uch pictorial representation of the e~mplete frame and which occur in CoDtigUoU~ field~ of the Yideo s~gn~l ~ have an even higher correl~tion therebetween.
- Accordingly, it ha~ been proposed by ~he assignee of thi~ appliea~ion to eff~ct error concea~ment by replacing error-con~alning data in a line of one field wi~h corresponding data ln the line of the next previous field which, in the pictorial represen~ation of the eomplete fr~me, ~B positioned immediately adjacent the error-containing line 80 that the dat~ u~ed for concealing an error will bear a closer re~emblance ~o the original or correct data which it replaces.
If ~he error concea~ment teehnique is relied upon exclusively, p~ceure degrada~ion becomes a problem, particularly af~er multiple generation~ of dubbing, unless the rate or error occurrence i~ very l~w.
OBJECTS AND SV~RY OF THE INVENTION
Accordingl~, it i6 ~n ob~eet of ~hi~ invention to provide a digital video signal processing apparatus which is capable of correcting and/or concealing errors in ~he digi~al video signal without undesirably increasing the redundant bits of the tr~nsmitted or recorded sign~l and without degradation o~ the pict~re resulting from the proces~ed signal.
More partlcularly, it is ~n ob~ect of this invention to provide an error correcting and/or concealing method and apparatu~, A~ aforesaid, which is suitable for use wlth a digital video tape recorder (VTR) ~n which an snalog video ~gnal i8 converted to a digi~al

-3--. .
. " ., . , . . . ~ . .... . .... .... . . ... .......

~ignal and recorded on a magnetic tape.
It i~ unother object of this inven~ion to provide an error correcting ~nd/or concealing me~hod and ~ppara~us, as ~foresaid, for u~e with ~ digltal video processing appar~tu~ and which doe~ Rot require a o~e-line delay cirouit or mean ~lue forming clrcuit. ' It ~ ~ further ob~ec~ of ~hi~ ~nventl~n ~o provide an error eorrecting and/or concealing ~ystem ~hich cRn use a field ~em~ry effec~ively for both error concea~ment ~nd error correc~ion.
According to an aspect sf the in~en~ion, in processing a digital ~ignal which forms a d~ta block for every predetermined number of b~ts ~nd which includes error detectin~ and error correcting signals, an error in a data block of the digital 8ign81 i~ detected by means of the error detecting ~ign~lp e~ch error-free data block i~ ~ritten ~n ~ first memory, an error-containlng data block is writ~en in a second memory, ~ dat~ block ls selectively read out from the first memory or from the second memory, ~nd an error vf ~ data block read out from the 6econd memory 1~ corrected by means of the respectlve error correct~ng ~ignal.
In the ca~e in which the digital signal to be processed i~ converted from ~n analog video signal field memory i8 de~irably used as the fir~t memorg, and each error-free data block ~8 wri~een at an ~ddress in the first memory corresponding ~o tha~ at which there was earlier written a da~a block of ~ line of the next -previous field wh~ch, ln the pictorial rcpresentation of a complete frame, i8 postloned immediately adjacent the l~ne of the error-free data block being written.
When an error contained in a data block is ~udged to be . . .. .. . . .. . .

- L~ 4 too ea~tens~ve f~r c~rrect~on by the respec~$Ye crror correctln~ signal, ~he Wr~ting ~ ~uch error-conta~n~g d~t~ ~loek ~ he ~ec~nd me~morg ~L8 ânh~b~ted a~d the error i~ ~once~led ~y ~neans of the error-free d&ta block earl~er written at the corre~p~ndlng ~ddres~f the f~rst ~emory or the ~ prevlous ~F~eld~
- - ~n the method snd ~ppara~u~ ~ccording t~ the invent~osl, ~n error detec~n~ ~ode 18 added for ~ch ~at~ bloc~c to form ~ ~gnal 2>13ck therewith and, ~f~er ~rranglng ~ plurality of t~e 8i n~l bl~ck5 in a ~a~ri~c form, error correct~ng code~ are added for each ¢clumn and ~ow of the m~tr~ ere'by an error orrect~Lc>n ~8 perfo~med in every col~on and every ra~.
More particularly, there is provided:
A method of processing a digital signal which forms a data block for every predetermined number of bits, and which includes error detecting and error correcting signals, said method comprising the steps of:
detecting each said error signal as an indica-tion of an error in a respective data block of said digital signal;
writing in a first memory each data block which is free of error;
writing in a second memory a data block contain-ing an error;
selectively reading out a data block from said first and second memories; and correcting an error of a data block read out from said second memory by means of the respective error correcting signal.
There is also provided:
A method of processing an analog video signal ,~ 5-~t~
composed of successive frames each having a plurality of fields constituted by successive respective lines which are interlaced in a pictorial representation of the complete frame, said method comprising the steps of:
converting said analog video signal to a digital signal;
forming a data block for each predetermined number of bits of said digital signal;
adding error detecting and error correcting signals to said digital signal;
detecting said error detecting signals as in-dications of errors in the respective data blocks of said digital signal;
writing each error-free data block at an ad-dress in a first memory corresponding to that at which there was earlier written a data block of a line of the next previous field which, in said pictorial repre-sentation of the complete frame, is positioned immedi-ately adjacent the line of said error-free data block being written;
inhibiting the writing of an error-containing data block in said first memory;
writing said error-containing data block in a second memory;
reading out a data block selectively from said first and second memories; and correcting an error in a data block read out from said second memory by means of the respective error correcting signal.
There is also provided:
An apparatus for processing a digital signal which forms a data block for every predetermined number 5a-of bits, and which includes error detecting and error correcting signals, said apparatus comprising:
error detecting means for detecting each said error detecting signal as an indication of an error in a respective data block of said digital signal;
first memory means for storing each data block which is error-~ree;
second memory means for storing a data block which has been indicated by said error detecting means to contain an error;
selector means for selectively reading out the contents of said first and second memory means; and error correcting means employing said error correcting signals for correcting said error detected by said error detecting means.
There is also provided:
Apparatus for processing an analog video sig nal composed of successive frames each having a plurality of fields constituted by successive respective lines which are interlaced in a pictorial representation of the complete frame, said apparatus comprising:
means for ~onverting said analog video signal to a digital signal;
means for forming a data block for each pre-determined number of bits of said digital signal;
means for adding error detecting and error correcting signals to said digital signal;
means for detecting said error detecting sig~
nals as indications of errors in the respective data blocks of said digital signal;
first and second memory means;

-5b-means for writing each error--free data block at an address in said first memory means corresponding to that at whi~h there was earlier written a data block of a line of the next previous field which, in said pictorial representation of the complete frame, is posi-tioned immediately adjacent the line of said error-free data block being written;
means for writing said error-containing data block in said second memory means;
means for reading out a data block selectively from said first and second memories; and means for correcting an error in a data block read out from said second memory means by means of the respective error correcting signal~
There is further provided:
Apparatus for processing an analog video ~sig-nal composed of successive frames each having a plurality of fields constituted by successive respective lines which are interlaced in a pictorial representation of the complete frame, said apparatus comprising:
means for converting said analog video signal to a digital signal;
means for forming a data block of each pre-determined number of bits of said digital signal;
means for adding an error detecting code to each said data block to form a signal block therewith;
means for arranging a plurality of the signal blocks in a matrix form having rows and columns;
means for adding error correcting codes for each said row and column of said matrix form;
means for transmitting and receiving said digi-tal signal in said matrix form with said error detecting ' t. 5c-.~

~..L ~

and error correcting codes added thereto;
means for detecting each said error detecting code as an indication of an error being contained in the respective data block of the received signal;
- first and second memory means;
first correction means employing one of said error correcting codes of the row and column, respec-tively, in which said error-containing data block is situated for correcting the error therein;
means for writing in said first memory means each data block ~hich is error-free at least after the action thereon of said first correction means, said error-free data block being written at an address in said first memory means corresponding to that at which there was earlier written a data block of a line of the next previous field which, in said pictorial repre-sentation of the complete frame, is positioned immedi-ately adjacent the line of said error-free data block being written;
second correction means employing the other of said error correcting codes of the row and column, respectively, in which said error-containing data block is situated for correcting an error remaining therein after the operation of said first correction means;
means for writing in said second memory means a data block which, following said operation of the first correction means, contains an error correcta~le by said secand correction means; and means selectively reading out a data block from said second memory means to said second correction means when said read-out data block contains an error correctable by said other error correcting code or -Sd-,. , reading out an error-f~ee data block from said first memory means.
The ~b~ve~ ~nt o~her ob,~ect$, feature~ and ~dvantage~ of ~hi~ invention" will be apparent fr~n th~ .
following detailed de~ccr~ption which 1~ to be read 1 ~on~unction wi~h the ~ccompanying dr~wln~s.

~RIEF DESCRIPTION OF THE DRAWI~S

F~g~. lA and 1~5 ~nd ~g~. ~ ~d 2B a~e ~chemat~c di~gr~ms illu~tratlng typlcal sampling po~tlon#
of a dig~tal ~ideo 8i n~ nd the phsse ~f a color subcarrier;
Figs. 3A-3I ~re schematic diagram~ to whi~
reference ~ill be made irl explaining ~ddres~ con~rol for a field memor~r;
~ ig~. 4 and 5 ~r~ block diagr~ns ~llu~trating recording an~ reproducing sect~LonsJ re6pective~, o~ ~
d~g~tal video ~cape recorder ~V~R) embodying this invent~on;
F~g. 6 ~8 a schema~ic lllustrat~on of ~ rotary head as~embly ~ncluded in ~he di~ al VTR of F~g . 4 and 3;

-5e-Fig~ 7 is a sche~atic vieW of rotary heads included in the ~ssembl~ of Fig. 6;
Fig. 8 is a schematic plan view of a section of magnetic tape showing tracks in which signals are recorded, Figs. 9, 10 and 11 are schematic diagrams to which reference will be made in explaining the digitization and code arrangement of a video signal for use in the digital VTR
embodying this invention;
Figs. 12A-12D are timing charts to which reference will be made in explaining the operation of an error control encoder included in the recording section of Fig. 4;
Fig. 13 appearing with Fig. 11, is a block diagram of an error correcting decoaer included in the reproducing section of Fig. 5;
Figs. 14A-14I, appearing with Figs. 12A-12D, are timing charts to which reference will be made in explaining the operation of the error correcting decoder of Fig. 13;
Fig. 15 is a block diagram of a horizontal judging circuit that is included in the error correcting decoder of Fig 13;
` Figs. 16A-16N are timing charts to which reference will be made in explaining the operation of the horizontal judging circuit of Fig. 15;
Fig. 17 is a block diagram of a horizontal parity checker included in the error correcting decoder of Fig. 13;
Figs. 18A-18H are timing charts to which reference will be made in explaining the operation of the horizontal parity checker of Fig~ 17;
Fig. 19 is a block diagram illustrating, by way of example, a buffer memory and a horizontal error correct-ing circuit included in the error correcting decoder of Fig. 13;

, Fig. 20 ~8 a block diagr~m 6howing a vertical ~udging circuit included in ~he error correcting decoder of Fig. 13;
Fig~. 21A-21K and ~igs. 22A-220 are t~ming charts to which reference wlll be made in explaini~g the operati~n o the ver~ical Judglng circuit of ~ig. 20;
Fig. 23 la ~ ~loc~ diagr~m ~howlng, by w~y of example, ~ sub-memory and i~8 as~oc~ated circuit arrangement th~t may be iDcluded in the ~rror correoti~g decoder of F~g. 13;
Fig. ?4 is 8 block diagram illustra~ing an ex~mple of an overflow preventing circuit included in the circuit of Fig. 23;
Fig. 25 i~ a block diagr~m illustrating ~n ex~mple of an error correcting circuit included ~n the error correct~ng decoder of Fig. 13; and Fig. 26 is a s~mplified block diagram illus~rating modification of an error correcting decoder accordi~
to the invention in which individual memories are provided for the luminance and the chrominance componenS~ of a reproduced NTSC color video ~ignal.
DESCRIPTION OF THE PREFERRED EMBODIMENT_ In order to facili~ate a better understandin~ of the present invention, there will first be described the conditions for digi~cal recording of an NTSC color video ~ignal.
The NTSC system color rideo signal ~ desirably di~itized with the follo~ing condltions be~ng establi6hed:
1. Since one frame comprises 525 line~, the n~nbers or' lines ~elected for a first ~third~ and ~ second (fourth) field are 262 ~nd 2~3, respectively. In the first field, a vertical ~ynchronizing pU18iE! and a horizontal synchronizing pul~e are in phase wi~h e~ch other, and the , . ..... ... ..... ,,.. ,. . ~.. ~, ... . . - ,., ., . , ,, .. ,, ~

5~
~ield in which they are out of pha~e is con~idered the second field.
2. The number of sampled pictuxe elements in each horizon~cal period ~H) v~rie~ wi~h the ~mpling frequency (fs) employed. Slnce ~Le eolor ~ubc~rrier frequency (fsc~ is 455/2 cimes ~e hc~rizontal fre~uency (fh), the numbers of ~ampled picture elements 1~ o~e horizon~cal perit~d are ~s ~hawn ln the below Table 1 in the case of fs ~5 3fc and in the c~lse of fs ~ 4fc.
Tsble 1 -~s Even ~O~l~ I rz,- _ . Odd frame 682 683 3fsc Even frame 683 682 .
Odd fraIne 91û 910 4fs~
Even frame 910 910 .
In the case of f8 ~ 3fsc~ the number of sampled picture elements in the line in which ~he horizontal synchronizing pulse and the color subcarrier are in phase with each other is taken ~s 682, and the number of ~ampled picture elements in ehe line in ~h~ch ~he horizoneal synchronizing pulse and the color subcarrier are out of phase is taken as 683. The odd frame star~s wi~h ~he line in which the horizontsl synchronizing pulse and eQlor subcarrier are out of phase from each o~cher, whereas the even frame starts with ~che line in ~hich they are in phase with each other. As will be ~ppreciated from Table -1, irl the case of fs ~ 3fsc, the numbers of s~mple~ picture elements in adjacent lines which are in the same field but differ by one horizon~l period (lH) in t~me from each other are different, but i data of the line of the previous field w~ich is positioned one line below ~s used as an interpolation line, the numbers o ~ampled picture elements in the erroneous line and in the interpolation line ~ecome equal to e~ch other. Further, as ~ill be evident from the follo~ing description, the eolor ~ubcarriers of the respective ssmpled ~icture element~ in both ~f ~uch lines ~re al~o of the same p~ase.
Figs. lA ~nd lB and Figs. 2A and 2B ~5w numbers of lines ~nd ~a~pled p~cture elemen~ ~hic~ are substantially smaller than ~he actual ~umbers therefor given ~n Table 1 for ~he purpose of ~implifying and clari~ying the relation Qf the number~ of ~mpled picture elements and the phase of the ~olor suboarrier. Fig~. lA
~nd lB represent the case,of f~ - 3f~c and Fig6. ~A and 2B represent the ease of fs ~ 4f~c. In the NTSC color television 8y8tem, ~he phase of the eolor ~ubcarrier i~
inverted between ad~acent lines ~n a field, and also between adjacent frames. Further, at each sampling point, the color subcarrier is ~hown to have a predetermined phase. Therefore, the phase varia~ions (a pha~e difference~) of the color ~ubcarrier a~ ~he ~ampling point~ of the respective lines are indicated by black and ~hite circles on Fig. LA and lB and Fig~. 2A and 2B, ln which lines of the irst field are indicated by ~ol~d lines ~nd the lines of the second field are indicatea by broken l~nes.
In ~che case oP ~ c 3fsc, an odd frame, for example, the first frame i~ as 8hown in Fig. h9. In the first field of the fir~t frame, eight line~ Q(l-Oa, 7) are sequentially formed and in the second field of the fir6t frame, nine lines ... ~ 8), Q(l-9), ... Q~l-lS) are ~equentially formed. In other word6, one frame i8 ~hown to comprise ~ 7 lines in ~11 merely for the purpose of a ~implified ~ llustration.
In the first line Q(l-O), the nwnber of ~ampled picture elements, i8 for example, five; in the nex~c line ~
OI' the first field, four sampled picture elements lie ~t ~g _ `positions displaced by one-half of the 6ampling perivd with respect to ~he line ~ ); and ln the next J~ 2), 'che number s~f ~mpled picture elemen~cs i8 iE$ve ~ wa~ 'che c~se with the line ~ 0). In ~e ~ubse~uent line~, the number~ of ~ampled picture element~ undergo change~
correspondin~g to those described ~bove.
I~ the odd field ollawing tl e zecond fie~ld of the flr~t frame, for ~cample, in ~he first field of the second ~rsme, eight lines ~(2-0), Q(2-1), .~. Q(2-7) are shotdn formed one ~fter anotller (Fig. lB3, ~nd in the ~ç~cond field thereof, nille lines Q(2-8), Q(2-9), ... Q(2-l63 are ~uccessively fonned, ~o that ag~in 17 lines exist in one framP. Since the number of lines is odd, the number of sampled pic~cure element~ and the phase of ~he color ~ub-carrier are oppo~ite to those in the firR~ fr~me. In other words, if the num~er of sampled pi~ture elemehts is ~Eitte in one of the lines of the firs~ or ~econd fra~e, then the number of sampled picture elemen~c~ in the lirle at the s3me position in the other of the r~mes will be four ~nd the color eubcarriers of ~he two lines are displaced apart in phase by lr. A part~cular line ~nd the line positioned one line therebelow ~n ~he previous field halve the same number of sampled picture elemencs and the same phase of the color ~ubcarrier. For example, if the line 10~ in the second field of ~che fir6t frame cont~ins an error, then ~che llne l~l-2) which i8 positioned lrl the previous field one line below ~he line ltl-10) i~ a suitsble interpolatlon line. The two lines ~ 2~ and ~ 10) both have fi~e sampled picture elesDents and have no phase difference between their color 6u~carriers. In all other cases, that i5, any other line ~ssumed to have an error and the respective interpol~tlon line po~itioned one line there below in the next previous field, ~re equal in the numbers .~

~10-3 ~ ~
~~f ~ampled pic~ure elements and in the phase of their eolor subcarrier , ~8 ~ill be Been Prom Figs. IA ~nd lB.
Table 2 below shows the interpolation lines which respectively corrPspond ~o the line~ Q(l-O) to ~(2-16) in case ~ny of the~e lines are erroneous. ~or the ~ke of brevity, in Table 2~ lines of a field precedi~g~the flrst field of the firs~ fr~me ~re al~o indic~ted ~y the line number~ in the second frame and the pref~x "~" is omitted:
Table 2 - ., ... _ . . _ ,.. _ ~rron-line 1-1 1-2 1-3 1-4 1-5 1-6 1-7 1-8 1- 1-10 1-11 Interpo-lati~n 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 1-0 1-1 1-2 1-3 Erron- _ ~ _ _ _ line 1-13 1-14 1-15 1-16 2-0 2-1 2-2 2-3 2-4 2-5 lation 1-4 1-5 1-6 1-7 1-8 1-~ 1-10 1~1l 1-1~ 1-13 1-14 Erron- _ _ _ l _ _ i eous 2-6 2-7 2-8 2-9 2-10 2-11 2-12~2-131-14 2-14 2 15 _16 2-0 2-1 2-2 2-3 2-4 ~ 7 Z-8 In the case of 8 ~ 4fsc, the correspondence between an erroneous l~ne and the respective interpol~tion line i5 such that, for example, if ~he llne ~ 10) i8 an erroneou~ line, then the line Q(1-2) becomes the interpolatlon line, as will be evident from Fig. 2A
(showing the first frame~ and Fig. 2B (~howing the second frame). In the case of fs e 4f~c, ~he numbers of sampled picture elemen~ in ~11 of ~he ~nes ~re equal, for example, are shown to be five. If line~ from Q~l-O) to Q(2-16) are error-containing 7ine~, th~ respective ~nterpolation lines are exactly as shown in Table 2, and each erroneous .. . . . ... . .. . ... ... .. . .. .. . . ...

J~.~
line and the respective in~erpola~ion line have the same phas e of the color ~ubc~rrler .
As ~rill be appreeia~ed from the abo~e, an erroneous 8ection of a digi~ized color video sl~nal ean be concealed by being seplaced with lnformation ha~r~ng a number of sampled pieture elemerlts and phase rel~ion-8hip which iR ~ lar ~o the origin~l. Moreov~r9 ~uch concea~ment can be performed ~hether the ~ampli~g frequency (fs) :18 :ES " 3f~c or f~ ~ 4fsc.
The interpola~ion method described above for concealing an error can be achieved w~th a random acoess memory (hereinaf ter referred to as RAM~ ~hich has eapacity larger than one field. Therefore, if the numbPrs of lines in each field are assumed to be as shc~wn on Figs. lA, lB and 2A, 2B, the ~AM may have line addresses 1 to 9, as sho~n by 'che numbers at the left ~ide of Fig. 3A.
In Figs. 3B to 3I, the l~ne addresses 1 ~o 9 of the RAM
are omitted for the sake of 8implicity.
In the fir~t field of the f$rst frame, data s~f the field are sequent~ally written in the addresses 1 to 8 of the RAl`I. Fig. 3A indicates ~ by the notations [l-OJ
71, that the da~a of the li~es gO) throug~ (7~ of the first field have been wri~ten a~c the addresses (1~
~B~, respectlvely. Next, data of the line [1-8~, that is, the first line of the ~econd field, iæ written at the address (1) ~n which the data of the line 11-0] of the first field of the same frame had been stored, ~Q8 depicted ~n Flg. 3B. The foregoing is ~ first condition that 8hould be satisfied in wr~ting data in the RAM~
Prior to ~his writing of the llne [1-8] at the address ~1), the data of line ll-OJ i8 read out fro~ that address, that is, the firs~ half of a memory cycle of the RAM i~
used as a read-out cycle and the later half is used as a wrlte cycle. The data of the respective lines of the econd field are sequent~ally written in the RAM, ~nd the data of the 188~ line [~-163 of the first fr~me ls written in ~he address ~9), as illustrated in Fig. 3C.
In principle, ~he reading of data i8 performed ~t ~he ~ddress at w~ich new dat~ i8 to be written,as ment~oned ~bove.
~owever, in the c~se of writ$~g ~he tatA of ~he 1~8 line of the fr~me, for e~ample, the line [1-16~, the data stored in ~he addre~s n2xt to the addres~ in which the data is to be written i& read ou As s~o~n in Fig. 3D, in ~hich writing of the data of the first frame has been c~mpleted, the d~ta of the line t2-0] of the first field of ~he second or next frame is written in the address next to the address in which the data of the line [1-8] of t~e second field of the first frame has been ~tored. This is a second condition that should be 6a~isfied in writi~g ~n the RhM. While following the above conditions concerning the writing and reading in the RAM, the operations proceed as hown in Figs. 3E and 3F, ~nd the writing of ~he data of all line~ of the second frAme i8 completed with ~he ~tored data in the RAM being as ~hown on ~ig. 3G.
Then, the data of the first line ~3-01 of the third frame i8 written while following the above described second condition, ~s shown in Fig. 3G, and further, the data of the line [3-83 that ~6, the first line of ~he second field of the third frame, i8 written, following the earlier described first condition, as depicted ~n Fig. 3H. Thus, the writing of the data of all llnes of the third frame iR completed, as shown in Fig. 3I.
As will be understood frcm ~ comparison ~f Fig~. 3A, 3D
and 3G, or of Figs. 3B, 3~ and 3H, the address at which the data of the leading line ~f each îield 18 written i~ shifted by one addre6~ every time the frame ehange6.
In other ~ords, the RAM oper~ce~ in a eirculating manner. The c~paciey of ~e RAM m~y be only ~o mu~h larger than one ield a~ i~ Rece~sary for it to pea~foD
~ueh operation.
Gener~llg, in aceordance with thi~ invent~on, da~a frcm a VTR, such as, it~ reproduced output, 1~
~upplied ~ia an error correcting circui~ to the RAM.
When the reproduced data i8 erroneous and the error is uncorrect~ble by an error correc~ing circu~t, ~he latter generates- a fl~g ~ignal indicating 8ueh fact. In respon8e to the 1ag sign~l, wTiting of the corresponding erroneous dat~ in the RAM is inhibited. ~ith the ~ belng acti~ated RS described above, the line of the previ.ous field positioned lH below the erroneous line ean be read out as interpolation data to conceal the error merely by inhibition of ~he writing operation.
~ or ~xample, ~n the case where the data of the line t2-l] i8 erroneou~ and uncorrectable, and hence a flag signal has been produced on the line 12-l]. ~riting ~n the RAM o$ the dat~ of the line 12-l] i~ inhibited in the next memory cycle represented in Fig. 3D.
Accordingly, the data ~tored in thi~ ~ddress i~ the data of the line [l-lO] Rreviously written. A6 illustrated in Fi~. 3E, in the next memo~y cycle in which t~e data of the line [2-~1 should be read out, the data of the l~ne [l-lO] i8 read out in place of-the data of the line t2-13. In other words, the line Q(l-lO) of the previous field lying one line below the erroneous and uncorrectable line ~(2-l) becomes ~n ~nterpolation line to conce~l the error in the.line [2-l].

~ ilhen ~he fields have equal number6 of lines, it i~ Buffic$enc merely to shift, by one l~ns~, the write ~ddre~s of the leading 11ne s:~f e~ch new fr~nne.
l~e present in~entiorl ~ill hereinafter ~se described as being ~pplied to a digit~l VTR made up of a recording ~ection (F~g. 4~ ~nd a pl~yback ~r reproducing ~ection (Fig. 5). In the digital VTR, el d~gital vIdeo ~ignal i8 recc-rded by a ro~ary head assembly ~Fig. 6~ in ~arallel tracks e~ctending obliquely on a ~agnetic t~pe T (Fig. 8). Since the tr~nsmitting bit rate of the digital ~rideo signal i~ high, ~wo rotary heads HA and HB (Fig. 7) are di~posed in close proximity to each other, ~nd ehe digital video signal~ of one field are distributed through ~wo channel ~co such heads and recorded on the magnetic tape in two parallel tracks TA ~nd TB. An audio signal i8 also converted to a P~
(pulse code modulated) ~ignal and recorded by a rotary head Hc in ~ third track Tc extending p~rallel to ~he video tracks TA and TB ~Fig. 8).
Referring in de~ail ~o Fig. 4, it will be 8een that an ~TSC color video 2ignal to be recordea i~ ~pplied through an input tenDinal 1 to an input processor 2.
The input processor 2 compri~es ~ clamp circu~t and a synchronizing and burs signal separator and supplies the ef$ective or video information portion of ~he color video signal to ~n A/D converter clrcuit 3. A synchronizing signal ~nd a bur~ nal ~epar~ted from the color .
video signal by proces~or 2 are applied to a master.clock generator 4 w~ich is desirably of PLL ~phase locked lo~p~
construction. The ~aster clock generator 4 generates clock pulses of the sampling frequency, for example, 3fsc.
The clock pulses from generator 4 ~nd the synchronizing signal are applied to ~ control signal ~enera~or 5 which produces various kinds of timing pulses, identification signals (~D) for identifying lines, f~elds, frames and tracks, and a control signal, such as, a train of sampling pulses.
The A/D converter circuit 3 generally comprises a sample hold circuit and an A/D converter for converting each sampled output to an 8-bit code which is supplied, in parallel form, to an interface 6. The duration or period of one line (lH) of the NTSC color video signal is 63.5 ~s and a blanking period therein is 11.1 ~s. Accordingly, the effective video region or portion is 52.4 ~us. When the sampling frequency is 3fsc = 3X455fh, the number of samples in one horizontal period is 682.5. Further, the number of samples in the effective video region or portion is 52.4 ~s/Ts = 562.7 samples, where Ts is the sampling psriod equal to 0.0931217 ~s. In consideration of the division of the video information to be recorded into two channelsl the number of effective video samples is selected to be 576 per line or horizontal period with 288 samples being assigned to each channel. As shown in Fig. 9, two horizontal periods (1365 samples) are considered as one unit, with the total number of samples in the line in which a horizontal synchronizing pulse HD and the color subcarrier are in phase with each other being selected to be 682 and the total number of samples in the line in which they are out of phase being selected to be 683.
The number of lines forming one field is 262.5H, with a vertical synchronizing period and an equalizing pulse period accounting for 10.5H. Since test signals VIT and VIR are inserted in the vertical blanking period, they are also regarded as effective video signals.

~. - 16 -Finally, the number of eff~3c~iYe video lines in one field period is ~elec~ed to be 252.
The digitized effective video region of the color vldeo slgnal i.6 dl~Tided by the ln~cerface 6 into two channels. Of the 576 ~mples in each line, data corresponding ~o khe odd-nuD~bered ~mples are --igned to one of ~he channels ~nd data corre~ponding to the even-number~d ~mple~ are assigned to the other channel. ~e s~at~ of ~he t~o chalulel~ are proce~s~d in the ~ame manner. An external digit~l video ~ignal Din, for e~ample, :Erom ~n !ditiag apparatus, may also be 8upplied to in~cerface 6 to be suitably divlded into l:wo channels. The data in one of the channels i~ derlved as a record signal for head HA at an ou'cput terminal l~lA
after being applied, in sequence, ~o a time base compression circuit 7A, an error control encoder 8A, n recording proces~or 9A and ~ recording ampl~ fier lOA.
The data in the other channel ~s ~lso processed by 'che same arrangement, that ~, by a time base eo~pression circuit 7B, an error control encoder 8B, a recording proces~or 9B and ~ recording amplifier 10B, to provide a record signal for hesd HB at an output te~minal 11B.
The output terminals 1LA and 17B are connected by way of a rotary transformer tnot shown) ~o the rotary heads HA
and H~ disposed in close proximity to each other.
The code arrangement of each of the record ~ignals respectively provided at the output terminals 11A ~nd 11B
will now be described with reference to Fig. 10. As there shown, ~ sub~block of ~he coded digit~l signal i~
composed of 105 samples t840 bi~s) in which a block synchronizing signal (S~NC) of three ~a~ple~ (~4 bits), an identifying (ID) and ~ddres~ (AD) signal of two -17~

3~

samples (16 bits), information data of 96 samples (768 bits) and CRC (Cyclic ~edundancy Check~ code of four samples (32 bits~ are arranged one after another. The data of one line or horizontal period of the color video signal comprises 288 samples per channel~ as previously mentioned, and these samples are divided into three, that is, there are three sub-blocks for each line, with 96 samples for each sub-block. The block synchronizing signal is used for identifying ~he beginning of a sub-blvck, whereupon the identifying and address signals, the information data and/or CRC code can be extracted. The identifying signals ID indicate the channel (track), the frame, the field and the line to which the information data of the sub-block belongs, and the address signal AD reprPsents the address of the respective sub-block. The CRC code is used for the detection o an error in the information data of the respective sub-block.
Fig. ll shows the code arrangement for one field in one channel. In Fig. ll, each reference character S~i (i = 1~~58) indicates one sub-block, with three sub-blocks) making up one block or line. Since the effective video region of one field is comprised of 252 lines, as mentioned previously, the data of 252 blocks (756 sub-blocks exist in one field. The video information data of a particular field are sequentially arranged in a 21x12 matrix form. Parity data are also provided in connection with the horizontal and vertical directions, respectively, of the video information data in the matrix.

More particularly, on Fig. ll, the parity data for the horizontal direction is shown positioned in the thirteenth column of blocks, and the parity data for the 5~

vertical direction is posi~ioned in the twenty-second row at the bottom. In the thirteenth column of blocks at the twenty-second row is disposed the horizontal parity data for the vertical parity data. The parity data for the horizontal direc~ion is formed in three ways by 12 sub-blocks respectively taken out o the 12 blocks forming one row of the matrix. In the first row, for example, parity data SB37 is formed by the modulo 2 addition:
[SB ] ~ [SB4~ ~3 1SB7] ~9 ~ 9 ~SB34 37 In the above, [SBi] means only the data in the respective sub-block SBi. In this case, samples belonging to respective ones of the 12 sub-blocks are each calculated in a parallel, 8-bit form. Similarly, by the modulo 2 additions:
2 ~3 [ 5] ~9 [SB8] ~ ..-. ~ [SB35] = [SB3 ]
[SB3] ~ [SB6] ~ ISB9] ~ .... ~ [SB36] = [SB39]
parity data [SB38] and [SB39] are formed. The parity data is similarly formed for each of the second to twenty-second rows in the horizontal direction. Enhancement of the error correcting ability results from the fact that parity data is not formed merely by the data of the 36 sub-blocks included in a row, but is formed by the data of 12 sub-blocks positioned at intervals of two sub~blocks in the ~ow.
The parity data for the vertical direction is formed by the data of 21 sub-blocks in each of the first to twelve columns of blocks. In the first column, parity data [SB820] is formed by the modulo 2 addi~ion:
[SB ] ~ [SB40] ~3 [SB79] ~9 [SB781] [ 820 In this case, samples belonging to each one of the 21 sub-blocks are each calculated in a parallel 8-bit form.

-19 - , `;

Accordingly, these parity data comprise 96 samples as is also the case with ~he video da~a of each sub-block. In the case of transmitting the digital signal of one field of the above matrix arrangement (22x13) as a series of first, second, third, ..~ twenty-second xows in sequence, since 13 blocks correspond to the length of 12H, a period o~ 12x22 ~ 264H is needed for transmitting the digital signal of one field.
Incidentally, if the VTR is of the C-format type, and thus employs an auxiliary head for recording and reproducing one pa~t of the vertical blanking period in one field, then a duxation of only about 250H can be recorded with a video head. In accordance with the present invention, a duration of 246H, leaving a~margin of several H's, has to be recorded in each track, that is, the pexiod of 264H of data to be transmitted is time-base-compressed (with a compression ratio Rt of 41/44) to a period or duration of 246H. Further, a pre-amble signal and a post-amble signal, each having the trans-mitting bit frequency, are inserted at the beginning andthe tenminating end of the record signal of one field having the period of 264H.
The time base compression circuit 7 in Fig. 4 compresses the video data with the above-noted compression ratio 41/44 and provides a data blanking period in which the block synchronizing signal, the identifying and address signals and the CRC code are inserted for each sub-block of video data of 96 samples, and at the same time, sets up data blanking periods in which the blocks of the parity data are inserted. The parity data for the horizontal and vertical directions and the CRC code of each sub~block are generated by the error control --~0--~

encoder 8. The block synchronizing signal and the identifying and address signals are added to the video data in the recording processor 9. The address signal AD represents the previously noted number (i) of the sub-block. Further, in the recording processor 9 there areprovided an encoder of the block coding type which converts the number of bits of one sample from 8 to 10, and a parallel-to-serial converter for serializing the parallel 10-bit code. As disclosed in detail in Canadian Patent Application No. 356,745 dated July 22, 1980 and having a common assignee herewith, the block coding is such that 28 codes whose DC
levels are close to zero are selected from 21 whose DC levels are close to zero are selected from 21 codes of 10-bit and arranged to have one-to-one aorres- -pondence to the original 8-bit codes. By means of the foregoing, the DC level of the record signal is made as close to zero as possible, that is, "0" and "1'' alternate with each other as much as possible. Such block coding is employed for preventing degradation of the transmitting waveform on the playback side by substantial DC free transmission. It is also possible to achieve the same results by employing a scramble system utilizing the so-called M-sequence which i5 substantially random in place of the block coding. In the case where each sample comprises 8 bits, the transmitting bit rate per channel is as follow~:
(3fsc) x 8 x ~ x 4l = 46.097 Mb/sec.
After converting the above 8-bit code to the 10-bit code, the recording bit rate is as follows:
46.097 x 18 = 57.62 MB/sec.

In the reproducing or play back operation of the digital YTR ~ccording to thi6 invention, the two channels of reproduced signal ~ are ~erlved fr~m the head~ ~ Bnd ~B which ~can track~ T~ and T~, respectively, corresponding ~here~o, ~nd are ~pplied to reproduced slgnal input tenminals 12A ~nd 12B, shown in Fig. ~.
m e reproduced signals ~re ~pplied from terminals 12A
and 12B through plAyb~ck amplifiers 13A ~nd 13B to ~aveform shaping circuit~ 14A and 14B, respecti~ely.
Each of the ~aveform shaping circui~s 14A and 14B
includes a playback equalizer for increasing the high-frequency componen~ of the reproduced ~ignal ~nd shapes the reproduced signal to B clear pulse signal. Further, each waveform ~haping circuit 14A or 14B ~xtract~ a reproducing bit clock synchronized ~i~h the pre-~mble ~ignal and supplies the reproduclng bit clock to a respective playback processor 15A or 15B toge~her with the data. In each of the playback processors 15A ~nd 15B, the serial dat~ is converted to parallel form, the block synchronizing signal i~ extracted, the data i~
separated from ~he block ~ynchronizing signal and from ~he ID~ AD and C~C code~ or ~lgnal~, ~nd further, block decoding or 10-bit to 8-bit conversion i~ performed.
The resultin~ data i~ applied to ~ respective t~me base co~rector 16A or 16B in which any time base error is removed from the data. ~ach of the time base correctors 16A and 16B i~ provided with, for example, four memor~es, in w~lch reproduced dat~ ~re sequen~ially wri~en by clock pulses ~ynchronized w~th the reproduced data,'and the da~a are ~equenti~lly read ~ut from the memories, by reference clock pulses. ~hen the reading opera~ion is likely to get ahead of the writing operation, the memory from which the data has ~ust been read is read ag~in.

The dat~ of each channel ls provided ~rom the respective one of the time base correctors 16A and 16B
~o one of ~he other of error correct~ng decod~r~ 18A
~nd 18B by wsy of ~ cormDon interchan8er 17. In ~n ordinary playback oper~tion ~ whieh the rotary hesds ~aithfully ~c~n the recording ~:r~cks on ~e magnet~c t~pe or in 810w motion or Y~ill picture play~ack ~i ~hich the rotary heads ~re controlled in position ~o that they fai~chfully follo~ ~he recording ~racks respeetively, ~gnals are reproduced only fr~m the tracks TA and TB corresponding to ~he ~wo rotary heads HA and HB and supplied to ~he ~nput terminals 12A and l~B, respectively. Hc~wever, during high ~peed reproducing, in which the running speed of ~che magnetlc tape is as high as several tens of tic~es its ordinary ~peed, each of the rotary heads scans a plur~lity of recc>rding tracks. As ~ result, slgnal~ reprodueed fxom the tracl~
TA ~nd TB are ~ixed together in the 6ignals surplied to the lnpu~ terminals 12A ~nd 12B. In such a case, the intercha~ger 17 identifie6 the correc~ channels of the reproduced signals, u~ing track identifying signals, ~nd supplies the reproduced signal~ to the error correcting decoder 18A or l$B for the respective channel.
Each error correcting decoder 18A or 18B
includes error detecting and correcting circuit~ u~ng CRC,horizontal and vertic~l pari~le~, ~ field memory and B0 on, as later de~cribed in detsil. However, dur~ng high speed reproducing, no error detection and correction are carried ou~ and the fleld memory i8 u~ed instead for converting the intermittently received reproduced data of each channel lnto ~ continuous form. The data from each error correcting decoder 13A or 18B 1~ applied to ., . ., , . ~ . . . ... ... .
., ., . ~......... : ..

æ respective time base expanter circuit l9A or l9B, , respectively, ~hich return~ ~he da~ to ~he origin~l tr~nSmi~iDg r~te and then applies ~he d~t~ ko ~ c~mmon interface 20. The Interface 20 serves to re~urn the reproduced d~a of ~he two ehannels into a ~ingle ~hannel which ~n~lude~ a D/A con~erter circui~ 21 for conver~ion ~f the data lnto analog fo~m. Fr~m ~he ~nterfaee 20 there may al~o be provided a digital v~deo output Dout.
Since ~ digital ~ideo input and a digital video output are provided in the recording and reproducing ~ec~ions of Fig8. 4 ~nd 5, ed$ting and dubbing can be c~rried out with digital 6ignals, that Ys, without conver~ion fr~m and/or to analog form.
The ou~put from ~he D/A converter circui~ 21 is applied to an output processor 22, from which a reproduced color video sign~ provided at Rn outpu~
terminal 23. ~n external reference ~ignal i8 BUpplied from a termiDal 24 to a mas~er clock generator 25, fram ~hich clock pul~es ~nd a reference ~ynchronizing ~lgnal are provided to a control u~gnal generator 26. The control signal generator 26 provides control ~ignals ~ynchronized with the external reference signal, such as, various timing pulses, identifying ~ignal~ for the line, field and frame, and ~ample clock pulse6. In the reproducing sec~ion,~he processing of the ~i~nals from input terminals 12A ~nd 12B to the ~put ~ide~ of t~me ;base correctors 16A ~nd l~B i8 t~med by ~he clock pulse extracted from the reproduced da~a, whereas the processing of the signal~ fro~ the ou~p~t ~ides of the t~me base correctors 16A and 16B to ~he output term~n~l 23 ~s timed by the clock pulse fr~m the master clock generator 25.
Before providing a more detailed description of the error correcting decoder~ l~A and 18B ~mbvdying ghe pre~ent inven~ion, ~he encoding operation OI' ~e error c~ntrol eDcoders 8A ~nd 8B ~111 be described with reference to ~igs. 12A-12D. In ~ig. 12A, a timing pulse ~DST i~ sho~n wh~ch indic~es the beg~nnlng o~ a data section ln one field ~nd, irl Fig. 12B, there ~
shown a par~llel, 8-bi~ d~t~ series nwi ~upplled frsm the time base compres~ion circuit 7A or 7B. The effective data ln one field are cont~ined ~n ~ total of 756 (~ 12x21x3) 8ub-blocks, ~and that data series DWi is shown to have a time Ælot in w~ich to in~ert the CRC
code following each sub-block ~nd a ~ime ~lot in which to insert horizontal parity data every 36 sub-blocks.
The length of time encompassed by one horizontal row of 39 blocks, including 36 sub-block6 and the time 810~
for the insertion of the horizontal parity data correspond-ing thereto, i~ 12RtH or ~12xzz~xH). Fig. 12C show~
timing PU1se~ }IPT, ~PT and CRCT ~hiCh aSSUme high 1eVe1~
"1" in the time S10t~ in whi~h ~he hOriZ~nt~1 Pari~Y, the VertiCa1 ParitY and the CRC COde, ~eSPe~t$Ve1Y~ ~re ~0 be 1nSerted.
The data 8~rie5 DWi ~8 ~PP1ied t~ a COnVentiO
Vertie~1 ParitY gener8t~ng CirCUit (n~t ~h~Wn) and 36 VertiCa1 ParitY data ISB820] t 1SB8551 generated by ~hi~
circuit are added, a~ the ~iming pul~e ~PT, ~o the delay~d data serles DWi. Nex~, the data ~eries DWi including the -vertical parity dat~ ~s supplied to a con~entlonal horiz~ntal ParitY generating eircuit (not shown), in which three horizontal parity data for the data serie~ of one horizontal rv~ are generated and added~ ~t the timing pulse HPT, to the data series DWi. Then, the CRC code is ~dded to the data series DWi in the period defined by the ~lming pulse CRC~ to provide a data ~erie~ DUo, as ~hown ln Fig. 12D. A~ ~2~ cr~bed previou~ly, ~t th~
beginning of eac~ ~ub-bl~ck of the dat~ ~eries DWi from the time base compre~sion circui~ or the data series D~o from the error control encoder ~, there is provided ~ t~me 810t in which ~he block ynchronlz~ng 8ignal and the identifying snd ~ddre~ ~ignals are added. In this way, ~ dat~ period of 246H is provided in each field period of 262H ~or 263H), ~nd, ~f~er ~
data bl~nk of 16H, the data of ~he nex~ field starts.
When the data ~eries D~o and the acc~mp~nying block 6ynchronizing and identifying ~nd address si~nals are recorded and then reproduced, ~he arrangement of the resulting data ~eries DRi (F~g. 14B) reproduced frQm the magnetic tape and applied to error corxecting decoder 18A or 18B ~ the same as that o~ the da~a series DWo shown in Fig. 12D.
Referring now ~o Fig. 13, it will be ~een that each of the error correcting decoder6 18A and 18B
embodying the present inYention generally comprise~
horizontal section 27 for performing error detection and correction by the CRC code and the horizontal parity da~a, and ~ vertical section 28 for performing error detection and correction ~y the CRC code and ~he vertichl parity da~a.
The parallel, 8-bi~ data ~eries DRi (Fig. 14B), which i~ reproduced from ~he magnetic tape by the head HA or HB and passed through the waveform ~haping circuit 14A or 14B, the playback processor 15A or 15B, and the tlme base corrector 16A or 16B, is supplied first to the horizontal section 27. A timing pulse RDST ~Fig. 14A3 defines the first timing of the data of one field.

.. ,.. , .. ,, ,,.. , . .. .. ,.,, .... . ,~ .. . ... . . .. . . .. .. .. .

~e data series DRi ~Fig. 14B) include6 in one field the period from a firs~ horizantal row period ~ of the matrix (Fig. 11) to a twent~-second horizontal row perisd TH21. A CRC ~hecker 29 is 8h~0Wrl to be ~cluded in horizontal section 27 and perfor~s an error detec~iDn for e~ch ~ub-bloek and yield~ ~n error ~ignal l~ hich - i~ ch~nged-over to ~he high level "1" only when an error i~ detected ln the d~tR ~er~es, ~nd whic~ i8 otherwise "O". All bit~ of each ~ub-block are checked for ansr error therein ~nd, ~hen e~ren one bi~ iB
erroneous, the ~ignal ERR is held at "1" for ~he period oIe the sub-block following the c~ne cont3ining the error (Fig. 14C~. The error ~ignal ERR i~ fed to a horizon~al judging circuit 3û. The horizontsl ~udging circuit 30 delays the error ~ignal ERR for a period corresponding to thirty-eight blockæ to fo:nn an error flag ERFLG (Fig. 14D) and, as described later, produces for each sub-block a ~udging signal CRCTH (Fig. 14E) which indicates whether or not ~he error i8 correctable, with signal C:RCTH being "1" when the error i6 correctable an~ "O" when the error i8 not correecable.
Further, the data ~eries DRi i~ supplied to a horizontal parity checker 31 ~o derive therefram a horizontal syndrome sequence SDH (Fig. 14F). The horizontal syndrome i~ calculs~ed in one horizontal row period (12RtH) ~nd held 80 ~ha~ it may be used for ;an error correction in ~he next horizontal row per~d.
In order to effect the foregoing, ~he horizontal pari~y checker 31 ~ncludes tw~ parts which alterna~ely perform the calculation of the horizontal ~yndrome snd the holding of the calculated horizontal syndro~e. In Fig. 14F, khe horlzont~l syndromes for the d~ta of the horizont~l row period ~Ho-TH~l are indicated at _~7 ~

SDHo-SDH21, respectively. l;ach horizontal syndrome 5DHi repeats the same content every ~hree sub-blocks.
The data ~eries DRi i~ ~180 applied ~o a buffer memory 32 in which ~t 1R delayed for one h~rizontal row period and then ~upplied to ~n ~rra~
correc~ing circui~ 33. l~e ~rror correc~n~g circui~ 33 ~naploys ~he horizontal ~yndroD~e SDHi to correct each ~ub-block indlc~ted ~co coalt~in an error ~by ~:he respective sign~l ERFLG being "l~')which i~ ~urther indicated ~o be oorrectable (by the respective ~i~nal CRCTH being "1"). The error flsg ERFL~ for ~he ~ub-block thus corrected ~ changed to "O" resulting in An error block ~ign~l E:RBLl~ shown ~ Fig. 14G. The data of the ~ub-block~ for which the error block ~ignal ERBLK iS "1", fOr example, 1SB2~, [SB75] . 1SB7BO3 [SBglg3 ~nd tSB~35g3, are thereby shown to contain error~ which have not been corrected by the horizontal parity .
The data sequence from the error correc~ing circuit 33 of horizontal ~ection 27 i8 ~pplied to a f~eld memory 34, ~ ~ub-memory 35 ~nd a vertical parity checker 36 which are included in ~he vertic~l sec~ion 2B.
Further, the error block ~i~nal ERBL~ from horizontal 3ectlon 27 i~ supplied to ~ vertic~l ~udging eircuit 37, field memory control circuit 38 ~nd a ~ub-memory control cir~uit 39. In thl~ c~e, since 66 sub-blocks composed of horizontal parity da~a are not u~ed after the error correction in the horizon~l or rvw direction, they ~re not stored in field memory 34. The 36 sub-blocks composed of vertic~l parity data are also not stored in memory 34.
Accordingly, the field memory 34 need only have a capacity for 756 sub-blocks and the P~M data ~re written ~n ~he field memory 34 one after another wlth reference to the addres6 ~lgnals of the reEpec~lve sub-blc~ck~q.
In the writin~ of the :PCM d~a ~r~ the field memory 34, the leading ~ub-block of each fr~lme i~
~hifted by three sub-block addre~es corresponding- o one line, ~nd a~ de~cri~ed previously, each sub-bl~ck ~ written in the same ~ddre~s ~8 the ~ub-block ~f ~e previous field positioned one line bel~w the former in the pic~orial represent~tion of the c~mple~e frame.
Each ~ub-block which has no~ been corrected ~n the horizontal section 27, that is J ea~ ~ub-block for ~ich the error block signal ~RBLK i~ "1", is inhibited by the memory control circuit 38 from be~ng written in the field memory 34. If each ~ub-block thu8 inhibited from being written in the field memory 34 i~ written ~n sub-memory 35 in response to the respective ERBI~
signal moni~ored by the sub-memory control c~rcuit 39 being "1", it i8 p~ssible that, w~en many error~ occur, the sub-memory 35 may overflow or, if the ~ub-memory 35 i8 arranged not to overflow, itB oapaclty has to be very large.
In view o thi~, ~ detection signal CRCTBL
iR generated by the vertioal ~udging circuit 37 and applied to the sub-memory control circui~ 39. The vertical 3udging circui~ 37 also gener~te~, for each sub-block, ~.~udging signfil CRCTV (Fig. 14I) which i8 "1" when the error ~B correctnble ~nd "0" when the error is not oorrectable by ~he vertic~l pari~y, as described later. In the present embodiment, the vertical ~udging circuit 37 i5 designed 80 that while data of an ith field i8 supplied from horizontal ~ection 27 to vertic~l sec~ion 38, the ~udgin~g signal CRCTV5 ~. for , .. . . . . . , ... , , .,. . ... , .. .. . ., .. , ... . , ., ~, . . . .

t5~

the (i-l) th-field preceding ~he ith field i8 provided.
At the 6ame e~me, i~ i~ detec~ed whether or ~ot ~he ~ub-block of the ith field ~hose error block sign~l ERBLK is "1'l c~n be corrected by the ver~ical p~rity.
In other words, when two or more of the 22 ~ub-bl~d~s in the 36 ~olumns in ~ig. 8 are sub-blocks for ~hich the error block 8ignal8 ~RBLR are ~ ', no error correction iæ po~sible, and, therefore, the detec~ion signal CRCTBL i~ ch~n~ed from "1" to "O". A8 ~
consequence, only those erron~ous ~ub-blocks w~ose ~ignals ERBLK ~nd CRCTBL ~re both "1'~ are seored in the sub-memory 35. At the same time, the addres6 of ~ach of the sub-blocks written in ~he sub-memory 35 i~
stored as a vertical error flag SFLG, ~s later described.
In order that during writin~ of the lth-field, the sub-block and the error flag SFLG ~tored a~ described above may be read out for correcting the error in the (i-l) th-field by the error correcting circuit 40, each of the sub-memory 35 and the ~ub-memory control circuit 39 includes ~wo part~ for wri~in.E~ and reading, respec~i~re dur~ng 8 certain f~eld per~od.
Since a sub-block ln each channel includes 96 samples in parallel, 8-bit configuration, ~s described previous ly, the total number of blt~ of the PCM data of on field ~ 580608 ~ 8x96x~56). llsirig the error rate (the prob~bility of bit ~rror) of the recording--reproducing system of the dig~t~l VTE~ ns ~ p~rameter ~nd ~ss~Ding that error~ do not center on the s~ne block but scatter to each sub-block for one erroneous bit, the n~ber of erroneous sub-b~ocks per channel in one field :18 as foll~w&:

Error rate _Number of erroneolls ~ub_lockl:
10-2 5806.
10-3 5~0 . 6 10~4 58 . 1 ~. 8 -6 1~.. 6 ....... -__ If lt i~ ~gumed ~hat ~he error r~te of the ~ctual recording-reproducing ~ystem i8 abou~ 10-5, capacity o$ sub-memory 35 corre~onding tn slx sub-bloeks w~ll be sufficient ln ~lmost all cases. Since the writing in ~ub-m~moxy 35 ~ controlled with reference to detection ~gnal CRCT8L, ~ described previously, when two or ~ore ~ub-blocks are erroneous in any one vertical column, only ~he fir~t one of the erroneous ~ub~blocks is written i~ ~u~-memory 35 80 that nn overflow of the ~ub-memory 35 can be avoided in almost all cases.
The data of ~he previous field is read out from field memory 34 or ~ub-memory 35 and supplied to the error correc~in~ circuit 40. In re~pect to e~ch sub-block for which ~he vertical error flag SFLG iæ
stored, the data from sub-memory 35 i8 given priority over the data from fleld memory 34 in being supplied to correcting circuit 40. For all o~her ub-blocks, the data from the field memory 34 i8 supplied ~o circuit 40. Correctable errors remaining ln ~he data applied to vertical sectio~ 28 ~re corrected by the~d~ta from the sub-memory 3~ and the ~ertical syndrome sequence SDV (Fig. 14H).
Each p~rt of the above briefly describ~d error correcting decoder 18A or 18B will now be described in greater detail, starting with reference to Fig. 15 which rel~tes ko ~he horizontal judging ~ircuit 30 supplied with the errc)r ~ignal ERP~ from the CRC checlter 29 eo proYide the error f la~ ERFLt~
and the ~udging ~ignal CRCTE~.
More par~icularly, Fig. 15 illustrates ~he collstr:uction of vne of ~he l:wo p~ar~s of cireult 30~
which operate alternately at e~ery horizontal row period. As shown, 'che error ~nal ERR i8 delayed by a ~hift regist~r 41 for a period correspond~ng t~
38 blocks, thereby to generate the error flag ERFLG.
The ~udgement as ~o whether e~rror correction by the horizontal parity is possible or no~ i~ carried out in the followlng manner: Since one horizontal row fo~s three error correcting block eodes e~ch of which comprises twelve data ~ub-blocks every lthree blocks and one horizontal parity sub-block, one horizontal row i8 proces~ed as three equivalently independent rows to detect how many sub bloeks are erroneous ~
each of the three ro~. ~hen ~wo or more ~ub-bls)cks are erroneou~, the ~udgement i8 ~aade th~c the error oorrection is impossible. A D-type fllp-flop 42, a counter 43 and a decoder 44 derive from timing pulses HBL~S ~Fig. 16B3 of the ~ub-block period synchronized with ~he tata series DRi~ gate pulses Y2~ ~1 and ~0 ~Fig. 16C) corresponding to the respeet~:ve sub-block~ in one bloc1c.
~lore particularly, ~ timing pulse RDST (Fig. 16A) indicates the beginning of the data section of the data ~eries DRi of each field ~nd, in the ~eriod in which timing pulse RDST is "1", D-type 1~p-flop 42 ls cleared and the timing pul~es HBl:.KS (Fig. 16B) synchroniæed by the D-type flip-flop 42 with the data series RDi are applied as load pulses to the counter 43 . Thereaf ter, counter 43 L~3~

counts the timin~ pulses HBLKS and ~he output from the counter 43 i6 deeoded by decoder 44 ~o ~enerate the three phase gate pul8e~ ~2~ ~1 and Yo ~hown $n ~ig. 16C.
The ~ate pulS2 ~ becomes "~" for a period corresponding ~o a first sub-bl~ck of each block; the ~ate pul~e ~l ~ecomes "O" for a period correspondin~ to the ~e~ct ~ub block; ~nd the gate pul6e Yo bec~mes "O" for a period correspondlng ~o the third ~ub-block of eaeh bloek.
The dat~ ~eries DRi 8hown ~n Fig. 16D indic~tes the 8tarting psrt8 of the first, second and third horizontal row period THo~ T~l ~nd TH2 of ~ certain field.
A pulse ~P-~-E~ is obtained by inver~ing a tLming pulse EPCEN shown in Fig. 16F whioh becones ~10l~ at the end of one horizontal row of ~hi8 data, and a ~iming pul8e (Fig. 16E) is provided by delaying the t~min8 pul~e HBLKS through a shift register 45 ~usin~ a sample clock pulse RCK as a shift pul6e) ant by inverting the output through an inverter 46. The pulses ~F~E~ and ~E~F are ~pplied to an Q~ gate 47, and th~ output from th~ AND
gate 47 is inverted by an inverter 48. D-type fli~-flops 49a, 49b, 50~, 50b, 51a and 51b are cleared foreach horizontal row period by the ~nverted output ~f 8ate 47. Flip-flops 52 9 53 ~nd 54 ~re provided a~ ~he output sides of ~he pairs of flip-flops 49a and 49b, 50a and 50b, and 51a and 51b, and the ~u~putof AND gate 47 iB used ~s ~ clock pulse for flip-flops 52, 53 and 54.
At ~he ~nd of each horizontal row period, ~he outpu~
from flip-flops 49b, 50b and 51b ~re transferred t~
flip-flops 52, 53 and 54 and i~me~ia~ely thereafter flip-flops 49a, 49b, 50~, 50b,51a and 51b are cleared.
Fig. 16~ shows ~ signal ~ obtained by inverting the error signal ER~ from CRC checker 29 by an -n~Jerter 55. The error 6i~nal ~ is ~upplied to NOR
gates 56, 57 and 58 and di~tingui~hed by ~he gate pul~e~ Y2 ~ ~nd ~O~ (htput pU18e6 3ECl (Fig. 16H) from NOR gate 56 ~re u~ed a~ clock pul~es fc~r flip~ ps 49a and 49b; output pulses EC2 fr~m NOR gate ~7 are used ~s clock pulses or flip-flops 50a snd 50b; ~nd output pul~es EC3 from the NOR gate 58 are used s~ ck pulses for flip-flops 51a and 51b. To ~che ~nput of each of flip-flops 49a, 50a aund 51a 1~ always applied 8 l~vel "1" (+~cc~. ~s ~hown in Fig. 16G, the error signal ~, ln the case of sub-blocks lSBl~, [sB4] 1 1sB41J ~ lSB42] ~nd 1S~78] ~ontaining error~, is ~eparated by gate pulse,e ~2 ~1 and ~1 into error pulses ECl, EC2 and EC3 (Fig. l~H) of the three equivalent horizoncal rows. In the horizontal row period THo, two error pulses ~Cl are derived rom NOR g~e 56 only, 80 tha~ t the end of the perlod ~0, the output fro~
flip-flop 49b becomes "1" and the outputs from the o~her fl~p-flops 50b and 51b are ~'0", and ~hese outputs are stored ~n flip-flopR 52, 53 and 54 at the ne~ct ~tage.
Accord~ngly, the ~ignal~ respectively held in flip-f lops 52, 53 and ~4 are ~ndicated at ~R-~T-~I, C~CTH~
and C~CTH~ ln Fig. 16I. In the next hori7-ontal period THl~ only the 8~gnal CRCTHI becomes "1". The outputs from flip-flops 52, 53 and 54 are respectively applied to NOR ~ates 59, 60 and 61 together with the p Y2, Yl and Y0 ~ig. 16C), and the outpu~c~
from NOR gates 59, 60 and 61 are fed to an OR ~ate 62 to derive therefrom a ~udging ~ignal CRCTH (Fig. l~J).
In the RboYe way, the ~udging ~ignal C~CT~I
is made ~o be "1" or "0" ~ dependence on whether the erroneous sub-block ~ 8 correctable or not, respectively, ~ ' 4 by the horizontal parity.
Referring now ~o Fi~. 17, ~t will be seen that the horizontal parity checker 31 there ~llustrated i~ pro~ided with tw~ part which alterna~e, at every horizontal row period, irl performing ~ hori20ntal syndxome c~lculating oper~tion and 8 horizontal 8yndrome holding opera~ion, re6pectively. ~he tWQ
parts of checlcer 31 respectively comprise adder~
S4A and 64B, which may be formed by clu~ive OR gates and each of which adds eoge~er the parallcl 8-bit series DRi and a fed-bac~c parallel 8-bit dat~ series DRl' in accordance with ~he algorithm of ~mod. 2).
Parallel, 8-bi~-inpu~ RAMs 65A ~nd 65B respectively receive, as data inputs, ~he ou~puts from the adders 64A and 64B snd latch circuit~ 66A and 66B ~re respectively supplied with the output data fr~m the RU~s 65A and 65B. The contents of latch circuits 66A and 66B are alternately selected or read out by a multiplexer 67 every h~rizontal row period to form the horizontal syndrome ~equence SDH.
Each of the RAMs 65A and 65B has a capacity capable of storing data (288 samples) of three ~ub-blocks and their addresses are sequen~ially changed from O to 287 by clock pulses RCK (Fig. 18A) of the am~ling period. The RAMs 65A and 65B are cleared by a clear pulse PSACL (Flg. 18B) which become~ "O" at every three sub-blocks of the tata ~eries DRl. As de~crlbed above, a sub-block of the data serie~ DRi includes data of 96 samples, block synchronizing s~gnals, ~ddress 3ign~1s and identifying 3ignals of five sa~ple~ preceding ~he dat~
and CRC code~ of the ~our samples following the dat~.
In the data blan~ing period between the sub-blocks, the b~
~upply of the ~ample clock RCK to the ~ddress counter ~ stopped to prevent stepping of the ~ddress, and the content~ ~f RAMs ~5A arid 65B are repeatedly read ou~c.
~ig. 18C shows variations in the addresses ADR OI' the RAMs 65A ~and ~5B. In the firs~ horizontal row period l~io of a certain field~ ~he read contr~ gnal ~~
(Fig. 18D) ~pplicd to RAM 65A c~uses it ~o oper~te~
~n the mode shown in ~i,g. 18E ~n which the hatched ~ections W repre~erlt ~rite cycles and the ~ection~ R
represent read cycles. In the horizorl~al row perlod THo, the control sign~l ~ (Fig. 18F) applied to ~AM 65B i8 in ~he sta~e "1", ~o that no data i~
wrltten in the RA~ 65B. In this period THo, the output from latch circuit 66~ i8 selected by multiplexer 67, but ~ince tl is is the r'irs~ horizont~l row period, no effective syndrome ic av~ilable fron~ latch circui~ 66B.
Further, ~ple cloclc pulses 3~ ~re applied as latch pulses to latch circuits 66A and 66B, and the data read out from RAMs 65A and 65B are sequentially taken in by the latch pulses ~: in the latch circuits 6~A and 66B. Xowever, latch clrcuit~ 66A ~nd 66B are respectively ~upplied wi~ch timing pulses HPCENA and ~PCENB (Figs. 16M
and 16N) wh~ch ace as clear pulses therein. These timing pulses HPCENA and HPCENB become "O" ~lternately with each other in the period of fir~t ~hree ~ub-blocks of successive horizontal row periods ~Hi of the field.
When either of the ~iming pulses HPCENA and HPCENB is "O", the latch circui~ 66A or 66B, respectively, i~ held in its cleared state and the ~-bi~ output DRi' therefrom i8 "O" in all bits. As a consequence, the first three sub-bloc~s in each horiæon~al xow reriod ~re writ~en in the RAMs 65A and 65B ~ithout any change though ~pplied ..... ,, ,. . , , .. . .,, , , ., , ... , .... , " ,... .

via the ~dders 64A ~nd 64B.
In the presently described embc~d~ment, da~
of 2B8 ~mple~ contained $n the first three sub-blocks ~;Bl, SB2 ~nd SB3 in the horizontal r~ period T~ ~e wri~cten, without change, in addres e~ O to 287 of ~!~ 65A. In the d~ bl~ ng period be~een the ~ub-blockfi SB3 ~nd SB4, the address 0 remains unchanged and henee no write operatlon t~ke~ place. A180 in ~he perlod iTl which the ne:~t shree sub-block~ SB4, SB5 and SB6 of data series DRi are sequentially ~upplied, the ~ddress o~ RAM 65A ~imilarly changes fr~m O t~ 287 in a se~uential order. A~ is evident from the Dode shown ~n Fig. 18E, the read cycle for ~ch ~ddress ~reeedes ~che write cycle, and parallel, 8-bit data of one ~ample read out prior ~o the wrlting question ~s loaded or taken ln the latch circuit 66A and fed back as an input DRi' to adder 64A. For exsmple, in the addresses 0 ~o 95 of RAM 65A, there has been ~tored da~ca of 96 samples of the sub-block SBl, and in the period in whi-~h the data of one ~ample i8 read out from each of the ~ddresses O to 95, a re~pective sam~le of the sub-block SB4 is supplied a~ the input data ~eries DRi. ~n other words, in the adder 64~, ~he corresponding samples of the ~ub-blocks SBl and SB4 are added together in a parallel, ~-bit form and the result~ of such addition~ are rewritten in ~he addresse~ O ~o 95 of R~I 65A.
When the aub-blocks SB1 to SB39 forming one horizontal row have all been ~upplied by repeating-the above operation, there i8 stored in ~he RAM 65A a syndrome SD~o concerning the first horizontal row.
More particularly, in the addresse~ O to 95 of RAM 65A, there are stored the result~ of additions of ~he .
~37-,.. ~. ........ . ... .. .. .

;

eorresponding ~amples of ~he sub-block~ S~l~ S~4, SB7, ... SB34 ~nd SB37; in ~he addresses 96 to 191 of ~ ~ 65A, there are stored the re~ults of additions of the corresponding ~ample~ of sub-blocks SB2~ SB5, SB~, ...
SB35 and SB38; and ~n the addresses 192 ~ 287 of RAM
65A, ~here ~re ~torea ~he result~ of ~dditlons of the corre ponding ~mple~ of ~he ~ub-bl~ck~ SB3, ~B6~ SB9, ... SB3~ ~nd SB39~ If the ~ample~ of the ~yndr~me SDHo are all "O", then it ~ 8 indicated thereby ~hat ~he da~a in the first horizontal r~w i~ not erroneouB;
conver~ely, if e~en one of the eight bits formin~ of the syndrome i~ "1", then i~ lndica~es that the data includes an error. W~en only one of the ehirteen sub-blocks constituting each of the three error correcting block codes is erroneous, the error ean be corrected by the modulo 2-addit~on of the erroneouc sub-block and the part of the syndrame SDHo corresponding ~o the erroneous sub-block.
In the next horizontal row period THl, ~ince the write control signal W~ (Fig. 18D~ for the RAM 65A
i8 ~ , only the read-out operatio~ of the ~M 65A 1%
repeatedly effected, ~s depic~ed in Fig. 18E. At the same time, the multiplexer 67 i~ made to select the output from latch c~-rcuit 66A by the ~elect ~ignal SHSL (Fig. 16L) for the multiplexer 67 be~ng "O". The syndroDe SDHo thus read ou~ from RAM 65A is made synchronous by the sample clock ~R applied to latch circuit 66A and i8 derived at the output by way o~.multi-plexer 67, as depict~d in Fig. 18H. The address ~DR i8 again made to vary from O to 286~ as shown in Fig. 18C, and is synchronized with thé data series DRi del~yed by the buffer memory 32 for one horizontal row period.

-3~-In the horizontal r~w period THl, the write control signal ~ (Fig. 18F) applied to ~M 65B, ~uses rep-eated alternation of the re~d ~nd the write cycles ~f RAM 65B. Accordingly, the ~yndr~me SD}~l f~r the second horizontal TOW c~mpo~et of the su~-blocks &~
to SB78 f 8 calculated. When the ~elect ~ignal S~SL
i8 "1" in the next horizontal row period TH2 (Fig. 16L) ~he syndrome SDHl i8 r~ad out from the RAM 65B ~ia latch circuit 66B and ~ultiplexer 67. By repeati~g ~uch operations, syndromes SDH~ to SDH21, respectively, for 22 horizontsl row~ of o~e field are all obtained.
The buffer memory 32 i~ provided to hold ~he input data eries DRi in it~ waiting ~tate while the CRC checker 29 detects an erroneous block and the horizontal parity checker 31 forms the horizontal syndrome ~equence SDH, as descrlbed above.
Since the cycle ti~e of the RAMs in checker 31 is slower than the tran~misælon s~eed of the input data ~eries DRi, parallel,4-sample (32-bit) processing i~
performed. The data (~6 ~amples) in e~ch sub-block and the address and identifyin~ signal (two 8~mple8) preceding the data are delayed by the buffer memory 32.
Since the total n~mber of 6~mple~ ~n ~hi~ case i~ 98, which i5 not a multiple of four samples, they are processed ~8 100 ~amples including, a~ dummies, ~wo samples in the part of the CRC code. More partlcularly~
as shown on Fig. 19, first two samples o~ the lnpur data series DRi are latched in one latch circuit 6~R
at the lnput sl~e of buffer memory 32. Then, the nex~
two samples are latched in another latch circuit 68B, by which ~he input data series DRi i8 converted to parallel, 4-sample form. The ~wo samples latched in s~
latch circuit 68A ~re written in a RAM 69A, and the two samples in latch circuit 68B are written ill a RAM 69B. If ~t i6 ~sumed that vne su'b-block ineludes 100 8amples, then one horizontal ro~? of the matrix includes 3900 8amples. The totlll capacity ~f the RAMs 69A and 69B ~ ~elected ~o ~chat the ~M6 CUl ~ore Ithe data of at least one horizont~l r~w. lrhe RAMs 69A and 69B are c~ch ~upplied with the data ~n parallel, 2-sample form, and ~he addre~ of each of these RA~s is sequentially varied from 0 to 974 every

4-sample period. When flrst and second samples of .
certain sub-block are latched in latch circuit 68A, two ~amples of the pre~iou~ horizontal row are read out from the address 0 of ~he RAM 69A and latched in a latch circuit 70A at the outpu~ ~ide, and when the third and fourth ~ampl2S are latched in latch circuit 68B, ~he fir~c ~nd second ~amples are written in the address of R~M S9A. The o~her RA~ 6gB is adapted to perform a read operat~on during the write cycle of ~ 69A and a write operatio~ of ~ 69B i~
performed during the read cycle of RAM 69A. In other words, the R~ 69B conducts the ~ame operations ~s the ~ 69A, bu~ delayed by two samples o~ the input data series DRi.
The four ~amples, ~lternately read ou~ from ~he RAMs 69A and 69B and latched in corresponding latch circuits 70A and 70B are ~aken ou~ one-by-one in a -sequential order and applied to one input of a modulo-2 adder 71 which for~s the error correcting circuit 33. To the other input of adder 71 is a~plied the horizontal sequence SDH generated by horizon~al parity checker 31. In ~he illustr~ted embodiment, the -~0-~yndrome sequence 5DH i8 provlded to adder 71 by way of a delay circuit 72, for ~x~mple, in the form of a ~hift regis~er, and a gate circuit 73 for effect~ng phase synchronization of the syndrome sequence ~ith the data 6eries. The delay circuit 72 al80 receiv~s ~ t~min8 pulse HBLXE ~8 a clear pulse. The ~ming pul~e ~B~KE
i6 ~milar to khe t~ing pul6e ~BLXS (Fi~. 16B) ~nd ~ ~nhibitc ~neffective data of he ~yndr~e w~ich oceur in the data blanking period between ~ub~block~. In other words, during the da~a blanking period9 the syndrome is conv~rted 80 ~hat all lts bi~s may bec~e "O", thereby preventing any change in the identifying and addres~ signal included in the data ~erie~ from the buffer memory when applied to the adder 71.
The gate circuit 73 i~ provided to su~ply only the syndrome corre~ponding to a ~ub-block containin~ a correctable error. The gate clrcuit 73 i~ controlled on the basi~ of t~e ~udging ~ignal CRCTU
fonmed by the horizontal ~udging circuit 30 ~nd the error flag E~FLG. Four combinationæ of the values "1" ~nd "0" of 8ign818 CRCTH and ERFLG mean the following:
(1) CRCTH - "0", ERFLG s "0": The ~ub-block iB contained in an uncorrectable horizontal row, but the sub-block itself doe~ not contain an error. Accord-~ngly, the ~ate circ~t 73 i8 ~FF.
(2~ CRCTH ~ "0", ERFLG ~ The sub-bl~ck is contained in ~n uncorrectable horizontal row, and 18 itself erroneous. Accordin~ly, the gate circuit 71 i6 OFF.
(3) CRCTH ~ "1", ~R~LG ~ "O": ~he ~ub-block iæ cont~ined ~n a correc~able h~rizontal ro~, bu~ i~ not erroneouæ. Accordin~ly, ~he gate circuit 73 1æ OFF.

(4) CP~CTH ~ "1", I:RFI.G ~ The ub-block contained ~n a correctable horizon~al row, ~nd ~che ~u~-block oont~lns ~n error. In thi~ ca~e only, the gate cirouit 73 i8 turned 0~ &nd l:he error i6 correc~ced by ~che modulo-2 ~dder 71. --The c~u'cput rom the ~ate oircuit 73 i8 "O" ~n~11 bit~ ~hen $~ it~ O~T state, ~nd, ~o loalg as gate circuit 73 ls ~n lts OFF ~tate, l~he da~ca applied to adder 71 does not change.
In order to achieve ~he above, ~he ~udging ~ignal CRCTH ~nd the error fl~ ERFLG are lprot~rided ~o an AI~D gate 74, and when the output of the latter becomes "1", ga~ce c:ircuit 73 i~ turned 01~l. Fur~her, a ~udging signal ~ obtained by i~Yer~iI3g the ~ignal CRCTH by means of an inverter 75 and the error flag ERELG are applied to an AND gate 76 to derive therefrom the error block ~ignal ERBLR ~ich becomes "1" for a sub-block which is 2rroneous but uncorr~ctable by the horizontal parity.
It will easily be understo~d that the compoDents of the horizontal section 27 deseribed above with reference to Figs. 15-19 perform the error correcting operations earlier described wi~h reference t~ Figs. 14A-14G.
Next, ~ m~re detailed description will be g$ven of illustrative embodiment~ of various part~ of the vert~c~l section 28 of the error correcting decoder 18A or 18B according ~o this inven~ion, The vertical par~ty checker 36 c~n be impleme~ed in a ~anner slmilar to that of horlzontal parity checker 31. A
vertical syndrome SDVi o~ 96 x 36 ~ 3456 sa~ples ~ 8 formed by the ~odulo-2 addition, in a parallel, 8-bit fonm, of ~he corre~ponding samples o 22 sub-block~
included in each of fix~t to ~hir~y~slxth columns in the eode ~rrang~men~ of Fig. 11. To perf~rm the foregoing, at a ~me whe~ a sub-block included in a certain column is bein~ supplied ~o the Yer~ic~l -.
parity checker 36, the inpu~ ~u~-block data and ~he read out sub-bloek data fram the ~sme column but ~he ~mediately preceding horizontal r~ period ~re calculsted by modulo-2 additions, find the resul~ of such calculation are wr$tten at the 8ame addre~.
For example, at the ~ame ~me of supplying the sub-block SB79 to the vertical parity checker 36, 1SB1] ~ [5B40] i8 calculated as read-ou~ data together with inpu~ dat~ ~nd ~he results of calculation [SBl]
lSB4~ SB79] are wTitten at the ~ame address.
5uch read and write operations for the ~ame address are carried out for each address of ~ horizontal r~w (36 sub-blocks) ~eq~entially and this is repeaeed for each of 22 horizontal r~ws. After thi8, in a RA~I
(not shown) of the vertical pari~y ehecker 36 are formed and stored vertieal syndromes respect~vely corresponding to fir~t to thirty-si~th column~. A~
is the case with the horizontal parity ehecker 31, vertical syndrome ~onmet ~n a certain ield period ~8 held ln the next field period. Further, ~milarly to the horizontal oarity checker 31, the vertical parity checker 36 i~ provided with two ~ections whi~h respectively perform the Yertical syndrome forming^
operation and the vertical syndrome holding operation, alternately. Thus, the vertical syndromes which are alternately held form a ~yndrome ~equence SDV as depicted in Fig. 14H.

5~
.
A~ shown in Fig. 14H, the ~rertical syndrome sequence SDV from ver~ic~l p~rity checker 36 $s synchronized wlth the ~nput data series DRi (Fig. 14B~
~pplied to ~he horizontal ~c~ion 27, bult i6 delayed for one f~eld period relative to the input data ~erie~ DRi. The dA~ erie~ suppl~ed from h~r~zontal section 27 to vertical ~ction 28 ha~ been del2yed-for one horizontal row period relative to the input data ~eries DRi and 1~ further delayed b~ the fi~ld memory 34 ~r the sub memor~ 35) in the vertical section. Of course, or proper oper~tion of ~he error correcting circuit 40 9 the dat~ series and the syrldrome sequence SDV hsve to be applied ~hereto in synchronization with esch other.
Fig. 20 lllustrates a ~ui:t~ble arrangemerlt of the vertic~l ~udgin~ circuit 37 which, in re~pect to the data ~upplled to the vertical section 2~, coun~cs the number of erroneous ~ub-blocks $n each column direction arld yields a de~ection ~ignal CRCTBL
which is "0" for indicating th~t ~he error cannot be corrected in the ca~e of two or more ~rroneous ~ub-block~ belng cont~ined in a column, o~ which $6 "1" for indicating the correc~ability of the error. Fur~her, the vertical ~udging circult 37 gener~te~, as a final result of ~uch detection, a 3udging ~ignal CRCTV ln the next field period. For ~chleving the foregoing function, it is possible ~o detect the number of error block .
8ign~18 ERBLK for each column by means of 36 count~rs each of wh~ch i~ supplled with the error bloc~ signal~
E~BLK for a respeetive one of the first to thirty-sixth cOlUmn8. However, i~ i~ uneconomical to u~e as many as ~hirty 8iX counters. Accordingly, ln the embodiment ;
of Fig. 20, the above-described functlon i~ performed by three shift regi~ters 77, 78 and 79.
In ordex that the ollowin~ de~cription of the vertic~ udging c~rcui~ 37 may ~e readily under~tood, ~ariou~ timing s~gnals ~nd control ~ignal~ for processing in ~he vert~cal ~ection 28 will flrs~c be described with reference to Fig6. 21A-21R.
~ ore particularly, ~ timing pul~e RDST
~Fig. 21A) havins~ a field peri~d i8 ~ynchronized ~ith ~he beginni~g of data of each field ~n the data serie~
DRi and DRo. This pul e ~DST defines a certain field TVi, the next field TVi~l and 80 forth. A field switching pul~e SVSL (Fig. 21B) i8 switched bet~een "0" and "1" every field in synchronization with the timing pulse RDST. A t~min~ pulse VPCEN (Fig. 21C) has a period of one horizon~al row period TH and becomes "0" in ~ period corresponding to ~he horizontal parity data. A timing pulse VB~E~ (Fig. 21D) lndicates a period for reading out the data from the field memory 34 and a period for ~xecuting the correction of a correct~ble erroneou6 block by means of the ver~cal syndrome SDV. A pulse VBENT ~Fig. 21E) indica~es ~he period in which the data serie6 i~ transferred fr~m the horizontal section 27 to the vertical section 28.
A timing pulse VBWEN (Fig. 21F) corre~ponds to ~he pul6e VBENT, but i~ expandet to ~nclude the ver~ical parity da~a. The data series ~ATA- SEQ (F~g. 21G) from horizontal ~ection 27 includes horizontal parity da-ta shown as a hatched region for the data of each hor~zontal row of the periods TH1 to ~22 and vertical par~ty data ~n the twenty-second horizontal row. Each ~ub-block of the data reproduced from the magnetic tape include~

05 samples, as mentioned previously, but ~he data period o each f~eld is reduced from 246H to ab~ut 243H ~ince the buffer memory 32 proce~es each sub-blo k a~ 100 sample~ (~o of whlch ~re dummies), a~
men~ioned previously. t)nly 96 ~ample6 O~e data are written at ~he addres~ ~n field m~mory 34 correspo~ding to a 10-bit address ~ignal included a~ the beginnir~g o~ a ~ub-block. However, ln Yertical section 28, the horizontal ~nd vertical parity data ~re no~ cor-rected, ~o that ~uch parity data ~re not written in the field memory 34 or in the ~ub~memory 35.
Since vertical pari~y ~ecker 36 has two parts similar ~co ~che two parts of the horizontal paxity checker 31 described above ~ith reference to Fig. 17, a latch clear pulse PBCLA (Fig. 21H) is provided to clear one of the latch circuits of checker 36 corresponding to the latch circuits 66A and 66B of checker 31.
la~cch clear pulse PBCLB (Fig. 21I), obtained by shifting the pulse PBCLA by one field period, i8 provided ~o clear the other of the latch circuits of Yertical parity checker 36.
In the vertical parity checker 36, vne la~ch circuit generates a syndrome while the pulse P~
assumes a high level "H" ln the field period ~Vi and holds the syndrome SDVi for a corrective calculation in the next field period TVI~l, and the other latch circuit holds a previously formed syndrome SDVi~l in ~he field period TVi and again calculates a ~yndrome while the pulse PBCL~ takes a high level "H" in th~
next field period TVi+l. Accordingly9 the v rt~cal syndrome sequen~e SD~ employed ~or the corrective calculation i~ lllustrated in Fig. 21J. Further, 3~
s the data aeries DRo (Fig. 21K) derived from the correcting circuit 40 of vertical section 28 ~fter correction i~ synchronized with the t~ming pul~e RDST
(Fig. 21A) snd has 96 s~mple~ in each sub-blvck, for each of which there iB a data blanking period corr$spond-ing to ehe other ~ynchronizing signal~ and the ~ddres~
~nd identifying ~ignal~ and a data blanking period~
corresponding to the parity t~ta. Such d~ta series ~Do is 8upplied to ~he corre~ponding t~me b~e eKp~nder circuit l9A or l9B ~Fig. 5) ~nd then prov~ded through ~he interface 20 ~o the D/A eonverter circuit 21, by which ~he data series DRo is returned to the origin~l analog signal configur~tion in which video ~ignals exist in the period other than the horizontal and the vertical blanking periods. Thereaf~er, 8uitable synchronizing signals and equal~zing pulses are added to the data seri es DRo in the output processor 22 80 that a reproduced analog video signal i~ obta~ned at output terminal 23.
A specific ~mbodlment of ~he vertic~l Judging circuit 37 will now be described w~th reference to Fig. 2n. When eve~ one erroneous ~ub-block ~xis~
in a vertical column in ~ field, the shift regi~ter 77 provide8 "1" at that one of its output terminal~ Ql to Q36 which corresponts to ~he column contain~ng the erroneous sub-block. S~nce the hori~ontal parity data i8 not included in the data to be corrected, ~8 noted previ~usly, only thirty-six vextical column~ need to be ~udged. Shift re~i~ter~ 78 and 79 are used al~ernately every field, that i8, while shift register 78 counts the number of erroneou~ bloC~8 in each ~ the ~ertical columns in one field~ shift register 79 provides ~he previous count result~ ~s ar. indication Df the correctability of the error.

The ~rror bloek siEsnal 3~RBLK ~Fig. 22D) i~
applied to shift regi~ter 37 ~hr~ugh an OR ga~e 80 which al~o receives a ~ignal fed b~ck fro~ ~he thir~y-sixth output terminal Q3~ of 8hift regis~er 77. Shift reg~ster 77 i~ suppli~d at ~t~ clear terminal with-the timing pulse VB~N (F$g. 22E) ~nd, in the period ln which ~his timLng pulRe i8 lo--, the shift regis~er 77 i8 cleared. AND gate6 81 and 82 produce ~ shift pulse CKl (Fig. 22I) when e~ch of the pulses YBWEN, YPCEN
and FBLKS is "1~', and such shift pul~e C~l i8, in turn, supplied to shift regi~ter 77. Figs. 22A-220 illustrate the fir~t three horizontal row per~ods TH
~1 and TH2 of the field in which ~he field switching pulse SVSL (Fig. 22A) is "O". As noted, ~hif~ pulse CKl ~Fig. 22I) is der~ved ~rom timing pulses VBI~EN
(Fig. 22E), VPCEN (Fig. 22C) and FBLKS ~Fig. 22F).
The error block signal ERBLK (Fig. 22D), starting with the horizontal row peri~d TX~ applied throu~h OR 8ate 80 to ~hift register 77. S~nce the error block signal ERBLK i5 ~'1" for the sub-block which has not been corrected by the horizontal parity and lloll for a correct sub-block, as described previously, if error block ~ignal ERBLK i8 ~ , for example, with respect to 6ub-block SB2 in the fir~t horizon~1 row, then shift regi~ter 77 provide~ "1" only at its output terminal Q35.
The error block signal ERBLK i8 ~l~o generated ~ each sub-block of the horizon~l parity data, but slnce the generation of the shift pulæe CK1 i~ inhibited in the period for the hor~zonta1 parity data, the error block ~ignal i~ not then applied to shift regi8t2r 77.

~e foreg;oing operation i~ carried out repeatedly, ~nd, in the event thf~t i~ i8 detected, in the twenty-~cwo hc~rizontal rows of the macrix lncluding the twenty-~econd ver~ic~l p~rity da~, that one or ~ore erroneous su~-bloelcs exi6t ln any of the first 'co ~
thir~cy-sixth columns, ~he ~hi~E~ register 77 provide~
"1" at each of its output tem~in~ls corre~ponding to the column of tho~e ~ub-blocks. Numeral attached to 'che error bloc~ ~ignal I~RBL~t in F~g. 22D and ~che data from the ~orizt~ntal section in Fig. 22L ~ndicate the numberc of the ~ub-block~, and any numerals attached to the other wavefon~s of Fig~. 22A-220 indicate ti~e Glots.
The output derived at the output terminal Q37 of 6hift register 77 ~nd ~che error block signal ERBLK
are supplied to an AND gate 87 (Fig. 20~. The output from the output terminal Q37 i8 ~aken out w~ch a l-bit time lag 80 that such output can be ~imed with the error block signal ERBLK. In the case o~E the error block signal ERBLK being "1" for the sub-block SB2, as described previously, the error blo~k 8ignal ERBLR for the sub-block SB41 i8 ~ppl~ed to AND gate 87 at the time that the sh~ft register 77 provide~ "1" at the output terminal Q37, 80 that with the error block signal ERBLK also being "1", the s:~utput from AND gate 87 become "1". In other word~, supplying ~o AND gate 87 the error block sign~l for each column, ~s detected -and held by ~hift register 77, and the error block 8ignal ERBLK for the sub-block after one horizontal row in synchronization with each other, in terms of column, i8 merely a way of de~ecting whether or not each of the column8 contalns two or more sub-blocks for which the error block si~nals l~RBLK are "1". Wh0n any -`bg-,~,s~
colwml contains two or more erroneou~ uloc~ nd protuces "1'1 at the outpu~ of AND gate 87, the error~
in the respective ~u~-blc~cks cannot be cs:rrected by the vertical parity data.
The ou~put from A~D gste 87 ~ provided to AND gates 88A ~nd 88B ~Fig. 20~ which h~ve ~heir -outputs respec~ively applied through OR gates 89A-~nd 89B to ~hift regi~ter~ 78 ~nd 79. ~he ~utputcs obtained 2t output term~nal~ Q36 of shit registers 78 and 79 are respectiYely fed bac~ to the input~
therec>f through OR gates 89A and 89B. If the results o$ the detection, that i~, the output of ~D gate 88A
and 88B becomes "1" even once, the re~ultfi of the detection ~n respect to the column i6 held by the described feedback. The shift regi~ters 7~ and 79 are supplied with a clear pulQe through~AND gates 90A snd 90B. The clear pul~e i~ generated at the beginnin~ ~
of each field per~od by in E~S flip-flop 97 from ~iming pulce6 ~ ~nd ~. The field switching pulse SVSL (Fig. 22A) 1~ inverted by an inYerter 91 and applied to AND ~ate 88A and NAND gate 90A.
Consequently, in the f~eld period in vhich field ~witching pul~e SVSL i~ "0", the output from the AND
gate 87 is supplied thrc>u&h ~D gate 88A and OR gate 89A
to ~hift register 78, snd the shift register 78 i~
cleared by the clear pulse ~pplied thereto through NAND gate 9OA ~ the beglnning of each field period.
In the field period in which the field switching pulse SVSL is "O", ~he other shift register 79 only circulates i~:8 content via the feedback loop extending from the output terminal Q36 to OR gate 89B. Thus, in the field period in which switching pulse SVSL i8 , .

"O", ~hift regi~ter 78 provides from ~he error block ~ignal ERBLK of the pre~ent field a detection sign~l lndicating whether e~ch sub-block thereof i~
correctable or not. During the 8ame period, the other ~hif~ register 79 hold~ a ~udging sign~l CRCTY for-.
finally indicating ~hether e~ch column 48 correctable or ~ot, based on the error bl~ck signal in ~he previou~
field. In the field period in which the field ~witching pulse SV5L i5 "1", the above opera~ion~ are exchanged, ~hat is, ~hift register 79 generates ~he detection ~ignal ~RFT~ and ~hif~ regi~er 78 generates the ~udging signal ~ .
The detection signal CR~TBL i8 derived fr~m the output eerminal Ql of ~hift register 78 or 79, and the ~udging sIgnal ~CTV i~ derived from the outpu~
tenminal Q36 of shift register 78 or 79. A multiplexer 93 determines from which one of the shift regi~ters 78 and 79 is taken out the de~ection signal -~RC~L- or the ~udging signal ~TY. Th~ multipl2xer 93 i~ switched by the field switching pul~e SVSL. In the case of the field switch~ng pulse SVSL bein~ '~0", ~he lnput ~o the side A of the multiplexer 93 becomes its output3 and in the case of the field switching pulse SVSL being "1", the input to the side B i8 the output. These outpu~s from multiplexer 93 are inverted by inverters 95 And 96 to obtain the detection signal CRCTBL and ~he ~udgin~ signal CRCTV. If the detection sign21 CRCTBL and the ~udging ~l~nal CRCTV ~re "1", it means that the block 1~ correctable, whereas if the s ignal CRCTBL or CRCTV i8 "O", i~ means that the block is uncorrectable. The detection signal CRCTBL ~ay sometimes be inverted from "1" to "O" dur~n~ a field, that is, the slgnal ~ "1" when only oIae sub-block 18 erroneous, bu~ ~he ~i~grlal beca~e~ "0" as ~oo~ ~s tWQ
or more erroneou~ 'blocks are coun~ed.
Sinee shlft regi8ter5 77 and 78 perfo~ the ~ ove operations alternately at every field, the ~ift pulse6 to t~e ~hift regi~cer~ are al~o swit:ched at e~very field by ~ multiplexer 94. More par~cu~arly, a shift pul~e CK2 (Flg. 22J) is derived by AND gate~
81 and 83 from the eiming pulses VBW~:N, VPCEN and YBLKS. The ~iming pulse VBLRS ~Fig. 22G) i8 t~f the sub-block period and ie delayed ~lightly in re~peet to t~ing pulse F~LKS (~ig. 22F) and, con~equently, the 6hift pulse CK2 is somewhat delayed $n phase relst~lJe to shift pul~e C~l. A shift pulse CR3 (Fig. 22K) i~ ba~ed on ~he ~iming pul~e~ VBREN, VPCE~
~nd VBLK~ and i8 produced by an inverter 84 receiving pulse VBLKS and A~ gates 85 and 86. ~inee ~he tlming pulse VBREN become6 "1" from the beginning sf the field (Fig. 22B), and ~i~ce ~he t~ming pul~e ~SRS
is as ~hown on Fig. 22H, shift pulse CR3 has the configurat~on shown on Fig. 22K. The ~hift pulse ~K2 (Fig. 2 W) i applied to the ~hif~ register 78 or 79 which generates the detection signal CRCTBL, snd the ~hift pul~e CK3 (Fig. 22K~ i8 supplied ~o the other 8hift register 79 or 78 whioh yields ~he ~udging sign~l CRCTV. For example, in ~he field ln which the field switching pulse SVSL i~ "0", multiplexer 94 i8 controlled ~o that ~hift pulse CK2 i8 provided to shift regist~r 78 and shift pulse CK3 ifi applied to ~hift register 79.
In the field in whic~ the field ~witc~
pulse SVS~ i~ "0'`, shift ~ulse CKl is no~ supplied to the shift register 77 durin~ the first horizontal row -S~-5~

period THo but i6 supplied from the ~ext horizon'cal row period T~l. Similarly, shift pulse CK2 i8 applied 'co the shift register 78 from the horizontal ro~
period THl. In the horlzontal row period THl~
~hift register 77 sequentially provides output6 a the output terminal Q37 138 depicted in Fig. 22M, but sinee the shift reglster 77 ha~ been lnitialty in it~ clear ~tate, such outputs in the horizoIltal row period TH~are 2l11 "0". Therefore, the GUtpUt supplied via the AND gate~ B7 and 88.A and the OR
gate ~9A So the shif~ register 78 i8 lll80 ~'0", and, consequently, the detect~on ~ignals ~RCTBL provided at the output term~nals Ql of ~hift re~81s~er 78 in ~e horizontal row period THl sre all "0", as illustra~ed in Fig. ~2N. On the other hand, in such field in which the field s~itohing pulse ~VSL i~ "0", ~ince the shift regis~cer 7g i8 controlled by shift pulse CR3 to circulate9 '~he ,~udging slgnal ~TV
of the previous field, which ~ndicate~ the correct-abil~ty (or uncorrectab~ cy) of each c>iE ~he irst ~o thirty- s ixth col~nns, ~ repeatedly provided at the output terminal Q36 o shift regi~ter 79, as shown in Fig. 220~
In the next horizontal ro~ per~od TH2, ~he error block ~ignal ERBL~ concerning each of the f~r~
to thirty-sixth ~ub-blocks 18 provided from the output termin~l Q37 of ~hift register 77 and supplied to AND gate 87 together wlth the lnput ~rror block ~ignal ERBLK. Accordingly, ~t the end of the horizontal row period TH2, the content of shif~
register 78 i8 ~ only at the positio~ where two erroneous sub-blocks exi~ in the same colu~n in two respective hc~rizorltal rows. Such sn operat~on i6 repe~ted for twenty~'cwo h~rizon~al rt~w perit7ds of one field, and ~he content of ~hif~c register 78 ulti-m~tely i~ "1" at each posi~ion corre~ponding to ~n uncorrectable column. In the next field in wh$ch ~he f~eld switching pulse SVSL i~ "1", the content of ~hift register 78 ~ ~aken out as ~he ~udg~ng signal by shift pulse CK3, ænd shift pUl8e ~R2 activates shift regi~ter 7~ ~o generate the detection signal ~RCTBL.
It will be appreciated that, in the ~ertical ~udging circuit described above wlth reference to Fig. 20, ~he detection signal CRCTBL and the ~udging ~ignal CRCTV can be produced merely by the shift registers 77, 78 and 79, and there i8 no need to provide numberous coun~ers respectively corresponding to the thirty-~ix columns. Therefore, the vertical ~udging circuit can be relat~vely s~mple in conetruction.
- As illus~rated in Fig. 13, ~he detection ~ignal CRCTBL from vertlcal ~udging circuit 37 is applied to the memory control eircuit 39 to control the writ~ng of data in Gub memory 35. Fig. 23 ~hows, by way of examplel ~ detai}ed arrangement ~hat may constitute sub memory 35 Rnd memory control circuit 39.
Two sub memories 97A and 97B and two flag memories 99A and 99B are provided to perform wrlte and read operations alternately at every field, ~nd memory control circuits 98A, 98B and 100 are provided in association with memory 97A, memory 97B and memories 99A and 99B, respectively. The data (DATA. SEQ) from horizon~al ~ection 27 is applied a3 ~npu~ data o `:
sub memories 97A and 97B, ~nd the output da~ca DTS there-from i8 ~upplied éo error correcting cir u~t 40. The iElag memories 99A and 99B ~tore l-bit vertic~l error flags SFLA and SFLB, respec~ively, in respect to all ~ub-bloeks (858) included in a field. The 8ub ~emories 97A ~nd 97B each have a capacl~y l~rge enough to store da~ca of ~ prede~srm~ned number of 3ub-blocks, for example, 8iX ~ub-block~, as de~cribed previou~ly. In the field period lr; ~hi~ the ~Eield switching pulse 5VSL i~ ~'0"~ the sub memory 97A and the flag memory 99A carry out write operRtions ~nd the ~ub memory 97B ~nd the.flag memory 99B perform read operations, and in the next field period ln which the field ~itching pulse SVSI. i8 ~ he operations are exchanged, that :L8, memorie~ 97B
and 99B perorm writing operation~ and memorie~ 97A
and 99A perform reading oper~tion~.
Addre~s codes from a wri~e ~ddre~ register lOlW and read addres~ counter lOlR are selectively provided to flag memories 99A and 99B. The ~ciming pulse FBLKS (Fig. 2?F) and clock pul~e RC~ (Fig. 18A) are supplied ko a load pul&e generator 102, and a 10-bit ~ddres~ signal ~n che data DATA SEQ. from the hor~zontal section 27 i8 loaded by a load pul~e from generstor 102 in ~he write address regi~er lOlW.
Further, the timing pul~e~ FBLKS and RDST (Fig. ~LA) are fed to ~ clear pulse generAtor 103 which provides therefrom a clear pulse at the beginning of a field, ~nd which i8 provided to read address counter lOlR for clearing the latter. The address counter lOlR there-after counts the ti~ing pulse FBLKS, by which the read ~ddress ~teps one-by-one for each ~ub-bloclc. The write address ~gnal and the read addre~s signal, each having 8 parallel, 10-bi~c configuration, are provided to multiplexer~ 104A and 104B. In ~he field period in ~hich the field switching pul~e SVSL 1~
the read address ~lgnal i8 selected by lthe mult~pl~cer 104A ~nd sppliLed to fla~ memory 99A and, ~t the s~me time~ the write address ~ignal iB ~elecked by multi-plexer 104B ~nd ~pplied to flag memoxy 9gB.
Timing signaLsVPCEN (Fig. 21C) and VBENT
(Fig. 21}:) are ~pplied to an AND gate 105 which has its oueput connected to 1ag memory control circuit 100.
The memory control circuit 100 i6 adapted l:o genera~ce write pulses for flag memorie~ 99A and 99B orlly in the period6 in which the ou~cput from the AND ~ate 105 i8 ~ . Thus, no wr~te pul e is provided in respect of ehe sub-blocks wl:lich concern the horizontal and the vertical psrity data, and the vertical error flags conce~ning fiuch parity data are alway~ ~'0". l'he foregoing ~al80 ~pplie6 to the writirlg of data in sub-memories 97A and 97B. More par~icularly, ~iming ~ignals VPCEN and VBENT ~re ~pplied to the memory control circui~s 98A and 98B, 80 that the writing of the parity data ~n ~ub-memories 97A and 97B is prevented.
The error block signal ~RBLK and the deteetior~
~ignal CRCTBL from verticaï ~udging circuit 37 are applied to an AND gate lOS. ~hen bo~h o these signals ERBLK and CRCTBL are "1" to pro~vide ~n output ~ rom AND gate 106, it means ~hat the sub-block i8 corre~table and erroneous. Even in ~he c~se that the detection ~ignal CRCTBL initially is "1", an erroneous sub-block .... .. ....... . . ... .. .....

~y later or.cur in the s~me colurnn. In that case, the aignal CRCTBL will became "0" to ind~cate thet the sub-block iB uncorrectableO To avoid thig, the output from AND gate 1~6 is ~pplied to An overflow inhibiting clrcuit 107 to prevent ~he ~u~-m~mor~es 97A and 97B rom overflowing. The output from overflow inhibiting circuit 107 ~ pro~ided az dst~
input ~co each of the flag memorles 99A ænd 99B and, at the ~me time, i6 ~upplied ItO sub memory control c~rcuits 98A and 98B to control the writing of d~t~
in the sub-memories 97A ~nd 97B and the write addres~es therefor. More par~icularly, the d~ta (excluding the parity data, as de~cribed ~bo~e) of the sub-!block for which the output ~Erom A~D gate 106 becomes "1" i8 wri~ct~3n in the ~ub-memories 97A ~nd 97B, and in this period the clock-pulse RCK causes the wr~te address ~o ~tep for 96 8ampleS. When the output from AND gate 106 becomes "1" again, the ~ame operat~on is performed and the ~rite addre~s i~ again ~tepped for 96 ~amples.
Thu~, in a f~eld defined by the f~eld switching pulse SVSL, a maxLmum of 8iX correctable erroneouC sub-blocks are ~tored in the 8U~ memory 97A or 97B, and "1" i~ written at each of ~he addresses of the flag memory 99A or 99B correQponding to the stored sub-blocks. In another field defined by field switch~ng pulse SVSL, the read addre6s signal which i8 provided by read address counter lOlR and ~teps at every sub-block 16 applied to flag memory 99A or 99B, and the read output therefrom i~ the vertical error flag SFLA or SFLB which 18 ~elec~ced by multiplexer 108 and oombin~d into a vertieal error flag SFLG. The vertical error flag SFLA or SFLB read out frc;m the fl2g memory g9A nr 99B i~ al~o applied to memory control c~rcu~t 98A or 98B to cau~e l:he read addreQs for ~ub-memory 97A or 97B to be stepped by one in ~ach ~ub-block period ln which ~e ~ertical error flag ~FLA
or 5FI.B iE "1". In thiR 61~y, da~ of a correctable erroneous sub-block i rea~ out :from ~ub-memory 97A
or 97B in a prede~ermined t~ne ~lot ln which the vertical error flag SFLG i8 "~
Referring no~ to Fig. 24, it ~ill ~e ~een that the overflow inhibiting c~rcuit 107 may co~I~ri~e ~ counter 109 iXI whlch a pre~et input of a predeter-mined value i loAded from a pre~et lnpu~c genera~or 110 by applying to a load terminal of counter 109 the timing pulse RDST lndicating the beginning of the field. In ehe example de~cribed ~bove ~ that 1~, ~rhere a maximum of six correctable erroneous ~ub-blocks are to be stored in l2ub-memory 97A or 97B, a numerical value of 6 i~ applied ~ the pr~et inpu~c eo coun'cer 109. The output from the A~D gatQ 106 i8 applied a~ one inpu~ to ~n A~1D gate 111 wh~ch has ie& outpu~ applied as a subtraction input to counter 109. A carry ou~put from the counter 109 iB ~pplled as thc other input to AND gate 111. The ~arry output i~ set ~o "1" by loading of the preset lnput into counter 109 and becomes "O" when the output fr~m the AND gate 106 exceeds the preset number. Accordingly, after thi~, the output from AI~D gate 111, and hence the output of circuit 107, becomes "0" to prevent sub memory 97A or 97B from overflow~ng.

3~

Referring now to Fig. 25, it will be æeen ~hat the error cc>rrec~ing clrcuit 40 of vertical section 28 receives the vertical syndrc>me sequence SDV (Fig. 21J) from vereical parity ehecker 36, ~he data series DTF read out ~Erom field memory 34 ~nd the da~a ~er~es DTS read ou~ from ~he ~ub-memory 35 i~h~k ~s, from sub-me~ories 97A and 97~ in Flg. 23).
Within c~rcu~t 40, ~he ~udging s~gnal GRCTV, after being delayed by ~ hift reg~ster 113, and ~he vertical error 1ag SFLG ~re supplied to ~n AND gate 112 which provide~ a selec~ signal SLCT a~ it8 outpu~c. The vertical- syndrome SDV is E1180 applied to delAy ~hift register 114 for phase synchronization. The ~elect signal SLCT turn~ O~ ~nd OFF a gate circuit 115 which i6 ~upplied with the vertical syndrome SDV, and a multiplexer 116 iB also controlled lby 13elect ~ignal SLCT for selecting the data ~eries DTlF or DTS. The outputs :Erom gate circu~t 115 and multiplexer 116 are supplied to ~ modulo-2 ~dder 117 for correcting sny errors, and from which ~ derived ~he output data series DRo.
In the case of eelect signal SLCT being ~'0", gate circuit 115 i8 turned OFF snd its output becomes "0", and at the ~ame time, the data serie~ DTF i~
~elected by multiplexer 116 for application to adder 117. I~ the case of select ~ignal SLCT being "1", gate circuit 115 i~ turned ON to supply vertieal syndrome SDV ~o adder 117, and data ~er~e~ DTS i8 -selected by mult~plexer 116 and also fed to the adder 117.
Four combina~ion~ ~f "1" and "0" of the ~udging signal CRCTV and ~he ver~ical error flag SFLG

5g~

. .. . . , . ., . , .... , .... ,, ... . . . ., ., ... ~ .

~ . .

will be hereinafter described:
(1) CRCTV ~ "O", SP~G ~ "O" ~LCT ~ "O") Since ehe sub-block is uncorrectable bu~c at least no longer erroneous, the d~ta ~eries DTF i~ ~elec~ed ~nd is taken out as the output data serie~ DRs~
case includes the case wherein the ~ub-block ~B
originally correct.
(2) CRCTV - "1", SFLG - "O" (SLCT - "O") Since the sub-block '18 correc~able bu~ ~ot erronesu~, the data ~eries~IlTF ls ~ ain ~elec~ed.
(3) CRCTV ~ l09l, SFI.G 8 ~ (SLCT ~ "0"~
l~e ~ub-block i~ uncorrectable and erroneous.
Accordingly, the da~ca ~eries DTF from ~he field m~mory 34 i8 taken out as ~e output data ~eries DRo. The writing vf the erroneou~ sub-block in field m~nory 34 is inhibited, and the gub-block appearing in the data series DTF i8 comprlsed of da~a included in the line of the previous field po~itioned one line lbelow ~hat cont~ining the erroneou~ daea. That i8, an error conceal ment operativn takeli place.
(4) CRCTV - '~1", SFLB ~ 5LCT ~ "1") The ~ub-bloclc i~ correc~able and erroneous. Only for the foregoing conditions does the select signal SLCT become "1"~ ~nd, a~ ~ result thereof, data ~eries DTS from sub-memory 35 1~ selec~ed by multipl~xer 116.
At the ~me t~me, gate circui~ llS i~ turned ON, ~nd -~he sub-block in the d~t~ ~eries DTS ~nd the vertical syndrome correspondin~ thereto are sub~ectea to modûl~-2 addition in ~dder 117, thereby correct~ng the error.
It will be understood fr~m the abo~e description of ~n embodiment of the present lnvention,that a field memory and ~ 8U~ memory are provided ~ith correct ~L5~
data being ~tored in the ield memory and data for error correction being ~tored in ~che ~ub-memory, ~o . that error correction and/or error concealment csn be ~a~ily carried out. Further, ~ince erroneou8 dat~ i8 inhibited from being wri~ten in ~che iField emory anQ ~ interpolat~d by the data of the previpus field p~ition~d one line below 1~ the pls~tori~l representa~iLon of a co~plete Pr~me, ~he interpolation can 'be effected with sl~t~ having ~ relati~ely higher correlation with the erroneous dlate than does data in an adjacent line of the 8ame field. Fur~her, no calculating circuif is needed for the interpola~cion unlike the exi~ting ~rrangement ~n which the ~nter- -polntion data i~ producet by ~eans of c~lculation.
Ill accordance with the prgsen inven~ion, only data of a correctable and erroneous sub-blcck i~ wrltten in the ~ub memory, ~o thst the capacity of the lat~er c~n be relatively small. In the wri~ing of dat~ ffl the ~ub-memory 35, the address therefor i~ stored by an error flag~ 80 that the read ou~ of data from the 8U~-memory and i~s error correct~n can be per$onmed with ease. Moreover, in accordance wl~h ehe present in~ention, the ~udgement as to ~hether ~n error in the column direction i~ correctable or not can be achieved by a simple arrang~ment whic~ a3 shown on ~ig. 20, merely employs three 6hift reg~ter~.
In the foregoing embodiment of thQ inventio~, the dat~ of each ~ield i8 recorded in two par~llel tracks TA ~nd TB, but ~t will be apparent th~t the data for each field may also be recorded in one track or in ~hree or more parallel tracks. Furthermore, ~he error ~orre~tion code need not be limited to ~he ~pecifically de~crlbed parity code, but other correction codes m~y be ~milarly used.
In the embod~ent of the inven~ion de~cribed above, ~t has been ~ ~umed that the luminance ~nd chrominance component of the dlgital color video ~gnal are ~uitably ~epara~ed frum each sther ~t ~ome point after being read out of field mem~ry 34 in error correcting decoder 18A or 18B. In o~her words, ~he data ~tor~d ln field m~mo~y 34 ~nd in ~ub-memory 35 represen~s a c~mp~site color v~deo signal having both luminance and chrominance components. Howe~er, if de~ired, the present invention can be s~milarly applied to an arrang~men~ in which the reproduced digi~al color video 8 ignal ~f ~ ch channel i8 suitably ~eparated into it8 luminance and chrominance component~ ei~her at or in adv~nce of the respective error correcting decoder, in w~ich case the field memory of the error correcting decoder i~ div~ted ~n~o a lumi~ance ~ignal memory and a ehromlnance ~ignal memory in which ~he ~eparated luminance and chrominance components, respectiv~ly, o each error-free field ~re to be temporarily stored. For ~ample, as 8hown shematically on Fig. 26, a field memory 34' of each of the error correc~lng decoderfi 18A and 18B may ~nclude a 6epar~0r 118 which suit~bly ~eparateæ the lumlnance and chrominance Gomponents from ~he ou~pu~ of the correction circuit 33 sn Fig. 13, ~nd whlch ~pplies such luminance ~nd chrominance components to a luminance signal memory 34'a and a chrominance ~ign~l memory 34'b, respectively. The m~mories 34'a and 34'b may be controlled from the fleld memory contrsl circuit 38 B0 that only s~nals w~lch are error-free, a~ received 5~
~, , from horizont~l correction circui~ 33, ha~e their luminance and chrominance components s~ored or writ~en in memories 34' ~nd 34'b, respec~ively. The luminance and chrominance component~ re~d out of memories 34'a and 34'b ~re appl$ed ~o ~n adder or c~mbining c~rcui~ 119 80 ~ ko recon~itute the digital composite color video slgnal which i~ to be applied to ~he vertical correction circuit 40 of Fig. 13. Apar~
fram the fore~oing, ~he error correcting decoder which includes the field memory 34' of Fig. 26 may be ~imilar to the error eorrec~ing decoder 18A or 18B of Fig. 13, or the sub m~mory 35 of the latter may al~o be divided ~nto sub-memories ~not ~hown) for re~pectively ~toring temporarily the luminance ~nd chrominance co~ponent~
of ~he error-eontaining signal~ recei~ed from circuit 33 ~nd being correctable in circuit 40.
Having deccribed var$0u8 embod~ment~ of ~he invention with reference ~o the accompanylng drawing6, it i~ to be understood that the invention i8 not limited to the~e precise embodlments and that ~any modification~ and variat~on~ may be effected therein by one skilled in the ~rt wit~out departing from the ~cope or spirit of ~he invention which i~ intended ~o be defined by the appended cla~s.

Claims (16)

WHAT IS CLAIMED IS:

1. A method of processing a digital signal which forms a data block for every predetermined number of bits, and which includes error detecting and error correcting signals, said method comprising the steps of:
detecting each said error signal as an indication of an error in a respective data block of said digital signal;
writing in a first memory each data block which is free of error;
writing in a second memory a data block containing an error;
selectively reading out a data block from said first and second memories; and correcting an error of a data block read out from said second memory by means of the respective error correcting signal.

2. A method according to claim 1; wherein said digital signal has been converted from an analog video signal.

3. A method according to claim 2; wherein said first memory has a capacity equivalent to one field of said video signal.

4. A method according to claim 1; further comprising the steps of:
judging whether an error contained in a data block is correctable by the respective error correcting signal;and inhibiting said writing in second memory of any error-containing data block which is not correctable by said respective error correcting signal.

5. A method of processing an analog video signal composed of successive frames each having a plurality of fields constituted by successive respective lines which are interlaced in a pictorial representation of the complete frame, said method comprising the steps of:
converting said analog video signal to a digital signal;
forming a data block for each predetermined number of bits of said digital signal;
adding error detecting and error correcting signals to said digital signal;
detecting said error detecting signals as indications of errors in the respective data blocks of said digital signal;
writing each error-free data block at an address in a first memory corresponding to that at which there was earlier written a data block of a line of the next previous field which, in said pictorial.
representation of the complete frame, is positioned immediately adjacent the line of said error-free data block being written;

inhibiting the writing of an error-containing data block in said first memory;
writing said error-containing data block in a second memory;
reading out a data block selectively from said first and second memories; and correcting an error in a data block read out from said second memory by means of the respective error correcting signal.

6. A method according to claim 5; further comprising the steps of:
judging whether an error contained in a data block is correctable by the respective error correcting signal; and inhibiting said writing in said second memory of any error-containing data block which is not correctable by said respective error correcting signal.

7. A method according to claim 5, wherein said analog video signal is a color video signal having a chrominance component with a color subcarrier which changes in phase at selected lines of each of said fields; and wherein said line of the next previous field is positioned, in said pictorial representation, immediately below said line of the error-free data block being written and has said color subcarrier phase synchronized with that in said line of the error-free data block being written.

8. An apparatus for processing a digital signal which forms a data block for every predetermined number of bits, and which includes error detecting and error correcting signals, said apparatus comprising:
error detecting means for detecting each said error detecting signal as an indication of an error in a respective data block of said digital signal;
first memory means for storing each data block which is error-free;
second memory means for storing a data block which has been indicated by said error detecting means to contain an error;
selector means for selectively reading out the contents of said first and second memory means; and error correcting means employing said error correcting signals for correcting said error detected by said error detecting means.

9. An apparatus according to claim 8:
wherein said second memory means includes a data memory for storing a data block and a flag memory for storing a flag signal corresponding to an address in said data memory at which the data block is stored, said flag signal indicating that the data block stored at the respective address contains an error.

10. An apparatus according to claim 8;
wherein said digital signal has been converted from an analog video signal composed of successive frames each having a plurality of fields constituted by successive respective lines which are interlaced in a pictorial representation of the complete frame; and further comprising control means for said first memory means causing the writing of each error-free data block at an address in said first memory means corresponding to that at which there was earlier written a data block of a line of the next previous field which, in said pictorial representation of the complete frame, is positioned immediately adjacent the line of said error-free data block being written.

11. An apparatus according to claim 10;
wherein said first memory means has a capacity substantially equivalent to one field of said video signal.

12. An apparatus according to claim 10;
wherein said analog video signal is a color video signal having a chrominance component with a color subcarrier which changes in phase at selected lines of each of said fields; and wherein said line of the next previous field is positioned, in said pictorial representation, immediately below said line of the error-free data block being written in said first memory means and has said color subcarrier phase synchronized with that in said line of the error-free data block being written.

13. An apparatus according to claim 10;
further comprising means for judging if an error contained in a data block is correctable by the respective error correcting signal; and means for inhibiting said writing in said second memory means of any error-containing data block which is not correctable by said respective error correcting signal.

14. Apparatus for processing an analog video signal composed of successive frames each having a plurality of fields constituted by successive respective lines which are interlaced in a pictorial representation of the complete frame, said apparatus comprising:

means for converting said analog video signal to a digital signal;
means for forming a data block for each predeter-mined number of bits of said digital signal;
means for adding error detecting and error c o rrecting signals to said digital signal;
means for detecting said error detecting signals as indications of errors in the respective data blocks of said digital signal;
first and second memory means;
means for writing each error-free data block at an address in said first memory means corresponding to that at which there was earlier written a data block of a line of the next previous field which, in said pictorial representation of the complete frame, is positioned immediately adjacent the line of said error-free data block being written;
means for writing said error-containing data block in said second memory means;
means for reading out a data block selectively from said first and second memories; and means for correcting an error in a data block read out from said second memory means by means of the respective error correcting signal.

15. An apparatus according to claim 14; further comprising:
means for judging whether an error contained in a data block is correctable by the respective error correcting signal; and means for inhibiting the writing in said second memory means of any error-containing data block which is not correctable by said respective error correcting signal.

16. Apparatus for processing an analog video signal composed of successive frames each having a plurality of fields constituted by successive respective lines which are interlaced in a pictorial representation of the complete frame, said apparatus comprising:
means for converting said analog video signal to a digital signal;
means for forming a data block of each predeter-mined number of bits of said digital signal;
means for adding an eror detecting code to each said data block to form a signal block therewith;
means for arranging a plurality of the signal blocks in a matrix form having rows and columns;
means for adding error correcting codes for each said row and column of said matrix form;
means for transmitting and receiving said digital signal in said matrix form with said error detecting and error correcting codes added thereto;
means for detecting each said error detecting code as an indication of an error being contained in the respective data block of the received signal;
first and second memory means;
first correction means employing one of said error correcting codes of the row and column, respectively, in which said error-containing data block is situated for correcting the error therein;
means for writing in said first memory means each data block which is error-free at least after the action thereon of said first correction means, said error-free data block being written at an address in said first memory means corresponding to that at which there was earlier written a data block of a line of the next previous field which, in said pictorial representation of the complete frame, is positioned immediately adjacent the line of said error-free data block being written;
second correction means employing the other of said error correcting codes of the row and column, respectively, in which said error-containing data block is situated for correcting an error remaining therein after the operation of said first correction means;
means for writing in said second memory means a data block which, following said operation of the first correction means, contains an error correctable by said second correction means; and means selectively reading out a data block from said second memory means to said second correction means when said read-out data block contains an error correctable by said other error correcting code or reading out an error-free data block from said first memory means.