CA1161544A - Passive data monitor for use with polling pattern generator in catv system - Google Patents
Passive data monitor for use with polling pattern generator in catv systemInfo
- Publication number
- CA1161544A CA1161544A CA000378441A CA378441A CA1161544A CA 1161544 A CA1161544 A CA 1161544A CA 000378441 A CA000378441 A CA 000378441A CA 378441 A CA378441 A CA 378441A CA 1161544 A CA1161544 A CA 1161544A
- Authority
- CA
- Canada
- Prior art keywords
- output
- data
- address
- coupled
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/16—Analogue secrecy systems; Analogue subscription systems
- H04N7/173—Analogue secrecy systems; Analogue subscription systems with two-way working, e.g. subscriber sending a programme selection signal
- H04N7/17309—Transmission or handling of upstream communications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04H—BROADCAST COMMUNICATION
- H04H60/00—Arrangements for broadcast applications with a direct linking to broadcast information or broadcast space-time; Broadcast-related systems
- H04H60/09—Arrangements for device control with a direct linkage to broadcast information or to broadcast space-time; Arrangements for control of broadcast-related services
- H04H60/14—Arrangements for conditional access to broadcast information or to broadcast-related services
- H04H60/21—Billing for the use of broadcast information or broadcast-related information
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04H—BROADCAST COMMUNICATION
- H04H60/00—Arrangements for broadcast applications with a direct linking to broadcast information or broadcast space-time; Broadcast-related systems
- H04H60/29—Arrangements for monitoring broadcast services or broadcast-related services
- H04H60/32—Arrangements for monitoring conditions of receiving stations, e.g. malfunction or breakdown of receiving stations
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04H—BROADCAST COMMUNICATION
- H04H60/00—Arrangements for broadcast applications with a direct linking to broadcast information or broadcast space-time; Broadcast-related systems
- H04H60/35—Arrangements for identifying or recognising characteristics with a direct linkage to broadcast information or to broadcast space-time, e.g. for identifying broadcast stations or for identifying users
- H04H60/38—Arrangements for identifying or recognising characteristics with a direct linkage to broadcast information or to broadcast space-time, e.g. for identifying broadcast stations or for identifying users for identifying broadcast time or space
- H04H60/41—Arrangements for identifying or recognising characteristics with a direct linkage to broadcast information or to broadcast space-time, e.g. for identifying broadcast stations or for identifying users for identifying broadcast time or space for identifying broadcast space, i.e. broadcast channels, broadcast stations or broadcast areas
- H04H60/43—Arrangements for identifying or recognising characteristics with a direct linkage to broadcast information or to broadcast space-time, e.g. for identifying broadcast stations or for identifying users for identifying broadcast time or space for identifying broadcast space, i.e. broadcast channels, broadcast stations or broadcast areas for identifying broadcast channels
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04H—BROADCAST COMMUNICATION
- H04H2201/00—Aspects of broadcast communication
- H04H2201/70—Aspects of broadcast communication characterised in that receivers can be addressed
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/16—Analogue secrecy systems; Analogue subscription systems
- H04N7/173—Analogue secrecy systems; Analogue subscription systems with two-way working, e.g. subscriber sending a programme selection signal
- H04N2007/17372—Analogue secrecy systems; Analogue subscription systems with two-way working, e.g. subscriber sending a programme selection signal the upstream transmission being initiated or timed by a signal from upstream of the user terminal
Abstract
PO-1-25820M/SK/81 A polling pattern generator system for use in a CATV system including a polling pattern generator and a passive data monitor, The polling pattern generator periodically generates polling pattern signals each of which has a specific address code for calling a corresponding terminal unit and a command code for requesting a designated answer from the called terminal unit, The passive data monitor compares an up data signal outputted from the terminal unit in response to the command code with the designated answer requested by the command code and judges whether or not an operational state of the terminal unit is acceptable from the resultant comparison output. The passive data monitor sets the address code in the designated terminal unit.
Description
POLLING PATTER~ GE~ERATOR FOR CATV SYSTE~
BACKGROU~D OF TH~ INVENTION
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The present lnvention relates to a CATV system.
~ore specifically, the invention to a polling signal generator in a CATV system for periodically transmitting a polling signal to terminal units to initiate the transmission of specific data from the terminal units.
A CATV system serves to transmit a variety of programs to television sets of terminal units installed in subscriber's homes through coaxial cables. Many CATV systems are capable of performing bidirectional simultaneous communications in addition to program transmission wherein the center simultaneous-ly transmits information to a number of the terminal units and receives information back from them. Specifically, predetermin-ed functions in the terminal units have to be periodicall~ or irregularly polled. This polling operation is conducted by transmitting a down data signal to the terminal units~ receiving up signals in reply to the down data signal and comparing the command in the down data signal therewith. However, in order to generate such a down data signal for polling the terminal units, a large-sized computer has heretofore been necessary.
Such a computer cannot easily be transported around the system, as would be desirable.
It is thus an object of the present invention to . . .
provide a polling pattern generator for a CATV system which eliminates the aforementioned drawbacks, is portable, has a simple construction, and can periodically generate a polling pattern for polling the terminal units.
5~
SUMMARY OF THE INVENTION
In accordance with this and other objects of the invention, there is provided a passive data monitor for a CATV system having a single center and a number of terminal units connected to the center fo`r transmitting television programs through cables to the terminal units. Each of the terminal units has an address setting device capable of arbitrarily setting an address number therein which may be unique to the terminal unit. The passive data monitor includes means for receiving a polling pattern signal having an address code for calling a corresponding terminal unit and a command code for requesting a designated answer from the called terminal unit, and means for comparing an output data signal output~ed from the terminal unit in response to the command code with the designated answer requested by the command code and for judging an operational state of the terminal unit from a resultant comparison output.
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BRIEF DESCRIPTION OF THE DRAWINGS
-Fig. 1 is an explanatory view showing a CATV system to which the invention is applied;
Fig. 2 is a block diagram showing the installation of a polling pattern generator;
Fig. 3 is a block diagram of a passive data monitor of the invention;
Fig. 4 is a front view showing the panel of the passive data monitor;
Fig, 5 is a block diagram showing a polling pattern generator of the invention;
Fig. 6 is a front view of the panel of the polling pattern generator of Fig. 5;
Fig. 7 is a plan view showing data switch groups used in the polling pattern generator of Fig. ~;
Fig. 8 is a perspective view of a portion of the interlor of a terminal unit showing an address block and address setting unit installed in the terminal unit; and Fig. 9 is a structural view showing an alternate installation of the polling pattern generator.
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DESCRIPTION OF THE PREFERRED E~IBODIMENTS
A CATV system in which the invention is used to advan-tage will be described with reference to Fig. 1. The CAT~ sys-tem includes a single center 1 and terminal units 28 which are provided, for example, in several tens of thousands of sub-scribers' homes. The center 1 is connected through coaxial cables to the terminal units 2~ in the subscribers' homes 2.
A main cable 3 extends from the center 1 and main cable amplifiers 4 and branching units 5 are provided at predetermined positions on the main cable 3. A plurality of branch cables 6 extend from each branching unit 5. Extension amplifiers 7 and tap-off units - g are provided at predetermined points on the branch cables 6.
Each tap-off unit 8 is connected to branch lines 9 which extend to the terminal units 28 in the subscribers' homes 2. Each ter-minal unit 28 includes a main unit 10, a television set 11 and a control unit 12. The b~anch line 9 is connected to the main unit 10 which is in turn connected to the television set 11 and to t]le control unit 12. As is apparent from the above descrip-- tion, the main cable extending from the center is branched into . 20 a first plurality of branch cables which are further branched into a second plurality of branch lines which are finally con-nected to the terminal units 28.
A signal receiving antenna 13 is installed outside -: the center 1. The antenna 13 is connected to a demodulator 15 ~ 25 in a source group 14 in the center 1. The source group 14 fur-~'.
: -5-~ 5 ;~4 ther includes a video disc player 16, a video tape recorder 17 and a studio 18. The output signals of the source group 14 are applied to a modulation output section 19 composed of two systems. One of the two systems includes an IF modulator cir-cuit 20, a scramble circuit 21, and an up-converter circuit 22 while the other system includes an IF modulator circuit 23 and a~ up-con~erter circuit 34. The outputs of the up-converters : 22 and 24 are connected to the main cable 3 to which a data transceiver 25 is connected for data communication between the center 1 and each main unit 10. The data transceiver 25 is con-nected to a computer 26 which is connected to a peripheral unit 27 such as a printer or a display unit.
- The operation of the CATV thus constructed will be de-scribed.~
- 15 First, the power switch of the television set ll is turned on. With the television set 11 set to a particular un-used channel, the control unit 12 is operated so that the fre-~uency of a ~esired channel to be received is converted into that of the unused channel. The channels which can be selected by the control unit 12 as described above can be classified into three groups of channels for ~A) retransmission programs in which .
television signals from local station are received without modi-- ~ fication, ~B) independent programs Cfree of charge), and ~C) chargeable programs. Each group is allocated ten channels, and therefore any of thirty channels can be selected by operating . . .
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the control unit 12.
~A) Retransmission programs Television signals received by the antenna 13 are de-modulated by the demodulator 15 and then applied to t~e modula-tion output section 19, The signal thus applied is modulatedby ~he IF modulator circuit 23. The frequency of the si~nal thus modulated is increased to a predetermined ~requency by the up-converter circuit 24 according to a determined frequency alloca-tion scheme. That is, it is assigned to a predetermined channel.
The resultant signal is applied through the main cable 3, the branch cable 6, and the branch line 9 to the television sets 11.
~B) Independent programs The independent programs include weather forecast pro-grams, news programs, and the like. In the case of programs re-corded by the video disc player 16 or the video tape recorder17 or in the case of live programs produced in the studio 18, the video signal is modulated by the IF modulator circuit 23 and the fre~uency of the signal thus modulated is increased to that of a predetermined channel by the up-converter circuit 24. The resultant signal is applied to the main cable ~. Reception of these programs is free of charge irrespective of the number of , times of program reception and the pe.riod of time used for pro-. .
gram reception. That is, the programs can be received for the basic monthly charge which is paid by the subscriber.
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, (C) Chargeable programs The chargeable programs include new ~ovie programs, special programs, and the like. In the case o-f programs provided by the video disc player 16 or the video tape recorder 17 or in the case o~ live programs produced in the studio 18, the video signal is modulated by the IF modulator circuit and is then pro-cessed by the scrambler circuit 21 so that they cannot be re-produced without special signal processing. Then, the frequency of the signal is increased to that of a predetermined designated ~ 10 channel, and is then applied to the main cable 3. In order to : receive the chargeable programs, the video signal must be de-scrambled by the main unit 10 in the subscriber's home 2 so that a regular image appears in the television set ll. The subscriber is charged for the reception of the chargeable programs. That is, predetermined charges are summed, and he is requested to pay a special charge at-a measured rate in addition to the mont~ly b as lC charge.
As described above, the center 1 is connected through the coaxial cables to the terminal units in the subscribers' 20~ homes 2. However, in order to charge the subscribers for the reception of the chargeable programs, it is absolutely necessary to detect which subscribers receive which channels. That is, it is necessary to detect the channels which have been selected by the subscribers at various times. In order to meet this re-quirement, the data transceiver Z5 outputs a retrieving signal . .
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at predetermined time intervals so that the terminal units 2~i are called with their assigned address numbers. That is, the chan-nels received b~ the terminal units at the time of transmission of the retrieving signal are detected, this operation ~eing re~erred to as ''polling". In response to this pollingl each terminal unit 28 answers the data transceiver 25 with data re-presentative of the channel which was received by the terminal unit at the time of polling. Various reception and transmission data for the data transceiver 25 are arranged and stored by the 10 computer 26 and are displayed or printed out by the peripheral unit 27. The polling operation is carried out at predetermined time intervals of several seconds to several tens of second and there~ore audience ratings can be readily calculated.
Sometimes, the subscribers may partlcipate in the pro-duction of programs. In this case, by operating the control units 12, they can answer to the programs while watching the teievision - sets 11. The answers are transmitted through the coaxial cables to the center 1.
Fig. 2 shows in block diagram form a preferred embodi-ment of a polling-pattern generator of the invention. A trap 30 for blocking the down data signal but which passes the video signal, has an input connected to a branch line 9. To the trap 30 is connected through a mixer 31 a passive data monitor 32, hereinafter abbreviated to '!PDM". The output of the PDM 32 is connected to a main unit 10. An add~ess setting unit 33, which g_ ..... .
will be hereinafter described in greater detail, is detachably provided at the main unit 10, and is connected through a cable to the PDM 32. Reference numeral 34 indicates a polling pattern generator, hereinafter abbreviated to "PPG". The output of the PPG 34 is connected to the mixer 31. The PPG 34 produces a poll-ing down data signal either by itself or in response to an exter-nal data unit coupled in at an external data input terminal. The PPG 34 can thus poll the respective terminal units 28 through the connection provided between the branch line 9 and the main unit 10 in Fig. 1.
In this apparatus, a down data signal, which will here-inafter be termed an "FSK signal" as it is a frequency shift keyed signal, and video signals and the like are transmitted from the center 1 and are received at the trap 30. Only the video signals are transmitted through the trap 30, the PDM 32 and the main unit 10 to television sets 11. In this manner, the ~elevi-sion set 11 can reproduce the video and audio signals~in the or-dinary manner even during polling.
The PPG 34 normally generates a polling pattern signal having in combination an address code and a command code in the same transmission mode as used by the center 1. The polling sig-nals incorporate all command codes in combination with respecti~e - address data which are repeatedly transmitted in sequence from the polling generator. The polling signals are transmitted through the mixer 31 to the PDM ~2. The terminal ùnit 28 is set to select . . .
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an address correspondingtoaspecial command code. In this man-ner, the PDM 32 can determine the content of an answer from the terminal unit 28. The address for the PD~I 32 can be freely selected and set by the address setting unit 33 in the main unit 10. The construction and operation of the address setting unit 33 will be hereinafter described in greater detail.
When the address is set in the main unit 10, the main unit lO receives only the polling pattern of the address code code set by the address setting unit 33 of the polling patterns from the PPG 34 and outputsan answer corresponding to the command code followed by the address code to the PDM 32. The PDM 32 compares the address code thus set with an answer signal from the main unit 10 and thus determines whether a normal opeTation or an erroneous operation has taken place according to whether c c~
or no~ the received address code agrees with the ~m~a code.
~ Fig. 3 is a block diagram of the PDM 32. The PDM 32 has an input terminal 35 connected to the mixer, an output ter-minal 36 connected to the main unit 10, and an address output terminal 37 connected to the address setting unit 33. The out-put terminal of a signal splitter ~8 is connected to the outputterminal 36 while the high side terminal thereof is connected -~ to the input terminal 35 and the low side terminal to a bandpass filter 39. The output of the bandpass filter 39 is connected to a signal detector 40. The output of the signal detector 40 is connected to inputs of both a high-pass filter 41 and a low-pass .
filter 42. The output of the high-pass filter 41 is connected through a wave shaping circuit 43 to a clock generator 44. A
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BPS-to-NRZ code converter circuit 45 receives the output of the wave shaping circuit 43 and the output of the clock generator 44 converting the BPS code into the NRZ code. A serial-to-parallel converter circuit 46 converts the output of the converter circuit 45 to a parallel signal. The output of the low-pass filter 42 is connected to a latch control CiTCUit 47. The out-put of the latch control circuit 47 is connected to both a data latch circuit 48 and a comparator 49. The output of the converter circuit 46 is connected to the data latch circuit 4~. 'Ihe output of the data latch circuit 48 is connected to both the comparator 49 and a.monitor circuit 5j0. The output of the comparator 49 is connected to a display unit 41, which may be an LED device or the like.
Reference numeral 5~ depicts a selector circuit which can ~e set manually. The output of the selector circuit 52 is ; connected to the inputs of both a data ROM 5~ and an address .. :
ROM 54 which store predetermined data and addresses, respective-ly. Th:e output of the data ROM 53 is connected to the comparator : 49. The output of the. address ROM 5;4 is connecte.d through an lsolation buffer circuit 55 to the ~ddress output terminal 37.
:~ The addre.ss setting unit: 3~ is connected to the address output . terminal 37.
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Fig. 4 shows a front pa.nel-of the PDM 3Z. T~e front .:
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panel has connectors 57 and 58 for the input terminal 3~ and the output terminal 36, respectively, on the uppe~ leftside portion, a multipLe pin connector 5g for the address output terminal 37 below the connector 58, and J~Ds (light emission diodes~ 60 through 65 as the monitor circuit sa and the display unit 51 in the vicinity of the central portion. The LEDs 60 to 62 for the monitor circuit are aligned rectilinearly horizontally. The characters A through J placed above the LEDs 60 indicate answer data from the terminal units. The character above the LLD 61 corresponds to a parity bit. AD designated above the LED 62 in-dicates an additional bit. The LEDs 63 through 65 for display-ing the terminal units condition are arranged above the LEDs 60 through 62. The LED 63 identified by the characters RCP indi-cates that an up signal, hereinafter abbreviated as "PSK" as it is phase shift keyed signal, from the main unit 10 has been received. The LED 64, identified with the cha~acters GO~D,indi-cates that the PSK signal is normal. The L~D 65 labelled NG
indicates that ~he PSK signal is in error.
The panel 56 also incorporates a power switch 66 and a power lamp 67 for indicating the on or off state of the power switch 66 on the upper rightside portion. The panel also has a check number knob 68, which is coupled to a rotary switch, posi-tloned under the power switch 66. This rotary switch is used in the selector circuit 5~.
Fig. 5 is a block diagram showing the circuit arrange-,~ :
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ment of the aforementioned PPG 34. The outputs of a data RO~I
70 in which is stored a Variety of address codes and command codes and outputs of a data switch 71 which is used to set the address code and the command code manually are connected to a selector circuit 72. A control signal from a timing control cir-cuit 73 which determines the timing for producing data is con-nected to both the data RO~I 70 and the data switch 71. The out-put of the selector circuit 72 is connected to an NRZ-to-BPS
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- ~ code converter circuit 74 for converting the NRZ code to the ~
code. The output of the converter circuit 74 is connected to an FSK signal transmitter circuit 75. The output of the transmitter circuit 75 is connected to an FSK output terminal 76. An exteTnal data input terminal 17 for inputting data from an external device is connected directly to the converter circuit 74.
Fig. 6 shows the outer appearance of the PPG 34. A
panel 78 at the fTont of this unit has a power switch 79 and a - power lamp ~ for indicating the on or off state of the power switch 79 on the upper left portion thereof, connectors 81 and 82 forming respectively the external input terminal 77 and the output terminal 76, ~elow the power switch 79, and a switch 83 for selecting one of the external input data and the internal data located on the right of the panel. ~he panel 78 also in-corporates attenuation switches 84 for setting output signal levels aligned in a row horizontally on the central portion.
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These attenuation switches 84 are a push-button type and are used : .
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for determining the output signal level. The panel also has a palling lamp ~ fo-r indicating polling and a function Icnob ~
for varying ~h~ polling speed on t~e right side. Also as seen in Fig. 6, $~e PPG 3~ incorporates a detachable cover 87 on the upper central portion and switch groups for setting desired data under the cover 87.
Fig. 7 shows the construction of the switch groups to which access is made by opening the cover :87 of the PPG 34.
The switch groups correspond to the aforement;oned data switch 71. The individual switches of the four s~itch groups 88, ~ , 90 and 91 can set to either "H" or "L" corresponding to high and low logic levels. The switches 88 and 90 have six individual switches corresponding to six digits while the switch gTOUpS 89 and 90 have five switches corresponding to five digits. The switch groups 8& and ~ are used to set a gTOUp address and the swit ~ 9Q is used to set an individual addTess. The switch 91 is used to set a command.
Fig. 8 shows the address setting section in the main unit 10 with the cover of the main unit 10 removed. A printed circuit board 93 is secured in an insulating manner onto a metallic substrate 9Z. An address socket g4 for determining the address of the main unit lQ is mounted at the corner of the printed circuit board q3. The address socket 94 incorporates two rows of twelve socket holes q5 opening upwardly in two rows and aligned linearly. In the normal receiving operation of television .
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programs, an address block 96 for setting the address o the main unit lQ is engaged with the add~ess socket 94s This aacress block 96 which is formed of plastic or the like, has t;o rows of twelve pins 97 on the lower surface. By selectively ma'iing con-nection between designated ones of the pins 97 inside ~he addressblock 96, a desired address is determined. The pins 97 are in-serted into the socket holes 95. When the main unit 10 is tested in operation, the address block 96 is pulled out of the address socekt 74 and the address setting unit 33 is instead enaged with the address socket 94. Pins 98 project from the lower portion of the address setting unit 33. When the pins 98 are inserted into the socket holes 95, the address setting unit 33 is elec-trically connected to the address socket 94. The control signal from the PDM 32 connects any of the pins 98 by a switching circuit built in the address setting unit 33 wherein the address is free-ly settable.
The operation of this embodiment will be described.
A. "Polling pattern generator 34 ~PPG)"
The operation of the PPG 34 will be described ~;ith re-ference to Figs. 5 through 7.
When the power switch 79 i5 turned on, the po~;er lamp80 is lit, and power is coupled to the various operating circuits.
If it is desired to use the built-in data ROM 70 or the data switch 71, *he selector switch 83 is set to the "INT" position. To set ^ 25 the output signal level, the attenuation switches 84 are set so . ' .
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as to produce the desired level. ~or example, if an output sig-nal level of -38 dB. is desired, the push-hutton ~O~ 10, 5 and 3 of the attenuation switches 84 are depressed.
When ~he power switch 79 is turned on as described s above, the address code and the data code are sequentially pro-duced periodically with predetermined period at the c.onnector 82. Then, the polling operation is conducted. When this type of data is outputted, the polling lamp 85 is turned on. The poll-ing speed (or period) can be varied by turning the function knob 86 (see Fig. 6).
~peration with Data ROM 70 When the power is on as described above, the timing control clrcuit 73 periodically outputs a timing pulse in a pre-determined period to the data ROM 70. The data ROM 70 thus applies the data stored therein at every timing pulse to the selector circuit 72. The selector circuit 72 operates to cut off the inputting of the switch data 71 and to apply only the input from the data RO~I 70 to the con~erter circuit 74 which - converts the NRZ code from the data ROM 76 to BPS code. The data ~hus converted is modulated with a predetermined frequency by the FSK signal transmitter circuit 75 and amplified. The data signal thus modulated and amplified is applied from the output terminal 76 and through the connector 82.
~ In the data ROM 70 is stored a plurality of sets of ~ 25 comblnations of an address code and ~ command code. The sets of -.. -17-- - - -:
data are sequentially outputted, one set at every timing pulse.
When all the data thus stored has been outputted from the data ROM 70, the data is repeatedly outputted starting from the initial data. Specific examples of the types of the data will be described. (The data ROM 70 is a 256 x 8 bit type.) '''' :
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Table 1 D8 D7 D6 Ds D4 D3 D2 D
~000000000 0 1 0 0 0 0 0 0 0 0 Spa~e O~OOOOOOOO
3 0 0 0 0 0 0 ~ ~rame 04 l 1 1 ~ l l l l ~G
0 5 1 1 l l . 0 0 '.1. 0 0 6 0 0 0 0 0 0 0 0 \
0 7 1 0 0 1 1 1 1 1 ~ MP1 4:E
08 1 l l l 1 0 0 0 /
09 0 0 0 0 0 0 0 0 \
o A 1 0 1 0 1 .l 1 1 ~ ~IP 2 ~LON
0 B l 0 0 0 0 l l 0 C O O O O o o o o OD 1 0 1 1 0 1 1 1 l~P3 PP .
0~510010100 O ~ O O G O O O O O
1 0 1 0 1 1 1 0 1 1 ~ ~IP 4 PCD
1 2 O O O ~ O O O O
1 3 1 0 1 1 1 1 0 1 ~Ps 4~ :
. . .
: .
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Tabl~ 2 D8 D7 D6, Ds D4 D3 D2 D~
1 5 Q 0 0 0 û O 0 (~ \
1 6 1 0 1 1 1 1 1 0 ¦ ~d~ LO~ I~
1 7 . 1 :1 0 0 0 1 0 0 /
1 8 0 0 ~ 0 .0 0 0 0 19 1 0 0 1 1 1 1 0 hLP7. 0110 1~ 1 0 1 1 0 0 1 0 i C 1 0 1 0 1 1 1 0 MP8 4 1 1:) 1 1 1 1 1 0 1 0 1 :E O O O O O o o o 1 ~ 1 0 1 1 0 1 1 0 l~Ps, .4-0 ;~ 100000000
BACKGROU~D OF TH~ INVENTION
.
The present lnvention relates to a CATV system.
~ore specifically, the invention to a polling signal generator in a CATV system for periodically transmitting a polling signal to terminal units to initiate the transmission of specific data from the terminal units.
A CATV system serves to transmit a variety of programs to television sets of terminal units installed in subscriber's homes through coaxial cables. Many CATV systems are capable of performing bidirectional simultaneous communications in addition to program transmission wherein the center simultaneous-ly transmits information to a number of the terminal units and receives information back from them. Specifically, predetermin-ed functions in the terminal units have to be periodicall~ or irregularly polled. This polling operation is conducted by transmitting a down data signal to the terminal units~ receiving up signals in reply to the down data signal and comparing the command in the down data signal therewith. However, in order to generate such a down data signal for polling the terminal units, a large-sized computer has heretofore been necessary.
Such a computer cannot easily be transported around the system, as would be desirable.
It is thus an object of the present invention to . . .
provide a polling pattern generator for a CATV system which eliminates the aforementioned drawbacks, is portable, has a simple construction, and can periodically generate a polling pattern for polling the terminal units.
5~
SUMMARY OF THE INVENTION
In accordance with this and other objects of the invention, there is provided a passive data monitor for a CATV system having a single center and a number of terminal units connected to the center fo`r transmitting television programs through cables to the terminal units. Each of the terminal units has an address setting device capable of arbitrarily setting an address number therein which may be unique to the terminal unit. The passive data monitor includes means for receiving a polling pattern signal having an address code for calling a corresponding terminal unit and a command code for requesting a designated answer from the called terminal unit, and means for comparing an output data signal output~ed from the terminal unit in response to the command code with the designated answer requested by the command code and for judging an operational state of the terminal unit from a resultant comparison output.
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BRIEF DESCRIPTION OF THE DRAWINGS
-Fig. 1 is an explanatory view showing a CATV system to which the invention is applied;
Fig. 2 is a block diagram showing the installation of a polling pattern generator;
Fig. 3 is a block diagram of a passive data monitor of the invention;
Fig. 4 is a front view showing the panel of the passive data monitor;
Fig, 5 is a block diagram showing a polling pattern generator of the invention;
Fig. 6 is a front view of the panel of the polling pattern generator of Fig. 5;
Fig. 7 is a plan view showing data switch groups used in the polling pattern generator of Fig. ~;
Fig. 8 is a perspective view of a portion of the interlor of a terminal unit showing an address block and address setting unit installed in the terminal unit; and Fig. 9 is a structural view showing an alternate installation of the polling pattern generator.
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DESCRIPTION OF THE PREFERRED E~IBODIMENTS
A CATV system in which the invention is used to advan-tage will be described with reference to Fig. 1. The CAT~ sys-tem includes a single center 1 and terminal units 28 which are provided, for example, in several tens of thousands of sub-scribers' homes. The center 1 is connected through coaxial cables to the terminal units 2~ in the subscribers' homes 2.
A main cable 3 extends from the center 1 and main cable amplifiers 4 and branching units 5 are provided at predetermined positions on the main cable 3. A plurality of branch cables 6 extend from each branching unit 5. Extension amplifiers 7 and tap-off units - g are provided at predetermined points on the branch cables 6.
Each tap-off unit 8 is connected to branch lines 9 which extend to the terminal units 28 in the subscribers' homes 2. Each ter-minal unit 28 includes a main unit 10, a television set 11 and a control unit 12. The b~anch line 9 is connected to the main unit 10 which is in turn connected to the television set 11 and to t]le control unit 12. As is apparent from the above descrip-- tion, the main cable extending from the center is branched into . 20 a first plurality of branch cables which are further branched into a second plurality of branch lines which are finally con-nected to the terminal units 28.
A signal receiving antenna 13 is installed outside -: the center 1. The antenna 13 is connected to a demodulator 15 ~ 25 in a source group 14 in the center 1. The source group 14 fur-~'.
: -5-~ 5 ;~4 ther includes a video disc player 16, a video tape recorder 17 and a studio 18. The output signals of the source group 14 are applied to a modulation output section 19 composed of two systems. One of the two systems includes an IF modulator cir-cuit 20, a scramble circuit 21, and an up-converter circuit 22 while the other system includes an IF modulator circuit 23 and a~ up-con~erter circuit 34. The outputs of the up-converters : 22 and 24 are connected to the main cable 3 to which a data transceiver 25 is connected for data communication between the center 1 and each main unit 10. The data transceiver 25 is con-nected to a computer 26 which is connected to a peripheral unit 27 such as a printer or a display unit.
- The operation of the CATV thus constructed will be de-scribed.~
- 15 First, the power switch of the television set ll is turned on. With the television set 11 set to a particular un-used channel, the control unit 12 is operated so that the fre-~uency of a ~esired channel to be received is converted into that of the unused channel. The channels which can be selected by the control unit 12 as described above can be classified into three groups of channels for ~A) retransmission programs in which .
television signals from local station are received without modi-- ~ fication, ~B) independent programs Cfree of charge), and ~C) chargeable programs. Each group is allocated ten channels, and therefore any of thirty channels can be selected by operating . . .
:
~ 5^^~
the control unit 12.
~A) Retransmission programs Television signals received by the antenna 13 are de-modulated by the demodulator 15 and then applied to t~e modula-tion output section 19, The signal thus applied is modulatedby ~he IF modulator circuit 23. The frequency of the si~nal thus modulated is increased to a predetermined ~requency by the up-converter circuit 24 according to a determined frequency alloca-tion scheme. That is, it is assigned to a predetermined channel.
The resultant signal is applied through the main cable 3, the branch cable 6, and the branch line 9 to the television sets 11.
~B) Independent programs The independent programs include weather forecast pro-grams, news programs, and the like. In the case of programs re-corded by the video disc player 16 or the video tape recorder17 or in the case of live programs produced in the studio 18, the video signal is modulated by the IF modulator circuit 23 and the fre~uency of the signal thus modulated is increased to that of a predetermined channel by the up-converter circuit 24. The resultant signal is applied to the main cable ~. Reception of these programs is free of charge irrespective of the number of , times of program reception and the pe.riod of time used for pro-. .
gram reception. That is, the programs can be received for the basic monthly charge which is paid by the subscriber.
..
, (C) Chargeable programs The chargeable programs include new ~ovie programs, special programs, and the like. In the case o-f programs provided by the video disc player 16 or the video tape recorder 17 or in the case o~ live programs produced in the studio 18, the video signal is modulated by the IF modulator circuit and is then pro-cessed by the scrambler circuit 21 so that they cannot be re-produced without special signal processing. Then, the frequency of the signal is increased to that of a predetermined designated ~ 10 channel, and is then applied to the main cable 3. In order to : receive the chargeable programs, the video signal must be de-scrambled by the main unit 10 in the subscriber's home 2 so that a regular image appears in the television set ll. The subscriber is charged for the reception of the chargeable programs. That is, predetermined charges are summed, and he is requested to pay a special charge at-a measured rate in addition to the mont~ly b as lC charge.
As described above, the center 1 is connected through the coaxial cables to the terminal units in the subscribers' 20~ homes 2. However, in order to charge the subscribers for the reception of the chargeable programs, it is absolutely necessary to detect which subscribers receive which channels. That is, it is necessary to detect the channels which have been selected by the subscribers at various times. In order to meet this re-quirement, the data transceiver Z5 outputs a retrieving signal . .
; -8-.
~ 5~
at predetermined time intervals so that the terminal units 2~i are called with their assigned address numbers. That is, the chan-nels received b~ the terminal units at the time of transmission of the retrieving signal are detected, this operation ~eing re~erred to as ''polling". In response to this pollingl each terminal unit 28 answers the data transceiver 25 with data re-presentative of the channel which was received by the terminal unit at the time of polling. Various reception and transmission data for the data transceiver 25 are arranged and stored by the 10 computer 26 and are displayed or printed out by the peripheral unit 27. The polling operation is carried out at predetermined time intervals of several seconds to several tens of second and there~ore audience ratings can be readily calculated.
Sometimes, the subscribers may partlcipate in the pro-duction of programs. In this case, by operating the control units 12, they can answer to the programs while watching the teievision - sets 11. The answers are transmitted through the coaxial cables to the center 1.
Fig. 2 shows in block diagram form a preferred embodi-ment of a polling-pattern generator of the invention. A trap 30 for blocking the down data signal but which passes the video signal, has an input connected to a branch line 9. To the trap 30 is connected through a mixer 31 a passive data monitor 32, hereinafter abbreviated to '!PDM". The output of the PDM 32 is connected to a main unit 10. An add~ess setting unit 33, which g_ ..... .
will be hereinafter described in greater detail, is detachably provided at the main unit 10, and is connected through a cable to the PDM 32. Reference numeral 34 indicates a polling pattern generator, hereinafter abbreviated to "PPG". The output of the PPG 34 is connected to the mixer 31. The PPG 34 produces a poll-ing down data signal either by itself or in response to an exter-nal data unit coupled in at an external data input terminal. The PPG 34 can thus poll the respective terminal units 28 through the connection provided between the branch line 9 and the main unit 10 in Fig. 1.
In this apparatus, a down data signal, which will here-inafter be termed an "FSK signal" as it is a frequency shift keyed signal, and video signals and the like are transmitted from the center 1 and are received at the trap 30. Only the video signals are transmitted through the trap 30, the PDM 32 and the main unit 10 to television sets 11. In this manner, the ~elevi-sion set 11 can reproduce the video and audio signals~in the or-dinary manner even during polling.
The PPG 34 normally generates a polling pattern signal having in combination an address code and a command code in the same transmission mode as used by the center 1. The polling sig-nals incorporate all command codes in combination with respecti~e - address data which are repeatedly transmitted in sequence from the polling generator. The polling signals are transmitted through the mixer 31 to the PDM ~2. The terminal ùnit 28 is set to select . . .
. ~......................... . --1 0--.. . . .
~ 5~
an address correspondingtoaspecial command code. In this man-ner, the PDM 32 can determine the content of an answer from the terminal unit 28. The address for the PD~I 32 can be freely selected and set by the address setting unit 33 in the main unit 10. The construction and operation of the address setting unit 33 will be hereinafter described in greater detail.
When the address is set in the main unit 10, the main unit lO receives only the polling pattern of the address code code set by the address setting unit 33 of the polling patterns from the PPG 34 and outputsan answer corresponding to the command code followed by the address code to the PDM 32. The PDM 32 compares the address code thus set with an answer signal from the main unit 10 and thus determines whether a normal opeTation or an erroneous operation has taken place according to whether c c~
or no~ the received address code agrees with the ~m~a code.
~ Fig. 3 is a block diagram of the PDM 32. The PDM 32 has an input terminal 35 connected to the mixer, an output ter-minal 36 connected to the main unit 10, and an address output terminal 37 connected to the address setting unit 33. The out-put terminal of a signal splitter ~8 is connected to the outputterminal 36 while the high side terminal thereof is connected -~ to the input terminal 35 and the low side terminal to a bandpass filter 39. The output of the bandpass filter 39 is connected to a signal detector 40. The output of the signal detector 40 is connected to inputs of both a high-pass filter 41 and a low-pass .
filter 42. The output of the high-pass filter 41 is connected through a wave shaping circuit 43 to a clock generator 44. A
. , .
BPS-to-NRZ code converter circuit 45 receives the output of the wave shaping circuit 43 and the output of the clock generator 44 converting the BPS code into the NRZ code. A serial-to-parallel converter circuit 46 converts the output of the converter circuit 45 to a parallel signal. The output of the low-pass filter 42 is connected to a latch control CiTCUit 47. The out-put of the latch control circuit 47 is connected to both a data latch circuit 48 and a comparator 49. The output of the converter circuit 46 is connected to the data latch circuit 4~. 'Ihe output of the data latch circuit 48 is connected to both the comparator 49 and a.monitor circuit 5j0. The output of the comparator 49 is connected to a display unit 41, which may be an LED device or the like.
Reference numeral 5~ depicts a selector circuit which can ~e set manually. The output of the selector circuit 52 is ; connected to the inputs of both a data ROM 5~ and an address .. :
ROM 54 which store predetermined data and addresses, respective-ly. Th:e output of the data ROM 53 is connected to the comparator : 49. The output of the. address ROM 5;4 is connecte.d through an lsolation buffer circuit 55 to the ~ddress output terminal 37.
:~ The addre.ss setting unit: 3~ is connected to the address output . terminal 37.
.
Fig. 4 shows a front pa.nel-of the PDM 3Z. T~e front .:
; -12-.
panel has connectors 57 and 58 for the input terminal 3~ and the output terminal 36, respectively, on the uppe~ leftside portion, a multipLe pin connector 5g for the address output terminal 37 below the connector 58, and J~Ds (light emission diodes~ 60 through 65 as the monitor circuit sa and the display unit 51 in the vicinity of the central portion. The LEDs 60 to 62 for the monitor circuit are aligned rectilinearly horizontally. The characters A through J placed above the LEDs 60 indicate answer data from the terminal units. The character above the LLD 61 corresponds to a parity bit. AD designated above the LED 62 in-dicates an additional bit. The LEDs 63 through 65 for display-ing the terminal units condition are arranged above the LEDs 60 through 62. The LED 63 identified by the characters RCP indi-cates that an up signal, hereinafter abbreviated as "PSK" as it is phase shift keyed signal, from the main unit 10 has been received. The LED 64, identified with the cha~acters GO~D,indi-cates that the PSK signal is normal. The L~D 65 labelled NG
indicates that ~he PSK signal is in error.
The panel 56 also incorporates a power switch 66 and a power lamp 67 for indicating the on or off state of the power switch 66 on the upper rightside portion. The panel also has a check number knob 68, which is coupled to a rotary switch, posi-tloned under the power switch 66. This rotary switch is used in the selector circuit 5~.
Fig. 5 is a block diagram showing the circuit arrange-,~ :
' ..
L S ! ~ ~
;
ment of the aforementioned PPG 34. The outputs of a data RO~I
70 in which is stored a Variety of address codes and command codes and outputs of a data switch 71 which is used to set the address code and the command code manually are connected to a selector circuit 72. A control signal from a timing control cir-cuit 73 which determines the timing for producing data is con-nected to both the data RO~I 70 and the data switch 71. The out-put of the selector circuit 72 is connected to an NRZ-to-BPS
3~S
- ~ code converter circuit 74 for converting the NRZ code to the ~
code. The output of the converter circuit 74 is connected to an FSK signal transmitter circuit 75. The output of the transmitter circuit 75 is connected to an FSK output terminal 76. An exteTnal data input terminal 17 for inputting data from an external device is connected directly to the converter circuit 74.
Fig. 6 shows the outer appearance of the PPG 34. A
panel 78 at the fTont of this unit has a power switch 79 and a - power lamp ~ for indicating the on or off state of the power switch 79 on the upper left portion thereof, connectors 81 and 82 forming respectively the external input terminal 77 and the output terminal 76, ~elow the power switch 79, and a switch 83 for selecting one of the external input data and the internal data located on the right of the panel. ~he panel 78 also in-corporates attenuation switches 84 for setting output signal levels aligned in a row horizontally on the central portion.
. . .
These attenuation switches 84 are a push-button type and are used : .
.
for determining the output signal level. The panel also has a palling lamp ~ fo-r indicating polling and a function Icnob ~
for varying ~h~ polling speed on t~e right side. Also as seen in Fig. 6, $~e PPG 3~ incorporates a detachable cover 87 on the upper central portion and switch groups for setting desired data under the cover 87.
Fig. 7 shows the construction of the switch groups to which access is made by opening the cover :87 of the PPG 34.
The switch groups correspond to the aforement;oned data switch 71. The individual switches of the four s~itch groups 88, ~ , 90 and 91 can set to either "H" or "L" corresponding to high and low logic levels. The switches 88 and 90 have six individual switches corresponding to six digits while the switch gTOUpS 89 and 90 have five switches corresponding to five digits. The switch groups 8& and ~ are used to set a gTOUp address and the swit ~ 9Q is used to set an individual addTess. The switch 91 is used to set a command.
Fig. 8 shows the address setting section in the main unit 10 with the cover of the main unit 10 removed. A printed circuit board 93 is secured in an insulating manner onto a metallic substrate 9Z. An address socket g4 for determining the address of the main unit lQ is mounted at the corner of the printed circuit board q3. The address socket 94 incorporates two rows of twelve socket holes q5 opening upwardly in two rows and aligned linearly. In the normal receiving operation of television .
:' .
programs, an address block 96 for setting the address o the main unit lQ is engaged with the add~ess socket 94s This aacress block 96 which is formed of plastic or the like, has t;o rows of twelve pins 97 on the lower surface. By selectively ma'iing con-nection between designated ones of the pins 97 inside ~he addressblock 96, a desired address is determined. The pins 97 are in-serted into the socket holes 95. When the main unit 10 is tested in operation, the address block 96 is pulled out of the address socekt 74 and the address setting unit 33 is instead enaged with the address socket 94. Pins 98 project from the lower portion of the address setting unit 33. When the pins 98 are inserted into the socket holes 95, the address setting unit 33 is elec-trically connected to the address socket 94. The control signal from the PDM 32 connects any of the pins 98 by a switching circuit built in the address setting unit 33 wherein the address is free-ly settable.
The operation of this embodiment will be described.
A. "Polling pattern generator 34 ~PPG)"
The operation of the PPG 34 will be described ~;ith re-ference to Figs. 5 through 7.
When the power switch 79 i5 turned on, the po~;er lamp80 is lit, and power is coupled to the various operating circuits.
If it is desired to use the built-in data ROM 70 or the data switch 71, *he selector switch 83 is set to the "INT" position. To set ^ 25 the output signal level, the attenuation switches 84 are set so . ' .
. . .
as to produce the desired level. ~or example, if an output sig-nal level of -38 dB. is desired, the push-hutton ~O~ 10, 5 and 3 of the attenuation switches 84 are depressed.
When ~he power switch 79 is turned on as described s above, the address code and the data code are sequentially pro-duced periodically with predetermined period at the c.onnector 82. Then, the polling operation is conducted. When this type of data is outputted, the polling lamp 85 is turned on. The poll-ing speed (or period) can be varied by turning the function knob 86 (see Fig. 6).
~peration with Data ROM 70 When the power is on as described above, the timing control clrcuit 73 periodically outputs a timing pulse in a pre-determined period to the data ROM 70. The data ROM 70 thus applies the data stored therein at every timing pulse to the selector circuit 72. The selector circuit 72 operates to cut off the inputting of the switch data 71 and to apply only the input from the data RO~I 70 to the con~erter circuit 74 which - converts the NRZ code from the data ROM 76 to BPS code. The data ~hus converted is modulated with a predetermined frequency by the FSK signal transmitter circuit 75 and amplified. The data signal thus modulated and amplified is applied from the output terminal 76 and through the connector 82.
~ In the data ROM 70 is stored a plurality of sets of ~ 25 comblnations of an address code and ~ command code. The sets of -.. -17-- - - -:
data are sequentially outputted, one set at every timing pulse.
When all the data thus stored has been outputted from the data ROM 70, the data is repeatedly outputted starting from the initial data. Specific examples of the types of the data will be described. (The data ROM 70 is a 256 x 8 bit type.) '''' :
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.
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Table 1 D8 D7 D6 Ds D4 D3 D2 D
~000000000 0 1 0 0 0 0 0 0 0 0 Spa~e O~OOOOOOOO
3 0 0 0 0 0 0 ~ ~rame 04 l 1 1 ~ l l l l ~G
0 5 1 1 l l . 0 0 '.1. 0 0 6 0 0 0 0 0 0 0 0 \
0 7 1 0 0 1 1 1 1 1 ~ MP1 4:E
08 1 l l l 1 0 0 0 /
09 0 0 0 0 0 0 0 0 \
o A 1 0 1 0 1 .l 1 1 ~ ~IP 2 ~LON
0 B l 0 0 0 0 l l 0 C O O O O o o o o OD 1 0 1 1 0 1 1 1 l~P3 PP .
0~510010100 O ~ O O G O O O O O
1 0 1 0 1 1 1 0 1 1 ~ ~IP 4 PCD
1 2 O O O ~ O O O O
1 3 1 0 1 1 1 1 0 1 ~Ps 4~ :
. . .
: .
..
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Tabl~ 2 D8 D7 D6, Ds D4 D3 D2 D~
1 5 Q 0 0 0 û O 0 (~ \
1 6 1 0 1 1 1 1 1 0 ¦ ~d~ LO~ I~
1 7 . 1 :1 0 0 0 1 0 0 /
1 8 0 0 ~ 0 .0 0 0 0 19 1 0 0 1 1 1 1 0 hLP7. 0110 1~ 1 0 1 1 0 0 1 0 i C 1 0 1 0 1 1 1 0 MP8 4 1 1:) 1 1 1 1 1 0 1 0 1 :E O O O O O o o o 1 ~ 1 0 1 1 0 1 1 0 l~Ps, .4-0 ;~ 100000000
2 2 . 1 0 1 1 0 1 1 ¦ ~P~ G~F
2 4 0 0 0 0 0 0 0~ 0 2 5 1 0 1 1 0 1 1 0 1 ~Ps DC
2 7 0 0 o 0 0 0 o 0 2 ~3 1 1 0 0 0 0 0 AG
., ~ :
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. -20-. ~
; ~ , . . . . ...
In this manner, the data o~ the address code and the command code are sequentially read out from the data ~O~I 7Q.
The da~a contains step's sequentially nu~ered "00" to "29" steps.
When step "29" of the data and this operation is repeated. When the in,terval of generating the timing pulses from the timing control circuit 73 is varied by operating the function knob 86, the polling speed or period varies.
Operati'on with'Dat'a'Switch' 71 When the cover 87 of the PPG 34 is opened, the built-in switch groups 88 through 91 are accessible. With the cover 87 thus removed, the selector circuit 72 is simultaneously auto-matically selected and only the slgnal of the data switch 71 is applied to the converter circuit 74. The switches 88 through 91 can bè manually set to the "H" or "L" position and the switches 88 and 89 are used to freely select the group address code, the switch 90 to set the individual code and the switch 91 t'o freely ,set the command code. (The start, index and parity codes are separately set beforehand.) The data thus set is applied to the selector circuit 72 using the timing pulse signal from the timing 20' contTol circuit 73 as described above.
Operation wi'th'E'xtern'al' Data''Input ; The output of the generator for generating other data is connected to the connector 81. The selector switch 83 is set to the "EXT" position. Thus, the external data input is applied ': 25 directly to the converter circuit 74. The external data thus .. . .
.
.' , ,. , , ' , .
i S L'3 ~L
app:lied is outputted throu~h the transmitter circuit.
B. "Passive Data ~lodulator 32 ~D~I)"
The operation of'the PD~I 32 will be described l~-ith - reference to Figs. 3 and 4.
When the switch 66 is turned on~ the power lamp 67 is lit and power is supplied to the various circuits of the units. When the check number knob 68 is turned, the built in ROM 53 and ROhl 54 are selected and the stored polling list is - changed. A pin plug (not shown) is connected to th~ address set-10' ting unit 33 by insertion thereof into the pin socket 59. The address of the mode selected by the check number knob 68 is out-putted as a control signal from the pin socket 59. The PSK sig-nal from the main unit 10 is applied to the connector 57. l~'hen ' the PSK signal is thus applied, the RCP LED 63 is lit indicating the reception of the PSK signal. If the PSK signal is correct, the LED 64 corresponding to GOOD is lit while if the PS~ signal is in error, the LED 65 corresponding to NG is lit. The LED 60 ~- indicates the content of the PSK signal, the LED 61 indicates - the presence or absence of parity, and the LED 62 indicates the presence or absence of the additional bit ~see Fig. ~).
`' Setting of Address .
When the selector circuit 52, which is set by the ' check nu:mber knob 68, is operated, the selector circuit 52 selects the address number corresponding to the function to be chec~ed to thereby output the desired address number from the address . ' .
:
:;, .. .. ... .
2 4 0 0 0 0 0 0 0~ 0 2 5 1 0 1 1 0 1 1 0 1 ~Ps DC
2 7 0 0 o 0 0 0 o 0 2 ~3 1 1 0 0 0 0 0 AG
., ~ :
,.,. ~ :: ::
. -20-. ~
; ~ , . . . . ...
In this manner, the data o~ the address code and the command code are sequentially read out from the data ~O~I 7Q.
The da~a contains step's sequentially nu~ered "00" to "29" steps.
When step "29" of the data and this operation is repeated. When the in,terval of generating the timing pulses from the timing control circuit 73 is varied by operating the function knob 86, the polling speed or period varies.
Operati'on with'Dat'a'Switch' 71 When the cover 87 of the PPG 34 is opened, the built-in switch groups 88 through 91 are accessible. With the cover 87 thus removed, the selector circuit 72 is simultaneously auto-matically selected and only the slgnal of the data switch 71 is applied to the converter circuit 74. The switches 88 through 91 can bè manually set to the "H" or "L" position and the switches 88 and 89 are used to freely select the group address code, the switch 90 to set the individual code and the switch 91 t'o freely ,set the command code. (The start, index and parity codes are separately set beforehand.) The data thus set is applied to the selector circuit 72 using the timing pulse signal from the timing 20' contTol circuit 73 as described above.
Operation wi'th'E'xtern'al' Data''Input ; The output of the generator for generating other data is connected to the connector 81. The selector switch 83 is set to the "EXT" position. Thus, the external data input is applied ': 25 directly to the converter circuit 74. The external data thus .. . .
.
.' , ,. , , ' , .
i S L'3 ~L
app:lied is outputted throu~h the transmitter circuit.
B. "Passive Data ~lodulator 32 ~D~I)"
The operation of'the PD~I 32 will be described l~-ith - reference to Figs. 3 and 4.
When the switch 66 is turned on~ the power lamp 67 is lit and power is supplied to the various circuits of the units. When the check number knob 68 is turned, the built in ROM 53 and ROhl 54 are selected and the stored polling list is - changed. A pin plug (not shown) is connected to th~ address set-10' ting unit 33 by insertion thereof into the pin socket 59. The address of the mode selected by the check number knob 68 is out-putted as a control signal from the pin socket 59. The PSK sig-nal from the main unit 10 is applied to the connector 57. l~'hen ' the PSK signal is thus applied, the RCP LED 63 is lit indicating the reception of the PSK signal. If the PSK signal is correct, the LED 64 corresponding to GOOD is lit while if the PS~ signal is in error, the LED 65 corresponding to NG is lit. The LED 60 ~- indicates the content of the PSK signal, the LED 61 indicates - the presence or absence of parity, and the LED 62 indicates the presence or absence of the additional bit ~see Fig. ~).
`' Setting of Address .
When the selector circuit 52, which is set by the ' check nu:mber knob 68, is operated, the selector circuit 52 selects the address number corresponding to the function to be chec~ed to thereby output the desired address number from the address . ' .
:
:;, .. .. ... .
3 4~
ROM 54 to the isolation buffer circuit 55 and to apply the ad-dress signal to the address output terminal 37, With the address setting unit 33 connected t~rough a soaxial cable to the address ~utput terminal 37 (the pln connector 59), the addTess signal is applied to the address setting unit 33. In response to the address sign'al, the address setting unit 33 sets interconnections between ones of the pins 9g (Fig. ~). Thus, since the pins 98 of the address setting unit 33 are inserted into the pin holes 95 of the address block 94, the address is set in the main unit 10 through the pin 98. When the set address number is polled, the data is applied to the main unit 10.
Setting of Data -, When the address number is selected in the address RO~I
54 by the selector circuit 42 as described above, the selected signal is simultaneously applied to the data ROM 53. The data corresponding to the address number is applied fTom the data ROM
' 53 to the comparator 49. That is, the address number and the data are treated as a pair. The special address number is always simultaneously outputted in combination with the special data.
The address number and the content of the data are equal to the ~' address number and the answer data corresponding to the following ., ~' command data generated by the PPG 34.
Reception--of'Data A co~mand is applied, as shown in Fig. 2, from the PPG 34 through'the PDM 32 to the main unit 10. Thi's command con-.' ,, .
tains an address number and data in combination as described - above. A plurality of types.of the commands are sequentially outputted. When the final command of a series of the commands is outputted, the initial command is a~ain outputted starLing . S from the first command. More particularly, several types of commands are continuously and repeatedly sequentially outputted from the PPG 34. Since the address number is set to a special value by the address setting unit 33 as described above, the .; main unit 10 starts operation upon reception of a particular . 10 one of the addresses applied from the PPG 34, reads the data . followed by the address number and transmits an answering PSK
signal toward the center 1 and accordingly towaTd the PD~I 32.
The PSK.signal is applied from the input terminal 36 ~the con-nector 58) to the signal splitter 38 and from these applied to the bandpass filter 39. (The FSK signal corresponds to the high frequency and the PSK signal to the low frequency.) The . PSK signal, after passing thTough the bandpass filter 39 is -~ detected by the signal detector 40, and is the.n applied to both the high-pass filter 41 and the low-pass filter 42. The output-: zo signal from the high-pass filter 41 is.applied to both the wave : shaping circuit 43 and the clock generator 44. The converter . circuit 45 co~verts the ~PS code into the NRZ code and to apply -. the NRZ code to the serial-to-parallel converter circui~ 45.
The PSK slgnal is applied to the clock generator 44 which detects and outputs only the clock information in the signal. The clock ~: -24-.. . . . .. .. . .. .
generator 44 thus applies the clock signal thus produced to both the converter circuit 45 which uses the clock signals to time their operations. Wit~ the clock signal thus applied to the conver~er circuit 45, the PSK signal is applied to the converter circuit 46 at every clock pulse.
The data latch circuit 48 receives the signal from the converter circuit 46 and holds the PSK signal of a predetermined bit-number parallel signal (for example, eight-bit parallel sig-nal). The output of the data latch circuit 48 is displayed by the monitor circuit 50. The latch control circuit detects effec-tive sections of the data and thus to control the data rewriting operation in the latch circuit. The output of the data latch circuit 48 is applied to the comparator 49. The comparator 49 receives tlle preset data from the data RO~I 53, compares the out-put from the data latch circuit 48 with the preset data from thedata ROM 53, and applies the compared result output to the dis-play unit 51. If the two signals are the same, it is indicated that the main unit 10 is operating normally by lighting the GOOD
LED 64. If, however, the two signals are different, it is indi-cated that the main unit 10 is operating erroneously by light-` ing the-NG LED 65.
~ IYith such a serles of operations, it is determined - whether or not a particular function o the main unit 10 is operating normally or erroneously by the special address and data ` 25 set ~y the selector circuit 52. Accordingly, when the selector .
.
. . .
L5~
circuit 52 is o~erated to set sequen,tially the designated address '- and the data cor~esponding to the designated address, almost all th,e functions of the main unit 10 are tested.
Fig. 9 is a ~lock diagram showing a system in w~ich the functions of the terminal units 28 can be tested by the cen~er 1 and the PDM 32.
The center 1 incorporates a polling pattern generator circuit 190 connected to a main cable 3, The generator circult 100 stores a plurality of address numbers and a plurality of data " 10 for checking the operating state of the terminal units 28 cor-, responding to the address numbers. The data corresponding to the address numbers is periodically applied to the main cable a.
The polling pattern signals are fed during an idling time for polling. (This time has a duration of 5 to 10 seconds.) The address in the polling pattern signal is not the one used in the - address of a plurality of terminal unit,s 28, but is a special ;' address not actually used so that a malfunction does not occur.
The PDM 32 is connected to the branch lines 9 from by the main cable 3. The main unit I0 is connected to the output of the `"~ 20 PDM 32. An address setting unit 33 is connected to the PDM 32 ,' as described above. The address setting unit 33 is connected ~'~ to the address socket of the main unit lC. Since in this e~bodi-'' ment the center 1 periodically outputs the c~ecking address and ~' the data during the idling time ofpolling, when the address to bechecked by the PDM 32 is set, the address setting unit 33 defines : ,". .
.
.: ~ ,,, .. . . .. ... . . .
5'il~
the address numb.er of the main unit 10. ~he the set address polling pattern signal is transmitted to the main unit 10, the main unit lQ outputs a PSK signal corresponding to the data to the PDM 32 and the PDM 32 analyzes the PSK signal in the same manner as described a~.ove.
In the polling pattern geneTator described above, ~he polling pattern is generated using a simple circuit arrangemen~
: and without using a large-size computer. ~oreover, since the generator of the invention is portable, it can be operated in the vicinity of the terminal units without moving the terminal unit as well as being used to test and repair terminal units in a factory or repai~ facility.
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ROM 54 to the isolation buffer circuit 55 and to apply the ad-dress signal to the address output terminal 37, With the address setting unit 33 connected t~rough a soaxial cable to the address ~utput terminal 37 (the pln connector 59), the addTess signal is applied to the address setting unit 33. In response to the address sign'al, the address setting unit 33 sets interconnections between ones of the pins 9g (Fig. ~). Thus, since the pins 98 of the address setting unit 33 are inserted into the pin holes 95 of the address block 94, the address is set in the main unit 10 through the pin 98. When the set address number is polled, the data is applied to the main unit 10.
Setting of Data -, When the address number is selected in the address RO~I
54 by the selector circuit 42 as described above, the selected signal is simultaneously applied to the data ROM 53. The data corresponding to the address number is applied fTom the data ROM
' 53 to the comparator 49. That is, the address number and the data are treated as a pair. The special address number is always simultaneously outputted in combination with the special data.
The address number and the content of the data are equal to the ~' address number and the answer data corresponding to the following ., ~' command data generated by the PPG 34.
Reception--of'Data A co~mand is applied, as shown in Fig. 2, from the PPG 34 through'the PDM 32 to the main unit 10. Thi's command con-.' ,, .
tains an address number and data in combination as described - above. A plurality of types.of the commands are sequentially outputted. When the final command of a series of the commands is outputted, the initial command is a~ain outputted starLing . S from the first command. More particularly, several types of commands are continuously and repeatedly sequentially outputted from the PPG 34. Since the address number is set to a special value by the address setting unit 33 as described above, the .; main unit 10 starts operation upon reception of a particular . 10 one of the addresses applied from the PPG 34, reads the data . followed by the address number and transmits an answering PSK
signal toward the center 1 and accordingly towaTd the PD~I 32.
The PSK.signal is applied from the input terminal 36 ~the con-nector 58) to the signal splitter 38 and from these applied to the bandpass filter 39. (The FSK signal corresponds to the high frequency and the PSK signal to the low frequency.) The . PSK signal, after passing thTough the bandpass filter 39 is -~ detected by the signal detector 40, and is the.n applied to both the high-pass filter 41 and the low-pass filter 42. The output-: zo signal from the high-pass filter 41 is.applied to both the wave : shaping circuit 43 and the clock generator 44. The converter . circuit 45 co~verts the ~PS code into the NRZ code and to apply -. the NRZ code to the serial-to-parallel converter circui~ 45.
The PSK slgnal is applied to the clock generator 44 which detects and outputs only the clock information in the signal. The clock ~: -24-.. . . . .. .. . .. .
generator 44 thus applies the clock signal thus produced to both the converter circuit 45 which uses the clock signals to time their operations. Wit~ the clock signal thus applied to the conver~er circuit 45, the PSK signal is applied to the converter circuit 46 at every clock pulse.
The data latch circuit 48 receives the signal from the converter circuit 46 and holds the PSK signal of a predetermined bit-number parallel signal (for example, eight-bit parallel sig-nal). The output of the data latch circuit 48 is displayed by the monitor circuit 50. The latch control circuit detects effec-tive sections of the data and thus to control the data rewriting operation in the latch circuit. The output of the data latch circuit 48 is applied to the comparator 49. The comparator 49 receives tlle preset data from the data RO~I 53, compares the out-put from the data latch circuit 48 with the preset data from thedata ROM 53, and applies the compared result output to the dis-play unit 51. If the two signals are the same, it is indicated that the main unit 10 is operating normally by lighting the GOOD
LED 64. If, however, the two signals are different, it is indi-cated that the main unit 10 is operating erroneously by light-` ing the-NG LED 65.
~ IYith such a serles of operations, it is determined - whether or not a particular function o the main unit 10 is operating normally or erroneously by the special address and data ` 25 set ~y the selector circuit 52. Accordingly, when the selector .
.
. . .
L5~
circuit 52 is o~erated to set sequen,tially the designated address '- and the data cor~esponding to the designated address, almost all th,e functions of the main unit 10 are tested.
Fig. 9 is a ~lock diagram showing a system in w~ich the functions of the terminal units 28 can be tested by the cen~er 1 and the PDM 32.
The center 1 incorporates a polling pattern generator circuit 190 connected to a main cable 3, The generator circult 100 stores a plurality of address numbers and a plurality of data " 10 for checking the operating state of the terminal units 28 cor-, responding to the address numbers. The data corresponding to the address numbers is periodically applied to the main cable a.
The polling pattern signals are fed during an idling time for polling. (This time has a duration of 5 to 10 seconds.) The address in the polling pattern signal is not the one used in the - address of a plurality of terminal unit,s 28, but is a special ;' address not actually used so that a malfunction does not occur.
The PDM 32 is connected to the branch lines 9 from by the main cable 3. The main unit I0 is connected to the output of the `"~ 20 PDM 32. An address setting unit 33 is connected to the PDM 32 ,' as described above. The address setting unit 33 is connected ~'~ to the address socket of the main unit lC. Since in this e~bodi-'' ment the center 1 periodically outputs the c~ecking address and ~' the data during the idling time ofpolling, when the address to bechecked by the PDM 32 is set, the address setting unit 33 defines : ,". .
.
.: ~ ,,, .. . . .. ... . . .
5'il~
the address numb.er of the main unit 10. ~he the set address polling pattern signal is transmitted to the main unit 10, the main unit lQ outputs a PSK signal corresponding to the data to the PDM 32 and the PDM 32 analyzes the PSK signal in the same manner as described a~.ove.
In the polling pattern geneTator described above, ~he polling pattern is generated using a simple circuit arrangemen~
: and without using a large-size computer. ~oreover, since the generator of the invention is portable, it can be operated in the vicinity of the terminal units without moving the terminal unit as well as being used to test and repair terminal units in a factory or repai~ facility.
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Claims (4)
1. A passive data monitor for a CATV system having a single center and a number of terminal units connected to said center for transmitting television programs through cables to said terminal units, each of said terminal units having address setting means capable of arbitrarily setting address number therein, said passive data monitor comprising: means for receiving a polling pattern signal having an address code for calling a corresponding terminal unit and a command code for requesting a designated answer from the called terminal unit;
and means for comparing an up data signal outputted from said terminal unit in response to said code with said designated answer requested by said command code and for judging an opera-tional state of said terminal unit from a resultant comparison output.
and means for comparing an up data signal outputted from said terminal unit in response to said code with said designated answer requested by said command code and for judging an opera-tional state of said terminal unit from a resultant comparison output.
2. The passive data monitor of claim 1 wherein said receiving means comprises a signal splitter having a high-side terminal adapted to be coupled to a cable extending from said center, and an output adapted to be coupled to a terminal unit, and a low side terminal; a bandpass filter having an input coupled to said low side terminal of said signal splitter; a signal detector having an input coupled to an output of said bandpass filter; a high-pass filter having an input coupled to an output of said signal detector; a wave shaping circuit having an input coupled to an output of said high-pass filter; a BPS-to NRZ converter having a data input coupled to an output of said wave shaping circuit; a serial-to-parallel convertor having an input coupled to a data output of said BPS-to-NRZ conveter;
a clock generator having an input coupled to said output of said wave shaping circuit and an output coupled to clock inputs of said BPS-to-NRZ converter and said serial-to-parallel convertor; a low-pass filter having an input coupled to said output of said signal detector; a latch control circuit having an input coupled to an output of said low-pass filter; a data lactch having a data input coupled to an output of said serial-to-parallel converter and a clock input coupled to an output of said latch control circuit; and monitor means coupled to an output of said data latch; and wherein said comparing means comprises a comparator having a first input port coupled to an output of said data latch; a selector switch having outputs coupled to address inputs of said data ROM; an address ROM
having address inputs coupled to said outputs of said selector switch; an isolation buffer having an input coupled to an output of said address ROM; and a judgement display operated in response to an output of said comparator.
a clock generator having an input coupled to said output of said wave shaping circuit and an output coupled to clock inputs of said BPS-to-NRZ converter and said serial-to-parallel convertor; a low-pass filter having an input coupled to said output of said signal detector; a latch control circuit having an input coupled to an output of said low-pass filter; a data lactch having a data input coupled to an output of said serial-to-parallel converter and a clock input coupled to an output of said latch control circuit; and monitor means coupled to an output of said data latch; and wherein said comparing means comprises a comparator having a first input port coupled to an output of said data latch; a selector switch having outputs coupled to address inputs of said data ROM; an address ROM
having address inputs coupled to said outputs of said selector switch; an isolation buffer having an input coupled to an output of said address ROM; and a judgement display operated in response to an output of said comparator.
3. The passive data monitor of claim 2 further comprising a front panel; a first connector mounted on said front panel coupled to said high side terminal of said signal splitter;
a second connector mounted on said front panel coupled to said output terminal of said signal splitter; and an address multiple pin connector mounted on said front panel, pins of said address multiple pin connector being coupled to outputs of said isola-tion buffer; and said selector switch and said monitor means being mounted on said front panel.
a second connector mounted on said front panel coupled to said output terminal of said signal splitter; and an address multiple pin connector mounted on said front panel, pins of said address multiple pin connector being coupled to outputs of said isola-tion buffer; and said selector switch and said monitor means being mounted on said front panel.
4. The passive data monitor of claim 3 wherein said judgement display in said monitor comprises LED's.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP73584/80 | 1980-05-30 | ||
| JP7358480A JPS56169481A (en) | 1980-05-30 | 1980-05-30 | Inspection signal analyzer in catv system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1161544A true CA1161544A (en) | 1984-01-31 |
Family
ID=13522494
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000378441A Expired CA1161544A (en) | 1980-05-30 | 1981-05-27 | Passive data monitor for use with polling pattern generator in catv system |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US4365267A (en) |
| JP (1) | JPS56169481A (en) |
| CA (1) | CA1161544A (en) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56169482A (en) * | 1980-05-30 | 1981-12-26 | Pioneer Electronic Corp | Test system for terminal device in catv system |
| US4450481A (en) * | 1981-08-25 | 1984-05-22 | E-Com Corporation | Tamper-resistant, expandable communications system |
| US4965825A (en) | 1981-11-03 | 1990-10-23 | The Personalized Mass Media Corporation | Signal processing apparatus and methods |
| US7831204B1 (en) | 1981-11-03 | 2010-11-09 | Personalized Media Communications, Llc | Signal processing apparatus and methods |
| USRE47642E1 (en) | 1981-11-03 | 2019-10-08 | Personalized Media Communications LLC | Signal processing apparatus and methods |
| US5053883A (en) * | 1988-12-23 | 1991-10-01 | Scientific-Atlanta, Inc. | Terminal polling method |
| US4994908A (en) * | 1988-12-23 | 1991-02-19 | Scientific-Atlanta, Inc. | Interactive room status/time information system |
| US5093786A (en) * | 1989-01-27 | 1992-03-03 | Fleetwood Furniture Company, Inc. | Remote response system |
| US5130983A (en) * | 1990-03-27 | 1992-07-14 | Heffner Iii Horace W | Method of polling to determine service needs and the like |
| US5724357A (en) * | 1992-01-28 | 1998-03-03 | Fleetwood Group, Inc. | Remote response system and data transfer protocol |
| US6021119A (en) * | 1994-06-24 | 2000-02-01 | Fleetwood Group, Inc. | Multiple site interactive response system |
| US20020002709A1 (en) * | 2000-03-28 | 2002-01-03 | Young-Sang An | Method and system for transmitting multimedia data with downstream data transfer over local TV broadcasting channel and for receiving request with upstream data transfer over another channel |
| GB2425442B (en) | 2002-08-15 | 2007-03-21 | Iml Ltd | Translation System |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3997718A (en) * | 1973-02-01 | 1976-12-14 | The Magnavox Company | Premium interactive communication system |
| JPS51115718A (en) * | 1975-02-24 | 1976-10-12 | Pioneer Electronic Corp | Bi-directional catv system |
| US4058829A (en) * | 1976-08-13 | 1977-11-15 | Control Data Corporation | TV monitor |
| US4107734A (en) * | 1977-01-31 | 1978-08-15 | R. D. Percy & Company | Television viewer reaction determining system |
-
1980
- 1980-05-30 JP JP7358480A patent/JPS56169481A/en active Pending
-
1981
- 1981-05-27 US US06/267,508 patent/US4365267A/en not_active Expired - Lifetime
- 1981-05-27 CA CA000378441A patent/CA1161544A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| US4365267A (en) | 1982-12-21 |
| JPS56169481A (en) | 1981-12-26 |
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Legal Events
| Date | Code | Title | Description |
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| MKEX | Expiry |