CA1167575A - Time slot multiple circuit for the selective establishment of connections in a t.d.m. digital telecommunications system - Google Patents
Time slot multiple circuit for the selective establishment of connections in a t.d.m. digital telecommunications systemInfo
- Publication number
- CA1167575A CA1167575A CA000358830A CA358830A CA1167575A CA 1167575 A CA1167575 A CA 1167575A CA 000358830 A CA000358830 A CA 000358830A CA 358830 A CA358830 A CA 358830A CA 1167575 A CA1167575 A CA 1167575A
- Authority
- CA
- Canada
- Prior art keywords
- time slot
- address
- store
- addresses
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/50—Circuit switching systems, i.e. systems in which the path is physically permanent during the communication
- H04L12/52—Circuit switching systems, i.e. systems in which the path is physically permanent during the communication using time division techniques
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
- H04Q11/08—Time only switching
Abstract
ABSTRACT OF THE INVENTION
"A TIME SLOT MULTIPLE CIRCUIT FOR THE SELECTIVE
ESTABLISHMENT OF CONNECTIONS IN A T.D.M. DIGITAL
TELECOMMUNICATIONS SYSTEM"
Summary Incoming channel signals, which may occupy more than one time slot per t.d.m. frame, are t.d.m. multiplexed (MUX) and stored cyclically in a signal store (SPS). Connections are established between incoming and outgoing channels by means of associations between signal store addresses and outgoing channel time slots on a t.d.m. trunk line (AML).
These associations are stored in a control store (STS) which is addressed cyclically by means of a counter (ZLZ). To write the associations into the control store an address register produces the associated addresses on instructions from a superordinate device. To minimise the operating time of the superordinate device when a connection involves more than one time slot per t.d.m. frame, one pair of associated addresses is arranged to produce automatically all the associated addresses required to switch signals from an incoming channel time slot to the associated outgoing channel time slot. Since the channel time slots are equi-spaced, a signal indicative of the number of transmission rate (number of time slots per frame) can be used to cause a comparator for triggering write-in into the control store to simulate more than one address per frame by disregarding one or more highest significant digits in the comparison. Alternatively the transmission rate indication may be used to substitute one or more highest significant digits or the count of a counter (ZLZ) for the corresponding digits of addresses received from the address register.
(Fig. 2)
"A TIME SLOT MULTIPLE CIRCUIT FOR THE SELECTIVE
ESTABLISHMENT OF CONNECTIONS IN A T.D.M. DIGITAL
TELECOMMUNICATIONS SYSTEM"
Summary Incoming channel signals, which may occupy more than one time slot per t.d.m. frame, are t.d.m. multiplexed (MUX) and stored cyclically in a signal store (SPS). Connections are established between incoming and outgoing channels by means of associations between signal store addresses and outgoing channel time slots on a t.d.m. trunk line (AML).
These associations are stored in a control store (STS) which is addressed cyclically by means of a counter (ZLZ). To write the associations into the control store an address register produces the associated addresses on instructions from a superordinate device. To minimise the operating time of the superordinate device when a connection involves more than one time slot per t.d.m. frame, one pair of associated addresses is arranged to produce automatically all the associated addresses required to switch signals from an incoming channel time slot to the associated outgoing channel time slot. Since the channel time slots are equi-spaced, a signal indicative of the number of transmission rate (number of time slots per frame) can be used to cause a comparator for triggering write-in into the control store to simulate more than one address per frame by disregarding one or more highest significant digits in the comparison. Alternatively the transmission rate indication may be used to substitute one or more highest significant digits or the count of a counter (ZLZ) for the corresponding digits of addresses received from the address register.
(Fig. 2)
Description
The invention relates to a time slot multiple circuit for the selective establishment of connections in a t.d.m. digital telecommunications system for transmltting digital, in particular delta modulated, communications signals which are transmitted in time channels governed by different transmission bit rates, those channels operating at a whole number of times a basic transmission bit rate having a number of equi-spaced time slots per pulse frame equal to the whole number.
In communications exchange and transmission systems equipped with communications channels of a given bandwidth and bit rate, it is generally known to carry out transmission ~ia transmission channels for communications signals of a large bandwidth and bit rate by combining an appropriate plurality of individual channels.
Devices for switching digital t.d.m. signals contain not only coupling devices for space-division switching, but also devices by means of which communications signals, ~7hich occupy a given time channel ~time slot) on an incoming feeder multiplex line within the pulse frame on which the multiplex system is based, are brought into a different time slot within the pulse frame on an outgoing trunk multiplex line~ A device of ~his kind is referred to as a time slot multiple circuit.
It normally comprises a buffer store which is referred to herein as a signal store and into which the communications signals of a complete pulse frame of the feeder multiplex line are input preferably in cyclic fashion, and from which they are output in a generally different sequence which corresponds to their time sequence within the pulse frame of the trunk multiplex line. The output (read-out) of the signal store is effected by means of a control store which, under each address characteristic of the time slot of a communications signal on the trunk multiplex line, stores the associated (for a given telecommunications connection) address of the signal store which characterises the time slot of the same communications signal (involved in the given connection) on the feeder multiplex line.
This control store is driven in cyclic fashion by means of a time slot counter and by appropriate addressing of the signal store produces the sequence in which the stored communications signals are read out to the trunk multiplex line.
The stored contents of a storage cell o_ the control store, i.e. the signal store address entered under an address of the control store, does not undergo any change for the duration of the relevant connection. Thus the control store maintains the assignment, corresponding to the relevant selected connection establishment, between incoming time channel and outgoing time channel for the duration Or the connection. Therefore the contxol store is frequently also referred to as the "holding store".
The lnput of signal store addresses into the contrvl or holding store is effected by means of a superordinate control device in accoxdance with an appropriate path hunting or determining procedure.
The control and signal store addresses which are output from the superordinate control device and which are to be assigned to one another in accordance with the connection which i5 to be established, are input into address registers which form part of a setting-up command register~ A flow control unit serves to output the signal store addresses from this register under the appropriate control store addresses and input these into the controlstore.
If a time slot multiple circuit of the type described above is to serve to establish connections involving wide-ba~`communications signals, (i.e. communications signals (multiple-slot channels~ whose bit rate is a whole number times a ~asic bit rate corresponding to that of one of the time channels the swi~ching procedure) which include the writing in of a signal store address into the control store under the appropriate control store address,the latter operation must be repeated with a fre~uency corresponding to said whole number. This entails a corresponding load on the super-ordinate control device which, in exchange equipment of the type in question, generally consists of a computer.
German specification No. OS 25 58 59g discloses a circuit arrangement for switching through PCM woxds with different bit repetition frequencies, in which the addresses of the sub-channels, which are assembled in accordance with predetermined interleaving plans, are written into a read only memory (ROM) which serves to address the signal store.
This ROM contains the full addresses of all the channels and requires a correspondingly high storage capacity.
A further developme~t of this known circuit arrange-ment is described in Gerrnan specification OS 28 14 415 in which the associated addresses for channel time slots which together form a multiple-slot communications channel, are derived independently. This is efIected with the aid of a ROM which contains code words which characterise the combinations of the individual, different bit rates and which act upon the control store via suitable decoding means in order to produce the channel time slot addresses which are assigned to one another in accorda~ce with the predetermined interleaving plans.
It is an aim of this invention to provide a time slot multiple circuit which can produce automatically the associatic~s between outgoing channel time slots and signal store addresses, which are required for establishing connections between multiple-slot communications channels, from a single given association between an outgoing channel time slot and a signal store address with the low outlay and avoiding repeated use of a superordinate control device.
According to this inven-tion there is providedJ in a time division multiplex system for the through-coupling of digital communications signals, said communications signals being transmitted in time channels with bit rates which are multiples of the frame rate by 2n~ where n is a positive integer, and wherein said communications signals are made up of digital character elements equally spaced within each frame, said time divisi.on multiplex sys-tem having an incoming multiplex line and an outgoing multiplex line, a sig-nal store into which communications signals are cyclically read from said in-coming multiplex line, wherein the communications signals of a channel having a multiple bit rate occupy a plurality of separate memory cells, a control store for cyclically addressing said signal store for furnishing addresses to said signal store for the read out of communications signals from said signal store to said outgoing multiplex line, a time slot counter for cycling said control store, and an address register for receiving and storing an associated pair of addresses for said control store and said signal store which are allo-cated to each other, a time slot multiplex unit, comprising; a storage device for storing data representative of a bit rate; a logic circuit having a first set of inputs connected to the highest order outputs of said time slot counter and a second~set of inputs connected to a plurality of bits of one of the addresses stored in said address regi$ter; and means for connecting an output of said storage device to said logic circuit as a control input, said logic circuit being responsive to said bit rate representing data for generating a plurality of addresses corresponding to time slots which include a time slot represented by address data stored in said address register and a plurality of other time slots, all of said time slots being equally spaced and to~aling said multiple; whereby the plurality of addresses required for storage of data in said controlstore for said multiple bit rate are generated automatic-3 ~ ~7~
ally in succession from a single such address in said address register during cycling of saicl time slo-t counter.
Preferably said control store addressing means comprises a time slot counter arranged to pro~ide in turn each address in the control store, a comparator being pro~idecl - 6a _ 7 ~ ~ ~
for comparing the address output signal from the time slot counter with a control store address signal corresponding to an outgoing channel time slo~ and provided by the address register, which is also arranged to supply a signal store address associated with the outgoing channel time slot and to be written into the corresponding control store address in dependence on the comparator providing an output signal indicating identity.
Advantageously said comparator includes a logic circuit arrangement for comparing corresponding digits of the two address signals and arranged to determine the comparison regardless of the comparison result for one or more of the highest signiicant digits in dependence on the transmission rate indication when the latter is a whole number times a basi~c transmission rate, so that addresses giving rise to a first comparison identity give rise to a recurrence of the identity at regular counting intervals of the time slot counter when one or more of the highest significant digits are disregarded.
Thus the time slot counter is additionally used for the cyclic addressing of the control store as a corlponent of an address generator for automatically producing those addresses or address components which are not contained in the address register.
Also, in a system using binary addresses, due ~o the equidistance in time slot count between the "sub-channels"
which form a time channel possessing a higher transmission rate than the basic rate o~ly specific binary digits of the binary numbers which represent the channel addresses (and thus the store addresses) and which are stored in the relevant address registers, produce comparisons which are affected by a change of address: in a pulse frame in which communications signals are interleaved, for example, in 1024 channel time slots, the ordinal numbers of the individual channel time slots, i.e. the channel time slot addresses, are designated by a 10-digit binary number. If a time channel possessing a higher transmission rate than the basic rate is now to be composed from for example two equi-spaced channel time slots of a pulse frame of this kind, the difference between the ordinal numbers (addresses) of these two channel time slots possesses the value 512. This means that the addresses of these two channel time slots are identical to one another in all their binary digits exceptin~ that which possesses the highest digit value ~i.e. the highest significant digit). If a time channel having a hi~her trans-mi~sion rate than the basic rate is to be assembled from ~our equi-spaced channel time slots, the address difference has the value 256. This means that the rele~ant addresses are identical in all their binar~- digits excepting the t~70 highest significant binary digits. Similar considerations apply to the addresses of eight channel time slots arranged to be equi-spaced within the pulse frame so as to form a communications ~ ~ $ ~
channel of a higher transmission rate than the basic rate, in which case the time slots differ from one another only in their three highest significant binary digits.
Alternatively said control store addressing means comprises a time slot count,erarranged to provide in turn each address in the control store, and the writing-in means includes switching means controlled by means of said-.txansmission rate indication and arranged to receive one or more of the highest significant digits of each of the control store addresses produced, in turn, by the time slot counterr and to receive the corresponding digits of a control store address produced as part of the association provided by the address register, the switching means being arranged to select as output, in dependence on the transmission '15 rate indication, a number of the o:ne or more highest significant digits, that have the highest signiicance, of the time slot counter address output signal instead of the correspondiny digits of the control stor~ address, so that equi-spaced control store addresses are produced as writing-in locations for signal store addresses of signals of the same incoming - channel.
Conveniently, for either control store address selection arrangement, said signal store is addressed cyclically to receive the incoming signais and said writing-in ~eans includes switching means controlled by means of said transmission rate indication and arranged to receive as inputs the one or more _g_ i ~7~7~
highest significant digits of the signal store address supplied by the address register and the one or more highest significant digits of the time slot counter address output signal, the swi.tching means being arranged to select as output, 5 - in dependence on the transmission rate indication, a number of the one or more highest significant digits, that have the highest significance, of the time slot counter address output signal instead of the corresponding digits of the signal store address, so that equi-spaced signal store addresses are written into the control store at correspondingly equi-spaced control store addresses.
Embodiments of this invention will now be described, by way of example, with reference to the accom~anying drawings in which:-Fig. 1 is a schematic diagram of a time slot multiple circuit for the selective establishment of connections in a t.d.m. digital telecommunications system;
Fig. 2 is a block circuit diagram of a time.slot multiple circuit embodying this invention;
Fig. 3 is a set of graphs illustrating the time positions of the diyital character elemer.ts on the individual incoming lines connected to the time slot multiple circui.t and their time-wise interleaving on a t.d.m. multiplex line;
Fig. 4 is a block circuit diagram of a first embodiment o~ port~on of the circuit shown in Fig. 2;
~ ~7~7~
Fig. 5 is a block circuit diagram of a comparator employed in the circuit sho~m in Fig. 4;
Fig. 6 is a block circuit diagram of an arrangement for the production of signal store addresses in the circuit portion shown in Fig. 4; and Fig. 7 is a block circuit diagram of a second embodiment of the same portion of the ci.rcuit shown in Fig. 2 as that to which FigO 4 relates.
Referring to Fig. 1, a time slot multi.ple circuit ZhV is connected to bidirectional lines L0 to L15. The time slot multiple circuit ZLV serves to establish connections between channels carrying the digital communications signals which occur on the bidirectional lines L0 to L15 and which are assumed to occupy channel time slots as in,~icated in the upper part of Fig. 3: thus :Eor examp~e a digital communications signal having a transmission bit rate of 8 Kbit/s (hereinafter referred to as "the basic rate"~ occurs on the line L0, a communications signal having a transmission bit rate 16 Kbit/s occurs on the line Ll, a communications signal having a transmission bit rate 32 Kbit/s occurs on the line L2, and a communications signal having a transmission bit rate 64 Kbit/s occurs on the line L3.
Referring to Fig. 2 in such a time slot multiple clrcuit ZL~ embodying this invention, the incoming channels on the lines L0 to L15 are connected to a multiplexer MU~ which interleaves the communications signals incoming on these 7.~3~
channels in such manner that they occupy channel time slots as indicated in the lower part of Fig. 3 on an associated feeder multiplex line ZML. The feeder multiplex line leads to a signal store SPS into which the communications signals of a pulse frame - which in the illustrated example comprises 1024 separate channel time slots - are input, preerably in cyclic fashion.
The time sequence in which the communications signals are OlltpUt from the signal store SPS to an outgoing trunk multiplex line AML, i.e. corresponding to the time shift of the individual time channels which represents the actual switching operation of the time slot multiple circuit ZLV, is subject to the control of a control store STS which is addressed in cyclic fashion by a time slot counter ZLZ.
The control store STS serves to store associations between outgoing (trunk line) channel time slots and signal store addresses under which are stored signals from incoming channels to be connected to the relevant respective outgoing channels provided by the outgoing channel time slots. In the 20 . embodiment described here, under addresses which characterise the ordinal number of a channel time slot on the tr~nk multiplex line ZML, this control store STS stores signal store addresses which characterise the time slot of the relevant time channels on the feeder multiplex line P~.
However, it would be readily possible to make the control store addresses correspond to the signal store.addresses and i ~ s to store the outgoing channel time slot addresses in the control store in appropriate associa,tion with the signal store addresses~
The items of data (e.g. signal store addresses) which are to be written into the control store STS are obtained from a superordinate control device (not shown) and repreSeIlt the result of a path hunting or determining procedure. The signals occurring on the trunk multiplex line AML are distribu ed between the outgoing channels on the lines L0 to L15 by means of a demultiplexer DEM.
The (time-wise) switching of the incoming communications signals, or example on the lines Ll,L2 and L3, which possess a higher transmission bit rate than the basic rate of the signals on the line L0, and which are composed of a plurality of individual channel time slots, requires that an appropriate number or address associations be entered into the control store S~S. In order to avoid a correspondingly ~requent use of the superordinate control device, most of the associated control store addresses and signal store addresses are to be produced automatically.
Referring to Fig. 4, there is shown a first arrangement for the automatic production of the associated con~rol store and signal store addresses of a communications connection involving a higher transmission bit rate than the basic rate, which is also referred to herein as a wide-band connection.
An address register comprising register Rey is provided into ~ ~7~7~, which the associated control store addresses and signal store addresses of a connection are written by means of the superordinate control device using setting-up data ED.
The register zones corresponding to the two types of address are referenced STS~Adr and SPS-Adr. In addition the register Reg possesses a store zone which is designated KSP and into which is written a three digit identi~ication signal indicating whe'_her the connection which is to be switched through involves a single channel ti~.e slot per frame or a plurality of channel time slots per frame and also indicates the number of channel time slots per frame (transmission rate) which the coImection involves. The outputs of the register zone STS-Adr are connected to a comparator ZLV in which the register entry is compared with the count of the time slot counter ZLZ and in the event of identity a comparison pulse VI is emitted to a flow control unit AS which, at an appropriate time in the store cycle, supplies a write pulse SI to the control store STS.
Referring to Fig. 5, the comparator ZLV comprises coincidence gates K0 to K9, OR-gates 01 to 03 and one AND-gate Ul. The coincidence gates K7 to K9 logic-link those outputs of the register zone STS-Adr and of the time slot counter ZLZ which are assigned to the highest significant binary di~its of the addresses being compared. The outputs of these coincidence gates K7 to K9 are connected to respective first inputs of the OR-gates 01,02 and 03. The other inouts 3 ~7~7~
of these OR-gates are connected to outputs of the register component KSP which contains the three digit identification (transmission rate indication). The three binary digits of the identification have the Eollowing significance:
000 1 channel time slot per frame 100 2 channel time slots per frame 110 4 channel time slots per frame 111 8 channel time slots per frame The comparator illustrated in Fig. 5 operates as follows: if the identification has the value 000, the AND-gate Ul supplies a comparator pulse to the flow control unit A5 (Fig. 4) when, and only when the count of the time slot counter ZLZ is identical in respect of all binary digits with the control store address stored in the register component STS-Adr.
If the identification has the value 100, the coincidence gate K9 assigned to the highest significant binary digit is switched inoperative so that regardless of the value entered in the register (0 or 1), coincidence is simulated whenever the count of the ti~e slot counter Z~Z is identical in respect of all the other binary digits with the register entry.
Accordingly two comparator pulses are produced per frame in equi-spaced channel time slots, which corresponds to two eaui-spaced control store addresses.
When the identification has the value 110, both the coincidence gate K9 and the coincidence gate X8 are switched i ]~ 7 ~
inoperative so that comparator pulses VI (and thus write pulses SI) are produced in four equi-spaced time slots.
Similarly the identification value 111 leads to the production of eight comparator and write pulses which are equi-spaced in time.
Referring to Fig. 6, there is shown an arrangement for the production of the signal store addresses which are associated with the different ~ontrol store addresses of a wide-band connection and which are likewise equi-spaced.
The arrangement comprises three switch-over devices M7,M8 and M9 which are assigned to the highest significant binary digits of the signal store addresses and which are designed as 1:2 multiplexers. These switch-over devices can be reversed by the outputs of the register component KSP which contains the identification in such a manner that either the relevant digit outputs of the register component SPS-Adr or the like-designated digit outputs of the time slot counter ZLZ are connected to the respective corresponding wires of ~ddress line AL which leads to the control store STS. This means that, in dependence upon the identification stored in the register component KSP, one,two, or three of the wires of the address line AL which represent the highest significant binary digits may be controlled by output signals fro~ the time slot counter ZLZ with the result that a corresponding number of equi-spaced signal store addresses are switched through to the data inputs of the control store STS.
l ~ & 7 ~
Referring to Fig. 7, there is shown a second arrange-ment for the automatic production of the associated control store and ~igna] store addresses of a communications conneclion involving a higher transmission rate than the basic rate.
This differs from the circuit illustrated in Fig. 4 only in that the control store addresses - similarly to the signal store addresses in the case of t~e circuit shown in Fig. 6 -are likewise produced on an address bus for the control store with the aid of a switch-over device MlO. The switch-over device M10 serves to switch over the addresses both for the write~in state and the read-out state.
In all the embodiments described above, the control store addresses and associated speech store addresses, which correspond to a wide-band connection, are automatically derived from one single predetermined pair of such addresses so that the superordinate control device is used for the establishment of these wide-band connections onlv once in respect o each connection direction.
In communications exchange and transmission systems equipped with communications channels of a given bandwidth and bit rate, it is generally known to carry out transmission ~ia transmission channels for communications signals of a large bandwidth and bit rate by combining an appropriate plurality of individual channels.
Devices for switching digital t.d.m. signals contain not only coupling devices for space-division switching, but also devices by means of which communications signals, ~7hich occupy a given time channel ~time slot) on an incoming feeder multiplex line within the pulse frame on which the multiplex system is based, are brought into a different time slot within the pulse frame on an outgoing trunk multiplex line~ A device of ~his kind is referred to as a time slot multiple circuit.
It normally comprises a buffer store which is referred to herein as a signal store and into which the communications signals of a complete pulse frame of the feeder multiplex line are input preferably in cyclic fashion, and from which they are output in a generally different sequence which corresponds to their time sequence within the pulse frame of the trunk multiplex line. The output (read-out) of the signal store is effected by means of a control store which, under each address characteristic of the time slot of a communications signal on the trunk multiplex line, stores the associated (for a given telecommunications connection) address of the signal store which characterises the time slot of the same communications signal (involved in the given connection) on the feeder multiplex line.
This control store is driven in cyclic fashion by means of a time slot counter and by appropriate addressing of the signal store produces the sequence in which the stored communications signals are read out to the trunk multiplex line.
The stored contents of a storage cell o_ the control store, i.e. the signal store address entered under an address of the control store, does not undergo any change for the duration of the relevant connection. Thus the control store maintains the assignment, corresponding to the relevant selected connection establishment, between incoming time channel and outgoing time channel for the duration Or the connection. Therefore the contxol store is frequently also referred to as the "holding store".
The lnput of signal store addresses into the contrvl or holding store is effected by means of a superordinate control device in accoxdance with an appropriate path hunting or determining procedure.
The control and signal store addresses which are output from the superordinate control device and which are to be assigned to one another in accordance with the connection which i5 to be established, are input into address registers which form part of a setting-up command register~ A flow control unit serves to output the signal store addresses from this register under the appropriate control store addresses and input these into the controlstore.
If a time slot multiple circuit of the type described above is to serve to establish connections involving wide-ba~`communications signals, (i.e. communications signals (multiple-slot channels~ whose bit rate is a whole number times a ~asic bit rate corresponding to that of one of the time channels the swi~ching procedure) which include the writing in of a signal store address into the control store under the appropriate control store address,the latter operation must be repeated with a fre~uency corresponding to said whole number. This entails a corresponding load on the super-ordinate control device which, in exchange equipment of the type in question, generally consists of a computer.
German specification No. OS 25 58 59g discloses a circuit arrangement for switching through PCM woxds with different bit repetition frequencies, in which the addresses of the sub-channels, which are assembled in accordance with predetermined interleaving plans, are written into a read only memory (ROM) which serves to address the signal store.
This ROM contains the full addresses of all the channels and requires a correspondingly high storage capacity.
A further developme~t of this known circuit arrange-ment is described in Gerrnan specification OS 28 14 415 in which the associated addresses for channel time slots which together form a multiple-slot communications channel, are derived independently. This is efIected with the aid of a ROM which contains code words which characterise the combinations of the individual, different bit rates and which act upon the control store via suitable decoding means in order to produce the channel time slot addresses which are assigned to one another in accorda~ce with the predetermined interleaving plans.
It is an aim of this invention to provide a time slot multiple circuit which can produce automatically the associatic~s between outgoing channel time slots and signal store addresses, which are required for establishing connections between multiple-slot communications channels, from a single given association between an outgoing channel time slot and a signal store address with the low outlay and avoiding repeated use of a superordinate control device.
According to this inven-tion there is providedJ in a time division multiplex system for the through-coupling of digital communications signals, said communications signals being transmitted in time channels with bit rates which are multiples of the frame rate by 2n~ where n is a positive integer, and wherein said communications signals are made up of digital character elements equally spaced within each frame, said time divisi.on multiplex sys-tem having an incoming multiplex line and an outgoing multiplex line, a sig-nal store into which communications signals are cyclically read from said in-coming multiplex line, wherein the communications signals of a channel having a multiple bit rate occupy a plurality of separate memory cells, a control store for cyclically addressing said signal store for furnishing addresses to said signal store for the read out of communications signals from said signal store to said outgoing multiplex line, a time slot counter for cycling said control store, and an address register for receiving and storing an associated pair of addresses for said control store and said signal store which are allo-cated to each other, a time slot multiplex unit, comprising; a storage device for storing data representative of a bit rate; a logic circuit having a first set of inputs connected to the highest order outputs of said time slot counter and a second~set of inputs connected to a plurality of bits of one of the addresses stored in said address regi$ter; and means for connecting an output of said storage device to said logic circuit as a control input, said logic circuit being responsive to said bit rate representing data for generating a plurality of addresses corresponding to time slots which include a time slot represented by address data stored in said address register and a plurality of other time slots, all of said time slots being equally spaced and to~aling said multiple; whereby the plurality of addresses required for storage of data in said controlstore for said multiple bit rate are generated automatic-3 ~ ~7~
ally in succession from a single such address in said address register during cycling of saicl time slo-t counter.
Preferably said control store addressing means comprises a time slot counter arranged to pro~ide in turn each address in the control store, a comparator being pro~idecl - 6a _ 7 ~ ~ ~
for comparing the address output signal from the time slot counter with a control store address signal corresponding to an outgoing channel time slo~ and provided by the address register, which is also arranged to supply a signal store address associated with the outgoing channel time slot and to be written into the corresponding control store address in dependence on the comparator providing an output signal indicating identity.
Advantageously said comparator includes a logic circuit arrangement for comparing corresponding digits of the two address signals and arranged to determine the comparison regardless of the comparison result for one or more of the highest signiicant digits in dependence on the transmission rate indication when the latter is a whole number times a basi~c transmission rate, so that addresses giving rise to a first comparison identity give rise to a recurrence of the identity at regular counting intervals of the time slot counter when one or more of the highest significant digits are disregarded.
Thus the time slot counter is additionally used for the cyclic addressing of the control store as a corlponent of an address generator for automatically producing those addresses or address components which are not contained in the address register.
Also, in a system using binary addresses, due ~o the equidistance in time slot count between the "sub-channels"
which form a time channel possessing a higher transmission rate than the basic rate o~ly specific binary digits of the binary numbers which represent the channel addresses (and thus the store addresses) and which are stored in the relevant address registers, produce comparisons which are affected by a change of address: in a pulse frame in which communications signals are interleaved, for example, in 1024 channel time slots, the ordinal numbers of the individual channel time slots, i.e. the channel time slot addresses, are designated by a 10-digit binary number. If a time channel possessing a higher transmission rate than the basic rate is now to be composed from for example two equi-spaced channel time slots of a pulse frame of this kind, the difference between the ordinal numbers (addresses) of these two channel time slots possesses the value 512. This means that the addresses of these two channel time slots are identical to one another in all their binary digits exceptin~ that which possesses the highest digit value ~i.e. the highest significant digit). If a time channel having a hi~her trans-mi~sion rate than the basic rate is to be assembled from ~our equi-spaced channel time slots, the address difference has the value 256. This means that the rele~ant addresses are identical in all their binar~- digits excepting the t~70 highest significant binary digits. Similar considerations apply to the addresses of eight channel time slots arranged to be equi-spaced within the pulse frame so as to form a communications ~ ~ $ ~
channel of a higher transmission rate than the basic rate, in which case the time slots differ from one another only in their three highest significant binary digits.
Alternatively said control store addressing means comprises a time slot count,erarranged to provide in turn each address in the control store, and the writing-in means includes switching means controlled by means of said-.txansmission rate indication and arranged to receive one or more of the highest significant digits of each of the control store addresses produced, in turn, by the time slot counterr and to receive the corresponding digits of a control store address produced as part of the association provided by the address register, the switching means being arranged to select as output, in dependence on the transmission '15 rate indication, a number of the o:ne or more highest significant digits, that have the highest signiicance, of the time slot counter address output signal instead of the correspondiny digits of the control stor~ address, so that equi-spaced control store addresses are produced as writing-in locations for signal store addresses of signals of the same incoming - channel.
Conveniently, for either control store address selection arrangement, said signal store is addressed cyclically to receive the incoming signais and said writing-in ~eans includes switching means controlled by means of said transmission rate indication and arranged to receive as inputs the one or more _g_ i ~7~7~
highest significant digits of the signal store address supplied by the address register and the one or more highest significant digits of the time slot counter address output signal, the swi.tching means being arranged to select as output, 5 - in dependence on the transmission rate indication, a number of the one or more highest significant digits, that have the highest significance, of the time slot counter address output signal instead of the corresponding digits of the signal store address, so that equi-spaced signal store addresses are written into the control store at correspondingly equi-spaced control store addresses.
Embodiments of this invention will now be described, by way of example, with reference to the accom~anying drawings in which:-Fig. 1 is a schematic diagram of a time slot multiple circuit for the selective establishment of connections in a t.d.m. digital telecommunications system;
Fig. 2 is a block circuit diagram of a time.slot multiple circuit embodying this invention;
Fig. 3 is a set of graphs illustrating the time positions of the diyital character elemer.ts on the individual incoming lines connected to the time slot multiple circui.t and their time-wise interleaving on a t.d.m. multiplex line;
Fig. 4 is a block circuit diagram of a first embodiment o~ port~on of the circuit shown in Fig. 2;
~ ~7~7~
Fig. 5 is a block circuit diagram of a comparator employed in the circuit sho~m in Fig. 4;
Fig. 6 is a block circuit diagram of an arrangement for the production of signal store addresses in the circuit portion shown in Fig. 4; and Fig. 7 is a block circuit diagram of a second embodiment of the same portion of the ci.rcuit shown in Fig. 2 as that to which FigO 4 relates.
Referring to Fig. 1, a time slot multi.ple circuit ZhV is connected to bidirectional lines L0 to L15. The time slot multiple circuit ZLV serves to establish connections between channels carrying the digital communications signals which occur on the bidirectional lines L0 to L15 and which are assumed to occupy channel time slots as in,~icated in the upper part of Fig. 3: thus :Eor examp~e a digital communications signal having a transmission bit rate of 8 Kbit/s (hereinafter referred to as "the basic rate"~ occurs on the line L0, a communications signal having a transmission bit rate 16 Kbit/s occurs on the line Ll, a communications signal having a transmission bit rate 32 Kbit/s occurs on the line L2, and a communications signal having a transmission bit rate 64 Kbit/s occurs on the line L3.
Referring to Fig. 2 in such a time slot multiple clrcuit ZL~ embodying this invention, the incoming channels on the lines L0 to L15 are connected to a multiplexer MU~ which interleaves the communications signals incoming on these 7.~3~
channels in such manner that they occupy channel time slots as indicated in the lower part of Fig. 3 on an associated feeder multiplex line ZML. The feeder multiplex line leads to a signal store SPS into which the communications signals of a pulse frame - which in the illustrated example comprises 1024 separate channel time slots - are input, preerably in cyclic fashion.
The time sequence in which the communications signals are OlltpUt from the signal store SPS to an outgoing trunk multiplex line AML, i.e. corresponding to the time shift of the individual time channels which represents the actual switching operation of the time slot multiple circuit ZLV, is subject to the control of a control store STS which is addressed in cyclic fashion by a time slot counter ZLZ.
The control store STS serves to store associations between outgoing (trunk line) channel time slots and signal store addresses under which are stored signals from incoming channels to be connected to the relevant respective outgoing channels provided by the outgoing channel time slots. In the 20 . embodiment described here, under addresses which characterise the ordinal number of a channel time slot on the tr~nk multiplex line ZML, this control store STS stores signal store addresses which characterise the time slot of the relevant time channels on the feeder multiplex line P~.
However, it would be readily possible to make the control store addresses correspond to the signal store.addresses and i ~ s to store the outgoing channel time slot addresses in the control store in appropriate associa,tion with the signal store addresses~
The items of data (e.g. signal store addresses) which are to be written into the control store STS are obtained from a superordinate control device (not shown) and repreSeIlt the result of a path hunting or determining procedure. The signals occurring on the trunk multiplex line AML are distribu ed between the outgoing channels on the lines L0 to L15 by means of a demultiplexer DEM.
The (time-wise) switching of the incoming communications signals, or example on the lines Ll,L2 and L3, which possess a higher transmission bit rate than the basic rate of the signals on the line L0, and which are composed of a plurality of individual channel time slots, requires that an appropriate number or address associations be entered into the control store S~S. In order to avoid a correspondingly ~requent use of the superordinate control device, most of the associated control store addresses and signal store addresses are to be produced automatically.
Referring to Fig. 4, there is shown a first arrangement for the automatic production of the associated con~rol store and signal store addresses of a communications connection involving a higher transmission bit rate than the basic rate, which is also referred to herein as a wide-band connection.
An address register comprising register Rey is provided into ~ ~7~7~, which the associated control store addresses and signal store addresses of a connection are written by means of the superordinate control device using setting-up data ED.
The register zones corresponding to the two types of address are referenced STS~Adr and SPS-Adr. In addition the register Reg possesses a store zone which is designated KSP and into which is written a three digit identi~ication signal indicating whe'_her the connection which is to be switched through involves a single channel ti~.e slot per frame or a plurality of channel time slots per frame and also indicates the number of channel time slots per frame (transmission rate) which the coImection involves. The outputs of the register zone STS-Adr are connected to a comparator ZLV in which the register entry is compared with the count of the time slot counter ZLZ and in the event of identity a comparison pulse VI is emitted to a flow control unit AS which, at an appropriate time in the store cycle, supplies a write pulse SI to the control store STS.
Referring to Fig. 5, the comparator ZLV comprises coincidence gates K0 to K9, OR-gates 01 to 03 and one AND-gate Ul. The coincidence gates K7 to K9 logic-link those outputs of the register zone STS-Adr and of the time slot counter ZLZ which are assigned to the highest significant binary di~its of the addresses being compared. The outputs of these coincidence gates K7 to K9 are connected to respective first inputs of the OR-gates 01,02 and 03. The other inouts 3 ~7~7~
of these OR-gates are connected to outputs of the register component KSP which contains the three digit identification (transmission rate indication). The three binary digits of the identification have the Eollowing significance:
000 1 channel time slot per frame 100 2 channel time slots per frame 110 4 channel time slots per frame 111 8 channel time slots per frame The comparator illustrated in Fig. 5 operates as follows: if the identification has the value 000, the AND-gate Ul supplies a comparator pulse to the flow control unit A5 (Fig. 4) when, and only when the count of the time slot counter ZLZ is identical in respect of all binary digits with the control store address stored in the register component STS-Adr.
If the identification has the value 100, the coincidence gate K9 assigned to the highest significant binary digit is switched inoperative so that regardless of the value entered in the register (0 or 1), coincidence is simulated whenever the count of the ti~e slot counter Z~Z is identical in respect of all the other binary digits with the register entry.
Accordingly two comparator pulses are produced per frame in equi-spaced channel time slots, which corresponds to two eaui-spaced control store addresses.
When the identification has the value 110, both the coincidence gate K9 and the coincidence gate X8 are switched i ]~ 7 ~
inoperative so that comparator pulses VI (and thus write pulses SI) are produced in four equi-spaced time slots.
Similarly the identification value 111 leads to the production of eight comparator and write pulses which are equi-spaced in time.
Referring to Fig. 6, there is shown an arrangement for the production of the signal store addresses which are associated with the different ~ontrol store addresses of a wide-band connection and which are likewise equi-spaced.
The arrangement comprises three switch-over devices M7,M8 and M9 which are assigned to the highest significant binary digits of the signal store addresses and which are designed as 1:2 multiplexers. These switch-over devices can be reversed by the outputs of the register component KSP which contains the identification in such a manner that either the relevant digit outputs of the register component SPS-Adr or the like-designated digit outputs of the time slot counter ZLZ are connected to the respective corresponding wires of ~ddress line AL which leads to the control store STS. This means that, in dependence upon the identification stored in the register component KSP, one,two, or three of the wires of the address line AL which represent the highest significant binary digits may be controlled by output signals fro~ the time slot counter ZLZ with the result that a corresponding number of equi-spaced signal store addresses are switched through to the data inputs of the control store STS.
l ~ & 7 ~
Referring to Fig. 7, there is shown a second arrange-ment for the automatic production of the associated control store and ~igna] store addresses of a communications conneclion involving a higher transmission rate than the basic rate.
This differs from the circuit illustrated in Fig. 4 only in that the control store addresses - similarly to the signal store addresses in the case of t~e circuit shown in Fig. 6 -are likewise produced on an address bus for the control store with the aid of a switch-over device MlO. The switch-over device M10 serves to switch over the addresses both for the write~in state and the read-out state.
In all the embodiments described above, the control store addresses and associated speech store addresses, which correspond to a wide-band connection, are automatically derived from one single predetermined pair of such addresses so that the superordinate control device is used for the establishment of these wide-band connections onlv once in respect o each connection direction.
Claims (6)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. In a time division multiplex system for the through-coupling of digital communications signals, said communications signals being transmitted in time channels with bit rates which are multiples of the frame rate by 2n, wherein is a positive integer, and wherein said communications signals are made up of digital character elements equally spaced within each frame, said time division multiplex system having an incoming multiplex line and an outgoing multiplex line, a signal store into which communications signals are cyclically read from said incoming multiplex line, wherein the communications signals of a channel having a multiple bit rate occupy a plurality of separate memory ceils, a control store for cyclic-ally addressing said signal store for furnishing addresses to said signal store for the read out of communications signals from said signal store to said out-going multiplex line, a time slot counter for cycling said control store, and an address register for receiving and storing an associated pair of addresses for said control store and said signal store which are allocated to each other, a time slot multiplex unit, comprising; a storage device for storing data repre-sentative of a bit rate; a logic circuit having a first set of inputs connected to the highest order outputs of said time slot counter and a second set of inputs connected to a plurality of bits of one of the addresses stored in said address register; and means for connecting an output of said storage device to said logic circuit as a control input, said logic circuit being responsive to said bit rate representing data for generating a plurality of addresses corresponding to time slots which include a time slot represented by address data stored in said address register and a plurality of other time slots, all of said time slots be-ing equally spaced and totaling said multiple; whereby the plurality of addresses required for storage of data in said control store for said multiple bit rate are generated automatically in succession from a single such address in said address register during cycling of said time slot counter.
2. A system according to claim 1 wherein said time slot counter is arranged to provide in turn each address in the control store, a comparator being provided for comparing the address output signals from the time slot counter with a control store address signal corresponding to an outgoing channel time slot and provided by the address register, which is also arranged to supply a signal store address associated with the outgoing channel time slot and to be written into the corresponding control store address in dependence on the comparator providing an output signal indicating identity.
3. A system according to claim 2 wherein said comparator includes a logic circuit arrangement for comparing corresponding digits of the two address signals and arranged to determine the comparison regardless of the comparison result for one or more of the highest significant digits in dependence on the transmission rate indication when the latter is a whole number times a basic transmission rate, so that addresses giving rise to a first comparison identity give rise to a recurrence of the identity at regular counting intervals of the time slot counter when one or more of the highest significant digits are disregarded.
4. A system according to claim 3 wherein said logic circuit arrangement comprises respective OR gates arranged for receiving as inputs the comparison re-sults for the one or more highest significance digits, other inputs of the respec-tive OR gates being connected to receive digits of the transmission rate indica-tion.
5. A system according to claim 1 wherein said control store addressing means comprises a time slot counter arranged to provide in turn each address in the control store, and the writing-in means includes switching means controlled by means of said transmission rate indication and arranged to receive one or more of the highest significant digits of each of the control store addresses produced, in turn, by the time slot counter, and to receive the corresponding digits of a control store address produced as part of the association provided by the address register, the switching means being arranged to select as output, in dependence on the transmission rate indication, a number of the one or more highest signific-ant digits, that have the highest significance, of the time slot counter address output signal instead of the corresponding digits of the control store address, so that equi-spaced control store addresses are produced as writing-in locations for signal store addresses of signals of the same incoming channel.
6. A system according to any one of claims 3 to 5 wherein said signal store is addressed cyclically to receive the incoming signals and said writing-in means includes switching means controlled by means of said transmission rate indication and arranged to receive as inputs the one or more highest significance digits of the signal store address supplied by the address register and the one or more highest significant digits of the time slot counter address output signal, the switching means being arranged to select as output, in dependence on the transmission rate indication, a number of the one or more highest significant digits, that have the highest significance, of the time slot counter address output signal instead of the corresponding digits of the signal store address, so that equi-spaced signal store addresses are written into the control store at correspondingly equi-spaced control store addresses.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DEP2934379.1 | 1979-08-24 | ||
| DE19792934379 DE2934379A1 (en) | 1979-08-24 | 1979-08-24 | MULTIPLE TIMES FOR A TIME MULTIPLEX SYSTEM FOR THE COUPLING OF DIGITAL, IN PARTICULAR DELTA MODULATED, MESSAGE SIGNALS |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1167575A true CA1167575A (en) | 1984-05-15 |
Family
ID=6079264
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000358830A Expired CA1167575A (en) | 1979-08-24 | 1980-08-22 | Time slot multiple circuit for the selective establishment of connections in a t.d.m. digital telecommunications system |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US4512014A (en) |
| EP (1) | EP0024708B1 (en) |
| JP (1) | JPS5632849A (en) |
| CA (1) | CA1167575A (en) |
| DE (2) | DE2934379A1 (en) |
| IL (1) | IL60899A (en) |
| NO (1) | NO151345C (en) |
Families Citing this family (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3228555A1 (en) * | 1982-07-30 | 1984-02-02 | Siemens AG, 1000 Berlin und 8000 München | CIRCUIT ARRANGEMENT FOR RECORDING AND FORWARDING DATA SIGNALS WITH RELATIVELY HIGH SPEED IN A DATA SWITCHING NETWORK |
| US4570258A (en) * | 1984-02-13 | 1986-02-11 | Wang Laboratories, Inc. | Exchange switch |
| US4656626A (en) * | 1984-12-14 | 1987-04-07 | Itt Corporation | Apparatus and method for providing dynamically assigned switch paths |
| NL8502023A (en) * | 1985-07-15 | 1987-02-02 | Philips Nv | METHOD FOR SWITCHING TIME LOCKS IN A TDM SIGNAL AND APPARATUS FOR PERFORMING THE METHOD |
| US4730305A (en) * | 1986-04-11 | 1988-03-08 | American Telephone And Telegraph Company, At&T Bell Laboratories | Fast assignment technique for use in a switching arrangement |
| FR2623953B1 (en) * | 1987-11-27 | 1992-11-20 | Cit Alcatel | MANAGEMENT UNIT FOR SWITCHING ELEMENT OF DATA TRANSMITTED BY ASYNCHRONOUS TIME MULTIPLEXING |
| US5163149A (en) * | 1988-11-02 | 1992-11-10 | International Business Machines Corporation | Combining switch for reducing accesses to memory and for synchronizing parallel processes |
| JPH0785592B2 (en) * | 1989-01-27 | 1995-09-13 | 富士通株式会社 | Data line switching method in exchange |
| JPH0371791A (en) * | 1989-08-11 | 1991-03-27 | Nec Corp | Time division channel |
| DE4019364A1 (en) * | 1990-06-18 | 1991-12-19 | Philips Patentverwaltung | TIME MULTIPLEX TRANSFER ARRANGEMENT |
| DE4116939A1 (en) * | 1991-05-24 | 1992-11-26 | Standard Elektrik Lorenz Ag | COUPLING PANEL FOR SWITCHING CHANNELS |
| JPH05276584A (en) * | 1991-09-26 | 1993-10-22 | Fujitsu Ltd | Time slot rearrangement device in multiplexer |
| DE19844732A1 (en) | 1998-09-29 | 2000-03-30 | Siemens Ag | Circuit arrangement and method for switching channels in a communication network |
| JP3455474B2 (en) * | 1999-08-27 | 2003-10-14 | 株式会社沖コムテック | Digital switching device and data switching method for the device |
| US6529983B1 (en) | 1999-11-03 | 2003-03-04 | Cisco Technology, Inc. | Group and virtual locking mechanism for inter processor synchronization |
| US6892237B1 (en) * | 2000-03-28 | 2005-05-10 | Cisco Technology, Inc. | Method and apparatus for high-speed parsing of network messages |
| US6505269B1 (en) | 2000-05-16 | 2003-01-07 | Cisco Technology, Inc. | Dynamic addressing mapping to eliminate memory resource contention in a symmetric multiprocessor system |
| DE10109974B4 (en) * | 2001-03-01 | 2006-02-16 | Infineon Technologies Ag | Method and system for digital real-time data processing |
| US6859434B2 (en) * | 2002-10-01 | 2005-02-22 | Comsys Communication & Signal Processing Ltd. | Data transfer scheme in a communications system incorporating multiple processing elements |
| US7492760B1 (en) * | 2003-03-31 | 2009-02-17 | Pmc-Sierra, Inc. | Memory egress self selection architecture |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS534711B2 (en) * | 1973-06-08 | 1978-02-20 | ||
| FR2265227A1 (en) * | 1974-03-22 | 1975-10-17 | Constr Telephoniques | Time multiplex exchange for binarily coded signals - which have different transmission speeds and uses topographic tables |
| FR2296320A1 (en) * | 1974-12-27 | 1976-07-23 | Texier Alain | MULTI-SPEED DIGITAL SWITCHING NETWORK BY MULTIPLEX |
| SE381394B (en) * | 1975-02-14 | 1975-12-01 | Ellemtel Utvecklings Ab | SET AND DEVICE FOR ADDRESSING A COUPLING MEMORY IN A SYNCHRONIC DATA SIGNAL TRANSMISSION STATION |
| SE383674B (en) * | 1975-04-28 | 1976-03-22 | Ellemtel Utvecklings Ab | SET AND DEVICE FOR ADDRESSING A BUFFER MEMORY IN A SYMCHRONA DATA SIGNAL TRANSMISSION STATION |
| FR2386952A1 (en) * | 1977-04-05 | 1978-11-03 | Telecommunications Sa | MULTI-SPEED CONNECTION NETWORK FOR DATA CHANNELS |
| FR2430141A1 (en) * | 1978-06-29 | 1980-01-25 | Glowinski Albert | BIT-TO-BIT DIGITAL TIME-SWITCHING NETWORK |
-
1979
- 1979-08-24 DE DE19792934379 patent/DE2934379A1/en not_active Withdrawn
-
1980
- 1980-08-06 US US06/175,692 patent/US4512014A/en not_active Expired - Lifetime
- 1980-08-22 JP JP11485380A patent/JPS5632849A/en active Pending
- 1980-08-22 DE DE8080105012T patent/DE3062539D1/en not_active Expired
- 1980-08-22 NO NO802496A patent/NO151345C/en unknown
- 1980-08-22 CA CA000358830A patent/CA1167575A/en not_active Expired
- 1980-08-22 EP EP80105012A patent/EP0024708B1/en not_active Expired
- 1980-08-22 IL IL60899A patent/IL60899A/en unknown
Also Published As
| Publication number | Publication date |
|---|---|
| NO151345C (en) | 1985-03-27 |
| US4512014A (en) | 1985-04-16 |
| EP0024708B1 (en) | 1983-03-30 |
| DE2934379A1 (en) | 1981-03-26 |
| DE3062539D1 (en) | 1983-05-05 |
| JPS5632849A (en) | 1981-04-02 |
| IL60899A (en) | 1983-05-15 |
| NO802496L (en) | 1981-02-25 |
| EP0024708A1 (en) | 1981-03-11 |
| NO151345B (en) | 1984-12-10 |
| IL60899A0 (en) | 1980-10-26 |
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