CA1168719A - Switched-capacitor resistor simulation circuits - Google Patents
Switched-capacitor resistor simulation circuitsInfo
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- CA1168719A CA1168719A CA000377406A CA377406A CA1168719A CA 1168719 A CA1168719 A CA 1168719A CA 000377406 A CA000377406 A CA 000377406A CA 377406 A CA377406 A CA 377406A CA 1168719 A CA1168719 A CA 1168719A
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- circuit according
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H19/00—Networks using time-varying elements, e.g. N-path filters
- H03H19/004—Switched capacitor networks
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H11/00—Networks using active elements
- H03H11/46—One-port networks
Abstract
D-23,199 SWITCHED-CAPACITOR RESISTOR SIMULATION CIRCUITS
by Man Shek Lee Abstract of Disclosure An integratable switched capacitor simulation circuit comprising an integrated capacitor C3 having bottom and top plates thereof electrically connected to first and second nodes, and a pair of integrated capacitors C1 and C2 having their top plates electrically connected together. The bottom plate of C2 is electrically connected to the output of a voltage follower that has its input terminal connected to the second node. A first switch means periodically connects the top plates of C1 and C2 to the first and second nodes at a prescribed rate. When the first node is connected to a voltage source and the bottom plate of C1 is connected to either ground or the first node, the circuit simulates a source resistor across the nodes. When the first node and bottom plate of C1 are connected to ground, the circuit simulates a grounded resistor. In alternate embodiments, the capacitances of C1 and/or C3 may be zero valued for presenting an open circuit across the terminals thereof. In yet another embodiment where C1 and C3 are zero valued and the first node is connected to ground, a second switch means essentially operating 180°
out of phase with respect to the first switch means is located in the electrical connection of the bottom plate of C2 and the output terminal of the voltage follower for periodically connecting the bottom plate of C2 to the first node and the output of the voltage follower for causing the circuit to simulate a bilinear grounded resistor. In an alternate embodiment of this structure, the first node is connected to the output of a voltage source for simulating a bilinear source resistor.
by Man Shek Lee Abstract of Disclosure An integratable switched capacitor simulation circuit comprising an integrated capacitor C3 having bottom and top plates thereof electrically connected to first and second nodes, and a pair of integrated capacitors C1 and C2 having their top plates electrically connected together. The bottom plate of C2 is electrically connected to the output of a voltage follower that has its input terminal connected to the second node. A first switch means periodically connects the top plates of C1 and C2 to the first and second nodes at a prescribed rate. When the first node is connected to a voltage source and the bottom plate of C1 is connected to either ground or the first node, the circuit simulates a source resistor across the nodes. When the first node and bottom plate of C1 are connected to ground, the circuit simulates a grounded resistor. In alternate embodiments, the capacitances of C1 and/or C3 may be zero valued for presenting an open circuit across the terminals thereof. In yet another embodiment where C1 and C3 are zero valued and the first node is connected to ground, a second switch means essentially operating 180°
out of phase with respect to the first switch means is located in the electrical connection of the bottom plate of C2 and the output terminal of the voltage follower for periodically connecting the bottom plate of C2 to the first node and the output of the voltage follower for causing the circuit to simulate a bilinear grounded resistor. In an alternate embodiment of this structure, the first node is connected to the output of a voltage source for simulating a bilinear source resistor.
Description
~ ~ ~8 s I ~? D-23,199 1 Background of Invention
2 This invention relates to switched capacitor circuits or
3 networks and more particularly to switched capacitor circuit replacements
4 for resistors.
Switched capacitor circuits for simulating resistors are 6 described in the references "Sampled Analog Filtering Using Switched 7 Capacitors as Resistor Equivalents" by J. T. Caves, et. al., E EE Journal 8 of Solid State Circuits, Vol. 12, No. 6, pages 592-599, December, 1977;
9 "MOS Sampled Data Recursive Filters Using Switched Capacitor Integrators"
by B. J. Hosticka, et. al., IEEE Journal of Solid State Circuits, Vol. 12, 11 No. 6, pages 600-608, December, 1977; "Switched Capacitor Filter Design 12 Using the Bilinear z-Transform" by G. C. Temes, et. al., IEEE Transactions 13 on Circuits and Systems, Vol. 25, No. 12, pages 1039~1044, December, 1978;
14 ~Derivation of Switched Capacitor Filters From Active-RC Prototypes" by G.
C. Temes, Electronics Letters, Vol. 14, No. 12, pages 361-362, June, 16 1978.
17 Techniques for reducing the effects of parasitic capacitances in 18 switched capacitor circuits are also described in the article 19 "Compensation for Parasitic Capacitances in Switched-Capacitor Filters" by G. C. Temes, et. al., Electronics Letters, Vol. 15, No. 13, pages 21 377-379, June, 1979. A number of the switched capacitor resistors 22 disclosed in these references are susceptible to top and/or bottom plate 23 parasitic capacitance effects. Also, a network using at least one of the 24 simulated resistors disclosed in these references and LDI (lo3sless discrete integrator) inductors of the type disclosed in the article 26 ~Switched Capacitor Filters Using Floating-Inductance Simulation Circuit"
27 by Man Shek Lee, Electronics Letters, Vol. 15, No. 20, pages 644-645, 28 September, 1979, requires 4-phase, rather than 2-phase, timing control 29 signals.
An object of this invention is the provision of novel switched 31 capacitor structures for simulating resistors.
~ g D-23,199 1 Summary of Invention 2 In accordan oe with this invention, an integratable switched 3 capacitor circuit for simulating a resistor comprises: first and second 4 nodes; voltage follower means having an input terminal electrically connected to said second node and having an output terminal; first 6 capacitor means having first and second terminals; first means 7 electrically connecting the ~irst terminal of said first capacitor means 8 to the output terminal of said voltage follower means; second means 9 electrically connecting said first node to one of a ground reference potential and the output terminal of a voltage source that is associated 11 with a ground reference potential; and first switch means for periodically 12 connectirg the second terminal of said first capacitor means to said first 13 and second nodes at a prescribed switching frequency so as to simulate a 14 resistor across the nodes. In alternate embodiments, a second capacitor means is electrically connected across the nodes and~or a third capacitor 16 means is connected between the switched terminal of the first capacitor 17 means and either ground or the first node. The capacitances presented by 18 the capacitor means are selected for causir~ the circuit to approximate 19 LDI resistors and bilinear resistors. In other embodiments, the capacitor means are integrated capacitors having bottom plates connected 21 to the output of a voltage source or a ground reference potential for 22 rendering the circuit relatively insensitive to bottom plate parasitic 23 capacitance effects of the integrated capacitors thereof. In a further 24 embodiment which does not include the second and third capacitor means and in which the second means electrically connects the first node to either a 26 voltage source or ground, the first means comprises a second switching 27 means for periodically connecting the bottom plate of an integrated 28 capacitor type of first capacitor means to the output terminal of the 29 voltage follower means and to the first node for simulating a bilinear source or grounded resistor that is relatively insensitive to bottom plate 31 parasitic capacitance effects associated with the integrated capacitor.
¦ 3 ~ 9 D-23,l99 1 Description of Drawing 2 This invention will be more fully understood frcm the following 3 detailed description of preferred embodiments thereof, together with the 4 drawing in which:
FIG. l is a schematic circuit diagram of a voltage source 34 6 driving a switched capacitor simulation circuit lO embodying this 7 invention so as to cause the circuit lO to simulate a source resistor;
8 FIG. 2 is a schematic circuit diagram of an alternate embodiment 9 of this invention for simulating a source resistor, the switch means 26 being shown in schematic form;
11 FIG. 3 is a schematic circuit diagram of another embodiment of 12 this invention in which node Nl is connected to ground for causing the 13 circuit lO to simulate a grounded resistor; and 14 FIG. 4 is a schematic circuit diagram of an alternate embodiment of this invention in which node Nl is connected to ground and a second 16 switch means 27 is inserted in line 25, the switch means 27 being 7 operative for causing the circuit 20 to simulate a grounded bilinear 18 resistor.
19 Description of Preferred Embodiments Some embodiments of this invention are described in the 21 articles, "Switched Capacitor Filters Using Floating-Inductance Simulation 22 Circuits" by Man Shek Lee, Electronics Letters, September 1979, Vol. 15, 23 No. 20, pages 644-645, and "Low-Sensitivity Switched-Capacitor Ladder 24 Filters~ by Man Shek Lee and C. Chang, IEEE Transactions on Circuits and Systems, Vol. 27, No. 6, June, 1980, pages 475-480, which are incorporated 26 herein by reference.
27 In a preferred embodiment of this invention in FIG. l that is 28 implemented in fully integrated circuit form, a switched capacitor circuit 29 or network lO for simulating a source resistor across a pair of nodes Nl 3 and N2 thereof comprises: integrated capacitors Cl, C2 and C3; a voltage 31 follower 24; switch means 26; and a source 28 of timing control signals.
32 The node Nl is connected to the output terminal of a voltage source 34 ? ~ 9 D-23,l99 1 which may be the output of an integrated operational amplifier. The node 2 N2 is connected to the input of the voltage follower 24 which is 3 essentially a voltage controlled voltage source having unity gain. The 4 output of the voltage follower is a very low impedance so that it is essentially insensitive to impedance loading effects on the output 6 terminal thereof. The input impedance of the voltage follower, however, 7 is very high. The voltage source 34 normally delivers whatever output 8 current is demanded by external circuitry such as the circuit lO.
9 The dots adjacent the one sides of the integrated capacitors indicate the locations of the top plates thereof. The integrated 11 capacitor C3 is connected across the nodes, with its bottom plate terminal 12 14 directly electrically connected to Nl and the output terminal 36 of 13 voltage source. Since the output impedance of this voltage source is 14 already substantially zero ohms, the bottom plate parasitic capacitance effects associated with the integrated capacitor C3 do not effect the 16 operation of the voltage source 34 or the circuit lO. The bottom plates 17 of integrated capacitors Cl and C2 are also connected to the output 18 terminals of associated voltage sources to obviate the effects of the 19 bottom plate parasitic capacitances thereof.
The switch means 26 comprises a pair of integrated MOS FET
21 transistors that are connected in series between Nl and N2. The common 22 terminals 31 of the transistors are connected to the top plates of Cl and 23 C2. The gate electrodes of the transistors are driven by different ones 24 of the two-phase non-overlapping timing control signals 01 and 02 that are produced by the source 28. These timing signals are 180 out of phase 26 with respect to each other as is indicated in FIG. l. The duty cycles of 27 these signals may be much less than 50%, although they are preferably 28 approximately 50% to provide maximum settling time for these pulse 29 signals. The switching frequency of the control signals is f = l/T, where T is the period of a switching cycle. The switching means completes a . :
~ 3 ~ ~9 D-23,199 1 cycle of operation every T seconds. The switching frequency is normally 2 greater than the Nyquist rate.
3 In operation, C3 is continuously charged to the difference 4 voltage across Nl and N2 since it is directly electrically connected between these nodes. When the control signal 01 is positive, only the 6 switching transistor 26A conducts to connect the top plates of Cl and C2 7 to node Nl for discharging Cl and charging C2 to the difference voltage 8 across the nodes. Conversely, when 02 is positive, only the switching 9 transistor 26B conducts to connect the top plates of Cl and C2 to the other node N2 for discharging C2 and charging Cl to the difference voltage 11 across the nodes. This operation of the switch means 26 causes circuit lO
12 to simulate a source resistor across the nodes. It can be shown that by 13 proper selection of the capacitances of the three integrated capacitors 14 that the resistor simulated by the circuit lO approximates an LDI
resistor, approximates a bilinear resistor, or is a truly bilinear 16 resistor. Consideration of the operation of the simulation circuit lO in 17 FIG. l reveals that the top plates of the three integrated capacitors are 18 either directly connected to or periodically connected to a floating node 19 N2 such that the circuit lO is susceptible to top plate parasitic capacitance effects of these capacitors. Since the top plate parasitic 21 capacitances of integrated capacitors are very small, however, their 22 effects can be neglected.
23 The LDI (lossless discrete integrator) analog to digital 24 transformation s = l (Zl/2 Z-l/2) (l) 26 and the bilinear transformation 27 s = T ~1 (2) 28 where s is the Laplace operator in the s-domain, z is the operator in the 29 discrete time or z-domain, and T is the reciprocal of the sampling rate, are used to transform continuous real time analog definitions of 31 electrical networks in the s-domain into corresponding discrete time 7 ~
D-23,199 1 definitions of corresponding switched capacitor sampled networks in the 2 z-domain. The general representation of the differential charge-voltage 3 relationship for an LDI and a bilinear resistor are determined to be 4 T -l/2 (3)
Switched capacitor circuits for simulating resistors are 6 described in the references "Sampled Analog Filtering Using Switched 7 Capacitors as Resistor Equivalents" by J. T. Caves, et. al., E EE Journal 8 of Solid State Circuits, Vol. 12, No. 6, pages 592-599, December, 1977;
9 "MOS Sampled Data Recursive Filters Using Switched Capacitor Integrators"
by B. J. Hosticka, et. al., IEEE Journal of Solid State Circuits, Vol. 12, 11 No. 6, pages 600-608, December, 1977; "Switched Capacitor Filter Design 12 Using the Bilinear z-Transform" by G. C. Temes, et. al., IEEE Transactions 13 on Circuits and Systems, Vol. 25, No. 12, pages 1039~1044, December, 1978;
14 ~Derivation of Switched Capacitor Filters From Active-RC Prototypes" by G.
C. Temes, Electronics Letters, Vol. 14, No. 12, pages 361-362, June, 16 1978.
17 Techniques for reducing the effects of parasitic capacitances in 18 switched capacitor circuits are also described in the article 19 "Compensation for Parasitic Capacitances in Switched-Capacitor Filters" by G. C. Temes, et. al., Electronics Letters, Vol. 15, No. 13, pages 21 377-379, June, 1979. A number of the switched capacitor resistors 22 disclosed in these references are susceptible to top and/or bottom plate 23 parasitic capacitance effects. Also, a network using at least one of the 24 simulated resistors disclosed in these references and LDI (lo3sless discrete integrator) inductors of the type disclosed in the article 26 ~Switched Capacitor Filters Using Floating-Inductance Simulation Circuit"
27 by Man Shek Lee, Electronics Letters, Vol. 15, No. 20, pages 644-645, 28 September, 1979, requires 4-phase, rather than 2-phase, timing control 29 signals.
An object of this invention is the provision of novel switched 31 capacitor structures for simulating resistors.
~ g D-23,199 1 Summary of Invention 2 In accordan oe with this invention, an integratable switched 3 capacitor circuit for simulating a resistor comprises: first and second 4 nodes; voltage follower means having an input terminal electrically connected to said second node and having an output terminal; first 6 capacitor means having first and second terminals; first means 7 electrically connecting the ~irst terminal of said first capacitor means 8 to the output terminal of said voltage follower means; second means 9 electrically connecting said first node to one of a ground reference potential and the output terminal of a voltage source that is associated 11 with a ground reference potential; and first switch means for periodically 12 connectirg the second terminal of said first capacitor means to said first 13 and second nodes at a prescribed switching frequency so as to simulate a 14 resistor across the nodes. In alternate embodiments, a second capacitor means is electrically connected across the nodes and~or a third capacitor 16 means is connected between the switched terminal of the first capacitor 17 means and either ground or the first node. The capacitances presented by 18 the capacitor means are selected for causir~ the circuit to approximate 19 LDI resistors and bilinear resistors. In other embodiments, the capacitor means are integrated capacitors having bottom plates connected 21 to the output of a voltage source or a ground reference potential for 22 rendering the circuit relatively insensitive to bottom plate parasitic 23 capacitance effects of the integrated capacitors thereof. In a further 24 embodiment which does not include the second and third capacitor means and in which the second means electrically connects the first node to either a 26 voltage source or ground, the first means comprises a second switching 27 means for periodically connecting the bottom plate of an integrated 28 capacitor type of first capacitor means to the output terminal of the 29 voltage follower means and to the first node for simulating a bilinear source or grounded resistor that is relatively insensitive to bottom plate 31 parasitic capacitance effects associated with the integrated capacitor.
¦ 3 ~ 9 D-23,l99 1 Description of Drawing 2 This invention will be more fully understood frcm the following 3 detailed description of preferred embodiments thereof, together with the 4 drawing in which:
FIG. l is a schematic circuit diagram of a voltage source 34 6 driving a switched capacitor simulation circuit lO embodying this 7 invention so as to cause the circuit lO to simulate a source resistor;
8 FIG. 2 is a schematic circuit diagram of an alternate embodiment 9 of this invention for simulating a source resistor, the switch means 26 being shown in schematic form;
11 FIG. 3 is a schematic circuit diagram of another embodiment of 12 this invention in which node Nl is connected to ground for causing the 13 circuit lO to simulate a grounded resistor; and 14 FIG. 4 is a schematic circuit diagram of an alternate embodiment of this invention in which node Nl is connected to ground and a second 16 switch means 27 is inserted in line 25, the switch means 27 being 7 operative for causing the circuit 20 to simulate a grounded bilinear 18 resistor.
19 Description of Preferred Embodiments Some embodiments of this invention are described in the 21 articles, "Switched Capacitor Filters Using Floating-Inductance Simulation 22 Circuits" by Man Shek Lee, Electronics Letters, September 1979, Vol. 15, 23 No. 20, pages 644-645, and "Low-Sensitivity Switched-Capacitor Ladder 24 Filters~ by Man Shek Lee and C. Chang, IEEE Transactions on Circuits and Systems, Vol. 27, No. 6, June, 1980, pages 475-480, which are incorporated 26 herein by reference.
27 In a preferred embodiment of this invention in FIG. l that is 28 implemented in fully integrated circuit form, a switched capacitor circuit 29 or network lO for simulating a source resistor across a pair of nodes Nl 3 and N2 thereof comprises: integrated capacitors Cl, C2 and C3; a voltage 31 follower 24; switch means 26; and a source 28 of timing control signals.
32 The node Nl is connected to the output terminal of a voltage source 34 ? ~ 9 D-23,l99 1 which may be the output of an integrated operational amplifier. The node 2 N2 is connected to the input of the voltage follower 24 which is 3 essentially a voltage controlled voltage source having unity gain. The 4 output of the voltage follower is a very low impedance so that it is essentially insensitive to impedance loading effects on the output 6 terminal thereof. The input impedance of the voltage follower, however, 7 is very high. The voltage source 34 normally delivers whatever output 8 current is demanded by external circuitry such as the circuit lO.
9 The dots adjacent the one sides of the integrated capacitors indicate the locations of the top plates thereof. The integrated 11 capacitor C3 is connected across the nodes, with its bottom plate terminal 12 14 directly electrically connected to Nl and the output terminal 36 of 13 voltage source. Since the output impedance of this voltage source is 14 already substantially zero ohms, the bottom plate parasitic capacitance effects associated with the integrated capacitor C3 do not effect the 16 operation of the voltage source 34 or the circuit lO. The bottom plates 17 of integrated capacitors Cl and C2 are also connected to the output 18 terminals of associated voltage sources to obviate the effects of the 19 bottom plate parasitic capacitances thereof.
The switch means 26 comprises a pair of integrated MOS FET
21 transistors that are connected in series between Nl and N2. The common 22 terminals 31 of the transistors are connected to the top plates of Cl and 23 C2. The gate electrodes of the transistors are driven by different ones 24 of the two-phase non-overlapping timing control signals 01 and 02 that are produced by the source 28. These timing signals are 180 out of phase 26 with respect to each other as is indicated in FIG. l. The duty cycles of 27 these signals may be much less than 50%, although they are preferably 28 approximately 50% to provide maximum settling time for these pulse 29 signals. The switching frequency of the control signals is f = l/T, where T is the period of a switching cycle. The switching means completes a . :
~ 3 ~ ~9 D-23,199 1 cycle of operation every T seconds. The switching frequency is normally 2 greater than the Nyquist rate.
3 In operation, C3 is continuously charged to the difference 4 voltage across Nl and N2 since it is directly electrically connected between these nodes. When the control signal 01 is positive, only the 6 switching transistor 26A conducts to connect the top plates of Cl and C2 7 to node Nl for discharging Cl and charging C2 to the difference voltage 8 across the nodes. Conversely, when 02 is positive, only the switching 9 transistor 26B conducts to connect the top plates of Cl and C2 to the other node N2 for discharging C2 and charging Cl to the difference voltage 11 across the nodes. This operation of the switch means 26 causes circuit lO
12 to simulate a source resistor across the nodes. It can be shown that by 13 proper selection of the capacitances of the three integrated capacitors 14 that the resistor simulated by the circuit lO approximates an LDI
resistor, approximates a bilinear resistor, or is a truly bilinear 16 resistor. Consideration of the operation of the simulation circuit lO in 17 FIG. l reveals that the top plates of the three integrated capacitors are 18 either directly connected to or periodically connected to a floating node 19 N2 such that the circuit lO is susceptible to top plate parasitic capacitance effects of these capacitors. Since the top plate parasitic 21 capacitances of integrated capacitors are very small, however, their 22 effects can be neglected.
23 The LDI (lossless discrete integrator) analog to digital 24 transformation s = l (Zl/2 Z-l/2) (l) 26 and the bilinear transformation 27 s = T ~1 (2) 28 where s is the Laplace operator in the s-domain, z is the operator in the 29 discrete time or z-domain, and T is the reciprocal of the sampling rate, are used to transform continuous real time analog definitions of 31 electrical networks in the s-domain into corresponding discrete time 7 ~
D-23,199 1 definitions of corresponding switched capacitor sampled networks in the 2 z-domain. The general representation of the differential charge-voltage 3 relationship for an LDI and a bilinear resistor are determined to be 4 T -l/2 (3)
5 and
6 ~Q(Z) = R (l+z )V(z) (4)
7 where Q(z) is the charge in the discrete time domain, T is the sampling
8 period, R is resistance, and V(z) is the voltage across the nodes Nl and
9 N2.
It is known that the voltages and currents in LDI reactive 11 elements are sampled at times that are T/2 seconds apart. The voltage and 12 current in an LDI resistor, however, are sampled at the same time. This 13 means that Kirckhoff's voltage and current laws cannot be satisfied 14 simultaneously f~r LDI resistive elements defined by equation (3) and LDI
15 reactive elements. It is therefore necessary to develop expressions such 16 as 17 iR(nT) = iR(nT+T/2) (5) 18 iR(nT) = iR(nT-T/2) (6) 19 iR(nT) = 2 {iR(nT-T/2) + iR(nT+T/2)} (7) that approximate the current in an LDI resistor. Consideration of these 21 equations (5), (6) and (7) in the z domain and associated relationships 22 for voltage and current in a resistor reveals that the resistances 23 associated with these currents are RZ1/2, RZ-1/2~ and 24 2R(Z1/2+Z-1/2)-1~ respectively.
The currents defined by equations ~5) and (6 ) are those existing 26 a half-period before and after the time nT, and that defined by equation 27 (7) iS the average value of the currents in e~uations (5) and (6). These 2~ currents are expressed in terms of the differential charge and voltage as Q( ) R
31 AQ(Z) = ~R v(z) D-23,199 1 ~Q(Z) = 2R (l+z ) V(z) (10) 2 It will be noted that equation (lO) corresponds to that of a bilinear 3 resistor, see equation (4), which approximates an LDI resistor if the 4 switching frequency l/T is high enough. It is desirable that the differential charge-voltage transfer function for the circuit lO satisfy 6 one of the equations (8)-(lO) if it is to simulate a resistor that 7 approximates an LDI resistor. Similarly, it is desirable that such a 8 differential charge-voltage transfer function for circuit lO satisfy 9 equation (4) if it is to simulate a bilinear resistor.
It has been found convenient to define the capacitances of the 11 integrated capacitors as 12 Cl = (l-g)C (ll) 13 c2 = gc (12) 14 c3 = (g-h)C (13) where "g" and "h" are constants and C is capacitance. The continuous time 16 representation of differential charge in line 41 is representable as 17Aq(nT) = (g-h) c {(vl(nT)-vS(nT)+v (nT-T)-vl(nT-T)}+ (14) 18gC{vl(nT-T)-vs(nT)} + (l-g)c{vl(nT)-vs(nT)}
19= (l-h)C{vl(nT)-vs(nT)}+hC{vl(nT-T)-vs(nT-T)} (15) 21where the first term in equation (14) is the charge in line 42 and C3, the 22second term in equation (14) is the charge flow in line 43 and C2, the 23 third term in equation (14) is the charge flow in line 44 and Cl, VS is 24 the source voltage on node Nl, vl is the voltage between node N2 and ground, vs(nT) is the voltage on node Nl at time nT, vs(nT-T) is the 26 voltage on node Nl at time nT-T, and q(nT) is the net charge in line 41 27 from time -~ to time nT. Assuming that the voltage v(nT) is 28 substantially equal to the voltage v(nT-T), then the average current in 29 line 41 is 3 i(nT) = ~5L~S~ = C(vl(nT) - Vq(nT)) (16) ~ 9 D~23,199 1 Considering the relationship for current and voltage in a resistor, it is 2 seen that the circuit lO in FIG. 1 simulates a resistor having a 3 resistance 4 R = T~C ( 17 ) across the nodes thereof~
6 Consideration of the equations (14) and (15) reveals that the 7 multiplier constants there must satisfy the relationships 8 O<g<l (18) 9 h<g (19) for the capacitances of Cl, C2 and C3 to all be positive. Taking the z 11 transform of the differential charge-voltage relationship in equation (15) 12 gives the expression 13 aQ(Z) = C(l-h+hz ) (Vl(z)-Vs(z)) (20) 14 The network lO has a similar differential charge-voltage relationship and also operates to simulate a source resistor when the bottom plate of Cl is 16 connected to ground instead of the node Nl, as is illustrated in FIG. 2.
17 Comparison of equation (20) with the expressions in equations (4) and 18 (8)-(10) reveals that the circuit lO does either simulate or approximate a 19 resistor across the nodes Nl and N2 thereof. The magnitude of the simulated source resistance is changed by varying T and/or the constants g 21 and h and the capacitance C which control the capacitances of Cl, C2 and 22 C3. The circuit lO in FIG. l also simulates a source resistor when the 23 circuit comprises either Cl and/or C2 or C3 together with Cl and/or C2, as 24 is described more fully hereinafter.
More specifically, when h=0 and O<g<l, the equation (20) reduces 26 to 27 ~Q(z) = c v(z) (21) 28 where the capacitances of Cl, C2 and C3 are all positive and greater than 29 0. Comparison of equations (21) and (9) reveals that the circuit lO now 3 simulates a resistor which approximates an LDI resistor having a 31 resistance R=T/C. If the constant g=0 when h=0, then the oapacitances of '7 ~ 9 D-23,199 1 C2 and C3 are both 0 and the circuit lO reduces to that disclosed in the 2 aforementioned Temes-IEEE Circuits & Systems article. Also, where the 3 node N2 is connected to a virtual ground point such as the inverting input 4 to a differential input operational amplifier (not shown), then the voltage vl=0 and the voltage follower 24 can be eliminated, since both the 6 input and output terminals thereof are then at ground potential. In this 7 instance, the term Vl(z) in equation (20) vanishes and the minus sign 8 there means that current is flowing in a direction opposite to that 9 previously indicated.
In an alternate embodiment where g=h=l, then the capacitances of 11 Cl and C3 are zero such that these elements are replaced by open circuits.
12 The differential charge-voltage relationship for this circuit then reduces 13 to 14 ~Q(z) = Cæ 1 V(z) (22) A comparison of equations (22) and (8) reveals that this modified form of 16 circuit lO also simulates a resistor that approximates an LDI resistor.
17 In another modified form of this invention in which h=1~2 and 18 l/2_g<l, the circuit lO includes all three of the capacitors Cl, C2 and 19 C3. The differential charge-voltage relationship for this simulation circuit is 21 ~Q(Z) = 2 (l+z ) v(z) (23) 22 Comparison of equations (23), (lO) and (4) reveals that the modified 23 circuit lO now simulates a source resistor across the nodes Nl and N2 24 which approximates an LDI resistor and which is a bilinear resistor. In the special case where g=h=l/2, the capacitance of C3 is reduced to zero 26 and Cl=C2. The modified circuit lO now only requires two equal-valued 27 capacitors Cl and C2 having capacitances C~2 for simulating a bilinear 28 source resistor having a resistance R=T/C. In the special case where g=l, 29 then the capacitance of Cl is reduced to 0 and the element replaced with 3 an open circuit. In this instance, the modified network requires only two _g_ D-23,l99 1 capacitors C2 and C3 having capacitances 2C ~nd C, respectively, 2 and simulating a bilinear source resistor.
3 In yet another embodiment of this invention, the capacitor C3 4 may be replaced by an open circuit. The differential charge-voltage relationship for this modified network is also defined by equation (20), 6 where the constant g is substituted for the constant h. This modified 7 network lO simulates a bilinear source resistor only when g=l/2. Although 8 the modified network simulates a resistor for other values of g between 0 9 and l, the simulated resistor is no longer a bilinear resistor.
It is also possible to connect node Nl to a ground reference 11 potential so that the voltage vs=O volts, as is illustrated in FIG. 3.
12 This connection causes the network lO there to simulate a grounded bilinear 13 resistor across the nodes Nl and N2. The differential charge-voltage 14 relationship in the z domain for the circuit in FIG. 3 is also defined by equation (20), with Vs(z)=O volts. The circuit in FIG. 3 may be 16 modified in the manner described above for the network lO in FIG. l to 17 produce alternate embodiments of this invention that simulate a grounded 18 resistor.
19 In yet another embodiment of this invention in FIG. 4, a circuit 20 for simulating a grounded bilinear resistor comprises a single 21 capacitor C2, a voltage follower 24, and a pair of switch means 26 and 27.
22 The circuit 20 is the same as the circuit lO in FIG. 3, with Cl=C2=0 and 23 a second switch means 27 inserted in line 25. The second switch means 24 periodically connects the bottom plate of C2 to the output terminal of the voltage follower and to node Nl. The switch means 26 and 27 operate as is 26 shown in FIG. 4, for alternately connecting the top plate of C2 between 27 nodes N2 and Nl, and connecting the bottom plate of C2 between the output 28 of the voltage follower and Nl, respectively. Alternatively, the circuit 29 20 simulates a bilinear source resistor across the nodes when Nl is connected to the output terminal of a voltage source.
~ l ~ ? ~ ~ 9 D-23,199 1 Although this invention is described in relation to preferred 2 embodiments thereof, variations and modifications will occur to those 3 skilled in the art. By way of example, the simulation circuits may be 4 realized with integrated circuit technologies other than MOS and in other than fully integrated circuit form. The simulation circuits may also be 6 fully implemented with discrete components and with only a portion thereof 7 in integrated circuit form. Further, the switch means may comprise other 8 types of switching elements such as discrete transistors, mechanical 9 switches, relays, and other types of integrated switches. Additionally, g and/or h may be negative, although this may require one or more of the 11 capacitors to have a negative capacitance. And when both Cl and C3 are 12 present, C2 is preferably not equal to zero since C3 may then be negative.
13 The scope of this invention is therefore defined by the appended claims 14 rather than the aforementioned detailed descriptions of preferred embodiments thereof.
It is known that the voltages and currents in LDI reactive 11 elements are sampled at times that are T/2 seconds apart. The voltage and 12 current in an LDI resistor, however, are sampled at the same time. This 13 means that Kirckhoff's voltage and current laws cannot be satisfied 14 simultaneously f~r LDI resistive elements defined by equation (3) and LDI
15 reactive elements. It is therefore necessary to develop expressions such 16 as 17 iR(nT) = iR(nT+T/2) (5) 18 iR(nT) = iR(nT-T/2) (6) 19 iR(nT) = 2 {iR(nT-T/2) + iR(nT+T/2)} (7) that approximate the current in an LDI resistor. Consideration of these 21 equations (5), (6) and (7) in the z domain and associated relationships 22 for voltage and current in a resistor reveals that the resistances 23 associated with these currents are RZ1/2, RZ-1/2~ and 24 2R(Z1/2+Z-1/2)-1~ respectively.
The currents defined by equations ~5) and (6 ) are those existing 26 a half-period before and after the time nT, and that defined by equation 27 (7) iS the average value of the currents in e~uations (5) and (6). These 2~ currents are expressed in terms of the differential charge and voltage as Q( ) R
31 AQ(Z) = ~R v(z) D-23,199 1 ~Q(Z) = 2R (l+z ) V(z) (10) 2 It will be noted that equation (lO) corresponds to that of a bilinear 3 resistor, see equation (4), which approximates an LDI resistor if the 4 switching frequency l/T is high enough. It is desirable that the differential charge-voltage transfer function for the circuit lO satisfy 6 one of the equations (8)-(lO) if it is to simulate a resistor that 7 approximates an LDI resistor. Similarly, it is desirable that such a 8 differential charge-voltage transfer function for circuit lO satisfy 9 equation (4) if it is to simulate a bilinear resistor.
It has been found convenient to define the capacitances of the 11 integrated capacitors as 12 Cl = (l-g)C (ll) 13 c2 = gc (12) 14 c3 = (g-h)C (13) where "g" and "h" are constants and C is capacitance. The continuous time 16 representation of differential charge in line 41 is representable as 17Aq(nT) = (g-h) c {(vl(nT)-vS(nT)+v (nT-T)-vl(nT-T)}+ (14) 18gC{vl(nT-T)-vs(nT)} + (l-g)c{vl(nT)-vs(nT)}
19= (l-h)C{vl(nT)-vs(nT)}+hC{vl(nT-T)-vs(nT-T)} (15) 21where the first term in equation (14) is the charge in line 42 and C3, the 22second term in equation (14) is the charge flow in line 43 and C2, the 23 third term in equation (14) is the charge flow in line 44 and Cl, VS is 24 the source voltage on node Nl, vl is the voltage between node N2 and ground, vs(nT) is the voltage on node Nl at time nT, vs(nT-T) is the 26 voltage on node Nl at time nT-T, and q(nT) is the net charge in line 41 27 from time -~ to time nT. Assuming that the voltage v(nT) is 28 substantially equal to the voltage v(nT-T), then the average current in 29 line 41 is 3 i(nT) = ~5L~S~ = C(vl(nT) - Vq(nT)) (16) ~ 9 D~23,199 1 Considering the relationship for current and voltage in a resistor, it is 2 seen that the circuit lO in FIG. 1 simulates a resistor having a 3 resistance 4 R = T~C ( 17 ) across the nodes thereof~
6 Consideration of the equations (14) and (15) reveals that the 7 multiplier constants there must satisfy the relationships 8 O<g<l (18) 9 h<g (19) for the capacitances of Cl, C2 and C3 to all be positive. Taking the z 11 transform of the differential charge-voltage relationship in equation (15) 12 gives the expression 13 aQ(Z) = C(l-h+hz ) (Vl(z)-Vs(z)) (20) 14 The network lO has a similar differential charge-voltage relationship and also operates to simulate a source resistor when the bottom plate of Cl is 16 connected to ground instead of the node Nl, as is illustrated in FIG. 2.
17 Comparison of equation (20) with the expressions in equations (4) and 18 (8)-(10) reveals that the circuit lO does either simulate or approximate a 19 resistor across the nodes Nl and N2 thereof. The magnitude of the simulated source resistance is changed by varying T and/or the constants g 21 and h and the capacitance C which control the capacitances of Cl, C2 and 22 C3. The circuit lO in FIG. l also simulates a source resistor when the 23 circuit comprises either Cl and/or C2 or C3 together with Cl and/or C2, as 24 is described more fully hereinafter.
More specifically, when h=0 and O<g<l, the equation (20) reduces 26 to 27 ~Q(z) = c v(z) (21) 28 where the capacitances of Cl, C2 and C3 are all positive and greater than 29 0. Comparison of equations (21) and (9) reveals that the circuit lO now 3 simulates a resistor which approximates an LDI resistor having a 31 resistance R=T/C. If the constant g=0 when h=0, then the oapacitances of '7 ~ 9 D-23,199 1 C2 and C3 are both 0 and the circuit lO reduces to that disclosed in the 2 aforementioned Temes-IEEE Circuits & Systems article. Also, where the 3 node N2 is connected to a virtual ground point such as the inverting input 4 to a differential input operational amplifier (not shown), then the voltage vl=0 and the voltage follower 24 can be eliminated, since both the 6 input and output terminals thereof are then at ground potential. In this 7 instance, the term Vl(z) in equation (20) vanishes and the minus sign 8 there means that current is flowing in a direction opposite to that 9 previously indicated.
In an alternate embodiment where g=h=l, then the capacitances of 11 Cl and C3 are zero such that these elements are replaced by open circuits.
12 The differential charge-voltage relationship for this circuit then reduces 13 to 14 ~Q(z) = Cæ 1 V(z) (22) A comparison of equations (22) and (8) reveals that this modified form of 16 circuit lO also simulates a resistor that approximates an LDI resistor.
17 In another modified form of this invention in which h=1~2 and 18 l/2_g<l, the circuit lO includes all three of the capacitors Cl, C2 and 19 C3. The differential charge-voltage relationship for this simulation circuit is 21 ~Q(Z) = 2 (l+z ) v(z) (23) 22 Comparison of equations (23), (lO) and (4) reveals that the modified 23 circuit lO now simulates a source resistor across the nodes Nl and N2 24 which approximates an LDI resistor and which is a bilinear resistor. In the special case where g=h=l/2, the capacitance of C3 is reduced to zero 26 and Cl=C2. The modified circuit lO now only requires two equal-valued 27 capacitors Cl and C2 having capacitances C~2 for simulating a bilinear 28 source resistor having a resistance R=T/C. In the special case where g=l, 29 then the capacitance of Cl is reduced to 0 and the element replaced with 3 an open circuit. In this instance, the modified network requires only two _g_ D-23,l99 1 capacitors C2 and C3 having capacitances 2C ~nd C, respectively, 2 and simulating a bilinear source resistor.
3 In yet another embodiment of this invention, the capacitor C3 4 may be replaced by an open circuit. The differential charge-voltage relationship for this modified network is also defined by equation (20), 6 where the constant g is substituted for the constant h. This modified 7 network lO simulates a bilinear source resistor only when g=l/2. Although 8 the modified network simulates a resistor for other values of g between 0 9 and l, the simulated resistor is no longer a bilinear resistor.
It is also possible to connect node Nl to a ground reference 11 potential so that the voltage vs=O volts, as is illustrated in FIG. 3.
12 This connection causes the network lO there to simulate a grounded bilinear 13 resistor across the nodes Nl and N2. The differential charge-voltage 14 relationship in the z domain for the circuit in FIG. 3 is also defined by equation (20), with Vs(z)=O volts. The circuit in FIG. 3 may be 16 modified in the manner described above for the network lO in FIG. l to 17 produce alternate embodiments of this invention that simulate a grounded 18 resistor.
19 In yet another embodiment of this invention in FIG. 4, a circuit 20 for simulating a grounded bilinear resistor comprises a single 21 capacitor C2, a voltage follower 24, and a pair of switch means 26 and 27.
22 The circuit 20 is the same as the circuit lO in FIG. 3, with Cl=C2=0 and 23 a second switch means 27 inserted in line 25. The second switch means 24 periodically connects the bottom plate of C2 to the output terminal of the voltage follower and to node Nl. The switch means 26 and 27 operate as is 26 shown in FIG. 4, for alternately connecting the top plate of C2 between 27 nodes N2 and Nl, and connecting the bottom plate of C2 between the output 28 of the voltage follower and Nl, respectively. Alternatively, the circuit 29 20 simulates a bilinear source resistor across the nodes when Nl is connected to the output terminal of a voltage source.
~ l ~ ? ~ ~ 9 D-23,199 1 Although this invention is described in relation to preferred 2 embodiments thereof, variations and modifications will occur to those 3 skilled in the art. By way of example, the simulation circuits may be 4 realized with integrated circuit technologies other than MOS and in other than fully integrated circuit form. The simulation circuits may also be 6 fully implemented with discrete components and with only a portion thereof 7 in integrated circuit form. Further, the switch means may comprise other 8 types of switching elements such as discrete transistors, mechanical 9 switches, relays, and other types of integrated switches. Additionally, g and/or h may be negative, although this may require one or more of the 11 capacitors to have a negative capacitance. And when both Cl and C3 are 12 present, C2 is preferably not equal to zero since C3 may then be negative.
13 The scope of this invention is therefore defined by the appended claims 14 rather than the aforementioned detailed descriptions of preferred embodiments thereof.
Claims (37)
1. An integratable switched capacitor circuit for simulating a resistor comprising:
first and second nodes;
voltage follower means having an input terminal electrically connected to said second node and having an output terminal;
first capacitor means having first and second terminals;
first means electrically connecting the first terminal of said first capacitor means to the output terminal of said voltage follower means;
second means electrically connecting said first node to one of a ground reference potential and the output terminal of a voltage source that is associated with a ground reference potential; and first switch means for periodically electrically connecting the second terminal of said first capacitor means to said first and second nodes at a prescribed switching frequency so as to simulate a resistor across said nodes.
first and second nodes;
voltage follower means having an input terminal electrically connected to said second node and having an output terminal;
first capacitor means having first and second terminals;
first means electrically connecting the first terminal of said first capacitor means to the output terminal of said voltage follower means;
second means electrically connecting said first node to one of a ground reference potential and the output terminal of a voltage source that is associated with a ground reference potential; and first switch means for periodically electrically connecting the second terminal of said first capacitor means to said first and second nodes at a prescribed switching frequency so as to simulate a resistor across said nodes.
2. The circuit according to claim 1 wherein said second means electrically connects said first node to the output terminal of a voltage source that is associated with a ground reference potential for causing the circuit to simulate a source resistor across said nodes.
3. The circuit according to claim 1 wherein said second means electrically connects said first node to a ground reference potential for causing the circuit to simulate a grounded resistor across said nodes.
4. The circuit according to claim 2 comprising second capacitor means having first and second terminals electrically connected to ground and the second terminal of said first capacitor means, respectively.
5. The circuit according to claim 4 wherein said first and second capacitor means each provide a positive capacitance C/2 between the terminals thereof for causing the circuit to simulate a bilinear resistor D-23,199 having a resistance R=T/C across said nodes, where T is the reciprocal of the switching frequency, said switch means completes a full cycle of operation every T seconds, and the circuit is characterized by the bilinear transformation = s.
6. The circuit according to claim 4 wherein the capacitances of said first and second capacitor means are gC and (1-g)C, respectively, and 0<g?1.
7. The circuit according to claim 4 wherein said first and second capacitor means are integrated capacitors having bottom plate terminals electrically connected to the output terminal of said voltage follower means and ground, respectively, for rendering the circuit relatively insensitive to bottom plate parasitic capacitance effects associated with said integrated capacitors.
8. The circuit according to claim 2 comprising second capacitor means having first and second terminals electrically connected to said first node and the second terminal of said first capacitor means, respectively.
9. The circuit according to claim 8 wherein said first and second means each provide a positive capacitance C/2 between the terminals thereof for causing the circuit to simulate a bilinear source resistor having a resistance R=T/C between said nodes, where T is the reciprocal of the switching frequency, said switch means completes a full cycle of operation every T seconds, and the circuit is characterized by the bilinear transformation.
10. The circuit according to claim 8 wherein the capacitances of said first and second capacitor means are gC and (1-g)C, respectively and 0<g?1.
11. The circuit according to claim 8 wherein said first and second capacitor means are integrated capacitors having bottom plate terminals electrically connected to the output terminal of said voltage follower means and said first node, respectively, for causing the circuit D-23,199 to simulate a source resistor that is relatively insensitive to bottom plate parasitic capacitance effects associated with said integrated capacitors.
12. The circuit according to claim 2 comprising second capacitor means having first and second terminals electrically connected to said first and second nodes, respectively.
13. The circuit according to claim 12 wherein said second and first capacitor means provide capacitances of C and 2C across the terminals thereof for simulating a bilinear resistor having a resistance R=T/C between said nodes, where T is the reciprocal of the switching frequency, said switch means completes a full cycle of operation every T
seconds, and the circuit is characterized by the bilinear transformation.
seconds, and the circuit is characterized by the bilinear transformation.
14. The circuit according to claim 12 wherein said first and second capacitor means are integrated capacitors having bottom plate terminals electrically connected to the output terminal of said voltage follower means and said first node, respectively, for rendering the circuit relatively insensitive to bottom plate parasitic capacitance effects associated with said integrated capacitors.
15. The circuit according to claim 2 further comprising second capacitor means having a first terminal electrically connected to one of the first node and ground reference potential, and having a second terminal electrically connected to the second terminal of said first capacitor means.
16. The circuit according to claim 15 further comprising a third capacitor means having first and second terminals electrically connected to said first and second nodes, respectively.
17. The circuit according to claim 16 wherein said first, second and third capacitor means provide capacitances gC, (1-g)C, and (g-h)C, respectively, across the terminals thereof for causing the circuit to simulate a resistor having a resistance R=T/C across said nodes, where T is the reciprocal of the switching frequency and said switching means D-23,199 completes a full cycle of operation every T seconds.
18. The circuit according to claim 17 wherein g and h are constants having positive values and satify the conditions 0<g?1 for causing the capacitances presented by said capacitor means to be positive.
19. The circuit according to claim 18 wherein g and h satisfy the requirements that h=1/2 and 1/2?g?1 for causing the circuit to simulate a bilinear resistor having a resistance R=T/C between said nodes, and the circuit is characterized by the bilinear transformation.
20. The circuit according to claim 18 wherein said first and second capacitor means are integrated capacitors having top plate terminals thereof electrically connected together for alternate connection to said first and second nodes by said switch means and said third capacitor means is an integrated capacitor having its bottom plate terminal electrically connected to said first node for rendering the circuit relatively insensitive to bottom plate parasitic capacitance effects associated with said integrated capacitors.
21. The circuit according to claim 17 wherein g=h and 0<g?1 for causing said third capacitor means to provide zero capacitance, which is essentially an open circuit, across the terminals thereof.
22. The circuit according to claim 1 wherein said second means electrically connects said first node to one of a ground reference potential and the output terminal of a voltage source and wherein said first means comprises second switching means operating at the prescribed switching frequency and phasing with respect to said first switching means for periodically electrically connecting the first terminal of said first capacitor means to the output terminal of said voltage follower means and to said first node as said first switch means connects said second terminal of said first capacitor means to said first and second nodes, respectively, for simulating one of a grounded bilinear resistor and a D-23,199 bilinear source resistor between said nodes when the circuit is characterized by the bilinear transformation.
23. The circuit according to claim 22 wherein said first capacitor means is an integrated capacitor in which the bottom plate terminal thereof is said first terminal so as to render the simulated resistor relatively insensitive to bottom plate parasitic capacitance effects associated with the integrated capacitor.
24. The circuit according to claim 3 comprising second capacitor means having first and second terminals electrically connected to ground and the second terminal of said first capacitor means, respectively.
25. The circuit according to claim 24 wherein said first and second capacitor means each provide a positive capacitance C/2 between the terminals thereof for causing the circuit to simulate a bilinear resistor having a resistance R=T/C across said nodes, where T is the reciprocal of the switching frequency, said switch means completes a full cycle of operation every T seconds, and the circuit is characterized by the bilinear transformation =s.
26. The circuit according to claim 24 wherein the capacitances of said first and second capacitor means are gC and (1-g)C, respectively, and 0<g?1.
27. The circuit according to claim 24 wherein said first and second capacitor means are integrated capacitors having bottom plate terminals electrically connected to the output terminal of said voltage follower means and ground, respectively, for rendering the circuit relatively insensitive to bottom plate parasitic capacitance effects associated with said integrated capacitors.
D-23,199
D-23,199
28. The circuit according to claim 3 comprising second capacitor means having first and second terminals electrically connected to said first and second nodes, respectively.
29. The circuit according to claim 28 wherein said second and first capacitor means provide capacitances of C and 2C across the terminals thereof for simulating a bilinear resistor having a resistance R=T/C between said nodes, where T is the reciprocal of the switching frequency, said switch means completes a full cycle of operation every T seconds, and the circuit is characterized by the bilinear transformation.
30. The circuit according to claim 28 wherein said first and second capacitor means are integrated capacitors having bottom plate terminals electrically connected to the output terminal of said voltage follower means and said first node, respectively, for rendering the circuit relatively insensitive to bottom plate parasitic capacitance effects associated with said integrated capacitors.
31. The circuit according to claim 3 further comprising second capacitor means having a first terminal electrically connected to one of the first node and ground reference potential, and having a second terminal electrically connected to the second terminal of said first capacitor means.
32. The circuit according to claim 31 further comprising a third capacitor means having first and second terminals electrically connected to said first and second nodes, respectively.
33. The circuit according to claim 32 wherein said first, second and third capacitor means provide capacitances gC, (1-g)C, and (g-h)C, respectively, across the terminals thereof for causing the D-23,199 circuit to simulate a resistor having a resistance R=T/C across said nodes, where T is the reciprocal of the switching frequency and said switching means completes a full cycle of operation every T seconds.
34. The circuit according to claim 33 wherein g and h are constants having positive values and satisfy the conditions 0<g?1 for causing the capacitances presented by said capacitor means to be positive.
35. The circuit according to claim 34 wherein g and h satisfy the requirements that h=1/2 and 1/2?g?1 for causing the circuit to simulate a bilinear resistor having a resistance R=T/C between said nodes, and the circuit is characterized by the bilinear transformation.
36. me circuit according to claim 34 wherein said first and second capacitor means are integrated capacitors having top plate terminals thereof electrically connected together for alternate connection to said first and second nodes by said switch means and said third capacitor means is an integrated capacitor having its bottom plate terminal electrically connected to said first node for rendering the circuit relatively insensitive to bottom plate parasitic capacitance effects associated with said integrated capacitors.
37. The circuit according to claim 33 wherein g=h and 0<g?1 for causing said third capacitor means to provide zero capacitance, which is essentially an open circuit, across the terminals thereof.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US171,523 | 1980-07-23 | ||
| US06/171,523 US4331944A (en) | 1980-07-23 | 1980-07-23 | Switched-capacitor resistor simulation circuits |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1168719A true CA1168719A (en) | 1984-06-05 |
Family
ID=22624056
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000377406A Expired CA1168719A (en) | 1980-07-23 | 1981-05-12 | Switched-capacitor resistor simulation circuits |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US4331944A (en) |
| CA (1) | CA1168719A (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58177028A (en) * | 1982-04-09 | 1983-10-17 | Hitachi Ltd | Switching circuit |
| DE3379931D1 (en) * | 1982-11-19 | 1989-06-29 | Toshiba Kk | Switched capacitor filter circuit |
| JPS59175209A (en) * | 1983-03-25 | 1984-10-04 | Hitachi Ltd | Signal transmitting circuit |
| US4659996A (en) * | 1984-02-27 | 1987-04-21 | Motorola, Inc. | Method and apparatus for de-ringing a switched capacitor filter |
| WO2002045283A2 (en) * | 2000-11-29 | 2002-06-06 | Broadcom Corporation | Integrated direct conversion satellite tuner |
| US7154346B2 (en) * | 2004-07-30 | 2006-12-26 | Broadcom Corporation | Apparatus and method to provide a local oscillator signal |
| US7535976B2 (en) * | 2004-07-30 | 2009-05-19 | Broadcom Corporation | Apparatus and method for integration of tuner functions in a digital receiver |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4179665A (en) * | 1978-09-08 | 1979-12-18 | American Microsystems, Inc. | Switched capacitor elliptic filter |
-
1980
- 1980-07-23 US US06/171,523 patent/US4331944A/en not_active Expired - Lifetime
-
1981
- 1981-05-12 CA CA000377406A patent/CA1168719A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| US4331944A (en) | 1982-05-25 |
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