CA1169567A - Method of controlling an apparatus, which is operated by a solid-state processor and powered by an electric mains, in case of a power failure and apparatus employing said method - Google Patents
Method of controlling an apparatus, which is operated by a solid-state processor and powered by an electric mains, in case of a power failure and apparatus employing said methodInfo
- Publication number
- CA1169567A CA1169567A CA000373419A CA373419A CA1169567A CA 1169567 A CA1169567 A CA 1169567A CA 000373419 A CA000373419 A CA 000373419A CA 373419 A CA373419 A CA 373419A CA 1169567 A CA1169567 A CA 1169567A
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- Canada
- Prior art keywords
- signal
- output
- processor
- voltage
- data
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1415—Saving, restoring, recovering or retrying at system level
- G06F11/1441—Resetting or repowering
Abstract
ABSTRACT:
"Method of controlling an apparatus, which is operated by a solid-state processor and powered by an electric mains, in case of a power failure, and apparatus employing said method."
Method of operating a mains-powered processor-controlled electrical apparatus when the power fails and is subsequently restored and apparatus therefor. In the case of a power outage data identifying the programme in pro-gress is transferred for salvage to a memory. When power is restored and if the duration of the mains-power failure is smaller than a predetermined value, physical parameters which define the instantaneous state of the apparatus are sensed in response to an instruction from the processor in order to determine the conditions under which the pro-gramme may be resumed by the apparatus.
"Method of controlling an apparatus, which is operated by a solid-state processor and powered by an electric mains, in case of a power failure, and apparatus employing said method."
Method of operating a mains-powered processor-controlled electrical apparatus when the power fails and is subsequently restored and apparatus therefor. In the case of a power outage data identifying the programme in pro-gress is transferred for salvage to a memory. When power is restored and if the duration of the mains-power failure is smaller than a predetermined value, physical parameters which define the instantaneous state of the apparatus are sensed in response to an instruction from the processor in order to determine the conditions under which the pro-gramme may be resumed by the apparatus.
Description
i'?St~
The invention relates to a method of operating an apparatus by means of a solid-state processor which holds a plurality of selectable programmed routines, which apparatus is powered by an electric ma:ins, and during a 5 conditional operation controlling, within a limited volume of space, at least one physical parameter through a pre-determined range of values in the case of a power failure during execution of a selected routine, said method com-prising a plurality of subroutines for the salvage of 10 identifier data associated with said selected routine interrupted by said failure.
The invention also relates to an apparatus oper-ated by a solid-state processor and powered by an elec-tric mains in which during a conditional operation, within 15 a predetermined volume of space, at least one physical parameter is controlled through a predetermined range o values, said processor holding a plurality of programmed routines, a~ least one of said routines being interrupt-able in case of power failure.
In general, the invention may be applied to all apparatus in which sequential programmes are controlled by a solid-state processor and whose cost price does not justify the use of cyclic and permanent control means, for example domestic appliances such as laundry or dish-wash-~5 ing machines, cooking appliances etc.
In appliances, equipped with electromechanical programming devices, the instantaneous setting in the case of a power failure is preserved but in the case of appli-ances whose operation is controlled by a solid-state pro-30 cessor a power failure results in the destruction of thedata identifying the programme in progress; when the power-supply voltage is restored this means that the programme of the apparatus is restarted without knowing exactly which part of the programme has already been carried out. This 35 problem is overcome by providing the apparatus with a data-salvaging device to which the data necessary for the subsequent continuation of the programme are transferred and in which they are stored as soon as a failure occurs.
~;Sr~ !~
~ '3 French Paten-t Specification no. 2,297,273 des-cribes an electronically controlled washing machine equipped with a data-salvaging device. If the power fail-ure is brief (approximately 8 seconds) the programme is 5 continued at the point where it was interrupted, employing the salvaged data. If the interruption is longer an accum-ulator maintains the logic circuit in the state which it occupied at the instant of failure. When power is restored the memory devices are re-activated in the reset state.
However, in certain cases the use of the saved data for exactly reprogramming the apparatus at the point of the programme where the power failure occurred may be undesirable for said apparatus or Eor objects to be treated by said apparatus. Indeed, the absence or incorrect value 15 of certain physical parameters at the instant that power is restored, compared with the values which would normally occur, may sometimes impair a correct execution of the programme. When proceeding as described in the event of a longer power failure, the user himself should select a new 20 programme when the power is restored.
United States Patent Specification no. 3,959,778 describes a device for salvaging processor data. When a power failure is detected during execution of a programme, the data present in the main memory is transferred to a 25 peripheral and non-volatile memory.
However, the device only comprises means for detecting a power failure, but does not comprise means for organizing the restarting process at the instant that power is restored.
It is an object of the invention to provide a method where the apparatus itself determines whether the interrupted programmed routine is to be stopped or con-tinued when the power is restored and in case of continu-ation determined under which condition restarting may be 35 effected.
The method of the invention comprises a power restoration subroutine. This power restoration subroutine determines whether or not the interrupted selected routine ,f~
3~
P~F 80 517 C 3 may be restarted after power restoration, and in case that a restart is allowed, determines the restart conditions.
The object of the invention is achieved in that the apparatus is equipped with a control device comprising means for organizing the restarting process.
An apparatus in accordance with the invention comprises - sensing means for sensing said physical parameter - a control device annexed to said processor, for, in con-junction with the processor controlling the operations incase of power failure and in case of power restoration.
In this respect "physical parameter" is to be understood to mean for example a temperature, pressure, volume, voltage etc. as well as electrical binary logic states.
The method in accordance withthe invention equal.ly applies to maahines whose processor is programmed in accor-dance with a "functional" mode or a "sequential" mode.
A "functional" mode is to be understood to mean a programming whose progress is primarily conditioned by the measurement of physical parameters to be taken into account for a correct execution of an operation, for exam-ple in a washing machine operated by a solid-state pro-cessor the measurement of the turbidity, which prevents the programme from proceeding as long as the rinsing water is not perfectly clear.
A "sequential" mode is to be understood to mean a programming which divides the programme into a certain number of basic "steps", which are used completely or partly, depending on the desired programme, and whose exe-cution is mainly governed by requirements with respect to time.
Suitably, the programme is not continued if the duration of the power supply failure is greater than a reference value. In most cases restarting an interrupted programme after a prolonged failure would make no sense.
For example, it makes no sense to continue baking a load in a baking appliance if the baking process has been inter-3~P~F 80 517 C 4 rupted or more than one hour~ Suitably, the length of the power supply failure is measured by sensing a residual voltage across an auxiliary power hold source which powers a memory in which data identiEying the interrupted pro-gramme are preserved during said failure, which auxiliarypower hold source is charged prior to the power failure and is gradually discharged during said failure. The power consumed by the memory during the failure is a measure of the duration of the failure. Suitably, at least one physical parameter defining the instantaneous state of the apparatus is measured after power restoration in response to a command from the processor, the measured value being compared with a re~erence value which corres-ponds to the phase of the selected programme to which the apparatus has proceeded. Thus, the processor has a cri-terion for the instantaneous state of the machine, in order to determine the conditions for restarting.
Suitably, the detection means comprise compara-tor circuits which in response to the result ofacomparison between two voltages generates signals whose level corres-ponds to a specific position of the elements which receive said signals. Said elements are then blocked or activated.
The invention also ensures that auxiliary func-tions are performed which allow for most of the transient effects w~ich may occur during a power failure and thereby ensures maximum operational security of the apparatus employing the method.
By design of the apparatus, the time during which the salvaged data can be preserved essentially depends on the auxiliary power hold source which powers the shift register. By a suitable choice of said source said duration may be varied as a function of the operation to be performed by the appliance, enabling a preservation time of several days to be obtained by means of a single high-quality electrolytic capacitor. Such a long duration which is superfluous in the event of an accidental power failure, may be useful in certain cases in which the power to the appliance is intentionally interrupted for reasons of safety or economy.
The invention will now be described in more detail with reference to the accompanying drawing.
Flg. 1 representsthe block diagram of an appara-tus employing the method in accordance with the invention.
Fig~ 2 represents the block cliagram of a micro-processor and its power supply, equipped with control cir-cuitry in accordance with the invention.
Figs. 3a to 3i are voltage levels as a function of time at different points of the diagram of Fig. 1.
Fig. 4 represents a flow chart of an example of a power outage subroutine.
Fig. 5 represents a flow chart of an example of a power restoration subroutine.
Referring now to Fig. 1I via a double circuit breaker 103, two mains terminals 101 and 102 are connected to a control unit 104 and to the commoned first terminals of some elements which are characteristic of the type and function of the apparatus. Thus, in for example a washing machine the element 105 will be an immersion heater, the element 106 a motor, and the elements 108 and 107 two elec-tric valves. The second terminals of the elements are con-nected to the control unit.
At 1 and 2, after the switch 103, the mains is also connected to a rectifier and stabiliser unit 109 which supplies two positive direct voltages Vbl and Vb2, whose common negative pole is connected to earth.
Via its input channels 112, 113, 114 and 115 a multiplexer circuit 111 receives the data necessary for the execution of the programme, for example the manual selec-tion of a programme via the line 112 and, depending on the type and function of the apparatus in question, data re~lat-ing to the value of physical quantities such as for example the temperature or others via the other channels.
An output channel of the multiplexer 111 is con-nected to a microprocessor 15 to which a read-only memory 160 is connected, said microprocessor comprising two out-put channels which are respectively connected to the ~ ;t3~
PEII~` ~0 Sl7 C 6 10-2-l981 control uni-t -lOI~ ancl to a display unit 117.
The positive supE~L~ term:inals of the m~ tiple~er t'l'l, of the microprocessor 15, of the memory 1'vO and o~ the display unit 117 are connected to a conclLlctor 1-l, which i9 at the volt,Lge Vbl, wllilst -the rLQ gative power sup-ply ter-minals are connectecl to earth.
The microprocessor l~ is also coI~-leeted to t'he control dev:ice l i~ via a two-way ehannel. 'rhe cont,rol de-vice is connec-ted to the earthirLg point via a swi-tch l ~1, 10 ~hich is mechc~icall7 couplacl -to the double circui-t-braker 103.
The microprocessor 15 in conjunction with -the memory l60 receives instructions and data v-La the multi-ple~er 'I 11 and supplies sequen-tial instruc-tions to -the control unit 104 for aetivating tho ele!nellts w]1ich are eharaeteristie o:L` the type ~nd t'urlet:ion o~ l;he applr~-tlls.
In parallel therer~Lth, the nllcroproeessor 15 sends instructiorls to the ~mit 1l7 whieh cl:isplL,vs t'he nature of` the selectecl progra~ e arld -tho prog~;r~s3 th~r~oP.
One of the principl t`lmct:ions o~ the control unit 119 is to protect data iden-tifying an in-terruptecL
routine, said unit being ~requently re:~errec1 -to as salvage unit or device.
In the event o~ a power ~ailure the salvage 25 ~mit 119 detects a difference in -the rate at which -the voltage aeross the eonduetors 11 and 120 deereases and immediately sends an instruction to the microprocessor to transfer the data of the programme i.Il progress before the voltage Vb1 has decreased below a speci~ic lower limit 30 value~
During -the ~ailure condition, the data is stocked in a memory of -the UIIit 119, ~hich memory is for e~ample of the CMOS type with a very low power cvnsumption and is energized by an au~iliary po~.rer hold source, for e~ample 35 a s-torage capaci-tor which replaces the soL~ce Vbl.
When the power returns the duratlon of the power failure is measured; indeed, independentLy of -t}le problem of salvaging the data, i-t may be desirable to inhibit ~1 1 t ~
P~[F ~O ~l7 C 7 lO-~-l9~1 contintLtLtion o~ the p:rogranlme after a po~er failure which has persis-ted too long, be it only for the reason that the appara-tus rnay be wi-tllotlt supervlsioll at the mornent that the power return3. I:~ a storage capacitor is used ns au~:illary power hold source, the dll-r.-L-t-i.on o~ the failu:re :is fourLd by measuri.ng -the :residual voltage across the capacltor, which WclS fully chargecl bci`ore the occurrence of the fa:ilure~
sa.id capaci.tor being suitably t:he ca.pacitor which energizes the salvage memory incorporated i.n -the unit Il9. The clura-tion of a power fa.ilure may also be derived from the read-ing of a counter, which i.s actuated when tne power failure coMmences and which coun-ts the number of clock pLllses.
The duratior after which it is desirab:Le to in-hibit continuation may also depend on the point to which lS -the programme has proceecled at -the ins-ta.nt of :~ai:Lurt? c~.Ld on -the natllre o~ the progralllme l~`or e.~amp:Le, :in a coolc:ing appliance, cooking of tl d:ish of` v~getables nltlr bo reswJllQcl after an i.nterrupt:ioll o~ a qualter o:~ an hour, ~1ri.Lst such a cluration woul(l be d:isast.Lotls ~:tlQI:L bal;:i.rlg a brotLd. [.:l 20 said duratiorl i9 sma:Lle.r than a p-redeterm:i.ned vaLne, varioLIs physical paramett~rs clefinin~ the instL~ntaneolls state of the t-lpparatus are measured by the mi.croproceSsol. The micropro-cessor compares these physi.cal paralntcrs with re~`erence values cor:cespondi.ng to the phase o~ the progranlme to which 25 -the apparatus has proceeded. The result of this compar~ison determines the conditions for Gontinuation of the interrup-ted programme flowever~ if the resul-t of -the comparison shows that the conditions for continuation of the programme are 30 not satisfied, the microprocessor will not proceed with tlle progrram~e and resets the apparatus to the s-tate e~isting at the beginning o~ each programme.
I~hen power is restored, a code is de-tected in the data received and re-turned by the salvage U~lit 119, an in-35 correct code indicating an incorredt da-ta salvage which in-hi~i-ts the continuation of the programme in prog:ress, sai.d code being cons-tituted by a first word entered into a shift register which is kept energised dur.LIlg the power fail-lre l..l.ti~
~:~1'F ~O ~1~ C 8 '.0-2-'1981 and WhiCll C0113 titutes the salvage memory of the unit 1'19.
If -the result of -the compari.son of t'he s-tate of the appara-tus with the r~ference values shows that the COIl-d:itions for a continuat:ion ol` the prograMn1e are no-t 9a-tis-fied, the micro-processo:r proceeds -to restore them Sorne of said conditions may be physical parame-tcrs, in which case the microprocessor al:1.ows thc prog-ramme to continue aIld s-i-Multaneously replaces sa:Ld physical parame-ters by their re-ference values in conformity wi-th -the said prog:ramme; for e~ample in a washing machine whose operation is controlled b~ a microprocessor, the microprocessor, after po~er restor-ation, instructs the temperature of the washing liq~Lid to be r~easured and compares said tempera-ture with the reference value corresponding to the phase of -the washing programrne 15 which the Machine has reached and, if the mcasured tempera-ture is insuffi.cien-t, g:ives an Lnstructiorl to rQheat -the washing liq~Li.d allcl at -the same ti1ne contin~LQ the p1~o~J~r~nmme.
The microprocessors :i.n cer-tain ty;pes o:L` apparatus aro program1necl :in pro~g.ralr11n~ ~s-teps~ in analogy wi.th the 20 operat:ion of electromechIl:ical prograrnrr1:i.rlg devicQs en1ployed .in a previous generat:ion of apparatus.
In -this -type of apparatus the total operat:irlg sequence is divided into a certain num'ber of 'basic "steps~' each corresponding to the e~ecution of a function and pro-25 ceeding depencling various requirements; a cer-tain nurnber of these "s-teps", which are differently situated in the sequen-ce~ ma~ be "skipped" depending on the nature of the pro-gramme selected b~r the user.
~'or the use of -the method in accordance with the 30 invention in such an apparatus when it is found that after comparison of the s-tate of the apparatus with -the reference values the conditions for a continuation the programme are not satis~ied, the microprocessor sets the machine to -the state corresponding to a programme step which precedes the 35 step during which the power failure occurred.
~ ig. 2, whose reference numerals correspond to -those u~ed in Fig. 1, represents the control device 119 in accordance w~th the invention within a dashed frame ~IIF ~O 517 C 9 IO~
The t~ro maills terIlllnals 1 and 2 are respectively cor~lected to t-he commonecl anodes md eathodes of t-wo pairs of rectifie- diocles 3, 4 and 5, 6.
The commoned cathodes oE` -the d-iodes 3 and 5 are connectecl to a positive L:ine 7 of a non-stabilizecl voltage supply~ whils-t the co~Imoned anodes o~ the diodes ~ and 6 are conneeted to a commoll earth, a smoothlng ea-pac:i-tar 9 bein~
ineluded between the line 7 and ear-th.
The line7 is eo~nec-ted -to -the input ot` a vol-tage iO 3tahili3ing eireuit 10, whose outpu-t is co~lectecl-to a po-sitive line 11 carrying a stabiIised voltage Vb, a smoothing capacitor 12 being ineluded between the line 11 ~nd earth.
Two power supply pins 13 and 1~ of a microprocessor 15 are respectively connected to the line I1 and to the 15 ear-th, whilst an output pin 16 of said ~Iicroproc~ssor is connected to the base o~ a ~NP switching traIlsistor IS ~ia a resistor 17~ a resis-tor I~ and a capacitor 20 1~sing ar-ranged between said tra}lsistor .~ncl the line '1'1 .
TIle eo:Lleotor o:~ the trallsistor I~ ix comlectod to 20 the anode oE` an isola-ting diod-3 2I, whose catho(le is connec-ted -to a positi~e line 22, a storage capaci-tor 23 being in-cluded between said positive line and the earthing poin-t g~
which storage capacitor is shunted by a switch 2~ which is mechanically coupled -to the t'star-t-stop" switch of the 25 app-lratus.
The positive power-supply pin o~ a shi~-t regis-ter 25 is connected to the line 22 and tne negati~e power-suppl~J
pin to the earth; tne "data-input" o~ the re~ister 25 is con-nected to -the output of an ~Nn~-gate 26, of whicll one input 30 is connected to a "general da-ta" output pin 27 O-r the micro-processor 15, whils-t -the "data outpu-t" of said register is connec-ted to an input o~ an "~D" gate 2g, l~hose outpu-t is connected to an input pin 2~ o~ the microprocessor I5.
Two ~Icoding~ O~ltput pins 3O, 31 and one clocl~
3~ output pin 32 of the microprocessor 15 are connected to the corresponding input pins o~ a dei~lultiple~er circuit 33, whose power-supply pins are respec-tively connected -to the line 11 and the earth.
- . .
~' '-.
~ 35 ~ ~
pll~? S~ 5l7 C. IO IO ~-198l One of the "clock" ou-tpu-ts Or tlle demultiple.~er 33 is eonnected -to an inpu-t of cm "~D"gate 34, w'rlo3e out-put :is conr~ected to the "cloclc" input o:~ the :regis-ter 25, a rssistor 35 being ;nclucLed '~etween t'he OutpLlt of said gate and the earth, '~he ~node of an isolatill~; diode 36 is connected to the li.ne 'I -I ~ l~hilst the cathodc is comlec-te(-l to a posi.-tive line 37, a storage capaci-tor 38 'being incL-ucLc,~d between said posi-tive line ancl the earth.
The negative inpu-t of the first comparator circuit 39 is connected -to a resistor bridge 4O, 41 included between the line 37 and the aarth, Irhilst the posi-tive input is con-nected to a further resis-tor b:Lidge 42, 43 included be-tween the line 7 and the earth/
The output o:~ the colrlpara-tor 39, w'll:ic:lL.is connec-ted to an "interrupt" lnpu-t pin L~ of -tho In:icroproeessor '15 is connected -to tllc l.ine 37 V.La a res-istor l~5 ancL-L;o L.llo posi-tivc inpllt vla a resi.st;or 46.
The poslti.ve :input of " seconcL eornparator c:Lrcll:it 20 44 i~ connected to a first resistor bricLge 55, 56 :included 'between the line 11 and the eart:hing -point S, whilst the negative input is collnected -to a second resi.s-tor bridge 57, 58 included between the line 37 and the earth.
The output of tl-e comparator 54, which is decouplecl 25 frorn ear-th by means of a capac:itor 59, is connected to the line 11 via a resistor ~O~ to the cont:rol input o~ the elec-tronic switch 50 and to the second inputs of the gates 26, 28 and 3L~.
The negative input of a third comparator clreuit 30 47 is eomlected to a resistor bridge 49~ 4~ included between the line 37 and the earth, whilst the positive input is connected to the line 22 via an eleetronic switch 5O, a re-sistor 51 ~eing included ~etween said pos~tive inpu-t and the earth.
The output of the comparator 47 is connected to a ~Ivalidation~ input 52 of the microprocessor 15 and via a resistor 53 to -the line 37.
A eapacitor 61 is included be-tlveen a reset input 3~ j~'7 P~ SO 5-17 ~ "-'19~-1 6~ of the microprocessor 15 and the earth, s.lid ca-paci-tor being bypassecl by the emitter-collec-tor pa-th of a PNP tran-sistor 63, wnose base is connec-tecl -to the O~ltput of the com-~parator 54 In or~er to simpl:il'y t;he :~ollowins descrip-tion, only the connect-ions o-f tlle microprocessor 15 which c~irectly rela-te to the da-~;a-salvage device in accordaIlce with the in-vention are sho~m, to the e~clusioll of other connec-tions re-lating to the cLata inputs ancl to the outputs for instructions which are specific o~ the apparatus in which it is incorpor-ated, which may be a laundry or dish-~-rashing machine, a cooking appliance etc.
The function of the control device eMployed in the apparatus in accorclance with -the invention .is -to salvage the data stored :i.n t'he rnicroprocossor 15 at -the i.nstz1rlt tllat the currellt on the n1fins term:Lnals 1 ancl '-' :is inte.rrupt~3d.
~ eferr:ing no~ to Figs. 3a ancl '3'b, wh:icll respect:ive ly represcl-lL; -the voltz.~ es O:tl th(3 l:ine 7 ~VR) arlcL on the li.ne '11 (V'b)~ it w-il~ e seen tha-t at L;lle :illS tant -t.1 at 20 which the failure occu:rs the voltage VR 'begills1:to dec:rez-1.se, whilst the vol-tage V'b remains stable until the :Lns-tant -t3 corresponding to -that value of VR which no .Longer perrt1i-ts stabilisation; this is achieved 'by giving -the smoothing capacitor 12 a higher value than the smGotl~ing capacitGr g.
In the case of a nominal supply vGl-tage o-f 5 V
for -the microprocessor 15, this voltage may decrease down to 4.5 V without impairing -the microprocessor operat-ion;
thus between the beginning of the fail~lre and -the critical threshold of the voltage Vb a time interval of a few m:illi-30 seconds is availa'ble which is utilized by the data-~salvage device in acco:rdance with the inveIltion.
During normal operation the voltage applied -to the posi-tive inpu-t of the cGmparator 39 fro1n the line 7 is higller -than that of the negative inpu-t, which is de-termined 35 by the resis-tor bridge 4O, 41 via the line 11; in th:is situ-ation the outpu-t o~ -the comparator 39 supplies a "high"
level to the "interrupt" input 44 of the microprocessor 15 (Fig. 3c).
1 ~ tj~3~''7 P~Ll~` SO 5'l7 ~ 1~ 'lO-~-l9$1 In the case of a po~er failure -the ~oltage VR on -the Line ,' begins to c1ecrease at the instant tl (Fig. 3a) and, when it reaches 8 V at the instant t2, the output of the compara-tor 3~ changes -to a "lo-~" level ~Fig. 3c) which, ~hen applied to t~Le ,nput ~l4 of the nlicroprocessor, inter-rupts -the normal progralnllle of' said rnicroprocessor in orcler -to replace i-t 'by a po~er--ontage subro1ltlno. This sub-rou-tine allot~s the clock pulses to be appliecl fron1 t'he output 32 to t'he ga-te 34 v~a -the cLenlult:iple~er 33 by me-ns of` a logic code OIl the ou-tputs 3O and 31 and the l'outp1ltl' of -thLe data necessary for a possible con-tinua-tion of the normal mode of operation ViQ the pin 27.
During t'his time the gates 2~, 2~ and 31~ ar0 open and the si~itch 5O is closed, -their control inputs being "high" (Fig. 3e) ot~ing to the stal;e of -the output of the comparator 547t~hose vol-tage Ol-L the pos-it:ivo :klp~-~t is h:icq;hor than voltage on the naga-tive input; ln this s:it~ L-tlon t'ho clock pulses are received fI`OI(I -the gale 31~, c~using thQ r~-gist;er ~5 to be :loadod t~:ith the data issul~ ron1 thc ~ato 20 26 (Fig. 3d).
4f-tier a -time interval nece3sary -L`or loaciing all the data into the re~ister 25~ ~hich in-terval is approxi-mately 35O/us, the "failure" subroutine of the nlicroprocess-or changes the logic code of tl1e ou-tpu-ts 3O and 31, and also 25 interrupts the loadlng operation; i-t is to be no-ted that for reasons of clarity this loading sequence ls considerably simplified in ~ig. 3c1, From the instant t3 (Fig. 3a) the voltage Vb on -the line 11 begins to decrease and ~1en i-t reaches -the 30 threshold of ~l.5 V the output of the comparator 5~ changes, thereby closing the gates 26, 2S and 3~, opening -the s-~i-tch 5~ and turning on the transis-tOr 63 ~R-~SET) (Fi~. 3e).
Si~ul-taneously~ the decrease of the voltage Vb on the line 11 causes the diocle 21 to be cut off, thereby main-35 taining the high charge of capacitor 23 as a re~sult of this,the C-MOS register 25 i~hich 1~as a ~ery lo~ power consum~-tion, remains energised withollt -the poss:bili-ty of an erro-neous read-out ia lts data inpu-ts and outputs ~ecause the PlIF .~) ~l7 C l3 ~ 2-'1981 ga-tes 26 and 2S are bloclced~
The clecrease o-f the voltage Vb on -the lirLe '1-1 als;>
ca~lscs tlhe diode 36 to 'be cut of-,, which for a certain time inter~al maintains the chLIrge of -the capaci-tor 3~ hicl1 cnergi~es the comparators 39, !l7 ancL 5~ via -the line 37.
When the power :i9 restore.l -t;ho voltage V~ at the ins-tant tL~ (F:ig. 3a) is surficie}1-t to enab1e thc vol-tage Vb to increase agclin -to ~.5 V (Fig. 3b) ~nd agai1l energi,ze the comparators, which l'irst of all causes -the gates 26, 28 and 34 to be opened .~ld -the swi-tch 5O to be closed (Fig. 3e).
However~ the transistor 18 is held in -t'he cut-off state by a posit:ive voltage applied to its base from the OLltpUt l6 of the microprocessor -15 (Fig~ 3f); in this si-tuation the '~
capacitor 23 retains :Lts charging voltage, whicll it held at thc instan-t that po~er WclS restorecl, this resid~ l vo].tal~7e 'heing applied to the posl-ti~t3 inp~lt; Or -t;'L~e co~ ral;or /17 via the 9 Wi tch 5O.
The va~ e of the resiclua;L voli;c~ e of t'he cnp~ci-tor 23 .at thc i~sl;an-t; that po~er is rt~stoL~ecl Or oourse clo-~ pends on the chlr~ti.ol1 of the powe-r failure; 'howe~e:r, there is a thresholcl value of t'he suppl~ voltage o~ -the register 25 below which -the preservation o~ the storecl da-ta is no longer guaranteed, for example 3 ~.
If` the residual ~oltage a-t -the instant -that th0 25 power suppl~r is restored is higher t~an said critical value (dotted lines Fig. 3g)~ the ou-tput of the cornparator 47 will supply a high le~el (~ig. 3h) to -t'he "valida-tion" input 52 of the microprocessor 15 at the instant tl~, which enables a transfer o-f the salvaged data con-tained in the register 30 25 to -the microprocessor 15 by way of the input terminal 29 via the gate 28 (Fig. 3d).
In the case that the value of the residual -~ol-tage is snaller than the threshold level (do-tted line Fig. 3g) the output o-f the cormparator ~7 will rermain low" (Fig. 3i) 35 and the microprocessor is set to a stancl-by posi-tion in anticipa-tion of` re-programming.
The instant at which -the choice is made between these two possibilities is the instan-t t5 (Fig. 3a~ a-t ~hich l .~.ti'.~5~7 Pl~ ~ 5l7 C 1l~ 10-2-19~1 the OUtpllt of the comparator 39 again sllpplies a "high"
level -to -the "interrupt" inpu-t 44 of the m croprocessor;
therefore, it is of importance that the transis-tor 18 is still cut of'f at this instant, which is realised 'by delaying th.e :instant at which the signal appears on the O~ltptlt 16 o~' the microprocessor which turns on trans:Lstor -18 ~Fig. 3f), which signal enables capacitor 23 to be rechargecl.
Steps are taken in order to cope wi-th certain situations which rmay ocour, thus) after the registers have 10 been loadecl~ the microprocessor 15 rerllains in a waiting loop Or appro~imately one second if normal operation could be restored in the case of' a mains voltage decrease which i5 too slow.
Equally~ in order to allow f'or an erroneous power 15 re-turn, the re-trans~er of the data stored i~ the register to the microprocossor is also ef:E~ectecl afte:r a w~l:ti.ng loop of` OllO second ~E'ter power has boen ~estored and berore t}lC vol-tage ~b ~eeding the microprocessor has reached a suf`:E':icient 20 valuc~ the output level on pin ~l~ rnay t;~e:ro:~ore assume in-correct values; in orclcr to preol.ude partial recharging of : the capacito:r 23 by ~ accidental turn-on o~ tr~lsist;o:r 18 before the value of the residual voltage has been taken into account, said transistor i9 kept cut-off b~r the in-25 clusion of -the Gapacitor 20, which provides a positive base bias whlle the voltage Vb i.s increasing.
The gate 34, ~hich is blocked when the voltage ~b :~ is lower th~n 4.5 ~ prevents any transfer of spurious sig-nals to the clock input of the register 25, which s.ignals 30 may affect the content of said register and which result from random operation of the microprocessor l5 and of the de-multiplexer 33 i.Tl the case of an insufficient supply voltage.
The switch 24 for short-circuiting the capacitor 23 is mechanicalLy coupled to the common "start-stop" switch ; 35 (not sho~n) of the apparatus, i~ such a way that it i9 closed after the terminals 1 and 2 are no longer energized and ~hich opens before said -terminals are connecbed -to the mains, ln thls way it is avoided -tha-t the device responds ~ ~ ' ;' ' ' ' ' ; ' . . .
.~ ' .
~ti~3'~
PHI;` SO 5 17 c I5 10-2-1981 -to a ~ollln-tary power cu-t-of r 0:~ -the c1pp~ra tus in the same ~iray as to an acc idental m~ins E)owe~ f`ailure .
Tlle use of the cont:roL method and o:f tl1e da-ta-salvage device in acco:rclance ~ri th t:he invcn-ti.on i.s iLlus-5 trat;ec1 by ~aS~ O:r e~amp~ y its ~I ;e ~in a lalLnd:ry ~raslLinmachine whose opera-tion :i.s con-t:ro.Llo~l by a mi.c:roproCeS50l .
Tlle m:icroproc2ssor ( l5) usecL :is corlmlerc:i all-~avai.lable frorn the Signetics company under the reference S035, -the demultiple~er (33) beirlg o:f tlLe type l174 LS 139"
10 al~d -the shi:ft reg~ister ~25) being :formecl by a double 7'4006"
f r o rn -the s am e c omp any .
Table I, by way of e~amplé:~ lists all -the programme "steps " o:E a washing maclline whose microprocessor is pro-grammed ~'s tep by s tep", ~`
Tab:Le I
No . of s-teps F~ulc tlons 1~1 filling s t:ir:r Ln~;
pr~ rash i.ng ~ .~ he a ting-s tl.r:r i.ng ¦ 3 s tirring ~4 dral ning-s tirr ing ~5 fi.Lling~sti:rring ¦ 6 heati.ng 7 s tirri.ng ~5 washing ~1 ~ "
t 2 replellishing ~13 draining-s tirring ls t rinseS14 :Eilling-stirring Ll 5 draining-s tirring 16 -filling 17 :~i:Lling+acld:ition detergerlt 2nd rinse lS sti.rring 19 draining filling-stirring 21 deteckion of motor direction 3rd rinse 22 draining * fast rotation 23 spindrying 24 filling 4th rinse 25 filling + softener addition
The invention relates to a method of operating an apparatus by means of a solid-state processor which holds a plurality of selectable programmed routines, which apparatus is powered by an electric ma:ins, and during a 5 conditional operation controlling, within a limited volume of space, at least one physical parameter through a pre-determined range of values in the case of a power failure during execution of a selected routine, said method com-prising a plurality of subroutines for the salvage of 10 identifier data associated with said selected routine interrupted by said failure.
The invention also relates to an apparatus oper-ated by a solid-state processor and powered by an elec-tric mains in which during a conditional operation, within 15 a predetermined volume of space, at least one physical parameter is controlled through a predetermined range o values, said processor holding a plurality of programmed routines, a~ least one of said routines being interrupt-able in case of power failure.
In general, the invention may be applied to all apparatus in which sequential programmes are controlled by a solid-state processor and whose cost price does not justify the use of cyclic and permanent control means, for example domestic appliances such as laundry or dish-wash-~5 ing machines, cooking appliances etc.
In appliances, equipped with electromechanical programming devices, the instantaneous setting in the case of a power failure is preserved but in the case of appli-ances whose operation is controlled by a solid-state pro-30 cessor a power failure results in the destruction of thedata identifying the programme in progress; when the power-supply voltage is restored this means that the programme of the apparatus is restarted without knowing exactly which part of the programme has already been carried out. This 35 problem is overcome by providing the apparatus with a data-salvaging device to which the data necessary for the subsequent continuation of the programme are transferred and in which they are stored as soon as a failure occurs.
~;Sr~ !~
~ '3 French Paten-t Specification no. 2,297,273 des-cribes an electronically controlled washing machine equipped with a data-salvaging device. If the power fail-ure is brief (approximately 8 seconds) the programme is 5 continued at the point where it was interrupted, employing the salvaged data. If the interruption is longer an accum-ulator maintains the logic circuit in the state which it occupied at the instant of failure. When power is restored the memory devices are re-activated in the reset state.
However, in certain cases the use of the saved data for exactly reprogramming the apparatus at the point of the programme where the power failure occurred may be undesirable for said apparatus or Eor objects to be treated by said apparatus. Indeed, the absence or incorrect value 15 of certain physical parameters at the instant that power is restored, compared with the values which would normally occur, may sometimes impair a correct execution of the programme. When proceeding as described in the event of a longer power failure, the user himself should select a new 20 programme when the power is restored.
United States Patent Specification no. 3,959,778 describes a device for salvaging processor data. When a power failure is detected during execution of a programme, the data present in the main memory is transferred to a 25 peripheral and non-volatile memory.
However, the device only comprises means for detecting a power failure, but does not comprise means for organizing the restarting process at the instant that power is restored.
It is an object of the invention to provide a method where the apparatus itself determines whether the interrupted programmed routine is to be stopped or con-tinued when the power is restored and in case of continu-ation determined under which condition restarting may be 35 effected.
The method of the invention comprises a power restoration subroutine. This power restoration subroutine determines whether or not the interrupted selected routine ,f~
3~
P~F 80 517 C 3 may be restarted after power restoration, and in case that a restart is allowed, determines the restart conditions.
The object of the invention is achieved in that the apparatus is equipped with a control device comprising means for organizing the restarting process.
An apparatus in accordance with the invention comprises - sensing means for sensing said physical parameter - a control device annexed to said processor, for, in con-junction with the processor controlling the operations incase of power failure and in case of power restoration.
In this respect "physical parameter" is to be understood to mean for example a temperature, pressure, volume, voltage etc. as well as electrical binary logic states.
The method in accordance withthe invention equal.ly applies to maahines whose processor is programmed in accor-dance with a "functional" mode or a "sequential" mode.
A "functional" mode is to be understood to mean a programming whose progress is primarily conditioned by the measurement of physical parameters to be taken into account for a correct execution of an operation, for exam-ple in a washing machine operated by a solid-state pro-cessor the measurement of the turbidity, which prevents the programme from proceeding as long as the rinsing water is not perfectly clear.
A "sequential" mode is to be understood to mean a programming which divides the programme into a certain number of basic "steps", which are used completely or partly, depending on the desired programme, and whose exe-cution is mainly governed by requirements with respect to time.
Suitably, the programme is not continued if the duration of the power supply failure is greater than a reference value. In most cases restarting an interrupted programme after a prolonged failure would make no sense.
For example, it makes no sense to continue baking a load in a baking appliance if the baking process has been inter-3~P~F 80 517 C 4 rupted or more than one hour~ Suitably, the length of the power supply failure is measured by sensing a residual voltage across an auxiliary power hold source which powers a memory in which data identiEying the interrupted pro-gramme are preserved during said failure, which auxiliarypower hold source is charged prior to the power failure and is gradually discharged during said failure. The power consumed by the memory during the failure is a measure of the duration of the failure. Suitably, at least one physical parameter defining the instantaneous state of the apparatus is measured after power restoration in response to a command from the processor, the measured value being compared with a re~erence value which corres-ponds to the phase of the selected programme to which the apparatus has proceeded. Thus, the processor has a cri-terion for the instantaneous state of the machine, in order to determine the conditions for restarting.
Suitably, the detection means comprise compara-tor circuits which in response to the result ofacomparison between two voltages generates signals whose level corres-ponds to a specific position of the elements which receive said signals. Said elements are then blocked or activated.
The invention also ensures that auxiliary func-tions are performed which allow for most of the transient effects w~ich may occur during a power failure and thereby ensures maximum operational security of the apparatus employing the method.
By design of the apparatus, the time during which the salvaged data can be preserved essentially depends on the auxiliary power hold source which powers the shift register. By a suitable choice of said source said duration may be varied as a function of the operation to be performed by the appliance, enabling a preservation time of several days to be obtained by means of a single high-quality electrolytic capacitor. Such a long duration which is superfluous in the event of an accidental power failure, may be useful in certain cases in which the power to the appliance is intentionally interrupted for reasons of safety or economy.
The invention will now be described in more detail with reference to the accompanying drawing.
Flg. 1 representsthe block diagram of an appara-tus employing the method in accordance with the invention.
Fig~ 2 represents the block cliagram of a micro-processor and its power supply, equipped with control cir-cuitry in accordance with the invention.
Figs. 3a to 3i are voltage levels as a function of time at different points of the diagram of Fig. 1.
Fig. 4 represents a flow chart of an example of a power outage subroutine.
Fig. 5 represents a flow chart of an example of a power restoration subroutine.
Referring now to Fig. 1I via a double circuit breaker 103, two mains terminals 101 and 102 are connected to a control unit 104 and to the commoned first terminals of some elements which are characteristic of the type and function of the apparatus. Thus, in for example a washing machine the element 105 will be an immersion heater, the element 106 a motor, and the elements 108 and 107 two elec-tric valves. The second terminals of the elements are con-nected to the control unit.
At 1 and 2, after the switch 103, the mains is also connected to a rectifier and stabiliser unit 109 which supplies two positive direct voltages Vbl and Vb2, whose common negative pole is connected to earth.
Via its input channels 112, 113, 114 and 115 a multiplexer circuit 111 receives the data necessary for the execution of the programme, for example the manual selec-tion of a programme via the line 112 and, depending on the type and function of the apparatus in question, data re~lat-ing to the value of physical quantities such as for example the temperature or others via the other channels.
An output channel of the multiplexer 111 is con-nected to a microprocessor 15 to which a read-only memory 160 is connected, said microprocessor comprising two out-put channels which are respectively connected to the ~ ;t3~
PEII~` ~0 Sl7 C 6 10-2-l981 control uni-t -lOI~ ancl to a display unit 117.
The positive supE~L~ term:inals of the m~ tiple~er t'l'l, of the microprocessor 15, of the memory 1'vO and o~ the display unit 117 are connected to a conclLlctor 1-l, which i9 at the volt,Lge Vbl, wllilst -the rLQ gative power sup-ply ter-minals are connectecl to earth.
The microprocessor l~ is also coI~-leeted to t'he control dev:ice l i~ via a two-way ehannel. 'rhe cont,rol de-vice is connec-ted to the earthirLg point via a swi-tch l ~1, 10 ~hich is mechc~icall7 couplacl -to the double circui-t-braker 103.
The microprocessor 15 in conjunction with -the memory l60 receives instructions and data v-La the multi-ple~er 'I 11 and supplies sequen-tial instruc-tions to -the control unit 104 for aetivating tho ele!nellts w]1ich are eharaeteristie o:L` the type ~nd t'urlet:ion o~ l;he applr~-tlls.
In parallel therer~Lth, the nllcroproeessor 15 sends instructiorls to the ~mit 1l7 whieh cl:isplL,vs t'he nature of` the selectecl progra~ e arld -tho prog~;r~s3 th~r~oP.
One of the principl t`lmct:ions o~ the control unit 119 is to protect data iden-tifying an in-terruptecL
routine, said unit being ~requently re:~errec1 -to as salvage unit or device.
In the event o~ a power ~ailure the salvage 25 ~mit 119 detects a difference in -the rate at which -the voltage aeross the eonduetors 11 and 120 deereases and immediately sends an instruction to the microprocessor to transfer the data of the programme i.Il progress before the voltage Vb1 has decreased below a speci~ic lower limit 30 value~
During -the ~ailure condition, the data is stocked in a memory of -the UIIit 119, ~hich memory is for e~ample of the CMOS type with a very low power cvnsumption and is energized by an au~iliary po~.rer hold source, for e~ample 35 a s-torage capaci-tor which replaces the soL~ce Vbl.
When the power returns the duratlon of the power failure is measured; indeed, independentLy of -t}le problem of salvaging the data, i-t may be desirable to inhibit ~1 1 t ~
P~[F ~O ~l7 C 7 lO-~-l9~1 contintLtLtion o~ the p:rogranlme after a po~er failure which has persis-ted too long, be it only for the reason that the appara-tus rnay be wi-tllotlt supervlsioll at the mornent that the power return3. I:~ a storage capacitor is used ns au~:illary power hold source, the dll-r.-L-t-i.on o~ the failu:re :is fourLd by measuri.ng -the :residual voltage across the capacltor, which WclS fully chargecl bci`ore the occurrence of the fa:ilure~
sa.id capaci.tor being suitably t:he ca.pacitor which energizes the salvage memory incorporated i.n -the unit Il9. The clura-tion of a power fa.ilure may also be derived from the read-ing of a counter, which i.s actuated when tne power failure coMmences and which coun-ts the number of clock pLllses.
The duratior after which it is desirab:Le to in-hibit continuation may also depend on the point to which lS -the programme has proceecled at -the ins-ta.nt of :~ai:Lurt? c~.Ld on -the natllre o~ the progralllme l~`or e.~amp:Le, :in a coolc:ing appliance, cooking of tl d:ish of` v~getables nltlr bo reswJllQcl after an i.nterrupt:ioll o~ a qualter o:~ an hour, ~1ri.Lst such a cluration woul(l be d:isast.Lotls ~:tlQI:L bal;:i.rlg a brotLd. [.:l 20 said duratiorl i9 sma:Lle.r than a p-redeterm:i.ned vaLne, varioLIs physical paramett~rs clefinin~ the instL~ntaneolls state of the t-lpparatus are measured by the mi.croproceSsol. The micropro-cessor compares these physi.cal paralntcrs with re~`erence values cor:cespondi.ng to the phase o~ the progranlme to which 25 -the apparatus has proceeded. The result of this compar~ison determines the conditions for Gontinuation of the interrup-ted programme flowever~ if the resul-t of -the comparison shows that the conditions for continuation of the programme are 30 not satisfied, the microprocessor will not proceed with tlle progrram~e and resets the apparatus to the s-tate e~isting at the beginning o~ each programme.
I~hen power is restored, a code is de-tected in the data received and re-turned by the salvage U~lit 119, an in-35 correct code indicating an incorredt da-ta salvage which in-hi~i-ts the continuation of the programme in prog:ress, sai.d code being cons-tituted by a first word entered into a shift register which is kept energised dur.LIlg the power fail-lre l..l.ti~
~:~1'F ~O ~1~ C 8 '.0-2-'1981 and WhiCll C0113 titutes the salvage memory of the unit 1'19.
If -the result of -the compari.son of t'he s-tate of the appara-tus with the r~ference values shows that the COIl-d:itions for a continuat:ion ol` the prograMn1e are no-t 9a-tis-fied, the micro-processo:r proceeds -to restore them Sorne of said conditions may be physical parame-tcrs, in which case the microprocessor al:1.ows thc prog-ramme to continue aIld s-i-Multaneously replaces sa:Ld physical parame-ters by their re-ference values in conformity wi-th -the said prog:ramme; for e~ample in a washing machine whose operation is controlled b~ a microprocessor, the microprocessor, after po~er restor-ation, instructs the temperature of the washing liq~Lid to be r~easured and compares said tempera-ture with the reference value corresponding to the phase of -the washing programrne 15 which the Machine has reached and, if the mcasured tempera-ture is insuffi.cien-t, g:ives an Lnstructiorl to rQheat -the washing liq~Li.d allcl at -the same ti1ne contin~LQ the p1~o~J~r~nmme.
The microprocessors :i.n cer-tain ty;pes o:L` apparatus aro program1necl :in pro~g.ralr11n~ ~s-teps~ in analogy wi.th the 20 operat:ion of electromechIl:ical prograrnrr1:i.rlg devicQs en1ployed .in a previous generat:ion of apparatus.
In -this -type of apparatus the total operat:irlg sequence is divided into a certain num'ber of 'basic "steps~' each corresponding to the e~ecution of a function and pro-25 ceeding depencling various requirements; a cer-tain nurnber of these "s-teps", which are differently situated in the sequen-ce~ ma~ be "skipped" depending on the nature of the pro-gramme selected b~r the user.
~'or the use of -the method in accordance with the 30 invention in such an apparatus when it is found that after comparison of the s-tate of the apparatus with -the reference values the conditions for a continuation the programme are not satis~ied, the microprocessor sets the machine to -the state corresponding to a programme step which precedes the 35 step during which the power failure occurred.
~ ig. 2, whose reference numerals correspond to -those u~ed in Fig. 1, represents the control device 119 in accordance w~th the invention within a dashed frame ~IIF ~O 517 C 9 IO~
The t~ro maills terIlllnals 1 and 2 are respectively cor~lected to t-he commonecl anodes md eathodes of t-wo pairs of rectifie- diocles 3, 4 and 5, 6.
The commoned cathodes oE` -the d-iodes 3 and 5 are connectecl to a positive L:ine 7 of a non-stabilizecl voltage supply~ whils-t the co~Imoned anodes o~ the diodes ~ and 6 are conneeted to a commoll earth, a smoothlng ea-pac:i-tar 9 bein~
ineluded between the line 7 and ear-th.
The line7 is eo~nec-ted -to -the input ot` a vol-tage iO 3tahili3ing eireuit 10, whose outpu-t is co~lectecl-to a po-sitive line 11 carrying a stabiIised voltage Vb, a smoothing capacitor 12 being ineluded between the line 11 ~nd earth.
Two power supply pins 13 and 1~ of a microprocessor 15 are respectively connected to the line I1 and to the 15 ear-th, whilst an output pin 16 of said ~Iicroproc~ssor is connected to the base o~ a ~NP switching traIlsistor IS ~ia a resistor 17~ a resis-tor I~ and a capacitor 20 1~sing ar-ranged between said tra}lsistor .~ncl the line '1'1 .
TIle eo:Lleotor o:~ the trallsistor I~ ix comlectod to 20 the anode oE` an isola-ting diod-3 2I, whose catho(le is connec-ted -to a positi~e line 22, a storage capaci-tor 23 being in-cluded between said positive line and the earthing poin-t g~
which storage capacitor is shunted by a switch 2~ which is mechanically coupled -to the t'star-t-stop" switch of the 25 app-lratus.
The positive power-supply pin o~ a shi~-t regis-ter 25 is connected to the line 22 and tne negati~e power-suppl~J
pin to the earth; tne "data-input" o~ the re~ister 25 is con-nected to -the output of an ~Nn~-gate 26, of whicll one input 30 is connected to a "general da-ta" output pin 27 O-r the micro-processor 15, whils-t -the "data outpu-t" of said register is connec-ted to an input o~ an "~D" gate 2g, l~hose outpu-t is connected to an input pin 2~ o~ the microprocessor I5.
Two ~Icoding~ O~ltput pins 3O, 31 and one clocl~
3~ output pin 32 of the microprocessor 15 are connected to the corresponding input pins o~ a dei~lultiple~er circuit 33, whose power-supply pins are respec-tively connected -to the line 11 and the earth.
- . .
~' '-.
~ 35 ~ ~
pll~? S~ 5l7 C. IO IO ~-198l One of the "clock" ou-tpu-ts Or tlle demultiple.~er 33 is eonnected -to an inpu-t of cm "~D"gate 34, w'rlo3e out-put :is conr~ected to the "cloclc" input o:~ the :regis-ter 25, a rssistor 35 being ;nclucLed '~etween t'he OutpLlt of said gate and the earth, '~he ~node of an isolatill~; diode 36 is connected to the li.ne 'I -I ~ l~hilst the cathodc is comlec-te(-l to a posi.-tive line 37, a storage capaci-tor 38 'being incL-ucLc,~d between said posi-tive line ancl the earth.
The negative inpu-t of the first comparator circuit 39 is connected -to a resistor bridge 4O, 41 included between the line 37 and the aarth, Irhilst the posi-tive input is con-nected to a further resis-tor b:Lidge 42, 43 included be-tween the line 7 and the earth/
The output o:~ the colrlpara-tor 39, w'll:ic:lL.is connec-ted to an "interrupt" lnpu-t pin L~ of -tho In:icroproeessor '15 is connected -to tllc l.ine 37 V.La a res-istor l~5 ancL-L;o L.llo posi-tivc inpllt vla a resi.st;or 46.
The poslti.ve :input of " seconcL eornparator c:Lrcll:it 20 44 i~ connected to a first resistor bricLge 55, 56 :included 'between the line 11 and the eart:hing -point S, whilst the negative input is collnected -to a second resi.s-tor bridge 57, 58 included between the line 37 and the earth.
The output of tl-e comparator 54, which is decouplecl 25 frorn ear-th by means of a capac:itor 59, is connected to the line 11 via a resistor ~O~ to the cont:rol input o~ the elec-tronic switch 50 and to the second inputs of the gates 26, 28 and 3L~.
The negative input of a third comparator clreuit 30 47 is eomlected to a resistor bridge 49~ 4~ included between the line 37 and the earth, whilst the positive input is connected to the line 22 via an eleetronic switch 5O, a re-sistor 51 ~eing included ~etween said pos~tive inpu-t and the earth.
The output of the comparator 47 is connected to a ~Ivalidation~ input 52 of the microprocessor 15 and via a resistor 53 to -the line 37.
A eapacitor 61 is included be-tlveen a reset input 3~ j~'7 P~ SO 5-17 ~ "-'19~-1 6~ of the microprocessor 15 and the earth, s.lid ca-paci-tor being bypassecl by the emitter-collec-tor pa-th of a PNP tran-sistor 63, wnose base is connec-tecl -to the O~ltput of the com-~parator 54 In or~er to simpl:il'y t;he :~ollowins descrip-tion, only the connect-ions o-f tlle microprocessor 15 which c~irectly rela-te to the da-~;a-salvage device in accordaIlce with the in-vention are sho~m, to the e~clusioll of other connec-tions re-lating to the cLata inputs ancl to the outputs for instructions which are specific o~ the apparatus in which it is incorpor-ated, which may be a laundry or dish-~-rashing machine, a cooking appliance etc.
The function of the control device eMployed in the apparatus in accorclance with -the invention .is -to salvage the data stored :i.n t'he rnicroprocossor 15 at -the i.nstz1rlt tllat the currellt on the n1fins term:Lnals 1 ancl '-' :is inte.rrupt~3d.
~ eferr:ing no~ to Figs. 3a ancl '3'b, wh:icll respect:ive ly represcl-lL; -the voltz.~ es O:tl th(3 l:ine 7 ~VR) arlcL on the li.ne '11 (V'b)~ it w-il~ e seen tha-t at L;lle :illS tant -t.1 at 20 which the failure occu:rs the voltage VR 'begills1:to dec:rez-1.se, whilst the vol-tage V'b remains stable until the :Lns-tant -t3 corresponding to -that value of VR which no .Longer perrt1i-ts stabilisation; this is achieved 'by giving -the smoothing capacitor 12 a higher value than the smGotl~ing capacitGr g.
In the case of a nominal supply vGl-tage o-f 5 V
for -the microprocessor 15, this voltage may decrease down to 4.5 V without impairing -the microprocessor operat-ion;
thus between the beginning of the fail~lre and -the critical threshold of the voltage Vb a time interval of a few m:illi-30 seconds is availa'ble which is utilized by the data-~salvage device in acco:rdance with the inveIltion.
During normal operation the voltage applied -to the posi-tive inpu-t of the cGmparator 39 fro1n the line 7 is higller -than that of the negative inpu-t, which is de-termined 35 by the resis-tor bridge 4O, 41 via the line 11; in th:is situ-ation the outpu-t o~ -the comparator 39 supplies a "high"
level to the "interrupt" input 44 of the microprocessor 15 (Fig. 3c).
1 ~ tj~3~''7 P~Ll~` SO 5'l7 ~ 1~ 'lO-~-l9$1 In the case of a po~er failure -the ~oltage VR on -the Line ,' begins to c1ecrease at the instant tl (Fig. 3a) and, when it reaches 8 V at the instant t2, the output of the compara-tor 3~ changes -to a "lo-~" level ~Fig. 3c) which, ~hen applied to t~Le ,nput ~l4 of the nlicroprocessor, inter-rupts -the normal progralnllle of' said rnicroprocessor in orcler -to replace i-t 'by a po~er--ontage subro1ltlno. This sub-rou-tine allot~s the clock pulses to be appliecl fron1 t'he output 32 to t'he ga-te 34 v~a -the cLenlult:iple~er 33 by me-ns of` a logic code OIl the ou-tputs 3O and 31 and the l'outp1ltl' of -thLe data necessary for a possible con-tinua-tion of the normal mode of operation ViQ the pin 27.
During t'his time the gates 2~, 2~ and 31~ ar0 open and the si~itch 5O is closed, -their control inputs being "high" (Fig. 3e) ot~ing to the stal;e of -the output of the comparator 547t~hose vol-tage Ol-L the pos-it:ivo :klp~-~t is h:icq;hor than voltage on the naga-tive input; ln this s:it~ L-tlon t'ho clock pulses are received fI`OI(I -the gale 31~, c~using thQ r~-gist;er ~5 to be :loadod t~:ith the data issul~ ron1 thc ~ato 20 26 (Fig. 3d).
4f-tier a -time interval nece3sary -L`or loaciing all the data into the re~ister 25~ ~hich in-terval is approxi-mately 35O/us, the "failure" subroutine of the nlicroprocess-or changes the logic code of tl1e ou-tpu-ts 3O and 31, and also 25 interrupts the loadlng operation; i-t is to be no-ted that for reasons of clarity this loading sequence ls considerably simplified in ~ig. 3c1, From the instant t3 (Fig. 3a) the voltage Vb on -the line 11 begins to decrease and ~1en i-t reaches -the 30 threshold of ~l.5 V the output of the comparator 5~ changes, thereby closing the gates 26, 2S and 3~, opening -the s-~i-tch 5~ and turning on the transis-tOr 63 ~R-~SET) (Fi~. 3e).
Si~ul-taneously~ the decrease of the voltage Vb on the line 11 causes the diocle 21 to be cut off, thereby main-35 taining the high charge of capacitor 23 as a re~sult of this,the C-MOS register 25 i~hich 1~as a ~ery lo~ power consum~-tion, remains energised withollt -the poss:bili-ty of an erro-neous read-out ia lts data inpu-ts and outputs ~ecause the PlIF .~) ~l7 C l3 ~ 2-'1981 ga-tes 26 and 2S are bloclced~
The clecrease o-f the voltage Vb on -the lirLe '1-1 als;>
ca~lscs tlhe diode 36 to 'be cut of-,, which for a certain time inter~al maintains the chLIrge of -the capaci-tor 3~ hicl1 cnergi~es the comparators 39, !l7 ancL 5~ via -the line 37.
When the power :i9 restore.l -t;ho voltage V~ at the ins-tant tL~ (F:ig. 3a) is surficie}1-t to enab1e thc vol-tage Vb to increase agclin -to ~.5 V (Fig. 3b) ~nd agai1l energi,ze the comparators, which l'irst of all causes -the gates 26, 28 and 34 to be opened .~ld -the swi-tch 5O to be closed (Fig. 3e).
However~ the transistor 18 is held in -t'he cut-off state by a posit:ive voltage applied to its base from the OLltpUt l6 of the microprocessor -15 (Fig~ 3f); in this si-tuation the '~
capacitor 23 retains :Lts charging voltage, whicll it held at thc instan-t that po~er WclS restorecl, this resid~ l vo].tal~7e 'heing applied to the posl-ti~t3 inp~lt; Or -t;'L~e co~ ral;or /17 via the 9 Wi tch 5O.
The va~ e of the resiclua;L voli;c~ e of t'he cnp~ci-tor 23 .at thc i~sl;an-t; that po~er is rt~stoL~ecl Or oourse clo-~ pends on the chlr~ti.ol1 of the powe-r failure; 'howe~e:r, there is a thresholcl value of t'he suppl~ voltage o~ -the register 25 below which -the preservation o~ the storecl da-ta is no longer guaranteed, for example 3 ~.
If` the residual ~oltage a-t -the instant -that th0 25 power suppl~r is restored is higher t~an said critical value (dotted lines Fig. 3g)~ the ou-tput of the cornparator 47 will supply a high le~el (~ig. 3h) to -t'he "valida-tion" input 52 of the microprocessor 15 at the instant tl~, which enables a transfer o-f the salvaged data con-tained in the register 30 25 to -the microprocessor 15 by way of the input terminal 29 via the gate 28 (Fig. 3d).
In the case that the value of the residual -~ol-tage is snaller than the threshold level (do-tted line Fig. 3g) the output o-f the cormparator ~7 will rermain low" (Fig. 3i) 35 and the microprocessor is set to a stancl-by posi-tion in anticipa-tion of` re-programming.
The instant at which -the choice is made between these two possibilities is the instan-t t5 (Fig. 3a~ a-t ~hich l .~.ti'.~5~7 Pl~ ~ 5l7 C 1l~ 10-2-19~1 the OUtpllt of the comparator 39 again sllpplies a "high"
level -to -the "interrupt" inpu-t 44 of the m croprocessor;
therefore, it is of importance that the transis-tor 18 is still cut of'f at this instant, which is realised 'by delaying th.e :instant at which the signal appears on the O~ltptlt 16 o~' the microprocessor which turns on trans:Lstor -18 ~Fig. 3f), which signal enables capacitor 23 to be rechargecl.
Steps are taken in order to cope wi-th certain situations which rmay ocour, thus) after the registers have 10 been loadecl~ the microprocessor 15 rerllains in a waiting loop Or appro~imately one second if normal operation could be restored in the case of' a mains voltage decrease which i5 too slow.
Equally~ in order to allow f'or an erroneous power 15 re-turn, the re-trans~er of the data stored i~ the register to the microprocossor is also ef:E~ectecl afte:r a w~l:ti.ng loop of` OllO second ~E'ter power has boen ~estored and berore t}lC vol-tage ~b ~eeding the microprocessor has reached a suf`:E':icient 20 valuc~ the output level on pin ~l~ rnay t;~e:ro:~ore assume in-correct values; in orclcr to preol.ude partial recharging of : the capacito:r 23 by ~ accidental turn-on o~ tr~lsist;o:r 18 before the value of the residual voltage has been taken into account, said transistor i9 kept cut-off b~r the in-25 clusion of -the Gapacitor 20, which provides a positive base bias whlle the voltage Vb i.s increasing.
The gate 34, ~hich is blocked when the voltage ~b :~ is lower th~n 4.5 ~ prevents any transfer of spurious sig-nals to the clock input of the register 25, which s.ignals 30 may affect the content of said register and which result from random operation of the microprocessor l5 and of the de-multiplexer 33 i.Tl the case of an insufficient supply voltage.
The switch 24 for short-circuiting the capacitor 23 is mechanicalLy coupled to the common "start-stop" switch ; 35 (not sho~n) of the apparatus, i~ such a way that it i9 closed after the terminals 1 and 2 are no longer energized and ~hich opens before said -terminals are connecbed -to the mains, ln thls way it is avoided -tha-t the device responds ~ ~ ' ;' ' ' ' ' ; ' . . .
.~ ' .
~ti~3'~
PHI;` SO 5 17 c I5 10-2-1981 -to a ~ollln-tary power cu-t-of r 0:~ -the c1pp~ra tus in the same ~iray as to an acc idental m~ins E)owe~ f`ailure .
Tlle use of the cont:roL method and o:f tl1e da-ta-salvage device in acco:rclance ~ri th t:he invcn-ti.on i.s iLlus-5 trat;ec1 by ~aS~ O:r e~amp~ y its ~I ;e ~in a lalLnd:ry ~raslLinmachine whose opera-tion :i.s con-t:ro.Llo~l by a mi.c:roproCeS50l .
Tlle m:icroproc2ssor ( l5) usecL :is corlmlerc:i all-~avai.lable frorn the Signetics company under the reference S035, -the demultiple~er (33) beirlg o:f tlLe type l174 LS 139"
10 al~d -the shi:ft reg~ister ~25) being :formecl by a double 7'4006"
f r o rn -the s am e c omp any .
Table I, by way of e~amplé:~ lists all -the programme "steps " o:E a washing maclline whose microprocessor is pro-grammed ~'s tep by s tep", ~`
Tab:Le I
No . of s-teps F~ulc tlons 1~1 filling s t:ir:r Ln~;
pr~ rash i.ng ~ .~ he a ting-s tl.r:r i.ng ¦ 3 s tirring ~4 dral ning-s tirr ing ~5 fi.Lling~sti:rring ¦ 6 heati.ng 7 s tirri.ng ~5 washing ~1 ~ "
t 2 replellishing ~13 draining-s tirring ls t rinseS14 :Eilling-stirring Ll 5 draining-s tirring 16 -filling 17 :~i:Lling+acld:ition detergerlt 2nd rinse lS sti.rring 19 draining filling-stirring 21 deteckion of motor direction 3rd rinse 22 draining * fast rotation 23 spindrying 24 filling 4th rinse 25 filling + softener addition
2~ stirring 27 stip with full tub ~28 detection of motor direction 29 draining + fast rotation spindrying 30 spindrying ~31 ' 32 stop The following description relates to the detailed logic used for this specific use.
Data salvag~ (Table II of Figure ~a) When the microprocessor 15 receives an interrupt instruction as a result of the detection of a voltage drop on the inputs of the stabiliser 10, it transfers all the data necessary for a subsequent continuation of the washing sequence to the register 33, namely:
- a four-bit code ~1000) for the register position, - a first eight-bit word containing the number of one of the selected washing programmes (cotton 95, synthetic fabrics, woollens, etc.) and the selected options, for example "prewash" on request, an "economy programme" with reduced temperature and water level, "half load" also with reduced water level, - a second eight-bit word representing the washing tempera-ture and the spindrying speed,- a third eight-bit word representing the display data for the washing cycles associated with the programme and the selected options (prewash, wash, four rinsing cycles, stop with full tub, final rinse), - a fourth eight-bit word representing the progress of the washing sequence at the instant of failure (number of steps from 1 to 32, Table I).
Each of the introductory cycles of the said four :
~;(3 words is prepared by the output sub-programme which is elaborated in Table III o Figure 4b.
The above data transer is eected in approxi-mately 350/us and ater a last output sub-programme, the 5 micro-processor 15 i5 set to a one-second waiting loop which serves to prevent the operation o the machine being resumed in the case a mains voltage which decreases too slowly.
Restoring (Table IV of Figure 5) The microprocessor 15, which is reset to the 10 beginning of its prograI~me when power is restored proceeds with the following operations:
- cancellation of the instructions rom the control unit 104 (Fig. 1), thereby rendering the machine inoperative, - turning o the seven-segment displays and light emitting 15 diodes o the display unit 117, - checking the residual supply voltage o the salvage regis-ter 25 by sensing the output o the comparator 47.
If the residual supply voltage o the capacitor 23 is smaller than 3 V, the machine is set to a stand-by 20 state in anticipation o a new washing programme; otherwise operation continues as follows:
- instruction to recharge the capacitor 23, - read-out of the code; this code is designed to enable a shift to the right o the register and to allow for this 25 during the read-out of the four salvaged words - which code is written as: 1000, valid codes: 1000 and 100, i the first or the second bit which is read is 1, the salvage operation is invalidated and the maching is also set to stand-by in anticipation of a new washing programme.
This tolerance of a shift by one position of the register enables to allow for the effect of a spurious pulse occurring at the instant at which power is restored and which could be mistaken for a clock pulse by said register.
- successive read-out of the four eight-bit words from the 35 register 25 - restoring the operational parameters in the internal registers (initialisation), - stop-cycle test. In two cases operation should not be PHF 80 517 C 1~
tinued from the step interruption occurred:
a) stopping during a heating step, operation is continued with the preceding fill.ing step in order to avoid heating without water;
interrupted during step 2, restart step 1 (table I) interrupted during step 6, restart step 5.
2) interrupted during a spindrying step, restarting from a preceding filling step, in order to ensure a correct balanc-ing of the load of launary during spin-drying (start spin drying with full tub).
interruption during step 22 or 23, restart step 20 interruption during step 29, 30 or 31, restart step 26.
Stopping with full tub (step 27) will not be effected for a second time if the machine stops at one o~
the cycles 29, 30 or 31, owin~ to the presence of a bit of the fourth salvaged word, which becomes "1" at the instant that the "stop with full tub" function is executed.
- Updating the display - Restarting of the washing sequence.
Data salvag~ (Table II of Figure ~a) When the microprocessor 15 receives an interrupt instruction as a result of the detection of a voltage drop on the inputs of the stabiliser 10, it transfers all the data necessary for a subsequent continuation of the washing sequence to the register 33, namely:
- a four-bit code ~1000) for the register position, - a first eight-bit word containing the number of one of the selected washing programmes (cotton 95, synthetic fabrics, woollens, etc.) and the selected options, for example "prewash" on request, an "economy programme" with reduced temperature and water level, "half load" also with reduced water level, - a second eight-bit word representing the washing tempera-ture and the spindrying speed,- a third eight-bit word representing the display data for the washing cycles associated with the programme and the selected options (prewash, wash, four rinsing cycles, stop with full tub, final rinse), - a fourth eight-bit word representing the progress of the washing sequence at the instant of failure (number of steps from 1 to 32, Table I).
Each of the introductory cycles of the said four :
~;(3 words is prepared by the output sub-programme which is elaborated in Table III o Figure 4b.
The above data transer is eected in approxi-mately 350/us and ater a last output sub-programme, the 5 micro-processor 15 i5 set to a one-second waiting loop which serves to prevent the operation o the machine being resumed in the case a mains voltage which decreases too slowly.
Restoring (Table IV of Figure 5) The microprocessor 15, which is reset to the 10 beginning of its prograI~me when power is restored proceeds with the following operations:
- cancellation of the instructions rom the control unit 104 (Fig. 1), thereby rendering the machine inoperative, - turning o the seven-segment displays and light emitting 15 diodes o the display unit 117, - checking the residual supply voltage o the salvage regis-ter 25 by sensing the output o the comparator 47.
If the residual supply voltage o the capacitor 23 is smaller than 3 V, the machine is set to a stand-by 20 state in anticipation o a new washing programme; otherwise operation continues as follows:
- instruction to recharge the capacitor 23, - read-out of the code; this code is designed to enable a shift to the right o the register and to allow for this 25 during the read-out of the four salvaged words - which code is written as: 1000, valid codes: 1000 and 100, i the first or the second bit which is read is 1, the salvage operation is invalidated and the maching is also set to stand-by in anticipation of a new washing programme.
This tolerance of a shift by one position of the register enables to allow for the effect of a spurious pulse occurring at the instant at which power is restored and which could be mistaken for a clock pulse by said register.
- successive read-out of the four eight-bit words from the 35 register 25 - restoring the operational parameters in the internal registers (initialisation), - stop-cycle test. In two cases operation should not be PHF 80 517 C 1~
tinued from the step interruption occurred:
a) stopping during a heating step, operation is continued with the preceding fill.ing step in order to avoid heating without water;
interrupted during step 2, restart step 1 (table I) interrupted during step 6, restart step 5.
2) interrupted during a spindrying step, restarting from a preceding filling step, in order to ensure a correct balanc-ing of the load of launary during spin-drying (start spin drying with full tub).
interruption during step 22 or 23, restart step 20 interruption during step 29, 30 or 31, restart step 26.
Stopping with full tub (step 27) will not be effected for a second time if the machine stops at one o~
the cycles 29, 30 or 31, owin~ to the presence of a bit of the fourth salvaged word, which becomes "1" at the instant that the "stop with full tub" function is executed.
- Updating the display - Restarting of the washing sequence.
Claims (14)
1. A method of operating an apparatus powered by an electric mains, said apparatus comprising a solid state processor which is provided with a memory for holding a plurality of selectable programmed routines, said proces-sor controls during a selected routine at least one physical parameter through a predetermined range of values within a limited volume of space, said method comprising a first number of steps which are executed by the apparatus in case of a beginning of a power failure during execution of a selected routine, and a second number of steps which are executed by the apparatus at the restoration of the power after said power failure occurred during said execu-tion of said selected routine;
(1) said first number of steps, comprising the steps of:
- sensing the beginning of said power failure;
- interrupting said selected routine;
- enabling a timer means to start from an initial position;
- saving identifier data associated with said selected routine, and indicating the point at which the interrup-tion of said selected routine occurred;
(2) said second number of steps comprising the steps of:
- sensing the end of said power failure;
- disabling said timer means and sensing its actual posi-tion;
- determining the duration of said power failure;
- determining whether said duration exceeds a predetermined limit;
- generating an "excess" signal if said duration exceeds said predetermined limit, generating a "non-excess" sig-nal if said duration does not exceed said predetermined limit;
- under control of an "excess" signal jumping to a termina-tion step;
- under control of a "non-excess" signal proceeding with PHF. 80-517C 20 said second number of steps;
- fetching said identifier data;
- sensing the value of at least one physical parameter;
- determining a reference value for said physical para-meter at said point at which the interruption of said selected routine occurred;
- comparing the value of said sensed physical parameter with said determined reference value for said physical parameter, and determining whether said sensed physical parameter has a value lying between a predetermined tolerance from said reference value for said physical parameter;
- generating an "acceptable" signal if said sensed physical parameter has a value lying within said predetermined tolerance; generating a "conditionally acceptable" signal if said sensed physical parameter has a value lying out-side said predetermined tolerance;
- under control of an "acceptable" signal restarting said interrupted routine;
- under control of a "conditionally acceptable" signal, determining from which point said interrupted routine has to be restarted in order to restore said parameter and proceed with said interrupted routine.
(1) said first number of steps, comprising the steps of:
- sensing the beginning of said power failure;
- interrupting said selected routine;
- enabling a timer means to start from an initial position;
- saving identifier data associated with said selected routine, and indicating the point at which the interrup-tion of said selected routine occurred;
(2) said second number of steps comprising the steps of:
- sensing the end of said power failure;
- disabling said timer means and sensing its actual posi-tion;
- determining the duration of said power failure;
- determining whether said duration exceeds a predetermined limit;
- generating an "excess" signal if said duration exceeds said predetermined limit, generating a "non-excess" sig-nal if said duration does not exceed said predetermined limit;
- under control of an "excess" signal jumping to a termina-tion step;
- under control of a "non-excess" signal proceeding with PHF. 80-517C 20 said second number of steps;
- fetching said identifier data;
- sensing the value of at least one physical parameter;
- determining a reference value for said physical para-meter at said point at which the interruption of said selected routine occurred;
- comparing the value of said sensed physical parameter with said determined reference value for said physical parameter, and determining whether said sensed physical parameter has a value lying between a predetermined tolerance from said reference value for said physical parameter;
- generating an "acceptable" signal if said sensed physical parameter has a value lying within said predetermined tolerance; generating a "conditionally acceptable" signal if said sensed physical parameter has a value lying out-side said predetermined tolerance;
- under control of an "acceptable" signal restarting said interrupted routine;
- under control of a "conditionally acceptable" signal, determining from which point said interrupted routine has to be restarted in order to restore said parameter and proceed with said interrupted routine.
2. A method as claimed in Claim 1, wherein said timer means is provided with an auxiliary power hold source for powering a memory holding said identifier data during said duration, which auxiliary power hold source has a con-trolled output level at said initial position and is drained during said power failure from said level to a threshold level, said duration being determined by measur-ing a residual voltage on said auxiliary power hold source and if said threshold level has been reached, said excess signal being generated.
3. A method as claimed in Claim 1, wherein said "conditionally acceptable" signal controls a jump to said termination step if said physical parameter is non-restorable.
4. A method as claimed in Claim 1, wherein said programmed routines comprise at least an earlier and a PHF. 80-517C 21 later program step, wherein said power failure occurs dur-ing execution of a later program step, said "conditionally acceptable" signal controlling a jump to said earlier step.
5. A method as claimed in Claim 1, wherein said programmed routines each comprise at least one program step, controlled by the required value of a physical para-meter identifying said program step, said "conditionally acceptable" signal controlling a restarting of said inter-rupted routine while simultaneously generating a restore signal for restoring said physical parameter to said required value.
6. A method as claimed in Claim 1, wherein a multi-bit code number is inserted into said identifier data, wherein said fetching of identifier data comprises detect-ing said code number in said identifier data, and wherein incorrect detection of said code number controls a jump to said termination subroutine.
7. An apparatus operated by a solid-state proces-sor and powered by an electric mains, in which during a conditional operation, within a predetermined volume of space, at least one physical parameter is controlled through a predetermined range of values, said processor holding a plurality of programmed routines, at least one of said rou-tines being interruptable in case of power failure and said apparatus comprising:
(a) converting means, for receiving a primary supply volt-age from an electric mains, and therefrom producing a secondary supply voltage on a first output, said first out-put being connected to a supply input of said processor;
(b) sensor means for sensing said physical parameter;
(c) a control device annexed to said processor, having a first input connected to said first output, and comprising:
c1 an auxiliary power hold source, comprising a source input for receiving said secondary supply voltage until the beginning of said power failure in said mains, comprising a source output for presenting an auxiliary voltage to a further element of said control device, further comprising current draining means for draining said auxiliary voltage PHF. 80-517C 22 from a nominal level to a lower threshold level within a predetermined length of time from said beginning;
C2 said further element comprising storage means for storing identifier data of said interrupted routine from said begin-ning for said predetermined length of time, said storage means having a data path to said processor;
C3 detecting means, connected to said converting means, for generating a failure indicating signal upon detecting said beginning, generating a restart signal upon detecting the end of said power failure, and generating under control of said restart signal a validation signal if said auxiliary voltage has not yet reached said lower threshold level, c4 gating means in said data path, for enabling under con-trol of said failure indicating signal a transfer of said identifier data from said processor to said storage means and for enabling under control of said validation signal a transfer of said identifier data from said storage means to said processor;
(d) said processor being provided with means for verifying received identifier data and, under control of verified identifier data, testing an output signal of said sensor for an allowable value.
(a) converting means, for receiving a primary supply volt-age from an electric mains, and therefrom producing a secondary supply voltage on a first output, said first out-put being connected to a supply input of said processor;
(b) sensor means for sensing said physical parameter;
(c) a control device annexed to said processor, having a first input connected to said first output, and comprising:
c1 an auxiliary power hold source, comprising a source input for receiving said secondary supply voltage until the beginning of said power failure in said mains, comprising a source output for presenting an auxiliary voltage to a further element of said control device, further comprising current draining means for draining said auxiliary voltage PHF. 80-517C 22 from a nominal level to a lower threshold level within a predetermined length of time from said beginning;
C2 said further element comprising storage means for storing identifier data of said interrupted routine from said begin-ning for said predetermined length of time, said storage means having a data path to said processor;
C3 detecting means, connected to said converting means, for generating a failure indicating signal upon detecting said beginning, generating a restart signal upon detecting the end of said power failure, and generating under control of said restart signal a validation signal if said auxiliary voltage has not yet reached said lower threshold level, c4 gating means in said data path, for enabling under con-trol of said failure indicating signal a transfer of said identifier data from said processor to said storage means and for enabling under control of said validation signal a transfer of said identifier data from said storage means to said processor;
(d) said processor being provided with means for verifying received identifier data and, under control of verified identifier data, testing an output signal of said sensor for an allowable value.
8. An apparatus as claimed in Claim 7, said auxili-ary power hold source comprising:
(1) a capacitor for receiving said secondary supply voltage until said beginning and supplying said auxiliary voltage from said beginning:
(2) a first line having one end connected to said source output and the other end to a first switch, said first switch being connected to the mains on-off switch of the apparatus for totally draining said auxiliary power hold source.
(1) a capacitor for receiving said secondary supply voltage until said beginning and supplying said auxiliary voltage from said beginning:
(2) a first line having one end connected to said source output and the other end to a first switch, said first switch being connected to the mains on-off switch of the apparatus for totally draining said auxiliary power hold source.
9. An apparatus as claimed in Claim 8, wherein said detecting means comprising:
(1) a first comparator circuit, comprising a first input terminal connected via a first voltage divider to said secondary supply voltage and a second input terminal con-nected via a second voltage divider to said primary supply PHF. 80-517C 23 voltage, for comparing said secondary supply voltage with a fraction of said primary supply voltage, generating a first failure indicating signal on a first comparator out-put in the case of a deviation from a first predetermined value, and generating a first restart signal on said first comparator output upon detection of a recovery to said first predetermined value;
(2) a second comparator circuit, comprising a third input terminal connected to said first output and a fourth input terminal connected to a first reference power source for comparing said secondary supply voltage with a first reference voltage, generating a second failure indicating signal on a second comparator output in the case of a deviation from a second predetermined value, and generating a second restart signal on said second comparator output upon detection of a recovery to said second predetermined value;
(3) a third comparator circuit, comprising a fifth input terminal connected to said source output via a second line and a sixth input terminal connected to a second reference power source, said second line including a second switch having a control input for receiving said second restart signal, for comparing, after said second switch has been closed by said second restart signal, said second reference voltage with the residual voltage of said auxiliary power hold source, generating said validation signal on a third comparator output if said residual voltage is higher than said threshold level determined by said second reference power source.
(1) a first comparator circuit, comprising a first input terminal connected via a first voltage divider to said secondary supply voltage and a second input terminal con-nected via a second voltage divider to said primary supply PHF. 80-517C 23 voltage, for comparing said secondary supply voltage with a fraction of said primary supply voltage, generating a first failure indicating signal on a first comparator out-put in the case of a deviation from a first predetermined value, and generating a first restart signal on said first comparator output upon detection of a recovery to said first predetermined value;
(2) a second comparator circuit, comprising a third input terminal connected to said first output and a fourth input terminal connected to a first reference power source for comparing said secondary supply voltage with a first reference voltage, generating a second failure indicating signal on a second comparator output in the case of a deviation from a second predetermined value, and generating a second restart signal on said second comparator output upon detection of a recovery to said second predetermined value;
(3) a third comparator circuit, comprising a fifth input terminal connected to said source output via a second line and a sixth input terminal connected to a second reference power source, said second line including a second switch having a control input for receiving said second restart signal, for comparing, after said second switch has been closed by said second restart signal, said second reference voltage with the residual voltage of said auxiliary power hold source, generating said validation signal on a third comparator output if said residual voltage is higher than said threshold level determined by said second reference power source.
10. An apparatus as claimed in Claim 7 or 9, wherein said storage means comprises a shift register, powered by said auxiliary voltage for said predetermined length of time, said shift register comprising a data input, con-nected to said processor for receiving said identifier data;
a data output,,connected to said processor for sending said identifier data to said processor, a control input for con-trolling said data transfers.
a data output,,connected to said processor for sending said identifier data to said processor, a control input for con-trolling said data transfers.
11. An apparatus as claimed in Claim 7 or 9, wherein PHF. 80-517C 24 said storage means comprises a shift register, powered by said auxiliary voltage for said predetermined length of time; said shift register comprising a data input connected to said processor for receiving said identifier data;
a data output connected to said processor for sending said identifier data to said processor;
a control input for controlling said data transfers;
said gating means of said apparatus comprises:
(1) a first logic gate, having a first gate input connected to said processor and a second gate input connected to said second comparator output, a first gate output being connected to said data input of said shift register for blocking, under control of said second failure indicating signal, the trans-fer of said identifier data to said shift register;
(2) a second logic gate having a third gate input connected to said data output of said shift register and a fourth gate input connected to said second comparator output, a second gate output being connected to said processor for enabling the transfer of said identifier data to said pro-cessor under control of said second restart signal;
(3) a third logic gate having a fifth gate input connected to a clock and a sixth gate input connected to said second comparator output, a third gate output being connected to a clock input of said register for transferring the clock signal to said register under control of a said failure indicating signal and said second restart signal.
a data output connected to said processor for sending said identifier data to said processor;
a control input for controlling said data transfers;
said gating means of said apparatus comprises:
(1) a first logic gate, having a first gate input connected to said processor and a second gate input connected to said second comparator output, a first gate output being connected to said data input of said shift register for blocking, under control of said second failure indicating signal, the trans-fer of said identifier data to said shift register;
(2) a second logic gate having a third gate input connected to said data output of said shift register and a fourth gate input connected to said second comparator output, a second gate output being connected to said processor for enabling the transfer of said identifier data to said pro-cessor under control of said second restart signal;
(3) a third logic gate having a fifth gate input connected to a clock and a sixth gate input connected to said second comparator output, a third gate output being connected to a clock input of said register for transferring the clock signal to said register under control of a said failure indicating signal and said second restart signal.
12. An apparatus as claimed in Claim 8, wherein said capacitor having an output connected to one end of a second line whose other end is connected to said first output, said second line including a diode and a transistor, which tran-sistor has its control electrode connected to a third line for receiving said failure indicating signal and said validation signal.
13. An apparatus as claimed in Claim 9, wherein said first and second reference power source each comprise a capacitor and a voltage divider, said capacitor being con-nected to said first output for receiving said secondary PHF. 80-517C 25 supply voltage until said beginning.
14. An apparatus as claimed in Claim 8 or 9 which apparatus being a domestic apparatus.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR8006414 | 1980-03-21 | ||
| FR8006414A FR2478686B1 (en) | 1980-03-21 | 1980-03-21 | METHOD FOR CONTROLLING A WASHING MACHINE OPERATING BY A MICROPROCESSOR, AND WASHING MACHINE IMPLEMENTING SAID METHOD |
| FR8006415 | 1980-03-21 | ||
| FR8006415A FR2478843A1 (en) | 1980-03-21 | 1980-03-21 | Solid state processor for e.g.washing machine cooker - uses subroutines for salvage of identifier data associated with selected routine interrupted by power failure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1169567A true CA1169567A (en) | 1984-06-19 |
Family
ID=26221674
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000373419A Expired CA1169567A (en) | 1980-03-21 | 1981-03-19 | Method of controlling an apparatus, which is operated by a solid-state processor and powered by an electric mains, in case of a power failure and apparatus employing said method |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US4412284A (en) |
| AT (1) | AT389716B (en) |
| CA (1) | CA1169567A (en) |
| CH (1) | CH656237A5 (en) |
| DE (1) | DE3110385A1 (en) |
| GB (1) | GB2072381B (en) |
| IT (1) | IT1136829B (en) |
| SE (1) | SE450299B (en) |
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| GB2145253A (en) * | 1983-08-17 | 1985-03-20 | Philips Electronic Associated | Method of controlling a domestic appliance |
| GB2145254A (en) * | 1983-08-17 | 1985-03-20 | Philips Electronic Associated | Domestic electrical appliance |
| GB8324156D0 (en) * | 1983-09-09 | 1983-10-12 | British Telecomm | Video player control |
| US4636949A (en) * | 1984-03-07 | 1987-01-13 | Amf Incorporated | Method and apparatus for controlling cooking cycles in a cooking system |
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| US5414861A (en) * | 1991-09-11 | 1995-05-09 | Fujitsu Limited | Data protection system using different levels of reserve power to maintain data in volatile memories for any period of time |
| DE19515884A1 (en) * | 1995-04-29 | 1996-10-31 | Hartmann & Laemmle | Device for securing an electrohydraulic drive unit |
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| DE19943124A1 (en) * | 1999-09-09 | 2001-03-15 | Bsh Bosch Siemens Hausgeraete | Device for detecting a power failure in a program-controlled household appliance |
| EP1148606B1 (en) * | 2000-01-28 | 2014-01-01 | Continental Automotive GmbH | Method to detect lost information in a microprocessor |
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| CN113818185B (en) * | 2020-06-19 | 2023-11-03 | 天津海尔洗涤电器有限公司 | Control method and system based on power failure memory and clothes treatment equipment |
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| JPS5749937B2 (en) * | 1974-09-25 | 1982-10-25 | ||
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| US4162526A (en) * | 1978-03-16 | 1979-07-24 | International Business Machines Corporation | Failsafe primary power control apparatus for systems using computer controlled power sequencing |
-
1981
- 1981-03-18 IT IT20394/81A patent/IT1136829B/en active
- 1981-03-18 CH CH1861/81A patent/CH656237A5/en not_active IP Right Cessation
- 1981-03-18 GB GB8108453A patent/GB2072381B/en not_active Expired
- 1981-03-18 DE DE19813110385 patent/DE3110385A1/en active Granted
- 1981-03-18 SE SE8101708A patent/SE450299B/en not_active IP Right Cessation
- 1981-03-19 CA CA000373419A patent/CA1169567A/en not_active Expired
- 1981-03-20 US US06/245,824 patent/US4412284A/en not_active Expired - Lifetime
- 1981-03-20 AT AT0133381A patent/AT389716B/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| IT1136829B (en) | 1986-09-03 |
| SE450299B (en) | 1987-06-15 |
| US4412284A (en) | 1983-10-25 |
| DE3110385C2 (en) | 1987-06-04 |
| CH656237A5 (en) | 1986-06-13 |
| AT389716B (en) | 1990-01-25 |
| ATA133381A (en) | 1984-07-15 |
| IT8120394A0 (en) | 1981-03-18 |
| GB2072381A (en) | 1981-09-30 |
| GB2072381B (en) | 1983-12-07 |
| SE8101708L (en) | 1981-09-22 |
| DE3110385A1 (en) | 1982-03-25 |
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