CA1171140A - Programmable digital cardiac pacer - Google Patents

Abstract

ABSTRACT
The specification describes an improved cardiac pacer, and more particularly a pacer which is adapted for implantation in a patient. The cardiac pacer apparatus has an electrode means including at least a first electrode adapted to stimulate the heart; control means including timing means which defines a sample time window and signal detector means including sensing means for sensing cardiac signals on the electrode means. Filter means including a filter circuit receive the signal sensed by the sensing means for quantizing the sensed signal and continuously generating digital words representative of the slope of the sensed signal over the sample time window. Parameter memory means store signals representative of predetermined selection criteria for defining at least one component of a cardiac cycle signal.
A selection circuit means including a selection circuit responsive to the quantized output signals of the filter means and the stored selection criteria signals generates a detection signal if the digital slope words meet the predetermined selection criteria. Finally generator means generate a stimulating signal and couple the same to the electrode means if the selection circuit means fails to generate the detection signal within a predetermined time from a previous detection signal or a previous stimulating signal.

Description

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1 ~7~0 sac~glound of the ~nvention ~ ~:
-The vresent invention relates to cardiac pacers;and' more particularly, it relat~s to caxdiac pacers which are adapted for implantation in a patient.

The present invention is seen as providing substantial improvements in many areas of conventional cardiac pacers, both in the ~unctioning of implanted pacers and in the circuitry and hardware used to implement .a design.
~ --One way to. improve current cardiac pacers, as expressed in the literature and known to persons skilled in the art, is to estabiish a normal cardiac rhythm between the contraction of the upper, smah er heart chamber or atriwn, and the lower or main heart chamber, called the ventricle.
In a normal heart, the atr.~:um.expands and contracts, forcing'' blood through the tricuspid valve intc the associated ' ventricle, thereby helping to fill the ventricle so that when *he ventricle contracts (normally about 150 milliseconds a~ter contraction of the atrium), lt is filled to normal capacity, and this augments the efficiency of the heart in the sense that more blood i5 pumped for each '' cardiac cycle. This also causes the ventricular rate to follow the atrial r~te as establislled by the sino-atriai ~node, thus adjusting the pacing rate to the body demands.

The most common implàntable cardiac pacer in commercial use today is a demand pacer--that is, it has a : single electrode.' which is lodge'd in the apex of the ventricle and senses contraction of the ventrlcle (an R
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wave). A demand paccr t}l~n establi'shcs a predetermined time out period or escape interval during which it tries t~ sen~e a natural R wave. If no natural ~ wave is sensed durin9 that period (which may be approximately 833 milliseconds), a stimulating pulse is generated ~nd transmitted to the ventricle. If a natural hear~beat is sensed, the time out period is reset to establish a new escape interval. Thu~
in a sardiac pacer of this type, no attempt is made t~
synchronize the contraction of the ventricle with that of the atrium.
--Early attempts were 'made to synchronize ventricular contraction with atrial contraction (called a P
wave), particularly when the prevailing practice was to use open chest surgery to in~plant the cardiac electrodes.. The electrodes were sutured to the walls of the atrium and the ventricle respectively. Current practice, however, has tried to avoid the use of open chest surgery with its accompanying trauma and risk, and therefore the prevailing practice is to introduce a single electrode which, as indicated, is lodged in the apex of the ventricle, and to employ a second or neutral electrode on the pulse generator casing for the circuitry which is normally lodged in the abdomen or chest'pocket of the patient.

The magnitude of the electrical signal accompanying atrial contraction, that is the P wave, is quite small and easily masked by ambient electrical noise or ar~ifacts, such as those generated by muscular activity.
When an electrode is sewn directly to the wall of 'the atrium, a P wave can be detected. However, when it became generally acc~pted that it is desirable to avoid open chest - ' 3 ', ' , ` ~J7~1~0 surgery, and therefore impossible to establish firm contact with the wall of the atrium, other electrode configurations were suggested.

One lead configuration that has been suggested is the so-called "J~Iead" which uses a flat ~etal contact in the form of a leaf spring which opens after the electrode is inserted in the heart.

Some of these configurations were either too dangerous (i.e., possible damage to the heart by forcing the contact th~ough the thin wall of the atrium), or too difficult to insert, or interfered with the operation of the heart to an extent that they were never widely used. ~ther suggested systems, which did not establish reliable contact with the wall of the atriùm, made it e~tremely difficult to detect a P wave in the presence of the vehtricular signals and normal noise.
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Noise, of course, also occurs in the ventricular electrode due to muscle artifact and the many sources of RF
energy a patient is likely to encolmter. For this reason, implanted pacers usually incorporate circuitry which, in the presence of excess ambient noise, causes the pacer to revert to a fixed rate mode.

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1.~ 0' Summary of_the Invention 9ne of the prin~ipal o~jects of the pre~ent invention is to include circuitry in an implantable cardiac pacer which will overcome the above problems of reliable signal detection and identi~i~ation, and en.~bie khe circuitry to detect a P wave with a ring electrode which iB
carr1ed by the same catheter which holds the ventricle electrode but is located in the atrium, and not necessarily in contact with the atrial wall; and which will also reduce the probability that the pacer will revert to fixed xate pacing in the presence of high a~bient electrlcal noise. ~4 Briefly, this i5 accomplished by using a first digital filter receiving the signal from the ventricle electrode, and a second digitai filter receiving the signal from the atrial ring electrode.
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Each of these filters incIudes a conversion circuit for converting the incoming signal to digital form.
Briefly, the conversion circuit is a sample data circuit ~he outp~t of which is a serial train of binary signals which operates on the input signal like a delta modulator, so it is referred to as a delta modulator. The output of the deita modulator is fed to a shift register. The parallel outputs of the shift register, when combined, are represent- ~ -ative of the slope of the incoming signal over a predeter-mined time period or "window", the length (i.e., time duration) of whicll ~iepends UpOIl tlle sa~ilple rate and the number of bits in the shlft reglster.

The P, R and T wa~es, Premature Atrial ?-;
Contractians (P~C) and Premature Ventricular Contrations ` 5 ~ -.. . . . . ~ ..... . . ..
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a "flat" segment (i.e., slope less than a predetermined value) lasting for a preset time, followed by (2~ a l~flat aelay" segment, and then followed by (3) an increasing '`
signai (positi~e or negative) called the "high slope"
segment having a slope greater than a predetermined value and, again, lasting for a preset time. These parameters ~magnitude and time for the flat segment, time for the delay segment, and magnitude, slope direction, and time, for the high slope segment), as well as factors which permit the physician ~o weight the importance of each in identifying a particular signaI are programmed into the system, and capable of being cllanged under program control.

The parame~ex identification data is stored in memories ca}led the atrial ~ilter parameter control memory (a division of the atrial control memory) and the ventircular filter parameter control memory. The data is transmitted to the associated digital ilter during the appropriate time in a cardiac cycle under control of a state controller. As will be explained, the physician has flexibility in setting these parameters and the times and conditions at which they are expected to occur. He may also set an error tolerance or acceptance in defining one or more of the parameters. Thus, the identification of the various cardiac signals can be made to be very ~eliable, particularly considering the continuous wave nature of commonly encountered noise (r energy and muscle artifact) versus the impulse waveform ~ature of the cardiac slgnals.

By requiring a flat segment, followed by a flat - 6 ~
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1 ~ 7~ 0 delay segment and then a high slope segment, all th~
parameters of which being tailored to the signal sought t~
be detected, a high degree of rejection is achieved against those noises or unwanted signals which normally are ~' encountered in a cardiac pacerO

Further, the filter parameters (which define the signal being sought) are stored in a memory and imp~emented in the filter under control of a state controller which, in turn, is governed by the ventricular digital filter to sense an R wave during the Ventricular ~ate Time Out period, but it also permits the digital filter to sense a T wave after a stimulating pulse is generated by the pacer in an eff~rt to verify that the heart has responded to the stimulating pulse (called "capture"). In another portion of à cardiac cycle, - the filter may be set to determine Premature Ventricular Contractions tPVCs). In other words, the parameters for an R wave, a T wave, and a PVC are loaded into the ventricular filter durïng the time when those particular signals are expected or sought. This aiso enables a physician to adjust the criteria necessary to establish any of these signals so that he has control over the rejection or susceptibility of the pacer to noise or unwanted signals.

The Ventricular Rate Time out period or escape interval is established from the last detected natural heartbeat or stimulating pulse. If a P wave or natural R
wave is not sensed during that period, the system generates a stimulating pulse for pacing the heart artificially, and uses the T wave parameters in the ventricular filter to verify capture.

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If a P wave is sensed before the Ventricular ~nte Time Out period ends, the system establishes a predetermined P-R delay period to'override the Ven~ricular Rate Time Out period of an effort to synchronize the ventricle within ~he atrium. ~uring the P-R delay, the ventricular filter is set to detect a natural R wave which would occur in this delay period if the heart functions normally. If an R wave is detected during the P-R interval, the'system resets itself without generating a stimulating pulse, but if'a natural R
wave is not detected during this time, a stimulating pulse is generated at the end af it to synchronize the ventricle with the atrium. ; ~k ' ' Prior to the Ventricular Rate Time Out period of each cardiac cycle, the ventricular filter is set to detect .PVCs. I$ a predetermined number of sequential PVCs are detected, the system generates a train of stimulating signals at a rate higher than expected tachycardia, in an effort to break the tachycardia.

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' According to another feature of the invention, many of the major functions of the system are implemented under control of a'state controller on the basis o data stored in a status control memory. This stored data can be p~ogrammed to provide great 1exibility and reliability.
One advantage of this ~eature is, for examp]e, the function for attempting to synchronize the ventricle with the atrium (called the "JAM'" function because a data word represent-ative of a predete~mined~ time lS forced into a counter that normally stores data representative of the end of the-Ventricular Rate Time Oùt) can. be disabled. Other major functions- can be locked out or disabled under' program control, as will be discussed. This enables a physician to .
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~ 3 7 1 1 ~1 0 implement whatever functions he feels will fit a patient~s needs with a single electronic circuit or system on which exte~sive use data can be obtained for reliability analysis and predictions. The physician does not have to familiarize himself with the particulars of many different type~ o pacers, as is now the case.

This feature of selective enabling and inhibiting of major functions or subsystems also permits a physician to change the basic operation ~ the pacer after implantation by external plogrammillg without op~rating on the patient.
With the same unit implanted, the physician can make it a P-synchronous, demand or fixed rate pacer. In any of these operating modes, he has the additional ~lexibility to adjust or "tune" the system to the individual cbaracteristics o~
the patient. Fo~ Example, if one patient has an R wave which is wider and more rounded (lower frequency contant) than the normal, the physician can program the criteria for R wave detection with this knowledge. This ability is also important to accommodate the system to any changes in conditions that normally occur after implantation.

Another important advantage of the system architecture is that the pacer can be placed in a power conservation mode by tlle manufacturer to extend shelf li~e, and then the pacer can be activated by the physician:upon implantation. The system uses non-volatile memory and CMOS
circuitry with a crystal main oscillator and voltage-controlled back-up oscillator. In the standby mode, p~wer is fed to the crystal clock oscillator only and all other clock signals, the detectors and the back~up oscillator are disabled until activated by a physician, or .
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the factory at shipping time, thereby significantly.reducing battery consumption while insuring start-up. of the crystal oscillator.

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In ordinary operation, the crystal oscillator and its associated count down circuitry determine the various timing marks in a cardiac cycle as well as the width of a stimulating pulse. The usual rate of the back-up oscillator, or vco, is established to be slightly higher than-the rate of ~he main oscillator. Because its rate is dependent on applied voltage, as the battery begins to deplete, the period of the back-up oscillator will eventually extend to the point where it is equal to a corresponding fixed period derived from the crystal oscillator.- When this occurs, the sys.tem increases the base period derived ~rom the crystal oscillator by 12.S% to conserve power and generates an elective replacement signal, but the system continues to detect for rate limit events--that~is, a detection that the period of the crystai osçillator is still less than the period of the VCO (or in other words, the frequency is greaterj. I f additional rate limit events are detected after the period of the crystal oscillator has been extended, it is taken as an indication of fault in the crystal or its associated count down circuitry, and the system is switched over to run at a fixed rate mode timed by the VCO only--that is, not only is the time base established by the vCo~ but the width of tlle stimulating pulse is also derived from the vco.
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Further, if both the main (crystal) and back-up ~VCO) timing systems are operating normally, the cardiac ~
cycle period for the VCO will end during the Ventricular ~ ~.
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Rate Time out period ~or the crystal oscillator. The period time out signal o~ t},e vco is u~ed as a Rate Limit Enable (RLE) signal for t~lC gclJcratioll of a ~.timllla~illg pulse.
That is, even if the maln timing circuitry times out, the RLE signaI wil} prevent the generation of a stimulating signal until the Vco period ends, thereby preventing the generation of stimulating pulses on a per beat basis at too rapid a rate for normal demand pacing operation.
' When a physi~ian tests a pacer after implantation, as by applying an external magnet, the basic timing functions are derived from the vCo~ but the Ventricular Rate ~o Time Out period is shortened in an effort to cause the generation of a stimulating pulse so that the physician can see the effect on the heart of a stimulating pulse. During this test, the width of the stimulating pulse is still determined by the main timing circuitry, thereby giving a more reallstic capture verification test.
- '', In addition to having the capability o programming many of the signal detection or noise rejection parameters in the ventircular and atrial digital filters, - many other system operating ~parameters can be programmed.
Further, some parameters may be programmed to change in response to detected condltions. For example, in the event capture is not verified after a stimulating pulse (sometimes referred to as 105s of capture), the system will exhibit a response that had been programmed by the pllysiclan. The responses may include increased pulse amplitude, increased ~. -pulse duration, either one followed by the other, or neither. The rate of the system can easily be programmed by changing the Ventricular Rate Time Out period. The pulse ' - . 11 . ' '~' .. .' ' ' . : ' :
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- width or pulse amplitude for stimulation may be programnted into the system, according to- the needs of the patient.
Other programmable parameters are the P-R delay, ventricular refractory time, and lead compensation time. When the system detects tachycardia, the number of successive PVC
detections that define a tachycardia and the number of stimulating pulses that will be generated to try to interrupt tachycardia may be programmed. The system thus permits a physician to program the 'cardiac pacer according to what he believes is best for a given patient in a given set of circumstances. It further enables him to accomodate the systeM to changes in the status of the patient or to new developments in the fleld of cardiac pacing.

' . Another feature of the present inventon includes positive and negative rate hysteresis (that is, changing the escape interval which is the time between a detected R wave or stimulating pulse and the end of the Ventricular Time Out period). The escape interval is shortened to a programmable period such as 550 milliseconds if a PVC condition has been previously sensed, and lengthened to a programmable number such as 900 milliseconds from a nominal pacing rate of 833 msec if an R wave has been sensed during the normal Ventricular Rate Time Out period of the previous caxdiac cycle. The apparatus also includes event tally counters which are used to maintaln~ a ~cumulative count of~events of~
interest to the physician, depending on the type of problem . ~ , :
encountered or condition of the patient. One of the more ~ .
important functions that can be implemented'in the event`
tally counters is a record of the percentage of time during which pacing (i.e., artificial'stimulation) of the heart has. ~.;
taken place over a week's perio~. This and other functions :
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capable of being performed on these counters will be further disclosed below.
Therefore~ in accordance with the present invention there is provided a cardiac pacer apparatus having an electrode means including at least a first electrode adapted to stimulate the heart; control means including timing means which defines a sample time window and signal detector means lncluding sensing means for sensing cardiac signals on the electrode means. Filter means including a filter circuit receiving the signal sensed by the sensing means for quantizing the sensed signal and conti:nuously generating digitaL words representative of the slope of the sensed signal over the sample time window. Parameter memory means store signals representative of predetermined selection criteria for defining at least .one component of a cardiac cycle signal. A selection circuit means including a selection circuit responsive to the quantized output: si~nals of the filter means and the stored selection criteria signals generates a detection signal if the digital slope words meet the predetermined selection criteria. Finally generator means generate a stimulating signal and couple the same to the electrode means if the selection circuit means:fails to generate the detection signal within a predetermined time from a previous detection ~:
signal or a previous stimulating signal.~ ~

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FIG. 1 is a functional block diagram of the .,.
detector portion of a sys~em incorporating the present invention;

Fl~. 2 is a functional block diagram of the control portion of a system incorporatin~ the present ~.
invention;
' FlG. 3 is a diagrammatic view of a heart with bo~h a ventricular sensing/stimulating and an atrial sensing electrode;
, FIG. 4 is a functional block diagram of a gain controlled delta modulator circuit which interfaces with the - analog cardiac signals;
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FIG. 5 is an idealized graph of an analog signal and illustrating the :output of a delta modulator circuit following the analog signal;

~ IG. ~ is an idealized cDrdiac signal;

FIG. 7 is a timing diagram-relating the various timing periods of the system of FlG. 2 to the idealized cardiac signal of FIG. 6;

FIG. B i~ a closeup view of a portion of the idealized waveform of FIG 6 illustrating ~he fllter characteristics of the digital filtexs of the system o~
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~ 3 7 ~ 1 ~0 FIG. 9 is a state table illustrating the content-of the window up/down COUDter O~ FiG. 1 and the manner in which the system may be programmed to select predetermined slope characteristics of an incoming waveform;

FI~. 10 is a timing diagram illustrating synchronization of the R wave with a detected P wave;

. . FIG; 11 is an idealized timing diagram illustrating the positive and negative hysteresis mode of opeFation; ' ,' ' , '' ,_, FIG. 12 is a flow chart illustrating the operation of the system under control of the state controller;

FIG. 13 is a timing diagram for the system's interaction with the temporary mode counter as is operated by actuation of the magnetic reed switch; : .
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FIG. 14 is a logic schematic diagram of the state controller circuitry;

FIG. 15 is a logic schematic diagram of the time mark sequence counter;
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crystal oscillator upper divlder; :

FIG. 17 is a logic schematic diagram of the rate iimit con~roller, sequcntlal rate llmit occurrence counter, and the rate limit enable synchronizer;
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, 1 171~0 . FIG: lB is a log.ic schematic diagram of the ve~ltricular digital fi1ter parameter controller;

FIG. 19 is a logic ~chematic diayram of the P-R
delay J~M controller and its timing diagra~;

. FIG. 20 is a logic schematic diagram of the temporary mode counter;
' - FlG. 21 is a loqic schèmatic diagram of the sequential PVC counter and the automatic tachycardia overdrive control1er;

FIG. 22 is a logic scllematic diagram of the 'sequelltial loss of capture counter and capture veri~ication controller: and.

FlG. 23 is a logic schematic diagram o~ the output volt~gc control1er.

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0 .~, , , Detailed Description .
- Due to the large number of figures and reference "~
numerals, a numeric system is adopted which has as its last two digits the particular reference numeral preceeded by the figure number in the hundred and thousands digit. For example, Reference 01 (the atrium) of Figure 3 uses the reference ~umeral 301.
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Referring first to FIG. 3, there is shown a diagrammatic illustration of a heart in which a pacing/sensing catheter 300 has been inserted. The catheter extends through the upper cha~ber or atrium 301, and into . the lower chamber or ventricle 303, where the tip of the catheter is lodged in the apex of the ventricle. The catheter includes a ventricùlar~ electrode 304 at the tip, and an atrial electrode 302 spaced approximately seven centimeters from the ventricle electrode 304 so as to be located in the atrium. The atrial electrode 302 is shown, in the illustrated embodiment in the form of a ring electrode, but other shapes and designs including those already suggested, as mentioned above, may also be used.
Further, although the atrial electrode 302 ie shown within the upper chamoer, it is not necessary that it touch the wall of tXat chamber, nor even that it be located within the atrium since it is not used for stimulating the atrium. All that is necessary is that it sense sufficient field vector from atrial de-polarizatlon that a P wave can be detected by the atrial detection clrcuitry to be described. In~ some cases it may even be possibIe to detect a P wave from the signal sensed on the stimulating electrode in the ventricle.
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The ventricular electrode 3~4 is connected by means of a ventricle lead or wixe (not shown in catheter 300) to the pacemaker circuitry which is normally located in "
the shoulder or abdomen of the patient; and the atrial ring electrode 302 is simi~arly connected to the circuitry by means of an atrial lead also in catheter 300. The ventricle lead is diagrammatically illustrated by the block 101 i~
FIG. ? i and the atrial lead Is similarly represented by ~he 'olock lOlA. Each of the leads 101, lOlA is connected to circuitry for identifying specific signals which form a part of an overall cardiac cycle o~ frame such as that shown in FIG; 6. This ideali~ed signal will be discussed more below, but as is known, it comprises five major signal portions which are identified respectively as the P, Q, R, S and T
waves. The P wave is associated with ceIlular depolarization or~m~uscul~ contraction in the atrium. The Q
wava is associated with initial stages of ventricle depolarization; the R-wave is associated with the peak of the depolarization of the ventricular myocardium; the S-wave is associated with the final stages of ventricular depolarization; and the T wave is associated with ventricular repolarization. The atrial repolarization is generally masked out by the QR5 complex of the ventricle.
Referring back to FIG. 1, the input clrcuitry includes an atrial filter section genexally designated lOOA in the lower left corner and a ventricular filter section generally designated 100 in the lower right hand corner. As will be explained, each filter is a digital filter which ~an be "set"--i.e., certain parameters of the filter can be changed under control of a state controller 231.
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' ': -- , 11 1711~0 Briefly the lnput'atrial filter lOOA is associated with the atrial lead lOIA and is set to identify a P wave sensed by the atrial electrode 302. Similarly, the ventricular filter section 100 ~s set to identify one of three waveforms, depending upon which portion of a cardiac cycle the heart has entered. This will be discussed in more detail below, but comparing FIGS. 6 and 7 ~which have similar time scales), in the period identified as AD4 (the Ventricular Rate Time Out perlod), the ventricular filter is set to identify an R wave.

The .period AD2 is the ventricular refractory period. If, during the immediately preceding cardiac cycle a natural R wave had been detected and the system generated a Master Reset pulse to reset the tlme:base, the ventricular filter would be set in AD2 with the parameters for i.dentifying either a T wave, an ~ wave, or .a PVC. This gi~es the physician flexibility in- determining how the system responds in certain cases. If, during the immediately preceding cardiac cycle, a stimulating pulse AD5 had been generated, the ventricular filter is set in AD2 to identify a T wave for verifying capture.

' The period AD3 e~tends from the refractory period to ~he Ventricular Rate Time Out period, and it is a "window" in which the system tries to identify any Premature Ventricular Contractions. That is, in AD3, the parameters of the ventricular filter seek to identify PVCs.
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The ventricle lead 101 is connected through a DC
isolation network }02 to the input of a delta. modulator circuit 104. It .is the output of the delta modulato.r cir-19 ' ' ' ., , '' ' , . '' , .. -.
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cuit lo~ wl~ich is operated on by the ventricular input filter 100.
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Similarly, the atrial lead lOlA i5 - connected through a conventional DC isolation network 102A to an atrial delta modulator circuit 104A, the.output of which i6 coupled to the input of the atrial digital filter IOOA.
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. The atria} delta modulator 104A and digital filter lOOA are similar to the ventricular delt:a modulator 104 and digital filter 100, except that they are, of course, actuated or enabled by different signals and the ~entricular diqital filter 100 performs more functions during one cardiac cycle than the atrial filter~ Hence, an understandi~g of the. ventricular input signal processing circuitry will enable a.person skilled in the art to readily understand the corresponding atrial digita~ signal processing circuitry.
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Ventricu}ar Delta ~odulator Referring now to -FIG. 4, the output of the DC
isolation circuit 102 is fed to the positive input 401 of a comparator circuit 402. The output of the comparator circuit 403 (a binary signai~ is fed to the data input of a D-type flip-flop 405. The output of the flip-flop 405 is .~
coupled to a source/sink control .of a gain-controlled current source 407 along lead 406; and the ootput of thè
current source 407 is connected to a capacitor *14 and to the negative input of the co~parator 402 on line 413. The . ~-capacitor 414 forms the delta modulatox capacitor.

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71~0 The currellt source 407 has five leads for programming the gain of the delta modulator. Two of these leads, designated 408 and 409 cause the output current to the sapacitor 414 to increase or decrease in fixed steps.
Hence, these leads change the gain of the current source but retain a linear characteristic for the delta modulator. T}le leads 411, 412, on the other hand, cause the gain of the current source 407 to be multiplied, and thereby cause the delta modul~tor to act as a logarithmic-companded analog to digital converter. The lead 412 causes a modification of the magnitude of one of the gain multipliers 411.

In operation, the comparator circuit 402 compares the magnitude of the input signal VIN 401 with the signal 413 on the storage capacitor 414. If the input signal 401 is greater, the comparator 402 generates an output signal ~03 which is a logic "l" and the flip-flop generates a corresponding "1" output signal 406 but synchronizes it with the input clocX ~04 which determines the sample rate for the delta modulator. If the input signal 401 is less than ~he signal 413 on the storage capacitor 414, the output signal 406 is a logic "0". The output signal is thus a train of binary signals or pulses in synchronism with the clock.
These signals are fed to the current source 407 whicll causes current to be fed to or drawn from the capacitor 414 depend-ing on the state of the output signal 406. If tlle output signal is a logic l, current is fed to the capacitor 414 to increase its charge or voltage; and if the output signal is a logic 0, charge is dra~m from the capacitor to reduce its voltage by a predetermined increment. The increment is ~etermined by sample clock 404 period and the gain o the current source 407. The signal on the capacitor 414 is thus ~ 21 -th~ integrated output of the digital signal 406--i.e,, it~
magnitude is an analog o the digital output that has been generated. Thus the digital output signal 406 is a digital derivative of the input signal 401 and therefore directly contains the slope information of the cardiac signal the delta modulator is connected to.
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The relationship hetween the input signal 401 and the signal on the storage capacitor 414 is shown in FIG. 5 where reference numeral 501 represents an analog input signal and the waveform 502 represents the voltage on the capacitor 414. The binary output train 505 for this example is shown below the abscissa, reading left to right for the order in which they are generated. As can be seen from an observation of FIG. 5 where the input voltage has a relatively low slope, so that the current source can feed enough charge to the capacitor 414 to cause it to approximate the input signal, the output signal is a proportional series of alternating l's and O's, as represented by the portion designated 510 in FIG. 5. Where the input signal increases rapidly, the outpu~ signal is a series of l's, as indicated by the portion 511; and the delta modulator is said to be positive "slew-rate limited", meaning that it is operating at the limit of its capacity to follow the rapid positive excursion of the input signal.
Eventually, the signal on the capacitor 414 catches up with the input signal 512 in the illustrated example. Conversely when the input signal decreas s rapidly, the output pulse train is a series of O's for a negative l'slew rate li~i~ed"
portion 513 and thereafter operation proceeds as described.
It will t]lUs be obser~ed, however, that the train of binary output signals 505 oves a period of time i5 represelltatlVe ,~

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of the slope of the curve S01. The more logic 1'6 contained .
in the signal, the greater the positive 610pe; and , conversely, the more logic 0~5, the greater the negative slope. If the incoming signal were a DC level, the output . ~:
signal would be alternate l's and 0's, as indicated by the portion 514 of FIG. 5 where the slope of the input signal iB
low.

r ~ , Returning then to FIG. 1, the delta modulator 104 has its gain adjusted by a gain control circuit 105; and its - . ;
output signal is fed to a Sample Window shift Register 106. -The output signals from the delta modulator are shifted along the shift register 106. The contents of the shift register 106 represent the output of the delta modulator for a predetermined time period or "window", the length or- 7 duration of which depends upon the clock rate for the shift register.

Ventricular Filter Before discussing the apparatus of the filter in ' ,-~.,, ..~
particular, a graphical illustration of what is accomplished . .
in the filter sections is shown in FIG. B. In this example, .. .
the ilter is set to detect an R wave, but the same principles apply equally well to the other signals being ,- -, detected. For purposes of detection, the signal is divided into three segmcnts occl;rriny in succession. These are in order of occurrence: the Flat Window Segment designated .
817, the Flat Delay Segment 818 and the High Slope Window ~.
Segment 819. Brie1y, the digita} filter will generate a "DETECTION" signal provided the slope of the incoming signaL . -. I

, ., ~ .

.. . . .

~ ~71 1~
meets- established criteria during the Flat Segment 817 and the High Slope Segment 819. Ihe Flat Delay Segment 81~ is used ~o define a time separation or delay between these other two segments.

Each segment or period is comprised of successiv~
shorter periods. For the flat window 817 and flat delay 818 segments the shorter periods are "Sample Compression Groups"
Tl, T2-and so on, each corresponding to the time or s~mple -data compression of the slope window signals ~1, Q2, etc., which become stored in a Flat Window Shift Register 114 and flat delay shift register 112. These "sample compression groups" are progra~oed to be either 8 or 16 milliseconds in duration (by cha~lging the clock rate of the Flat Clock on line 131, as will. be discussed). The physician also programs the Low Slope Selection Criterla 930 used for the compression groups 821-827 (i.e., he selects one of the states 901-904 of FIG. 9). The system stores ~an error signal in the sample compression group if the programmed Low Slope Selection Criteria 930 are exceeded during that sample compression group time period. These compression groups are shifted through the Flat Delay Window 818 into the three - compression group 821-B23 flat window 817 where they are tested for the number of compression group errors in the window 817. If these programmed criteria are exceeded (i.e., errors detected in each compression group time and number of compression group errors in the flat window3 by more than a predetermined number ~also programmed), t en the criteria for that parameter are said to be violatedj so that a "DETECTION`' cannot be present.
': . . , . , ' , :
24 !-;
' ~ ' . . ' ' ' , - ' ' ' . ' .~ -, . . . .

. .. - , - _. , ~ :

'' . .:
.
-.. . .
:.

t ~ ...................................... .
1 1711~0, , '.,~ , ~

The Flat Delay Segment is used to insert one ~ofour (as programmed) "Sample Compression Groups" T4, T5, T6 and T7 (824-827) as a time delay between the Flat Window Segment 817 and the High Slope Window Segment B}9. Thi~
section B18 is a programmable delay and ~5 implemented in Flat Delay shift Register 112 with the selection of the programmed number of compression groups being ef~ected in a Flat Delay Selector 113 of FIG. 1. The purpose of the flat delay section ~18 is to mask or ignore the Q wave portion of the cardiac cycle due to inconsistencies between patients.
The programming of the delay time enables the physician to place the Flat Delay Segment 817 safely between the Q wave and the P wave of the cardiac cycle.
.
The amount of time compressisn implemented in the Flat Window Segment 817 and F}at Delay Segment 818 are programmable to allow the physician to select the time width of the Flat Window Segment B17 and modify the delay.- This is implemented in the time compressor 111 of FIG. 1, to be discussed. For the High Slope Seyment 819 which is samples ~1 to ~16; the High Slope Selection Criteria 931 (one of the programmed states 905 or 906 of FIG. 9) are used, and a programmable higher sample rate is used for the High SlopP
Detection so that the high slope selection criteria become more difficult to meet.
~, ~
Turning now to the apparatus of the Ventricular Filter, as inllica~cd above, the output o~ tlle Vcntricular Delta ~odulator 104 is coupled to the input of the,Sample , Window Shift Register 106. A 2 ~Hz clock is fed to the sample window shlft register iO6 on line 119 and this clock is counted down to one,of 2 K~z, 1 KHz, .5 KHz, or .25 KHz ~ ~ -25 . . : . .
"' ~' ' ' " ' ' ',, ~
, ' ,~

'. ' . ~'371140f ' ' ~J . ' sample rates ~nd sele~ted ac~ording to two bi~s ~f informa-tion received on bus iines 201A compri~ing ~ portion oF a Ventricular Filter Parameter Data Bus 201. This bus couples data stored in a Ventricular Filter Parameter Control RAM
(Random ~cccss Memo~y) desigllatcd 213 of FIG. 2 wlllch determines the parameters of the ventricular filter. These parameters are changed for detecting T waves, R waves and PVCs, as described above, and the various con.trol bits of each of the three parameter sets may be programmed for a given type of detection; such as an R wave, as will be clear from subsequent discussion.

The two bits of information on bus lines 201A, as indicated, set the clock (on line 119) division to generate a Sample Clock on line 127. The Sample Clock is fed to the delta modulator 104 to define the sampling rate for the incoming cardiac signal and.determine the rate at which the .; information is fed to the shift register 106, and it also determines the clock rate for a Slope ~p/Down counter 107.
The counter 107 receives, on the line designated IN (1~3), the output of the delta modulator 104, and on a line designated OUT ~124), the output of the shift register 106.
Briefiy, the function of the counter 107 .is to maintain a running count of the number of l's generated by the delta modulator in the window heing sampled by the shift register 106. Tllus, tl-e counter 107 is a three.~bit 907 plus sign latch 910 counter, each bit corresponding to a column in 907 and the sign 910 corresponding to positive or negative relative to CENTER ZERO 911, for the table shown at the left of FIG. 9. The sign latch is set by the direction the . cou~ter increments from CENTER ZERO 911. The lines below CENTER ZERO represent negative numbers of l's or the cGmple~
' - ' ' . 26 .
, :` . . f . . . : . ~ ~ " ~a ,.
-.
:

-:` ' ~ . ' , ,, 1 171~0 ' mcnt ~i.e., thP number of O's contained in the sample window ~hift register 106). The sign bit 910 is normally used in detecting PVCc and PACs and normally ignored for other waves. This produces similar detections for either positive or negative R, T, and P waves.

The two inputs 123 and 124 to the counter 107 are fed to an internal exclusive OR gate which is clocked by the sample. clock on line 127. The signal on the line lN 123 indicates what value is being clocked into the shift register 106, and the signal on the line OUT 124 indicates what value is being clocked out of the shift register 106.
If there is a O on the IN line, and a O on the OUT line, or if there is a 1 on the IN line and a 1 on the OUT line, then there is no net change to the contènts of the shift register 106, so the counter 107 does not count. If there is a 1 on the IN line and a O on the OUT line and the slope i~
positive, then the counter 107 counts up one, indicating an increasing positive slope. If there is a O on the IN line and a 1 on the OUT line, the counter 107 counts down one, indicating a decreasing slope. For negative slopes the counter 107'counts down for a 1 on the IN line and a O on the OUT line, indicating a decreasing negative slope; and the caunter 107 counts up for a o on the IN line and A 1 ON
the OUT line, indicating an increasing negative slope.

It is the contents of the counter 107 which define whether the incoming signal mcets the programmed High Slope Selection Criteria 931 of the states designated 905 or 906 i~ FIG. 9 for the high slope segment 819 as well as the programmed Low Slope Selection Criteria 930 of the states 901-904 for the compression groups T1-T7 in the Flat Delay -: .
~ ~ 27 ' . ~ '. , ' '" ' ~.

. ~ ' ' ' '-`' 'i~? ~ . ...
1 ~ 71 1~ .

Segment 81~ and the Flat Window Segment 817. Thus, the cont~nts of counter 107 comprises a digital word that is representative of the average input signal slope over the ~,~
sample window period. The time length o the windo~, is detérmined by the number of bits in the shift register and the programmed sample clock period.

The contents of the counter 107 are sensed by a High Slope Selector 108 which is set via a bus line 201B of the ventricular filter parameter data bus 201 to establish either ~igh Slope Selection Criteria 905 or 906 (depending upon the state of the bus control bit at 201B) as illustrated in FIG. 9. T~o more control lines on the ventricular filter parameter bus at 201B enable a positive slope sign and a negative slope sign to independently or together qualify a high slope detection 126 for PVCs. The High Slope Selector 108 is operating at the sampIe clock 127 rate of the shift register 106. It generates an output signal which is a logic "1" to AND gate 109 whenever the programmed High Slope Selection Criteria are met. The other input to AND gate 109 indicates that the low slope criteria have not been violated 136.

The contents of the slope counter 107 are also fed to a Low Slope Selector 110. The selection criteria for the Low Slope Selector 110 arf~ coupled by two lines diagrammatically illustrated at 20iC of the ~entricular Filter Parameter Data Bus 201. These two ~bits determine which one of the four~possible Low Slope Selection Criteria 930 of states 901-904 are to be employed for the Flat Window Segment 817. ~ ' ;'~ 28 .

.

...... . . " . , . _ ..
.
.`' ' '' ~ : ` ` ' .

.

t l 71 ~0 If the contents of the slope counter 107 are within the criteria defined by the proqrammed .state (901 904) of the Low Slope Selector }10, a 0 output signal is generated and fed to a Time Compressor Circuit 111. The time compressot 111 is a latch flip-flop which is set by a "1" signal from the Low Slope Sélector 110 (indicating a violation of the programmed Low Slope Selection cxiteria), and is reset by the Flat Clock of line 131, which is derived from the 128 Hz clock 130, and hence is synchronous with it.
The freguency of the Flat Clock, as defined by one bit of information on a bis llne at 201D of the Ventricular Filter Parameter Data Bus 201, may be 128 or 64 Hz.
.
The ~lat Clock determines the time duration of the compression groups T1-T7 (821-827), and it is used to shift data in determining whether the Low Slope Selection criteria are met for the Flat Segment 817 of FIG. 8. Its repetition rate is slower than the rate at which data is clocked into the slope counter 107 from which the High Slope Selector 108 determines whether the High Slope Selection criteria for the :
High Slope Segment 819 of EIG. 8 are met. - :

. In other words, the sampling rate for the High Slope Segment 819 is higher than that for the segments 817 .
and 818. However, none of the data for Low Slope Selection is lost because the time compressor 11~ is a latching circuit clocked by the low rate flat clock 131, and any ti~e that a selection violation is sensed in the Low Slope Selector 110, a corresponding bit is transerred to the shit register 112 clocked by the Flat Clock. The Flat Delay shift Register 112 may be a four-bit shift regi~ter, each bit corresponding to one of the time periods T4-T7 - . --.
~ ~ ` ~ 29 . .

': .

'' ~ - ' , :

- ~ l 71140 (824-~27) of the Flat Delay.Segment 818 at the $ime of detection. In other words, the Flat Delay shi~t Re~ister 112 ~and a~sociated flat detection circuitry to be described) is clocked at a much lower rate than the Sample Window shift Regis~er 106. Hence, the "Sample Compression Groups" Tl-T7, repre~enting time segments over which the contents of the respective registers are representative, are longer for the Flat segment 817 and Flat Delay Segment 818 than they are for the ~igh Slope Segment 819.

The contents of the Flat Delay shift Register 112 are coupled to a Flat Delay Selector 113 which is programmed by two bits along lines 201E of the Ventricular Filter Parameter Data Bus. 201 to determine the number of time periods or compression groups in the Flat Delay Segment 818.
In the illustration of FIG. 8, FOUR sample compression groups are used.
' The output of the Flat Delay shift Register 112 is fed through the Flat Delay Selector li3 to a Flat Window shift Register 114, which in the illustrated embodiment comprises three bits, corresponding to compression groups Tl-T3 (821-823) of FIG. 8. The Flat Window Shift Register 114 corresponds to the Flat Segment 817 of FIG. 8, and the contents of this shift register are sensed by a Flat Error Up/ Down Counter 115 which is similar to the previously described counter 107 except that it counts the nu~`oer o~
ones ~i.e., violations of flat criteria) in the flat window shift register 114 as a number without algebraic sign. The regis~el- 114 and the couil~cr 115 are both clocked ~y the Flat Clock on line 131.
- ;~
.. . . . . .
. .
..
,- , . --- .

.

The contents of the Flat Error Counter 115 are fed to a Flat Err~r Selector Circuit 116 which is set by two bits on bus 20I~ to accept zero, one, two, or three errors ~or the ~ow Slope Selection Criterion 930--one of the states 901-904 of FIG. 9 as previously explained. If the Flat Error Selector circuit 116 is pro~rammed to accept three errors, it is equivalent to ignoring the Flat Segment 817 because it indicates that an error would have occurred in each of the three compression groups ~l-T3. In other words, the Flat Error Selector would accept up to and including three errors in the 3-bit Flat Window Shift Register.
,: .
If fewer than the progran~ed nu~`oer of errors are found for the ~lat Window Segmen* 817, an enabling signal called Flat Detect is transmitted along line 136 to an AND
gate 109, the other input of which is a signal labeled SLOPE
DETECT 126 ~rom the High Slope Selector 108. It will be observed that at the time the :Flat Error Selector Circuit 116 generates a Flat Detection ~ignal, the contents of the flat window shift register 11~ will correspond respectively to compression groups Tl, T2 and T3; the contents of the flat delay shift register 112 will correspond to compression groups T4, T5, T6 and T7 (if the: ~lat delay is 50 programmed to 4 compression groups~, and the contents of the - sample window shift register 106 will correspond to future compression groups in the high slope segment 819 of the cardiac signal.

Thus, the output signal of AND gate 109 is a signal representative of the fact that all selection criteria have been mèt, and this signal is fed to a Ventricular Detection S~nchronizer 117 which.sets:a latch when:a detection lS present. The latch is reset only after : . 31 ., ~

. . . . _ _ , : :

.
11711,~ ;
the contents of the Up/Do~n Counter 107 return back through CENTER 2ERO 911 (see FIG. 9). This prevents multiple ventricular detectio~s during any one cardiac cycle complex (such as QRS). The circuit 117 al50 synchronizes a VENTRICULAR DETECTION with the system clock which is ~t a lower rate than the rate at which tbe Sample Window Shift Register 106 and the Ventricular Delta Modulator 104 are r~locked.

. .
The ventrir_ular detection circuitry is initialized when a Lead Compensation ~LC) address (~Dl~ 711 pulse is generated as a result of Master Reset (MR) and held in reset for the duration of ADl. The ADs are described in connection with FIG. 7 in the next section on timing, circuitry. This detector reset loads the contents of the Sample Window Shift Register 106 with alternate l's and O's ~represelltative of an initial flat slope), and it resets the contents of the slope Up/Down Counter 107 to CENTER ZERO 911 as indicated in FI~. 9. The counter 107 contains a separate latch which indicates, if the contents of the counter are all O's, whether the counter is at either end position 913 or 929 or the CENTER ZERO position 9~1, referring to ~he chart 907 at the left side of FIG. 9. This detector reset ADl is used to set the flat portion of the detector 100 to a full error state so that an initial delay to the first detection in AD2 (712) may be delayed out past the QRS
complex previously detected ~V PET 709) or created (AD5) in generating the current master reset 710 and ADl (711) if so desired by the physician. If the first detection is delayed by a- long ADl and the flat detect 136 is enabled by the T-wave parameters, a T-wave is used for capture verification (to be discussed), otherwise a short ADl and ignoring the t . :

,

3~
..
.. . . ' . ' , . r ,........... , ~ . ' ,' . ' ~ i 71 1,~ 0 ~

- - flat detect.l36 in the T-wave parameters will use the R-wave created by a stimulating output in the previous AD5 for capture verification.

~ When the flat poxtion of the'detector is reset, ADl in line 293 is used to set the time compressor 111 to an error state and set the Flat Delay shift Register 112 (T4, T5, T6 and T7 in FIG. 8), the Flat Wihdow Shift Register 114 ~.
(Tl, T2 and T3) and the:Flat Error Up~Down Counter llS all to a full error state ~by the set signal in line 131). . ~ ' ':
Thus, if all of the selection criteria are met, ~~
the AND gate..,lO9 ,generates an output signal 'which is synchronized with the system clock in the Ventricular Detection Synchroniz~r Circuit 117, and a corresponding detection signal labeled V DET is generated on line 138.
,:
The ventri:cular filter : 100 is set with corresponding sets of parameters to detect R waves, T waves and PVCs during various portions of the cardiac cycle as will be subsequently described. The signal V DET on line 138 is representative of the detection of an event corresponding with the parameters which have been set in the ventricular detection filter from the Ventricular Filter Parameter Control Memory 213. Tlle programmed parameters f~r the Ventricular Detector are summari7.ed in Table 1. They also apply to the atrial detector. , ' ::
- . ' : ~:
:
', ' . '' :, - ~ . . - ~ -~ ' ' ' ' `"i ~
.
33 ~ ' .... ~ . . , ~ _ .:
. .

.

_ - TABLE I - DE~ECTOR'S PROGRAM~lED PAl~IETERS
~ ~ ~1 140 - Re~erence - Circ~it Numerals No. Bits B~s Ports Function Gain C~ntrol 105, 105A 5 202A, }g9G Sets gain of Delta Circuit . }lodulator 408-412.
Sa~ple Windcw106, 106A 2 201A, 199A Determines Sam~le Rate Shift ~egister for Del~a ~odulaLor - 104, Slo~e Up/Down Counter 107, and wid~h of "windo~;" o~ Shif~
Register 106.
High Slope 108, 108A 1 201B, l99B Selects criteria gn5 Se1ec*or or 906 (FIG. 9) for High Slope Segment 819.
.. . .
- Slope Sign 108, 108A 2 201B, 199B Enables positive and Ena~le negativc high slope signs to indep~ndently . qualify the ~olarity . of a high slope de~ect.
Iow Slope 110, llOA 2 201C, 199C . Selects criteria Selector . 901-904 (FIG. 9) of compression groups - . . for Fla~ Delay Segment 818 and . Flat Window - . . Segment 817.
Ti~e Cl~npres- 111, ll]A 1 201D, 199D Determines rate of .
sor . Flat C]ock (length of "compression groups" T1-T7 of FIG. 8).
.
~lat Delay 113, 113A 2 201E, l99E Determines number Selector of compression groups T4-T7 (824-827) in Flat D~lay Sc~mcn~
818.
~lai Error 116, 116A 2 201F 199F ~et~rmincs acce~table Selector . n lJml~c r of violation~
of s~lcc~ed criteria ~or Flat Windo Scgm~nt 817.

34 : -: .

- . : ::

::
.:

. : . . ~

~ ~ t ~711~
.

. As indicated, the gain of the Delta Modulator 104 may be varied. This is accomplished in the Gain Control Circuit 105 which receives information along a Ventricular Filter Gain Control Bus 202A, as will be disGusse~. Ther~
are five separate bits 408-412 of information fed to the Gain Control Circuit 105. Two of these bits are additive gain con~rol bits 408 and 409, and they set the feedback current in the delta modulator gain-controlled current source 407 of FIG. 4 so that the magnitude of the charge current to the delta modulator capaci~or 414 can be set to relative values of 1, 2, 3 or 4. In addition, there are two multiplier bits 410 and 411 which.~ontrol the reference for the currellt sou~ce 407. Tl-ese can be set to relative values of 1, 5, 27,.or 32. If both multiplier bits are a logical "0", the multiplier value is 1; and if both bits are a logical "1", the multiplier value is 32 (the sum of 5 and 27). Thus the charging current can be set to relative values of 1, 2,. 3, 4, 5, 10, 15, 20, 27, 32, 54, etc., to form a companded or log type of output control. These four bits are d~namically controlled as the sensing circuit goes through the cardiac cycle. One additional bit 412 is used to control the high multiplier value for a lower multiplying factor of .18 in place of its normal factor of 27. This bit is not varied through the cardiac cycle. Its purpose is to give better resolution on low amplitude R-waves when set for 18X multiplication and provide the capibility of the tracking high amplitude R-waves when set to 27X.

After a stimul~ating pulse is generated, there is a period of time ADl (which may be of the order of 5-35 milliseconds) in .which the. ~esidual charge on the stimulating.electrode is compensated by shorting the lead to , . : - ~ . :

` ' ''' ' ' ~ ' ' ' ,, .. ,. .... .. .. . ' ! -- . ' " .
_ ' ' , ' -,';

.
'~ ' ` ' : ' ~ " ' 1 1 71 1~0 .
circuit ground. During this pe~iod th2 delta modulator has it5 high gain multiplier bi~ set to lB or 27X. The delta modulator is then permitted to more rapidly adjust to the expected large step function while compensating ~or lead polarization voltage or follow the R-wave complex. Due to the large differance between 27X and lX, the delta modulator is first stepped through SX 5for 8 milliseconds) on the way down to its lower AD2 value at the transition time from AD}
to AD2 in the cardiac cycle.

Timinq Circuitry ~4 , The main time base is established by a crystal oscillator 227 generating a signal 251 at 32,768 Hz. This .. . . .
signal is fed into a Crystal Oscillator upper Divider 226, the output of which is a clock sign~l which normally ruDs at 128 ~z and is coupled on a line 252 to a Crystal Oscillator Lower Frequency Divider 225. The lower divider 225 is a counter clrcuit; and its parallel outputs are coupled by means of a bus 2~8 to one set of inputs of a digital comparator 224. The other set of inputs to the digital comparator 224 are received from a ~rystal Time Mark Data Bus 246A, which receives information from a Time Mark Memory 210. The Time Memory 210 contain~ a series of words which represent, in digital form, various time marks in a cardiac cycle. A typ~cal cardiac cycle is shown in FIG. 6.

In FIG. 7 (which has approximately the same time scale as FIG. 6), there is shown a timing diagram of the portions into which a typical cardiac cycle lS broken.
Referring then to line 7Ll, assuming that, for purposes of - - : - - . . :

, . ...... -. . , , ~ _ ^

:

1`~ , ~;.j, . , ~ , , 1 ~ 71 140 ~ ~
illustration, a natural heartbeat is detected and the pulse V DET 7~9 is generated by the Ventricular Detection Synchronizer 117 of FIG. 1, this pulse is transmitted on line 138 to a state Controller 231 which generates a master reset (MR) pulse as seen on line 7L2 of FIG. 7. In a manner to be described presen~ly, a series of se~uential time pulses are generated at predetermined times in a cardiac cycle which are, for the most part, programmable. These are the time marks TMl-TM5 (720-724) of FIG. 7.

The period between Master Reset 709 and TMl 720 is referred to as AD1 ~711). It is during this tlme that digital filters are reset and compensation for residual charge on the stimulating lead is made. The time between TMl (720) and TM2 t?21) is referred to as AD2 (712); and this is the ventricular refractory time of the heart. If the heart had been electrically stimulated, capture verification by detection of T-wave takes place in this time period. That is to say, the ventricular filter 100 is set with parameters, determined by a physician, to identify a T-wave. At the physician's option, the generated R-wave could be used for capture verification by appropriate programming discussed above in connection with the ventricular filter. TechnicalIy the pacemaker's Ventriclular Refractory Time Period is actuall~ the sum of the ADl (711) and ~D2 (712) but in this embodiment AD2 (712) is referred to as Ventriclular Refractory Time.

. The time between TM~ (721) and TM3 (722) is referred to as AD3 (713), and durlng this time, the ventricular filter 100 is set to detect PVCs. lf the i detection criteria for a PVC are met during this period, and 37 `
.. . . . " .

- ~ -- . , . . , . _ .. .
.
- ~. , : ' ~ ' : ':
:

1 171140 ~

the system is accordingly enabled, ,a shortened ventricular rate $ime out period ~f 550 miliiseconds may be set to try to reestablish normal sinus rhythm. This is xeferred to as "~ .
negative hysteresis as will be described with FIG. 11 below.

The time period between TMl (720) and TM3 ~722) is the atrial r~e,fractory period 725 of the heart. The time period between TM3 (722) and TM~ (723) is referred to as AD4 (714), and it is the normal ventricular rate time out period. If a natural heartbeat is not detected by TM4 ~723), thcn a stimulating pulse is gencrated during the subsequent time period AD5 (716) and a Master Reset 717 is - ~
generated immediately thereafter. , Returning now to FIG. 2, when the State Controller 231 generates a Master Reset signal, it lS communicated to the crystal oscillator dividers 226 and 225 to initialize them and to a Time Mark Sequence Counter 232 (upper right hand corner of FIG. 2) to start that sequence counter. The Time Mark Sequence Counter 232 generates an address code (comprising fo~r parallel bits) which is transmitted along a Ventricular Address Bus 249 to a Time Mark Address DecQder 206. The decoder 206 decodes the address on the bus 249 and ' , '~
causes the contents of the decoded address in the Time Mark Memory 210 to be placed on the Crystal Time Mark Data Bus ' ' ~ ~' 246. The information is then fed 246A to one'input of'the comparator 224. As the lower divider 225 continues to cGunt the~signals from the Crystal Oscillator, the comparator 224 will eventually detect equa~lity~ on line 254 to generate one ~ ~;
of the time mark signals TMI-TM5 ~720-724) described above.
These time mark data words are arranged in sequence in the ,!'j ' Time Mark Memory 210, -and each memory~locatlon, as indi-' ~ ' 38'~
'' :: ~ :- ' ~ ; ., , ... . . .

: . : :
.
, - ~ :- ' ,, :
: ~ . ~ ..

-- ~ .

cated, defines in binary coded form for its associaked Time Mark. Thus, the various time marks are capable of being progra~med.

Functions of the VCO

As seen just to the left of the Crystal Oscillator 227, a Voltage-Controlled Oscillator (VCO) 217 is used as a backup oscillator; and it has associated with it a minimal timing circuit similar to that just described, incIuding a VCO Upper Divider 216 which feeds a VCO Lower Divider 215, the output of which is fed to a VCO Digital Comparator 214, the other inputs of which are received from a VCO Control Nemory 209 which contain the same TM4 (plus an alternate) coded time mark word as the Time Mark Memory 210 for the crystal oscillator. The time mark addresses on the Ventricular Address Bus 249 are overridden by the Rate Limit Controller 236 in the VCo Control Addrèss Decoder 205 which addresses the memory locations in the VCo Control Memory 209 and feeds the decoded time mark data along a VCO Data Bus 245 to comprise one set of inputs to the VCO Digital Comparator 214.
.
. . .
Whereas the crystal clock is used for generating the various timing signals in FIG. 7--namely, TMl, TM2, etc., the VCO, on the other hand, is primarily concerned with generating the Rate Limit Enable (RLE) signal 715, 60 it has only one time mark which is seen as line 7L8 of FIG.
7 in relation to the multiple time marks of the crystal oscillator.

. . . ,:. , -` : . . , . ' '; - -- ~ . .. ~ . , ., :~

...... ...... ~. , ~

1 1711~0 .
By setting the rate o~ the VCO to be higher than that of the Crystal Oscillator, and by using the same data in the codcd time mark for. con~parison in both the Crystal Oscillator Compar2tor 224 and ~he VCo Comparator 214, the VCO Comparator 214 will generate an output signal (indi-cative of egua}ity between both inputs) before the Crystal Oscillator Comparator 224. If the comparators 214, 224 generate their respective TM4 outputs in the proper sequence, the system operates normally. However, should the Crystal Oscillator Comparator 224 generate an output signal before the VCO Comparator 214, the VCO Comparator is used as a hold off to limit the rate of the system. In generating time mark TM4 (723), the signal RLE ~Rate Limit Enable), as seen in FIG. 7, on line 7L8, is taken from the output o the VCO, not the crystal oscillator, and it is used to inhibit generation of a stimulating pulse until the signal RLE goes high, as indicated at 744. ln this manner, the VCO is used to "pace" the Crystal Oscillator in the sense that the system requixes an enable 744 before the stimulating pulse AD5 (716) is generated. If this sequence is wrong, the system enters into Rate Limit Processing to be described.

' In addition, the VCO is used for establishing an ~lective Replacement Time (ERT) indicator. That is, the rate of the VCO oscillator (actually the output clock rate-, 257 of the VCO Upper Divider 216) is set to be slightiyhigher (10 to 15 per centj than the corresponding crystal oscillator output clock rate 252 of the Crystal Oscillator Upper Divider 226 and its (VCO) repetition xate 257 is dependent on the terminal voltage of the battery as detected in the Mirror Reference Generator 218. As the battery depletes, the period of the VCO RLE 744 will increase to-'. ,. ' ' , ' ' .

', , , " ~"
, :~

- : :,. ,.,, . . :

~? ,~, .

1~1711~'0 wards the period of a corresponding crystal oscillator period TM4 t ~23 ) and when ~he signal RLE becomes equal ~
TM4 for the cryst~l, the system goes into a mode o operation referred to as Rate Limit Processing, described i~
a subsequent section with an object of establishin~ an Elective Replacement signal, to indicate the battery or pulse generator should be replaced. For the present, not only is the VCo used to determine battery depletion, but, as will be described, should the crys~al Oscillator fail to operate as designed, the VCO will be substituted as the main timin~ source in the system.

In addition, when a physician, during the course of a checkup, applies an external magnet, the VC0 is used to determine the time base, not the crystal osciIlator.
However, the crystal oscillator determines the width of a stimulating pulse. Thi6 enables the physician to check t~e operability of the rate limit circuitry as well as to verify capture under realistic circumstances. Finally, as described more fully below, the rate of the VC0 is used to sense moisture invasion o~ the pulse generator enclosure ~o~
the pacer circuitry, to determine whether moisture has breached any of the seals.

Bus Arrangemene and MemorY Read/Write .
It will be observed that the Ventricular Filter Parameter Data Bus 201 may be connected to a Ventricular Fi}ter Gain Control Bus 202 by means of a set of trans-~ission gates 244. Similarly, transmission gates 243 !;
inteiconnect the Cryst~l Data Bus 246 and the Ventricular ~ . . . .
-`;: 41 ; - -.
~: .

. . . , . , _ -~, ~ ~711~ :
, Filter Gain Control Bus 202. Still another set of trans-mission gates 242 interconnect .the Crystal Bus 246 with the VCo Data Bus 245; and a set of transmission gates 241 connects the vco Data Bus with an Atrial JAM Data Bus 195.

Each individual 6ection can serve its function during normal operation, but it is also capable of being connected into a continuous bus for writing information into or reading information from any selected memory. Each control RAM or memory-is connected to the data bus by means of a set of read gates and a set of write gates, diagrammatically illustrated as R and W respectively. The read gates are used to transmit the contents of an addressed memory~location onto the data bus; and the write gates are used to write from the data hus into an addressed location.
For example, referring to the Time Mark Memoxy 210, if it were desired to change, for example, the Time Mark TM3 during a write cycle, an Address shift Register 180 (see the center of the top ro~ of FIG. 1 ), generates: an address corresponding to the address of TM3 in the ~ime Mark Address Decoder 206 which decodes that address; and the new data would be transmitted fro~ Data Input/Output Shift Register6 lB2 onto the Atrial JAM Data Bus 195, under control of a Transceiver State Controller 176~ With a Master ~eset (MR) signal the data bus transmission gates 241, 242j 243, and 244 c.onnect the data bus together and the write gates (W) associated with the Time Mark RAM 210 would then be enabled, again under control of the:Transceiver State Controlier 176, and the new word would be. written into the addressed memory location via data bus 246~ This occurs during a;Naster Reset so the pacemaker opera:tion is ~no~ interrupted. as determined by the programmer which forms no part of ~he .
:

.. . . . . . . .

. _.. . . ., , . , . . ~ . , . - . - -~ :, :
"' '""'' ~' ,' '; ' ' ' --` A~ ~

1 1 71 ~0 present invention. In this manner, the various operational-and definitional para~eters used in the ~ystem can b~
pro~rammed or ~hanged.

State Controller Referring to FIG. 14, the State Controller 231 logic diagram includes Master Reset Latch 1401, Mastex Re~et Width One Shot 1402, Last Reset Paced Latch 1403, Output Pulse Width Source Control Logic 1404,~VCO Reset Width One Shot 1405, TM5 Catch Latch 1406, TM4 Catch Latch 1407, Start Pulse Width Lower Divider Reset One Shot 1408, and the crystal lower divider time mark (TMl-5) Phasing Logic 1409.
The inputs and outputs to the state controller are identified in Table II.

Referring first to the Time Mark Catch Latches 1406 and 1407, the function of latch 1407 is to store the occurrence of Time Mark 4 until Rate Limit Enable has occurred in the event of the circuit operating under rate limited conditions. It also permits the rate limit enable function tQ occur in AD4 without interference by the incidence pulse Cl on line i459 which also occurs at TMl, TM2, and TM3. The signal Cl is representative of an equal to comparison between the Time Mark Memory 210 and the L~wer Crystal Divider 225 having occurred in the comparator 224.
In other words, this occurs at ~Ml, ~T~2, TM3 and TM4 as defined by Cl within ADl, AD2, A~3, and AD4 respectively.
The output of latch 1407 is coupled to a gate 1491, ~he output of which inhibits the crystal clock from incrementing the Time Mark Seguence Counter 232 until Rate Limit Enable 744 has occurred.
43 ~
~' ' . ' . - , , ~. . . . , , :

_ ~ . TABLE II - STATI. r~o~lRoLLER t231? INPUTS_AND OUTPUTS
INPurrs TO STA~E CONTROLLER

INPUT NAME FIG. 14 REF. FIG. 2 REF. ~UNCTIO~?.~L DESCRIP.ION
DISABLE COMPA~E 1410 255 . Inhibits the generation of a time mark (C1) during an a~rial JAM sequence.
XTAL CMP 1411 254 Raw equal to output of the crystal oscillator digital comparator 224 indicating bus 246A equals crystal oscillator lower divider output 248.
XTAL C~ 1412 252 Adaptive crystal derived ~ys~e~ clock.
ADS 1413 293 Time Mark sequence & 1413 address 5 = Pulse Width . 716. ~`
AD4 1415 293 Time Mark sequence address 4 ~ R-wave time window 714.
AD3 1414 - 293 Time Mark sequence address 3 = PVC time window 713 AD2 1420 293 Time Mark sequence address 2 = Ventricular Refractory time window - 712.
2 XHz XTL CX 1416' Z ~Iz 2048 Hz clo~k from Crystal Oscil1ator U~er Di~ider ?
. 226.
1 ~z VCO 1423 1 KHz ~ I ~{z VC~ derived clock VCO from the VCO U~er Divider 216.
PS9 ~ PVP 1417 203H Allows a burst of PVCs to recycle the~ - :
pacemaker refractory.
. . .
PS10 S~UT DOWN 141~ 203H Status Control RAM Bit PS-10 used to power down pacemake circuit.

. ~ .

.: : , . . ~
. .
.. , ~ .

- TABL~ Sl'AT~ CONTROLLER t231) INPUTS AND OUTPUTS
~NPUTS TO STATE CONTROLLER
. (Continued) INPUT N~ FIG. 14 REF. FIG. 2 REF. FI~CTIO~AL DESCRIPTIO,Y
V REV 1421 139 Ventricular ~eversion detected during current cardiac cycle.
V DET 1422 138 Detect output of Ventricular De~ector 100.
RL>~ 1424 250 Circuit running in rate limit mode.
MP2 1425 - 284 Ma~net Phase 2 = f~rce : raLe limi~ed mode RLE ~1426 250 Rate Limit Enable 715.
.
WPS 1427 270 Wide Pulse Status indicates if the progranuned Pulse WidLh ~PW) is wider than l millisecond OUTPUTS FRO~l STATE CON~ROLLER

OUTPUT N~ ~ FIG. 14 REF. FIG. 2 REF. FUNCTIO~AL DF.SC~PT1ON
.~
Cl 1430 285 Increment address (Time -~
Mark 720-724) in Time Mark Sequence Counter 232.
XTL RST 1431 253 Reset Crystal Oscillator Lower Divider 22S.
Cl ~ AD4 .1432 295 Hold crystal compare for - Ra~e Limit ~nable.
HR 1433 ~ ~las~er Reset = begin s,ew cardiac cycle.
LRP 1434 2~0 Last Reset Paced = last reset ~as not from a - ventricular detection.
OVTPUT - 1435 267 Ou~rut a st~mula~in~ ;n~lse ~or Lhe dura~ion o ~his signal.
RL RST 1436 253 Reset VCO rate limit Lo~er Divider 214 - . and o~her functions.
' ' .

' ~
. ., ~

l 3 ~ 0 .
The function of latch 1406 inhibits the generation of the Master Reset pulse until the signal ~D5 ha~
terminated. The output of the latch 1406 is fed to a gate 1474 having a~ one input the signal AD5 on line 1418, and the output of the gate 1474 feeds the set side of the Master Reset Latch 1401 made up of gates 148~ and 1485, the output of which lasts the duration of the Master Reset Pulse. A
Master Reset can occur from any one of the signals indicated as being an input to the Gate 1484. These signals may be broken down into inhibiting ~signals or enabling signals.
The enabling signals include the coincidence of Cl and AD5 fed through the gate 1474 and representative of a time out (generating a stimulating pulse); the output of gate 147 generates a Master Reset upon the detection of a natural heart`oeat during the time periods AD4 or AD3 (non refractory time), which may be inhibited in the event of the result of exceeding the predetermined reversion count on line 1421 if not disabled by PS9 and a tachycardial chain of PVCs (line 1417); on line 1446, when the rate timing is derived from the VCo during magnet application or when the crystal oscillator has run away. The signal which inhibits the Master Reset Latch is fed on line 1419 and is PS10 which is represent,ative of "power down", which is a power conser~
ation operating mode for shelf liLe storage which will be discussed below. Reference numeral 1402 designates a one shot circuit which defines the time duration of the Master Reset pulse.
' ' ' ' '' ' A latch 1403 made up of Gates 1488 and 1489, called "Last Reset Paced," stores an information bit representative of whether th,e last reset had occurred as a result of a stimula~ing pulse AD5 having been generated by ~ 46 . -'` - ' ' ' ' ~ , ' ' ' ." ~:
..... . , . . .. ,,,, ~-. ' ' ' .

? ~

~ 1 7 ~ 0 the circuitry, and is simply a one bit memory for thi~
purpose, the output line being designated LRP 1434.
Referring back to FIG. 2, ~here is a line Cl desi~nated 2B5 which is fed from the State Controller 231 to the Time Mark Sequence Counter 232. It is this signal which increments the Time Mark Seguence Counter -232 for seqUenCiDg the Ventricle Address ~us 249 for generation o~ pulses TM1-TMS
of FIG. 7. Briefly, the Time Mark Sequence Counter 232 is a conventional digital counter 1501 shown in FIG. 15, the outputs of which indicate which portion o~ the cardiac cycle system is operating. An inhibit gate 155* is used to inhibit generating the comparison signal until RLE 15~6 has timed out if the system is operating in AD4, as discussed.
' ~ eferring to the Crystal ~pper Divider Loyic diagram in FIG. 16, it will be recalled that the system operates basically on 128 Hz. clock during time periods ADl-AD4, but during AD5, the 32 KHz crystal signal 1610 is used to generate the timing for a stimulating pulse, using the same dividers 225 and comparator 224. This is sometimes referred to as an adaptive clock 1625 because it changes frequency as a function of the portion of the cardiac cycle in which the system is operating. It is also possible to reduce the 128 Hz. frequency by 12.5% when either of the ERT
1613 or loss of capture 1614 indicators are present as discussed. The adaptive clock signal 252 is ~ed from the crystal upper divider 226. The state controller controls the adaptive clock along line 295. ~he crystal lower divider 225 is initialized twice during a cardiac cycle--once by a Master Reset, and once by means of a Start Pulse Width One Shot circuit l~B in FIG. 14 which generates a narrow reset pulse at the beginning of ~D5, which signal is fed in on li~e 253.

,7 _ _ .. _ . ' ' ~ .' ' ., _ .
' ' ~ ' ' ' ' ' ' ~ , ' ~

- IJ71~40' The rate limit and ERT control logic o~ FIG. 17 i~
shown as a separate ~unctional blvck designated Rate ~imit Controller 236 in FlG. 2. It contains the counter 1701 which counts the number of occurrences of the crossover of RLE and AD4 (indicating that the battery may be being depleted). This is discussed in more detail in connection with the flow diagram of FIG. 12.

.
Atrial Filter; Settinq P-R Delay; The JAM Function .
Referring now to the lower left hand portion of~ ~o~
FIG. 1, and particularly the atrial filter lODA, it contains functional blocks similar to those which have already been disclosed in connection with the ventricular filter 100; and for brevity, those functional blocks in the atrial filter which have a corresponding functional block in the ventricular filter have been identified with the same reference numeral followed by an A. The atrial filter acts in a manner similar to that disclosed in connection wi~h ventricular filter, seeking to detect a P-wave or PAC by identifying a Flat Segment, a Flat Delay Segment, and a High Slope Segment.

.. . .
Coincidence of all the necessary conditions is determined in AND gate lO9A, and an Atrial Detection Synchronizer 117A generates a ~orresponding output pulse in synchronism with the 128 Hz system clock. This output pulse i6 fed on a line 13~A to a circuit referrèd to as the JAM
controller 1690 . ~
` 48 ~ ~;
.
~ .
,, ' ~, ~

. , .

-: - ~ . ' ~ , .' . .

.

- . : :, . . ~ .

The iunction o~ the JAM Controller 169 is, in the - event of a P wave detection, to load a time word (the JAM
word~ into the Crystal Oscillatox ~ower Divider 225 (and VCO
Lower Divider 215) which i5 a predetermined time to define the desired P-R delay inte~val relative to the Ventricuiar Rate Time out Period (TM4 723 of FIG. 7). This is gxaphically illustrate9 in FIG. 10; and it will be assumed for purposes of illustration that a physician has already determlned that a desirable P-R delay interval is lSO
milliseconds and that the end of the Ventricular Rate Time Out Period TM4 is 900 milliseconds--that is, if a natural ventricular beat is not detected within 900 milliseconds o~
the previous paced or natural beat, then the system will ~enerate a stimulating pulse. The JAM word is, therefore, .3 time word egual to 750 milliseconds. If the Atrial Detection Synchronizer 117A generates a detection pulse and transmits it to the JAM Controller 169 sometime~ in the period AD4 (it is not enabled prior to TM3 which ends the atrial refractory time), then the contents of the lower dividers 225 and 215 are set to be e~ual to 750 milliseconds irrespective of what the actual time is. This is accomplished along data buses 246B and 245B respectively.

Referring to FIG. 10, if the P wave is detected at 550 milliseconds in the cardiac cycle, the normal ventricular rate time out period will be shortened as indicated on line lOL2 of FIG. 10. Conversely, if the P
wave is detected at 300 milliseconds into the cardiac cycle, that particul-ar ventricular rate time out period will be extended to 950 milliseconds as indicated on line lOL3.
This is done, as indicated above, ~o synchronize the ventricle with the atriu~ to establish a normal sinus rhythm in which contraction of the atrlum helps to f111 and time :, . . , : ~ .

.

: . - -': ' : ~ . ' :
, - . , : -.
.

~.r~

' ,' the ventricle. If a natural R wave i8 detected during the preset P-R delay interYal, a stimulating pulse is not generated, and a Master Reset is generated to establish a new cardia~ timing cycle. It will be observed that the transmission gates 242, 241 are also enabled by the ~AM
signal so as to connect the Crystal Data Bus 246 and the VCo Data Bus 245 with the atrial JAM Data Bus 195. Thus, the data word that is loaded into the Crystal Oscillator Lower Divider 22~ is also loaded into the VCO Lower Divider 215.
~he word that is loaded (JAM~E~ is stored as a sèparate word in an Atrial Control R~M lB~, which is actuated by the JAM Address 186 through an Atrial Memory Address Decoder 187 for any time a P wave is detected after the ventricle re~ractory period and provided an MR is not being generated.

After the JAM Controller 169 disables the outputs of comparators 224 and 214 by means of Gates 230 and 234 respectively and connects the segments o~ the data bus as indicated, and loads the contents of the preset time memory w~rd from the Atrial Control RAM 188 into ~he respective dividers 225 and 215, it then disconnects the segments of the data bus and re-enables the comparator outputs in a nested sequence 1970 as shown in the lower right hand c~rner of FIG. 19. It hereafter ignores any subsequent JAM si~nals ~rom atrial detections 138A until a Master ~eset .has occurred.. .

Because the JAM word is loaded into the lower di~iders 215 and 225 along the VcO Data Bus 2453 and the Crystal Data Bus 246B ~connectqd in common by the transmission gates 2423, the word also appears momentarily on the other inputs of ~he co~parators 214 and 224 at VCO
Data Bus 245A and XTL Data Bus 246A. Thus, th~ comparator~
. . ' .
. . . .

:
.
~ ' ~

- ~ ~711~ t ' "' will gene~ate a~ 'lequali' output during this time on line~
256 and 254; and this output signal is disabled by Gates 230 and 234 until the normal outputs from the VCO Control RAM
209 and Time Mark RAM 210 are re-established. This is what is meant by reference to a "ne ted seguence" above.
.
Atrial refractory time is defined as the time periods AD1, AD2, and AD3. Duri~g atrial refractory PAC
parameters are loaded into the Atrial Digital Filter lOOA
and the system counts the number of atrial detections on the Atrial Reversion Counter 118A. When this count exceeds a predetermined number as indicated on the Atrial Control Data Bus l99J, a signal referred to as Atrial Reversion (A REV) 139A is generated which is used by the JAM Controller 169 to inhibit the JAM function.
', ~ .' ' ~ .

Atrial Input SteerinQ
. .
The overall object here is to steer the input signal, if desired, from the Ventri d e Lead 101 to th0 Atrial Delta Modulator 104A. The reason for this is that it may be possible, in the case of a previously implanted cathcter having only a single electrode implanted in the ventricle to receive enough signal identifying the P wave~
(even though the electrode is in the ventricle), and in that case, the signal from the ventricle lead would be routed to the atrial inpuk filter lOOA.~ Referring to the block diagram of FIG. 1, there is a lead ?20 from the DC Isolation :-Clrcuit 102 through a tie point 103 to an analog transmission selertor gate designated 103A. This may be a conventional analog switch, the other input of ~hich is received ~rom the DC Isolation Circuit-102A coupled to th~

' 51 .: . , f .

~ '"' ' ' I ~ 71 1~ -Atrial Le~d and Electrode at 101~. A signal is received on one lead of the Atrial Control Data Bus 199H, to st~er either the DC insulation output from the atrial lead or the ventricle lead to atrial digital filter. It may al~o be desirable to implant a separate lead, not in the heart, but in muscle surrounding the pacemaker to sense a P wave in the muscle. In this case, the analog gate 103A would be used to route the output signal from the muscle lead (in place of the atrial ring lead in 101A), through the atrial DC
Isolation 102A, to the AtrIal Delta Modulator 104A.

.
Status Control RAM
. ~ .
As iDdicated above, a main feature of the inventian is that major system functions can be disabled under program control. This has two major advantages.
First, from the viewpoint of manufacturing, the same large scale integrated circuit can be used to produce a "family"
of cardiac pacers all of which can have the same "operational" history. The other major advantage is that once the pacemaker is implanted its operation and functional configuration can be changed substantially under program control without the need to directly access the implanted pacemaker.

~ he Status Control RAM is designated 211 in the block diagram of FIG. 2 and its principal function is, under program control, to selectively disable control functions.
It does this by communicating along the Ventricular Control Bus 203. The memory bit~locations are designated by the PS
prefixes and these status bits are summarized in Table III.
.
One important memory bit in the Status CGntrOl MM 211 is ~i 52 . , .
- - ~

- : . : - :

.: ' -.: . ... .
" . ~: : : ~ :

11 7I 1~0 r ~
TABL~ P~3YSICIA~ STAT~S (PS~ CONTROL sIT SU~ARY

~HYS. BLOGK DIAGRAM
STATVS SYMBOLIC REFERENCE NOMINAL
NUMBER NAME BUS BLOC~ FUNC~IONAL DESCRIPTION STATE
PSO Vent - SW INV 203B 220 EXCLUSIVE OR with reed switch 0 PS40 _Atr - SW INV 203B 220 (inverts switch function). __ O
PSl Ve~t - MAG FI~ 20I A ~- 106 Disables detectors with PS41 ` Atr - MAG FIX 199 A, 106A Reed Switch (MAG). I

PS2 ~P2 Enable203N 239 Limits Rate Limi~ High to O
- 32 nulses with HAG
PS8 - ~P4 Eoable . 203N 239 Enablës ~fAG Phase 4 for delta mod out ~ ~G
PS48 Yent - Di~o w/~G l99K 172 Vent electrogram outputs during MPl~MP2+~fP3.
PS~9 Vent - DMO CONT 199K 172 Vent continuo~s electrogram O
outpu~s.
PS88 Atr - D~O S/MAG l99K 172 A-r electrogram outpu~s during O
~PI~MP2~MP3.
~S89 Atr ^ D~10 CONT l99K 172 Atr continuous elec~rogram O
outputs.
~ PS48, 88 CONTPS49,89 ~G Electrogram - . 0 0 None ; . I Wit}l Mag--. 1 O .~ ntil.Mag.
l l - Continuous - -. , .

~ 1 7~ l~V
,~ , .
T~BLE lII - PHYS~ClhN S'l'~TUS (PS) coN~rRoL ~IT SU~MARY
(Continued ) PHYS. .BLOCK DIAGRAM
5TA111~ SY~BOLIC REFERENCE ~IN~
.~F.R NAME BUS BLOC~ FUNCTIONAL DESCRIPTION STATE
PS99 EXI~ 203C 222 Exits to safe operating O
203N 239 conditions (~P2 ~ith 60 PP~I
203P 209 min. to approx. 120 PPM max.
rate, I or 2 ms pulse width, and at least 2x output voltage) at the first ~ -application of ~ag. and stays until program~ed out by ~ pro~rammin~ PS99 back to zero.
PS3 IXV Out 203C 222 Turns off first output ~ I
vol~age multiplier.
PS11 3XV Out 203C 222. Turlls off second output O
voltage multiplier.
PSll PS3 Output ~lultiplier Sta~es '~
O 0 3X Both O 1 2X First 1 1 lX None PS4 CV Enable 203F 228 Enables capture ~ O
veri~ication ol)cration~
PS18 CVA-3XV 203F 228 Turns on 2nd output 0 voltage multiplier ~stage.
PSl9 CVB-WPW 203F 228 Uses wide pulse width. - 1 -- . .
, PS~8 PS19 - NOTE: ~ate is CVA 3XV CVB~~PW @ 4 Loss ~ 1I Loss decrea~sed by O O WPW --12~ as a loss of O 1 WPW 3XV
- capture indicator 1 0 3XV WPW

'~
.

:

~.

:

, 114~
T~BLE III - PIIYSICIAN STATUS (PS~ C0NTROL BIT SUM~RY

(Continued) .
PHYS. I BLOCK DIAGRAM
STATUS SY~BOLICRF.FERENCE NOMmNAL
NUMBER ~AME BUS BLOCK FUNCTIONAL DESCRIPTION STATE
_. .
PS12 ATO En~ble 203D 238 Enab. automatic tachycardia 0 overdrive funct PS20 ATO-LSB 203D 238 LSB of sequential PVC 0 . detections ~ ATO.
PS21 ATO-~SB 203D 238 MSB of sequential PVC 0 detections i ATO.

PS~ ~S20 Sequell~ia1 PVC Counts A~O MSB A~O LSB _ _ Before ATO Start .
- PS80 OR Enable 199L 174 Enahlcs Overdrive oommands from 0 external system to Overdrive system tirning and deliver - a stimulating pulse AD5 and rese~
timing with a Dormal paced ~laster Rese~. -PS83 Steer ATR 199H 103A Steers atrial input from atrial Or' Input lead to vent. lead.
PS82 E~able JAM199R 169 Enables P-synchronous mode of O
pacing.
PS81 A~R Shut 199A 106A Disables clocks in atrial LGwn 199C 110A de-ector and po~ers it do~n.
: 199G 105A
PS lO Shut Down 203M 218 SLOPS ali clocking~and stops 0 all bias curren-s except crystal oscillator to shut do~n pacemaker circuit current drain to extend shclf life or disable pacemaker.
Pacemaker circuit is re-enabled : ~ and operates as it ~as prG~rammed prior to shut do~n by application of a ~agnet or Po~er-0n reset.
. :

., : ~: , ' .. : .
. , ~ .
, . . . ~
.:

TA13L~ PIIYSICI~ S1~TJS ~ ON'rRO~ ~IT SU~I~tARY
(Con~inued~

PHXS. BLOCK DlAGRAM
ST~TUS .S~lBOLIC REFERENCE NOMINAL
~ER N~ BUS BLOC~ FUNCTIONAL DESCRIPTION STATE

PS~ ~h~ @ ~PR 203G 233 T-~ave parameters @ FPR.
201~ ~06 201C' 110 PS6 PVP @ FPR 203G 233 PVP/R-wave parameters @ FPR. O

201C ~0 -~

ln ad~ition to selecting the fil~er ~arameters to be used during the First P.lrt o~ Rerrac~ory, Lhese two ~a~us . hiLs ~lso control Vel)~ricu1ar Dclec~or Shut Down for fixed rate pacing mode o~
orc ration: -. PS5 - TWY @ Fl'R PS6 - PV~ @ FPR pl)R Parameters . . .
O O RWr - 1 0 Th~
] 1 Fi~cd Rate - . :

PS7 PVP @ SPR 203G 233 PVC parameters @ Second Pa1t of O
Refractory Time instead of R-wave parameters.
PS7 - PVP @ SPR SPR Parameters O . ~h'P
,. ' , ' I PVP
PS9 PVC 203H 231 Ena~les a PVP detec~i~n to . O
RECYCLE rccycle the ~acemaker ~IR~
circuit during refractory time ~only h~hen Premature Ventriclllar Parameters are loaded iu the venLri~ular detector) :~ :

. . . ~ .. - .
- ' , ' ' ~: ' . : .
, : . : . ,' $~ 7 1 1 ~ 0 . ~ -.

PSO, and it is ~his bit which permits program control of an externally applied ~eed switch 221. The Reed swit~h i~
coupled t~ one input of an ~XCLUSIVE OR gate and PSO i6.
coupled to the ,other input. I'f PSO is a logic 0, then the Reed Switch 221 acts directly. If PSO is a logic 1 then the Reed Switch 221 is inverted in sense. The output of the EXCLUSIVE OR is a signal designated MAG or the magnet signal. This enables magnet control or simulation under program opera~lon. It also permits the system to disable the MAG signal if the Reed Switch 221 witch fails in the closed position.
;~* .
Bit 'PS4 enables capture verification if it is a logic 1. Hence, if it,is a logic 0 then it disables the capture verification circuitry by disabling the clock signal which is fed to that circuitry. Alternatively, a status control bit could be used to inh,iiblt the lnput signal to or the output signal from t~e circuitry whose function is being disabled, or to hold that circuitry in reset.

Another major function which can be disabled by PS12 which is entitled "ATO ENAsLE". Ps 12 is used to enable the automatic tachycardia operation in one logic state and to disable it in the other, disabling~an output latch through which the tachycardia overdrive output signal i~ coupled.
- -Another mode of operation is fixed rate pacing.' This is implemented by Status Control RAM bit E55 and ~S6.
If both bits are set to a 1 the ventricular detector is disabled by removing clocks from ventricular detector logic ~;
power from the,current sources, and locking the output V DET
138 in a non-active state. This would cause the pacer to ' ~ "' ~: .
-~ revert to fixed rate p,acing. , , ' -~
, , 56 ,~ . '. ' , - : . . :
., . ,-.

' ' ' . , Addi~ional PS 6tatus bits are i~ the Atrial Control R~M 1~8 and are communicated along the Atrial Control Data Bus 199 to t~e various subsystems. An example is PS82 which permits the JAM function to occur. If it is in a logic 0 state, the JAM ~unction is disabled. This would inhibit the operation of any atrial detector that may have been implanted, or at a subseguent date, it would allow the use of the atrial detection circuitry. PSBl is thè
, atrial detector enable/disable status bit which causes the atrial detector to shut down like the ventricular detector with PS5 and PS6 = 1 above. With PS81 ~ 1 and PS 82 = 0, the atrial detector can be "dry run" prior to using it in the P-synchronous mode, for evaluation of its operation over an extended period of time by recording its output in the Event Tally Counters 189 discussed in that section below.
. ~

Shelf Life 5tandby Mode The pacemaker may be put into a mode of minimum consumption of power for extending the shelf life of the battery. In this mode, PS10 holds the VCO in reset through Bus 203K, the output of the Crystal Oscillator is disabled through Bus 203J, alt}lougll the cryatal clock is powered and circuit bias currents I REF 259 are turned off through Bus 203M. ~t will be appreciated that because ;CMOS logi circuitry is uscd, power need not be removed from the power bllses to thc Ci.l Cllitl`y si~llCC CMOS circuitry docs not consllme power withou~ clocking. Further, the memory is non-volatile and information will be preserved as entered at the factory so that the system can be activated simply by the application of an external magnet. The application of a magnet (MAG signal) resets~ the PS10 latch, the output of . ' . ., ' . .
57 , ' ..
.... ... . . . .. ., . . .. ... . ., .. :

~ :~711~0 ., .
which enables ~he operatlon of the crystal.clock and -the VCO. The PS10 latch i~ also xeset by a Power-On reset signal derived from low battery voltage 50 that the .-pacemaker circui~ will not turn itself off in the case where it is programmed to a high current state around the time of battery depletion.. As summarized in Table III, this latch is set by programming PS10 of the Status Control RAM to a one.
.

Overall System O~eration Referring now to the flow chart of FIG. 12, there are three principal paths to be taken by the system from the beginning of. a cardl~c-~ycle~to- the end of the refractory period which occurs at TM2. The beginnin~ of a cycle occurs at the beginning of time period ADl (see the left margin of ~IG. 12) following a Master Reset. These paths are generally designated respectively 1200, 1201 and 1202. Path 1200 is taken if the.Master Reset was generated in response to a stimulating pulse. Path 1201 is taken if a natural R
wave is sensed tthe signal V DET) during the Ventricular Rate Time out period AD4. Path 1202 is taken if a PVC is detected (V DET) during the PVC detection period AD3.
.. .. . .
The modes are~determined by the status of two latches, one (1403) associated with the State Controller 231 of FlG. 2, and the other ~1801) associated :with the Ventricular Filter Parameter Controller 233. The first refexred to as Last Reset Paced Latch 1403, of these.latches is set if the system generates a stimulating output pulse - signal or."paced" beat and, in this case, the controller . . . .
follows the path 1200. The other latch, referred to as PVP
' : , ' . 58 ., ~ . _. , -- .

. ", ,, l l 71 140 - .
latch (1801?, stores a.signal representative of a detected PYC; and in this case, path 1202 of the flow chart i~
followed. If both latches generate the complements of their respective signals, then path 1201 is taken indicating that a Master Reset. has occurred but that it has not been generate~ by generating a paced beat or by detecting a PVC.
It therefore has been genexated by the detection of. a natural'R-wave heartbeat.
' . During the time period AD2 the system irst tests for capture, in Capture ~erification Processing 1200B, if a stimulating pulse had been generated. If capture is verifie.d by detecting a :waveform tllat satisfies the re~uirements for a T-wave detection parameters before the end of AD2 or if a natural R-wave had been detected in the previous cardiac cycle (path-1201), the'system passes to a mode in which it tries to:detect whether the patient is in a noisy environment--Reversion Processing 1200C.~ In this mode or phase of AD2, the noise threshold may be varied according ~ : to any one of the three parameters:for which the ventricular filter 100 is capable of being~set for ~T ~aves, R waves, or PVCs), as select~d by the Ventricular Filter Parameter Controller 23~ ~hich is controlled.by the State Controller~ ' 231 and is programmed by the Status Control RAM.211 along Data Bus 203G. If the programmed noise threshold is exceeded, the syste~; revsr`ts to fixsd rate pacing as controlled by the Ventricular Revcrsion Counter 11~. In the time period AD3, the ~entricular filter is losded with PVC: .
parameters for PvC Processing 1200D; and in the time period AD4, the ventricular filter is~loaded with natural R-wave parameters for R-wave 1200E and P synchronous 1200F'~
Processing. When the escape lnterval has timed out, the system goes through Rate Limit Processing 1200G prior to , ... ... . .
- producing a stimulating output pul~e.
. 59 . ~ ~ . ,., . :
_ _ , ' ~

.

~ 1171~0 ., - , . ' ' .
Before discussing the operation in detaiI it will be helpful to further understand that the term "refractory period" as used herein in reference to the veDtrical refractory period can mean either the periods ADl and AD2 or simply the period AD2, according to the context. The reason for this interchangeability is that the true ventricular refractory period of the heart includes ADl and AD2, but the ventricular filter is held in reset during Lead Compensation (~Dl), so for all pract~cal purposes the detection and filtering circuitry is disabled during this period.

Referring now to System Housekeeping (1200A) in path 1200, after a stimulating pulse is generated, the digital filter feedback gain is multiplied byi27 in block 1214, the reversion counters and detectors are reset in block 1215, the refractory and rate limit timers are started from zero in 1216, and the residual charge on the stimulating electrode 101 is compensated in 1217. After tXe electrode is compensated, the 27 multiplication on the ~eedback is turned off in 1219, the ventricular filter 100 is loaded with T wa~e parameters for Capture Verification Processing (1200B) in block 1220 in an attempt to verify capture of the heart; and this is the primary function performed in this mode, as indicated in block 1221. If no detection is made by the end of the refractory period as indicated in block 1222, a loss of capture event counter (to be described) is incremented in 1223; and in this event, the system enters a programmed procedure for effecting capturè~
As a first step, it increases the width or amplitude (according to the procedure programmed by the physician) of the output pulse in block 1225. If loss o~ capture persists for the pulses of increased power the other parameter may then be increased so that both width and amplitude are in 6~ -.

:

.

--- ` f~ 1 7 1 1 ~; 0 , creased (also in block 1225). This procedur~ may be reset by the physician by the appIication of an external magnet (see block 1226). If a T wave is detected, thereby verifying capture of the heart, the ~ystem resets the loss of capture counter in 1226 and pr~ceeds along ~ath 1245 for the "second part of refractory" for Reversion Processlng 120QC where either R-wave parameters (Path 1246) or PVC
parameters (Path 1247), as defined by the Status Control RAM
211, are loaded into the ventricular detector 100 in an attempt to detect interference noise for the remainder of refractory time to TM2 ~1210). The system enters the PVC
time window ~1205) AD3 af~er TM2 where the ventricular detector .is set for PVC parameters 1272 in an attempt to detect a PVC which will be described shortly.
.
If the Master Reset were generated in response to a natural heartbeat 1201, again depending upon the contents of Status Control Memory 211, the system may load the ventricular fi.lter to detect either a T wave, as indicated in sub-path 1231, an R wave as indicated in sub-path 1232, or a PvC as indicated in sub~path 1233. If any of these waves are detected during the refractory period, the program shifts to a path 1245 which is reerred to as the "second part of refractory". This refers to the fact that a single signal may normally be expected during refractory. This slgnal may be indication of a natural T ~Yave, an R-wave from . a stimulating output, or. it may even be a premature ventricular contraction (a~single PVC is not taken to be harmful). : .

The system will look for a second detection duri~g refractory in the "second parti' of the refractory period, and depending upon a status bit that has been program~ed ~ . . ~ , :
. : 61 . . ~ , ... .

.

-: . :

, , (and whether a PVC was ~reviously detected in 1240, as indi-cated in block 1248, the system may be programmed to detect .
an R wave in sub path 1248, or a PVC in sub-path 1247during "
the second part of refractoryO When either of these signals i5 detected, a reversioI) counter is incremented. If the .
reversion counter exceeds a preset limit, the system will proceeed along either line 1270 or 1270A to enter a Ventricular Reversion Mode, to be discussed and ultimately gener~te a stimulating output pulse in ~block 1299.
.
Assuminq that no signal had been detected during refractory or during the second portion o refractory, the system proceeds normally into the PVC detection period, to be described shortly.

Referring now to path 1202, if a PVC is detected in time period AD3, the reversion counters 118, llBA, and detectors 100, lOOA are reset in 1261, a rate limit timer and the refractory period are started from zero in block 1262; and the ventricular filter is reloaded for detecting PVCs in block 1264. If a PVC is detected-in block 1265, a reversion counter is incremented in block 1266 and the PVC
count is incremented in block 1267. If the reversion limit is exceeded, the system enters a ventricular re~ersion mode as indicated by line 1271 and ultimately generate~ a stimulating output pulse in~block 1299. If a PVC is not detected by the end of the refractory period,-the syste~
.
proceeds to the normal PVC detection period, AD3.
, ~:
At the end of the refractory period, the ventricular filter is set to detect PVCs in block 1272 for !';
PVC Processing 1200. If a PVC couplet ~two or more sequential PVCs) i~ detected in block 1281 at ~he end of .
. - 62 , .. . .. . . , . , . ~ . .. . ... . .. .
,: . , :

o~

: AD3, a block 1282 may record a Pvc couplet event in the - Ev~nt Tally counters 189 described below. Next, the ~VC
.counter is reset in block 1283, and the ventricular filter is set to detect an R wave in block 1284 for tlme period AD4 for R-wave 1200E and P s~nchronous 1200F processing.
.
If a Pvc were detected in block 1273 during time period AD3, a PVC counter is incremented in block 1275 and the system determines whether tachycardia exists in block 1276. If it does not exist, the system enters path 1202 described above. If tachycardia is detected and the system is programmed accordingly, in block 1277, a series of stimulating pulses at a predetermined high rate axe generated ~for example, eight consecutive pulses at 400 millisecond intervals may be used). After the end of this train of pulses, thP sequential PVC counter 240 is reset in block 1279 and in block 1280 a tachycardia may be recorded in the Event Tally Counters 189; and the system proceeds along path 1200 described above.

During the R-wave Processing 1200E, the system enables the JAM function of the Atrial Detector lOOA for detection of a P-wave in 1287 and a pre~setting of the lower dividers 215 and 255 in block 1289 if the. system did not detect atrial reversion at 128B.

If a natural R wave is detected during the Ventricular Rate Time Out Period AD4, as indlcated in block 12B5, the system proceeds along path 1201. I~ no natural heartoeat is detected during period AD4, the system proceeds towards rate time out in 1286..

.
.63 '~

': ':

1 71 ~40 r -- Before discussing Rate Limit Processing 1200F, as i~dicatcd in the lower left portion of the flow chart of FIG. 12, it will be observed that once the PVC mode of operations is en~ered as indicated by the path 1202, the system cannot exit this mode within ADl, AD2, or AD3. In other words, time mark TM3 must be generated so the system enters time period AD4 for detecting a normal heartbeat.
.

It will also be observed in connection with path 1201 that a main consideration in determining whether the ventricular filter will be set to detect T waves, R waves or ~ .
PVCs in time period AD2, will be the noise criterion which a physician will consider safe. In other words, the criteria for establishing an R wave will be met only by a noisier environment than necessary to identify a T wave; and a still ~oisier environment would be required to meet the criteria ~or detection of a PVC. If a patient is in a noisy environment, and the reversion reguirements are met, the system will revert to fixed rate pacing.

The number of ventricular detections V DET during ventricular refractory time (AD2) is counted in the Ven-tricular Reversion Counter 118. The physician determines the noise thresllold by programming which set o parameters T, R or PVC parameters is in the ventricular filter during AD2. If the number of counts during one re~ractory period exceeds a predetelmincd programmable number (1 to 7) then the system will automatically revert to fixed rate pacing for that cardiac cycle. A master reset pulse will re-initialize the system to its original mode and noise/reversion criteria.
. .
.. .

64 . ~ ~

.

,' ' . '.
r . ~

-The nu~oer o~ atrial detections A DET during atrial refractory time ~AD2 plus AD3) ls counted in the Atrial Reversion Counter 118A. PAC parameters are loaded into the Atrial Digital Filter during atrlal refractory time in an attempt to identify Premature Atrial Contractions, and the Atrial Reversion Counter 118A is used to disable (in 12~8) the P sy~chronous JAM in the event o~ atrial fibrillation or flutter~ -.

Ventricular Filter Parameter Control Circuitry ,~
The Filter Parameter Control Circuitry, diagram-matically illustrated in Block 232 of Fig 2, is shown in detail in Fig. 18. Briefly, this circuitry establishes the se~uence of operations descrioed above in connection with the flow diagram of Fig. 12.

Referring then to Fig. 18, there are 3 outputs of the Filter Parameter Control circuitry designated respectively 1835, 1834, and 1837, representative respectively of Premature Ventricular Parameters ~PVP), R-wave Parameters ~RWP), and T-wave Parameters (TWP). If the signal on any o~ these lines is a Logic 1, that signal is communicated to the Ventricular Filter Parameter Address Decoder 208 and the Ventricular Filter Gain Control Address Decoder 207 to load the associated filter parameters on the Ventricular Filter Parameter Data Bus 201 and the Ventricular Filter Gain Control Bus 202 respectively. This might occur, for example, in the flow chart of Fig. 12 ~hen the system enters one of the paths designated 1231, 1232, or - 1233, as described above.

.

' : . ' ' -' - 1 :171~0 .
Thr~ cir~uitry includes a PVC Latch generally designated 1801. The output of this latch generates the signal PVP which, as indicated above, enables the system to transmit or load the PVC parameters into the ventricular filter. The latch can be reset by the signal AD4 which is transmitted on a line designated 1818, ~r by t~e Override signal ORD on line 1820 which externally resets the circuitry for the generation of a pacing pulse.

The other inputs to the Filter Parameter Control circuitry are as follows: V DET ~indicating a ventricular detection) on line 1810; the complement of AD2 (refractory time) on llne 1811; MR (Master Reset) on line 1812; PS7 on 1813; AD3 (PVP time window) on line 1814, LRP (Last Reset Paced) on line 1815; PS5 and PS6 on lines 1816 and 1817; and the complement of ventricular reversion on line 1819.

The PVP latch 1801, in summary, can be set by the signal AD3 on Iine 1814, and this corresponds to the bloc~
1272 in the fIow chart.

.
An AND gate 1855 is responsive to input sig~als PS7 on line 1813, described above, and an internally generated signal SPR (Second Part of Refractory) on line 1~31 for effecting the decision indicated in block 1248 of the flow chart of Fig. 12. A similar AND gate 1859 is also responsive to the following signals: PS6 on line 1817, th~e complement of PS5 1875 (which appears on line 1816), the complement of LRP 1874 (whi`ch appears on 1815), and another internally generated signal which appears on line 1832 which is desisnated FPR (representing the First Part o~
Refractory). The function performed by the AND gate 1859 corresponds to entering path 1~33 as disclosed in connection with the flow chart of Fig. 12.
~6 : ~ . ~ . : . .' ~ :
- ' . , : - . . - ;: , , . . : .

, ' ,', ' '. . ,.'. ' `' ~

;~ -~ 1 7 1 ~4~ -Moving now to the circuitry which causes the ventricular filter to be set with T-wave parameters 1804, afi - indicated by the signal TWP on line 1837, gate 1866 corresponds to entry of the path ~231 on the flow chart; and the path 1232 is entered if neither path 1231 nor 1233 are entered as described above, corresponding to a default decision. Gate 1867 and 1868, in co~bination, effect the mode of operatio~ described in block 1220 and following, in the flow chart of Fig. 12. The default decision mentioned above to place the system in the operation of path 12i2 is ef~ected by the gate 1863.

Reference numeral 1853 identifies a flip-flop which is set by a Master Reset pulse on line 1812 to generate a signal FPR 1832, in combination with refractory time in gate lBS6 representative of the First Part of Refractory; and the first detection thereafter is coupled in on line 1871 to cloek the flip-flop 1853 to its reset state, thereby generating, in combination with gate 1854, a signal SPR 1831 representative of the Second Part of Refractory.
Any additional detections during the Second Part of Refractory generate clock pulses on a line 1830 by means of a qate 18SO to increment the Reversion Counter 118. The outputs of gates 1862 and 1865 are signals coupled to the event counters, described above, to communicate to them reversion events and what parameters the system is currently operating on.
., , ' , . .

As indicated elsewhere, an external signal may be used to place the system in an Override condition if enabled by an associated P5 status control bit. Such an override condition generates a pacing pulse i~nediately. When this signal is effected by coupling a slgnal designated O~D

' ',~'~'' ' ' ~ ' - r ~ 3 ~ ' ~ ~, ' ' , , ' .
..

(Override) 1~20 the PVP Latch 1801 is reset WhiC]I causes the system to exit from any PUC mode it may have been in. This PVP signal is transmitted on output line 1835 as indicated above. ~s indicated, the 0RD signal i5 also used to pre-set the Time Mark Sequence Counter 232 to AD5, R5 indicated in the functional block diagram of Pig.- 2.

' Rate Limit Control Referring to the iogic schematic diagram of Figure 17, the Rate Limit Controller 236 consists of the 'Rate Limit Event Latch and Logic 1702, the ERT Latch 1703, and the Continuous Rate Limit Mode Logic 1704. The Rate Limit Counter 237 is a 3 bit counter generally designated 1701; this is the counter which counts sequential occurrences of TM4 occurring prior to RLE indicating a rate limited condition, or `'Rate Limit Event." This counte~ is reset every time RLE occurs prior to TM4 indicating normal operation. The resetting logic gates are designated 1756/1760, and the clockiny logic gate is designated 1759.' ' An input gate 1753 determines whether a rate limit event occurred (the rate limit event is defined as abo~e, namely, the occurrence of TM4 prior to RLE). This output '.
~eeds a latch 1702 made up of gates 1754 and 175~. The function of gate 1753 is accomplished by inputting'AD4 on line 1714, RLE on line 1730, and comparison pulse Cl on line 1715. I'he comparison pulse Cl is generated by the Digital Comparator 224 when the contents of the divider 225 fed by the Crystal Oscillator equal the data word representative o ~-TM4 which defines the end o~ period AD4. Normal operation (i.e., no rate limit event~ is defined as AD4 on line 1714 , ' 68 ' ~ -.. _ .. ...... - - ~ , _ .
. . . : : .

:
,, : , : : : . , :
. . . . ' '............... ' . :
~, ~ . - .

0 ~, and Cl complement on line 1715 being 1' 5 and RLE 1730 going high to set latch 1702 resulting in a low on line 1773 which steers the incoming AD5 on line 1718 to the counter reset through Gates 1756 and 1760. If a rate limit event occurs, latch 1702, is not set by RLE going high while the other two inputs of gate 1753 are high, thereby steering the incoming AD5 thrsugh Gate 1759 ~'1773 is left high) to clock the counter 1701 and register a rate limit event in the counter.
If, during the next sequential cardiac cycle, a rate limit event is not detected, then the counter is reset. This occurs for any cardiac cycle that a rate limit event is not detected. When the counter 1701 registers a count of 4, it sets an ERT latch 1703. This generates the ERT signal on line 1734. An ERT signal generates the WPW ~wide pulse width) signal and reduces the pulsing rate by 12.5% by changing a counter in the ~pper Divider Z26 fro~ a."divide by eight" circui~ to a "divide by nine" circuit,.a technique known in the art and is illustrated as "12.5% ERT" 1602 in Figure 16.

The 12.5% rate change in response to ERT or loss of capture indicator is to be distinguished from the rate of the VCO which is 10-15% higher than the rate at which it operates when the battery is at a depletion level.. Once the four sequential occurrences in counter 1701 have occurred as defined by the setting of ERT Latch 1703 as just discussed, and the rate of the system Adaptive Clock 1625 is decreased by 12.5%, the next cycle should reset the counter 1701.
However, if it does not, and the counts continue to seven successive counts as defined, it is taken as an indicati~n . that the ~rystal Oscillator has run away, and this causes the system to enter a "fail safe" mode which is essentially . .

:, ' ~ '. . . ..

, : ' :
' , 1~711~0 the same RS Magnet Phase 2 ~MP2), as will be discussed. The signal that causes the system ~o enter this mode is gener-ated by Continuous Rate Limit Mode Logic (1704) gate 1765, inputs of which are either the signal MP2 on line 1713 or the RL>7 on line 1733 and output o~ the gate 1764 is on line ; 1733. The result is that the rate is determined by the RLL
word on the VCO, and the VCO determines the pulse width (1 or 2 milliseconds depending on the PW word being programmed greater than or less than 1 millisecond~.

. ' VCO Pulse Width Generation Referring to the block diagram of Figure 2, there is a line from the Time Mark RAM 210 to the State Controller 231 of ~he VCO circuitry. The line 270 is designated PWS
(Pulse Width Statùs). If the programmed pulse width is less than 1 millisecond, it is sensed by the State Controller 231 along the PWS line; and it generates a~signal on line 267 identified as OUTPU~. In the instance being discussed, the output pulse width when the VCO determines pulse width will be about 1 millisecond. If, on th~ other hand, the programmed pulse width in the Time Mark RAM 210 was 1 millisecond or greater, then the output pulse width in MP2 will be 2 milliseconds (approximately). Referring to the logic schematic Figure 14, this occurs in a flip-flop 1479 in the State Controller 231.
.
If this PWS signal 1427 is in one state, the flip-flop dlvides the incoming 1 KHz clock signal by two on line 1423 ~(1 KHæ VCO). There are -three gates involved designated 1480, 1481 and 1482, the outputs of which are -joined in a gate 1483. If the ~ate 1480 is enablPd, the .. . ..
~ 7~
.

.

.

~ J711~0 ~J
first 1 millisecond pulse width is fed to the gate 1483. I~
the gate 1481 is enabled, t~e second half of the cycle is added. The gate 1481 adds the second hal~ cycle of the complement of the flip-flop 1479 which, as indicated previously, generates an output signal at a freguency of S12 ~z. The third gate, namely gate 1482 couples the crystal pulse width (AD5 on line 1418) to the output gate 1483.
There are two other signals to the gate 1482 which disable the crystal pulse width. These are indicated on lines 1425 and 1424, and they are respectively, Magnet Phase 2 ~MP2), and a signal indicating that more than seven successive rate limit events have been detected (line 1424). In other words, if either of these signals is present the crystal clock is disabled in the gate 1482. The occurrence of either of the signals on line 1425, 1424, generates a VCO
derived output pulse by means of the gate 1477, in conjunction with RLE (which times this output pulse) on line 1426 which causes an enable in the gate 1478 which enables the flip-flop 1479. In the case of gate 1482, the signal ADS not only indicates the ti~ing of a stimulating pulse, but also the width. In the case of the gate lg80 or 1481, the signal RLE on line 1426 indicates when a stimulating pulse should be generated, and the remainder of the circuitry discussed abo~e, defines the width of that pulse.
.
. .

Rate Limit Synchronizer/Jam Enable Control Turning now to the the Rate Limit Synchronlzer, it is identified in the functional block diagram of FIG. 2 as 235 and along the top 1706 of FIG. 17. The output of the VCO
Digital Comparator 214 is fed on a line 256 to a Gate 234, - the other input of which is received from the JAM Controller 7 1 .

... . ~ . .
~ .
.
,. . ' , ~ . : ~ ` , . . .

' ~? ;~ . .
..

169 via 144. The function of ~ate 234 is to disable the Rate Li~nit Synchronizer 235,during a JAM f~nction imple-mentation. A similar Gate 230 is associated with the State Controller 231. The reason for this is that the JAM
function forces a predetermined word into both sides of t`he digital compa~ators 214 and 224 (from the bus through the bus preset lower dividers 21S and 225 respectiuely) a~d an eguality would otherwise result. The output of the gate 234 is the~signal RLC 295 (Rate Limit Compare). Correspondingly the output of the .gate is crystal compare--namely XTAL CMP
277.
,~, The function of t}le rate limit synchronizer is to -synchronize the VC0 derived rate limit enable sisnal's transition to its high or enabling state with the Crystal Oscillator derived timing to enable the generation of crystal oscillator based stimulating,pulses.

Turning now to the detailed logic circuit of FIG. 17, the output of the gate 234 of FIG. 2 is indicated on line 1711--namely, the signal RLC which, is derived from the VCO oscillator. The signal is used to set a latch 1705, the output of which generates a'signal RLE ~Rate Limit, Enable) 1730 which 'is not yet synchronous with the Crystal Oscillator. The Master Reset signal generates a Rate Limit Reset signal on line 1710 to reset the latch 1705. When the non-synchronous Rate Limit Enable signal goes high, the D
input of an edge-txiggered D type flip-flop 1752 goes high, thereby enabling a 2 ~ crystal clock signal on line 1712 to clock the flip-flop 1752, thereby synchronizing the output signal on line 1731 to the incoming clock signal on line 1712. The signal on line 1731 (which may be called RLE SYN or Synchronous Rate Limit Enable~ synchro~i~es t~e ~' 72 ' "
:
..... , . .... . _ . ~

:

- ~i71~0 .
functions performed in the Rate Limit CircUit with the crystal clock signal. It is fed in line 250 to the ~ime Mark Seyuence Counter 232 for forcing AD5 when operating in the Magnet Phase One mode to be described bslow.

Rate Limit Processinq .
Returning now to the flow chart of FIG. 12 and relating the VCO pulse width circuitry to the rate limit control discussed above, if the time mark TM4 generated by the Crystal Oscillator occurs sooner than the signal RLE ~o which is generated by the time mark word RLL in the VCO
Control RAM 209 for the. VCO Digital Comparator. 214, a Rate Limit Event (or simply R/L Event) is detected by comparing in blocks 1286, 1291, and counted in block 1293. If RLE
occurs first in block 1291, a ~ate Limit Event count is -~
reset in block 1292 and a stimulating pulse is generated in 1299, followed by a ~Iaster Reset.
, Assuming that AD4 occurred before RLE, then R/L
events are counted in block lZ93 and tested in block 1294.
For the first three sllch events ~occurring in sequence), the Rate Limit Evcnt counter is incremented in 1293 and the system waits until the RLE signal is generated in 1295 and then gencrates an output pulse in 1299. The delay is shown diagrammatically by the loop 1295A.
:
If four or more R/L Events .have been detected in decision block 1294, then the system proceeds to decision . block 1296. If four or more but less than seven sequenti~
R/L Events are detected, it is tàken as an lndication that the battery has depleted and should be replaced. In this ~ 73 _.

l 1 71 ~0 case, the rate is d~creased and the pulse width is increased, as indicated in block 1297, and an ERT
signal is generated. If, on the other hand, seYen or more events are detected in block 1296, it i~ taken as an indication that the Cryqtal Oscillator circuit has increased dramatically in frequency. Then the system reYerts to a fixed pacing in block 1298 and the cardiac cycle time base as well as the pulse width are determined by the VCO. The system cannot exit from this mode except by application of an external magnet~ If four or more R/L Events are counted, the system generates a signal referred to as ERT (Elective Replacement Time) in block 1297 to indicate that at the election of a physician, the pacer should be replaced. The ERT signal switches the system to an alternate pulse width word (WPW) in the Time Mark RAM 210 for a predetermined (programmable) wider . . .
s~imulating pulse width and the system decreases the adaptiYe crystal clock rate by twelve and one-half per cen~ in block 129i. This is accomplished by substituting a divide-by-nine circuit in place of a divide-by-eight circuit in the crystal oscillator upper divider 226 (by means of a signal transmitted along the ~RT line 297).
This action (-12.5% rate) should eliminate the asynchronous inequalities between the time periods - ~ .
of the ~CO an~d the crystal oscillator. lf additional coincidenoes are detected, it is taken as an indication that the frequency of the crystal oscillator has increased dramatically, and the system i y .
--:
`

l ~ 71 ~0 . ~. ... ~
swi tches over to use the back-up os cillator, namely the VCO 217) as a primary time base re~erence. If the programmed pulse width is greater than 1 millisecond (PWS), a double width VCO output pulse is derived. It is from the time mark work Rate Limit ~ow ( RLL ) , : :

1 ~ 7 ~

. .
.
that the signal Rate Limit Enable ~RLE) 744 of FIG. 7 is generated. However, during ~ check by a physician when he applies an external magnet, the Rate Limit High (RLH~ w~rd generates the Rate Limit Enable (RLE) signal for generation of stimulation pulse rate for ~hich the VCO is used as the time base. If the timing were derived from the RLL time mark for generating a stimulating pulse, the system would not have increased the rate to the level desired by a physician to stimulate the heart during testing. In other words, the physician wants to pace at a higher than normal rate (for example, at 100 beats per minute) so that he can test whether the system is actually capturing the heart without competing with it as in fixed rate modes of pacing.
When the magnet is applied, the Rate Limit High (RLH) word is used to define the higher fixed rate. In summary, when the magnet is applied, the Crystal Oscillator is not used to yenerate the time base so that time mark TM4 has no meaning.
Secondly, the time mark word RLL associated with the VCo is not used, and a shorter time period identiied by RLH is substituted, and this is used to determine the time o occurrence of the stimulating pulse.

.
Even though the VCO defines the basic cardiac cycle timing with RLH when the external magnet is applied, the width of the stimulating pulse is still determined by the Crystal Oscillator. This maintains the same pulse characteristics of a normal stimulating pulse as though the Crystal Oscillator wcre operating. In summary, all of the physical parameters that define an actual stimulating pulse are maintained, and it is therefore a~more true test.
,'' ' ' ' ~ ' ' ', ' `";. ` ~
.
~ 75 ', ' . . : . , ., ~:
-.... .. . : ~ ' ?
,,,, ~ . . . . . _ .
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1 1 711~0 . -. ~

. .

Since the time mark RLH is merely an address in ~7cO Control RAM 209 and used during magnet application, any other rate can be substituted into this location. This permits of a rate that may be slightly higher than tachy-cardia for any given patient. ~his would be useful in trying to break up tachycardia. The system is designed so that it will not go more than thirty-two outputs using the Rate Limit High word for programmed RLR rates over 120 .
This prevents a failure mode in which the reed switch actuated by the magnet would stick. To continue at the higher rate could possibly result in harm to the patient.
This count of thirty-two is determined by ~284) magnet phase 1 (see the signal MPl to be described in connection with Magnet Phases and Figure 13) which feeds into the VC0 control address decoder 205 above the VC0 Control RAM 209.
At the end of the thirty-two outputs, magnet phase 2 is entered. This function of limiting the number of output pulses to a successive count of thirty-two is used when employing a high rate for tachycardia (in other words, the normal RLH word has been substituted by a "tachycardia" rate word). The limit of 32 outputs on RLH may also be enabled for RLH rates below 120 PPM by programming PS2. In summary, in normal operation, as long as the magnet i5 on the system is set to operate at the 100 beat per minute rate repre-sented by the normal RL~ word. If a "tachycardia" word i~s substituted in RLH, then the function of limiting~outputs to thirty-two is implemented.
'' , ' ' :
- Maqnet Phases - ~eferring now to FIG. 13 which is a timing diagram~
of the temporary modes implemented by th~ application o an .:

-. :. ' ' ' . , , . : ~^ ' ' : . . : :: . , , ~ 3711~0 ~ . .

., . ~ .
external magnet, an overall brief description will first be given of the definltions of the magnet phases, the manner in which the different phases are exited and entered, and how they affect the system's operation. The specific circuitry for eff~cting these functions and operations will then be described. Turning then to FIG. 13, the signal on line 13Ll represents the application of an external magnet at a time TO (1392) followed by the removal of the magnet at time T1 (1393), It is assu~ed that the magnet is continuously applied for that t1me and that the Reed switch which is shown in functional block 221 in FIG. 1 is actuated (closed) by the application of the magnet.

The state of the Reed Switch 221 is sensed bj a Reed switch Controller 220 which also senses the status of Physician Status Bit PS0 on Bus 203B and performs ~n EXCLUSIVE OR logic unction and generates a signal designated MAG (262) which is synchronized with the Master Reset Signal. It is this EXCLUSIVE OR logic function which inverts the sense of the Reed switch. This is helpful in tXe event the Reed Switch becomes stuck in the open or closed position since the physician can program its inversion to avoid possible danger or entering undesired modes. The sense of the Reed Switch can be logically inverted relative , to the Atrial Detector independently of the Ventricular Detector. PS40 controls the inversion ~or the Atrial Detector, and PS0 controls this inversion function for the Ventricle Detector. The signal MAG is representative of the state of the magnet ~whether the reed switch fanction is logically inverted or not), and it is synchronized with Master Reset to derive a signal referred to as synchronou~ ' (or SYNC3 MAG which is an input to the Temporary Mode Counter 239 to be described presently in ~connection with FIG. ~2. ~ . , . :~
77 "

.
,,: ~ .

~ 1 7~L14~ . ~
Returning then .to FIG 13, when the m~gnet is applied, the system enters Magnet Phase 1 (MP1) 1354, as - indicated on line 13L2. Briefly, Magnet Phase l is defined by the following parameters: Rate Limit High RLH is used to define the rate of generation of pacing pulses (it will be recalled that RLH can be programmed): secondly, the VCO or backup oscillator is used to provide the basic cardiac cycle time base; and thirdj the primary or Crystal Oscillator is used to define the width of the s~imulating pulse~ The system operation during magnet phase l and 2 are also defined by the status of PSl. That is to say, if PSl had been programmed to a 1, the system operates in a fixed rate mode for the duration oE MAG. If, on the other hand, the PSl had been programmed to a O, the system continues to operate in a demand mode during the magnet application (MAG).

If PS2 is a logic O, then as indicated by solid . line on line 13L2 of FIG. 13, Magnet Phase 1 (1357) continues indefinitely until the external magnet is removed (1352~. Normally, during the operation of Magnet Phase 1, the Rate Limit High ~R~H) word is set such that.the pacing rate is at approximately 100 beats per minute. This enables the physician to determine whether the stimulating pulse as defined by the primary (crystal) oscillator in its normal operating condition is capturing the heart. It also permits the physician to obtain a quantative measurement o~
the status of the battery since the rate is determined by the backup oscillator which, it will be recalled, has a peFiod which is a funct1on of the battery telminal vvltage.

If at the time of the application of the external .
magnet, P$2.had been programmed to a 1, or if during MPl the ..
^ ~ i8.
- ', . . .

.-... .. , : . , . . -. . ", . ~ , ... l~71.1.~0... - ..

.
rate had been programmed to a rate higher than 120 beats per minute ~in which case PS2 is internally set to a 1), then a circuit referred to as the Temporary Mode counter 239 limits the operation in the current status mode to a predetermined nun~er (such as 32) complete pacing cycles. This is deter-mined by counting 32 ~aster Reset (MR) pulses in ~he Temporary Mode Counter 239. Magnet Phase 2 (MP2) is considered an inherently safe mode because it derives both pulse width and rate from the backup oscillator. For this reason, Magnet Phase 2 can be entered in other ways. An example of Magnet Phase 2 as an lnherently safe mode, it will be recalled, was described in connection with the ~low diagram of FIG. 12, and particularly in the decision block 1296 in which it was descrlbed that if seven consecutive Rate Limit Events were detected, then block 1298 was implemented. In this block, which is MP2, the system operated in a fixed xate with the rate and pulse width determined by the Voltage Controlled Oscillator.
, If the rate had been programmqd using RLH, to a rate higher than 120 beats per minute as indicated above, then the Temporary Mode Counter limits the system to 32 cycles of operation 1359 as diagramatically illustrated on line 13L3, and thereafter the system enters Magnet Phase 2 - as just described. If nothing else happens, the system stays in MP2 as programmed until the magnet is removed as indicated at Tl.

secause battery drain may have been excessive durinq an earlier magnet phase (~or examplej the rate may have been programmed to a`high rate for testing purposes or for breaking a tachycardial chain), it is desirable to implement a battery voltage recovery mode; and this is de-.
-79 - , , .. . ..

' ' ' ~' '' ' ~ ~ ' l 71 1~0 - -. .
.. . ..
fined as Magnet Phase 3, as indicated on line 13L5.
Briefly, Magnet ~hase 3 (137i) is entered when the ~agnet is removed at time Tl; and it uses the Temporaxy Mode counter 239 to hold a reset 1381 (13L8) on the Rate Limit Counter 237 (that is, the counter which counts rate limit events, as defined above). The Rate Limit Enable (RLE) signal described above always acts on an individual cycle basis as a rate limit below which period a stimulating pulse cannot be generated, but because the battery voltage may have been depleted, rate limit events as counted in block 1293 of the flow diagram of FIG. 12 are ignored during this battery recovery mode.

It may also be desirable to generate an electrogram, as will be described below and this is implemented by programming PS48 to a 1 and PS49 to a 0.
During this phase, the outputs 123,123A of the Delta Modulators 104 and 104A are coupled to an Output Enocder circuit 172 (FIG. 1) which transmits the signal through a Coil Controller 171 to a Coil diagramatically illustrated at 170 from which an external electromagnetic signal may be detected. The physician has the option to disable either the atrial filter electrogram (if he wishes to provide an electrogram only of the ventricle signal) or the ventricle filter electrogram (if he wishes to record the electrogram of the atrium only).
. . ' ' ~.
Continuing on with the magnet phases, when the external magnet is removed at Tl, the Temporary Mode Counter 239 is used to continue the operation of the electrogram output 1377 for an additional 32 Master Resets `;
as to 1376 indicated in ~ine ~3L7. This enables the phy-.. ..

-, . . --. . . ~ . , _ .
, 1 17~1~0 , .

sician to record an electrogram for the ~ucceeding 3Z
cardiac cycles in a normal mode of operation -- that isj as the pacer system operates normally. ~`

lt will be observed, however, that during the generation of an electrogram, battery current drain is increased, and for that reason, the Temporary Mode Counter is used for another 32 Master Resets 1374 (13L6~ MP4 to disable the counter which accumulates detections of Rate Limit Events, 237 as described above; and this is diagram-matically illustrated 1382 ln llne 13L8. In su~nary, during the generation of an electrogram, following the removal o~
the magnet, 32 additional cardiac cycles during MP3 are transmitted cxt~rnally as an elec~rogram; and a recovery period MP4 is thereafter implemented to permit the battery terminal voltage to recover.

Turning now to line 13L9, the physician, in an attempt to define the limits of capture verification, may have prograrnmed the pulse width to be very narrow. If he has done so and progra~ned the pulse width to less than 0.25 msec, the system, upon the application of the external magnet as indicated in line 13L9, enables the apparatus to operate at this programmed setting but upon the termination of the first 3~-such cycles (as determined by the Temporary Mode Counter again), the system adds 0.5 msec to the pulse width at the end of the temporary mode. ~his mode can be texminated at any time by romoval of the magnet and it may .
be re-initiated, after removal of the magnet or at least one Master Reset Cycle, by subsequently re-applying the magnet.

.
~- , ', ', ', -,' . ' :' ... .. . _ , .

J 71 1 ~ O
~ llis temporaly rnode 1385 on line 13L9 also defincs a mode of system operatibn useful for "manually" breaking up tachycardia during the application of a magnet by a physician, and aid, or the patient. If an effective high paciny rate for a patient is determined it may be programmed into RLH of the VCO Control RA~l 209, where it is used to define a high or overdriving rate. Application of the magnet ~ill output this rate (RLH) for a miximum of 32 beats as limited by the temporary mode in line 13L9.

Turning now to line 13L10, if the physician had programmed PS12 so that the system would be enabled to enter the Automatic Tachycardia Overdrive mode ~ATO), then the Temporary Mode Counter 239 generates an output signal 1389 which lasts for a count 'of eight Master Reset Pulses.
During this time 1389 the pacemaker' outputs a high rate burst of 8 pulses'which may be egually distributed over one or two cardiac cycles or just overdrive at a higher rate.
', ., '.' . ' . . " , , , ' Ternporary Mode Counter The Temporary Mode Counter 239, as described above counts 32 Master Resets. Referring to FIG. 20, the ~emporary l~ode Co~nter includes a seven bit counter generally d~signated 2001. It is reset by the incoming signal SYNC t~C on line 2011, and it is clocked by ~aster Resets on line 2010~ The signal SYNC ~G is ~e signal ~G
262 generated by the Reed Switch Controller 220 of FIG. 2 which is synchronized with a Master Reset signal. One shots 2004 and 2005 store initializin~ signals indicative of which magnet phase it is desired to have the system operate in.
Flip-flop 2049 is set by the leading edge of ~IAG and in~edi-j.
:, l ~71140 ately reset by the counter running signal R32 TMG 12020) toallow the first 32 MR pulses commencing with the applicatio~
of a magnet ~see line 13L3 of FIG. 13). The signal MPl i~
generated on line 2~23. At the count of 32 MR's, the R32 timing signal is disabled on line 2020 and this signal is fed through gates 2050 and 2052 to generate the signal MP2 and terminate signal MP1. Flip-flop 2046 is actuated on the trailing edge of SYNC MAG and i,s used to implement Magnet Phase 3 (see line 13L5 of FIG ~3. This phase is used, it will be recalled, to reset the Rate Llmit Counter 237, and it essentially is a signal NP3 occurring when the signal SYNC MAG is in its complementary or off state.
.
It should be observed that line 2021 carries a signal to enable the output of the delta modulators to be coupled to the Output Encoder 172 for the transmission of an external electrogram. There is a latch generslly designated 2003 which is responsive to a count of eight in the counter 2001 for generating the eight high rate pulses used in the Automatic. Tachycardia Override Mode discussed in the connection with line 13L10 of FIG. 13.
.
: ~ ' . . ,' , .
:
Forced Back-up Mode ~ F

~ There are situations in which it is desirable to. .:
'- orce system operation into~ a predetermined mode with the foreh.and knowledge tllat that n)ode is intrinsically safe. By~
intrinsically safe,~it is meant that the energy contained in the stimlllating pulse is at least normal or:above and that.
::
. the rate of the pacing cycle ~s iD a range:which is known to ~
be safe for a majority of patients, including particularly . .: ~ :
patients known to have~cardiac disease.
:-: . 83 : . : .. . . . . . .
: ~ : -; ~ , . ~ :

~' ~ ~ ' .: ' ' : : . .
:: . . :, . . :

i 1711~

One of the features of this aspect of the invention i_ that it can be implemented during the time an external progran~er is being used to program the implanted pacer circùitry. During this time, the physician may notice something in the patient that would cause him to want to terminate programming, or he may ~ind it necessary to seek additional information to complete his programming, or he may feel he has made a mistake and wants time to evaluate what has been done without placing the ~patient in a poten~ially dangerous condition.
, - To engage this mode, in any such case, the ~RJ~
physician simply applies an external magnet which, as described above, generates a signal defined~as MAG, which is a signal representative of *he fact that the Reed switch has been actuated by the application of an external magnet.

To implement this mode of operation, one of the status control bits in the Sta~us Control RAM 211, nam01y PS
99 will have been programmed to a "1". If the MAG signal is - generated, it is used to set a latch which generates a i signal designated as EXIT.
. :

The EXIT signal forces the system to operate in this back-up mode by effecting the following functions~
it forces the system to operate in Maget Phase 2, as described above; (2) it disables Magnet Phase 1 which might have been programmcd to cause the system to operate at a higher cardiac cycle rate; (3) it defines a minimum cardiac rate as 60 beats per minute on the Rate Limit Low (RLL) word which also has a maximum of 120 PPM; and (4) it doubles the ~ ~ ;battery voltage in the case where it has been programed to ~ ~
.
one times the battery voltage for the stimulating pulse.
: . . .

_ .

. . : . ~ ~

f~ ~ 1 171~0 .
Auto~ati _ hycardia Overdrive Hardware .
Re~erring to FIG. 21, and to a gate designated 2155, which has th~ee inputs, one o~ which is on a line 2114 indicating that a ventricular detection has occurred and the gate is enabled on line 2113 any time that the PVC
parameters (the signal being designated PVP for Premature Ventricular Parameters) are loaded into the ventricular filter~ In other words, the pulses coming out of the gate 2155 are representative o~ PVC detecîion; and they are $ed to a 5-~it counter generally designated 2101. This relates . , to the PVC Processing 1200D and loop generally designated 1202 in the flow diagram of FIG. 12. The counter 2101 is enabled only during the time period when Premature Ventricular Parameters (PVP) are loaded in thç ventricular detector. If the circuit passes through AD3 into AD4 it i5 taken as the end of any seguence of premàture ventricular contractions to reset the PVC Counter 1283 in the flow chart of FIG. 12; and this is implemented by resetting with the signal AD4 on the line 2111. This signal is coupled through the gate 2157. Two or more counts registered in the counter .~ 2101 sets a latch generally designated 2102 to generate a signal representative of the occurrence of a PVC Couplet (defined as two or more sequential PVCs), and this signal is generated .on line 21-30. The latch is reset, it will be observed by the signal AD4 :on line 2111. The PVC Count signal is fed via line 2130 through an Event Counter Signal Conditioner 193, through a Counter Selector 191 or 192, to the Event Tall~ Counters 189.
, . Still re~erring to the drawing of FIG. 21, i, selection circuitry generally designated 2103 is used to select a predetermined number of counts, responsiv~ to the .85 ' ' ' . .

` ~

- ~ 1711~ -.
contents of the collnter ~lol for generating a signal whi~h identifies a condition of tachycardia, and this signal is generated on line 2131 to commence the mode ATO (the signal being designated ATO ST for "ATO start"). ATO, it will be recalled, stands for Automatic Tachycardia Overdrive.
Referring now to the Table III -- Physician Status CoDtrol sitS, the control PS 20 (2110) and Ps 21 ~2118~ are used to set the enabling count in the count selection circuitry 2103. This enables a physician to define a tachycardia condition as 4, 12, 20, or 28 successively occurring PVCs in PVP time period. The output of the count selection cir-cuitry 2103 is fed along the line 2131 = 2013 in FIG. 20 and is used to enable the latch 2003 in the Temporary Mode Counter 239 described above with the the magnet phases. In connection with ATO, the first eight counts o~ counter 2001 may used to generate MPl (Magnet Phase I) which runs on the programmed time period RLH for determining cardiac cycle time. This is enabled autvmatically --irrespective of whether an actual magnet is being applied, if enabled by PS12, which is fed into the circuitry on line 2012 to the latch 2003.

.
In summary, if PS12 is a logic 1, then the ATO
Mode i5 ena~led. The Eunction of this circuitry can be disabled if desired; and because CMOS circuitry is used, the major subsections of the system may be disabled selectively withollt increasing power consumRtion by removing power from the circuits. After the ATO mode has been implemented, ~
signal on lead 2117 (Rate Limit Reset signal) disables gate 2157 to prevent resetting the counter 2101. -This has the effect that the counter cannot be used to count PVC events for a period of time, the period of time being defined by a 86 , , ,. - '- , ,, ' ' :

~ i711a~0 -- count of 32 from the Temporary Mode Counter 239 so that ~ ; -second ATO function cannot be implemented during thi~ ' period. This hold-off time period is e~ual to the second ..
1364 plus third sequence 1365, if used, on line 13L3 of t~.te temporary mode timing diagram of FIG. 13.
.

.
capture Veri.fication Control Loqic ~rhe overall function of the capture verification circuitry, as described above, is to identify a T-wave after a paced output. This can be referenced to the path 1200 in the flow diagram of FIG. 12, and specifically, to the Capture Verification Processing 1200B within the First P~rt of Refractory prior to path 1245. ~The block 1220 indicates that the ventricular filter is set to detect T-waves.
': ' Referring to FIG. 22, the circuitry is enabled by PS4 (see Table III). This signal PS4 is fed on line 2212 to a gate 2253. Every time a stimulating o.utput is generated (AD5) a signal LRP (Last Reset Paced) appears on line 2213 ~; to allow the signal being representative of the First Portion of Refractory 2211 to clock the three bit loss of capture coun~er 2201 once. The counter 2201 is incremented each time a First Part of Refractory (FPR) occurs after a stimulatin~ output when the capture verification circuitry is enabled. The counter is reset if a T-wave is detected during this FPR pexiod, which detection defines the beginning of the Second~Part of Refractory.
.
To review this circuitry, first the circuitry is . - ~;
enabled on line 2212, next,~on line 2213 there is a signal ., , . . ~ ~
87. . .
~; ' ! - , ' ''~ , : ' .;' . ' .

. . ..

1 ~ 7 ~ 0 - :

LRP (Last ~ese~ Pa~ed) indicating that a stimulating pUl has been generated by the ~ystem. Next, a signal on line 2211 represents that the First Part of ~efractory ~the signal being designated FPR~ has been entered. This signal (2211 = 1832 in FIG. 1~) is gene~ated in the Ventricular Filter Parameter Controller 233. The signal line is not shown on the block diagram of FIG. 2 for brevity.
.
If the counter 2201 reaches a count of 4, a latch 2202 is set. This is the CV 2 4 latch (the output signal of which i5 represen~ative of the fact that capture has not been verified for four successive~ cardiac cycles of paced beats). This is the first stage of loss of capture.

Referring to Table III, a physician has control by means of PS18 and PSl9 over the selection of one of two modes of recourse in the event of failure to verify capture.
These are designated CVA-3XV (voltage magnitude increase), and CVB-WPW ~pulse width increase or use of WPW word for pulse width). The resulting operation is indicated in Table III under PS18 and PSl9 depending upon the status of the two bits. The circuitry which implements the function of counting to 11 is generally designated 2205 in FIG. 22, and this causes a reset of the counter 2201 after the first ?
count of four, permitting it to count an additional 7 for a total of 11. To read Table III, for example, i~ the status bits PSl~ and ~Slg are 0, 0, then at a count of 4, the pulse width of the stimulating signal is increased, and at a count of 11, nothing else happens. If the status bits are 0 and 1 respectively, then the pulse width is increased at a count of 4 and the voltage is increased ~battery voltage tripled if previously set to double or doubled if previously set to single) at a count of 11. The status bits PS18 and PSl9 ar~

- : . . .. :

.
. : . , , . , . . ' ~: :

,- l ~'711~0 -~
coupled in ~espective]y on the ]ines 2217 and 2210; ,and the count c,f 11 line is designatod 2270. These signals are couplcd into two selection circuits gener~11y dcsignated 2203 and 2204, the outputs for W}liC21 are the signals WPW
2231 to increase pulse width and the signal 3XV 2232 to increase the output amplitude.

Wide Pulse Width Wide Pulse Width is a word that is programmed and stored in the Time Mark RP~I 210. This word is used by the system in place o the normal pulse width word whenver it is desired to generate a pulse width wider than the normal programmed pulse width. This may occur when an ERT signal is generated, or it may also be used in the event of loss of capture. It provides a safety margin wliich may be pro-grammed Into the system.

.

Output Volta~e_ ontrol , The present system provides circuitry for both increasing and decreasing the OUtpllt voltage from a nominal voltage. It may be desirable to decrease the output voltage in cases where the patient may experience muscle twitch under a normal stimulating current, and it may be desirable to incLease output voltage where a patient has developed higher pacing thresholds such as from increased scar tissue surrounding the stimulating electrode, commonly referred to as "exit block". - ~- -.

. .
,, , - , - . . l J 7 ~

To accomplish this, either the Status Control RAM
211 conmllnicates along a Ventricular Control Bus 203C with a Voltage Multiplier circuit 222, or the Capture Verification '`
Control circuit 228 communicates directly with the Voltage Multiplier circut 222 along line 26;. The Voltage Multiplier circuit 222 controls the state of its multiplier capacitor switohes to selectively switch in or out one or more stages of voltage multiplication and apply the multiplied voltage to the pacemaker Stimulating Output Switch 223 along line 264. Briefly, this Voltage Multiplier circuit contains two small capacitors. During one-half cycle, the battery is used to charge the small capacitors in parallel so that they are charged to the full termina~
voltage of tlle ba~tery. During the next half cycle, the battery is connected in series with none, one, or both of the small capacitors to a large holding capacitor. Thus, there is the possibili~y, under program control, of either having the battery voltage alone determine the output voltage (1 x V), the battery voltage plus one capacitor ~2 x V), or the battery voltage plus the voltage across both capacitors in series (3 x V). Finer voltage control may be accomplished by stopping the voltage multipiier clock on line 263 upon reaching the desired voltage. The number of clocks reguired to reach this desired output voltaye is an indication of output current or the load impedance. ~he Voltage Multiplier Control Lo~ic is shown in FIG. 23 Event TD1IV Counters, Re~erring to FIG. l, the system includes two i~;
twenty-bit Event Tally Counters diagrammatically illustrated at 189. Each of thcse counters provides a counting capacity - .: ! ' !
7i' 90 ' ; '~

.

~ 1711~0 of over one million events. They may be connected in serieS
(for example, if it is desired to count pacing puls~s~
there~y yielding a capacity of one trillion for counting over a time period far in excess of a human lifetime. U~ing only a single counter, with a capacity to count to one million, it may count continuous pacing for approximately ten days.

.
When the Event Tally Counters are not being used in series, one counter may accumulate sensed beats and the . other counter may accumulate paced (stimulated) outputs. In this mode, the event counter system locks up both counters when either one of the counters reaches an over10w condition, so that a ratio is determined between paced events and sensed events according to the contents of the two counters. By lockillg up both of the counters when one of the counters reaches a maximum, the physician need not be concerned with whether one or both of the counters has gone through a cycle thereby glving a false indlcation.

Either of these counters may be designated, under program control, to be used to count one of sixteen different event occurrences as indicated by the Primary ~vent Counter Selector 191 and Secondary Event Counter Selector 192 (FIG. 1). As mentioned, the system may be programmed, for example~ to count pacing pulse outputs ~stimulating outputs~ on one counter and sensed Master Resets (that is, signals gcncrated in response. to the detection of a natural heartbeat~ on the other counter.
This will detelmine tl-e percelltage of reqllired stimulating pulses ovc-r the period of a week, and this information migh~
be used to extrapolate the life of the pacer or to make adjustmellts in the various thresholds, according to the ' ' 9 1 ., . , ' , ~ ~ , ' . "

: ' ` . ' ,: ` , ' . . ~, . . . ~.

,. ~ 1711~0 ~ -discretion and judgment of a p~ysician. Some other event~
that one might want to detect and count are: Loss o~
Capture occurrences, P wave detections, P wave detections during P wave refractory, noise detection& during ventricl~
refractory, pacemaker reversions for ventricle or atrium, Premature Atrial Contractions ~PACs), Premature Ventricular Contractions tPVCs~, or PVC couplets.

These counters may be used to "dry run" various circuit functions so they may be adjusted to the patient's individual needs, for example: P-synchronous function, capture verification, or automatic tachycardia overdrive.
The counters may also be used for diagnostic purposes such as xecording the ~ccurrences of atrial or ventricular reverslon.

Reference Data RAM
':' ' ' ' , A Reference Data RAM 190 may be used as a sta~us data holding RAM with a limited number of bits of memory available to the user. Preferably, it will contain the pacer model number and any revision letter, serial number, the week the pacer was implanted or the week of manufacture and the implanting (or tendingj physicians names and phone number. A large portion of the RAM's capacity will be .
undesignated and available to the physician to store data, such as initial chronic parameters ~for example, rate, intrinsic rate, pacing threshold, R wave amplitude and .
slope, T wave amplitude and slope, previous percentage pacing over one week, presence of muscle twitch ~t high amplitude, previous percent of PVCs and couplets, circuit current drain, initial magnet rate, etc.). From this initial data, progressive trends may be observed.
g2 ' ., . . : :, ~ J 71 ~
.
Softwal~ Jm~]ementnt.ion of, the Syrtem , ~ The pacemaker system may be operated in a mode where both Delta Modulator Signals 123, 123A are transmitted out of the body and picked up by an external computer. The external computer processes these signals on a software equivalent of the pacemaker system with some additional software for optimizing a function in response to the patient. A few examples would be filter paramater tuning, tachycardia operations, determination of the strength duration curve of the output pulse, or pacemaker circuit diagnostics. In addition to pacemaker programming, the output of the computer to the pacemaker during this inter-action with the patient would be the Overide (ORD) 140 signal whicll causes the pacemaker to output a stimulating pulse immediately a~ter it is detected and follow it by a Master Reset. This computer model of the pacemaker could easily be extendcd to an alternate embodiment of this system where the pacemaker circuit is an implantable microcomputer and this system model is a program in it. In this micro-computer configuration the circuit could be.used for other biological control units such as a brain pacer by simply using different software in the system to time it dif~erently and detec~ different signals.

. . . .

.' ' ' ' ~ .
- ' " ' :
' !' :

; 93 '' ' ' - ,' ', ~ ..- , ' ' ' ' ' ~ , . .

Claims (97)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. Cardiac pacer apparatus comprising: electrode means including at least a first electrode adapted to stimulate the heart; control means including timing means which defines a sample time window; signal detector means including sensing means for sensing cardiac signals on said electrode means, filter means including a filter circuit receiving the signal sensed by said sensing means for quantizing said sensed signal and continuously generating digital words representative of the slope of said sensed signal over said sample time window, parameter memory means for storing signals representative of predetermined selection criteria for defining at least one component of a cardiac cycle signal; selection circuit means including a selection circuit responsive to the quantized output signals of said filter means and said stored selection criteria signals for generating a detection signal if said digital slope words meet said predetermined selection criteria; and generator means for generating a stimulating signal and coupling the same to said electrode means if said selection circuit means fails to generate said detection signal within a predetermined time from a previous detection signal or a previous stimulating signal.

2. The apparatus of claim 1 wherein said timing means includes timing circuit means for generating timing signals synchronized with a predetermined portion of a cardiac cycle, said generator means being responsive to said timing signals for generating said stimulating signal.

3. The apparatus of claim 2 wherein said timing circuit means generates a refractory signal representative of ventricular refractory period in a cardiac cycle, said selection circuit being responsive to said refractory signal and said selection criteria signals representative of a T wave for generating a capture verification detection signal during a refractory period following a stimulating signal if a T wave is detected in such refractory period.

4. The apparatus of claim 3 wherein said generator means includes means responsive to said selection circuit means for increasing the energy of a subsequent stimulating signal if said selection circuit means does not detect a T wave during said refractory period.

5. The apparatus of claim 4 wherein said timing circuit means further generates a rate time out signal in each cardiac cycle subsequent to said refractory period and wherein said parameter signal storage means stores a plurality of data words representative of different selection criteria; and said control means including controller circuit means responsive to said timing means for coupling one selection criteria data word to said selection circuit means during said refractory period for identifying a T wave and for coupling a second selection criteria data word to said selection circuit means during said rate time out period for identifying an R wave in said cardiac signal.

6. The apparatus of claim 5 wherein said filter means comprises a second filter circuit and said selection means comprises a second selection circuit, said second filter means receiving said signal sensed by said sensing means for quantizing said sensed signal and continuously generating digital words representative of the slope of said sensed signal over a sample time window; and said second selection circuit means responding to the quantized output signals of said second filter means for detecting an atrial contraction signal during said rate time out period, said controller circuit means being responsive to said second selection circuit means for establishing a predetermined P-R time out period in response to the detection of an atrial contraction signal in said rate time out period irrespective of the time remaining in said rate time out period prior to said detection of said atrial contraction signal, whereby the heart is permitted to synchronize contraction of the ventricle with a sensed contraction of the atrium for said P-R time and said first selection circuit means is set to detect an R wave during said P-R time, said generator means generating said stimulating signal if said R wave fails to be detected in said P-R time period.

7. The apparatus of claim 1 wherein said timing means includes timing circuit means for generating timing signals defining a commencement of a cardiac cycle and representing respectively a refractory time period and a rate time out period, each of predetermined duration;
and said control means including controller circuit means for coupling first selection criteria signals from said parameter memory means to said selection circuit during said refractory time period and for coupling second selection criteria signals from said parameter memory means to said selection circuit during said rate time out period.

8. The apparatus of claim 7 wherein said selection criteria signals define slope ranges of said cardiac signal.

9. The apparatus of claim 7 wherein said electrode means comprises a first sensing electrode associated with the atrium of the heart and a second electrode implanted in the ventricle of the heart for both sensing ventricular activity and for coupling said stimulating signal from said generator means to said ventricle, said signal detecting means comprising first and second signal detector means associated respectively with said first and second electrodes and having separate selection circuits for receiving selection criteria signals for detecting respectively a T wave identifying atrial contaction and an R wave identifying ventricular contraction.

10. The apparatus of claim 9 wherein said parameter memory means for said second signal detector means stores first selection criteria signals representative of a T
wave and second selection criteria signals representative of an R wave; said controller circuit means being responsive to said timing signals for coupling said T

ave selection criteria signals to said selection circuit of said second signal detector means during a refractory time period whereby said second signal detector means is set to define a T wave for capture verification during said refractory time, said controller circuit means being further operative to couple said R wave selection criteria signals to said selection circuit of said second signal detector means during said rate time out period whereby said second signal detector means is set to identify an R wave during said rate time out period.

11. The apparatus of claim 10 wherein said timing circuit means further generates a PVC time period signal between said refractory period signal and said rate time out period signal, said parameter memory means for said first signal detector means further storing selection criteria signals representative of a PVC cardiac signal, said controller circuit means coupling said PVC selection criteria signals to said selection circuit means for said first signal detector means during said PVC time period in response to the generation of said PVC time period signal.

12. The apparatus of claim 11 wherein said control means includes PVC counter circuit means, means for incrementing said PVC counter circuit means for each detection of a premature ventricular contraction during said PVC time period, said timing circuit means generating a rate limit refractory time period signal in response to the detection of a premature ventricular contraction, said first signal detector means being set to detect a PVC signal during said rate limit time refractory period and for incrementing said PVC counter circuit means in response thereto, said pacing apparatus reverting to fixed rate pacing if said counter circuit means exceeds a predetermined count.

13. The apparatus of claim 11 further comprising tachycardia detection means responsive to a first detection of a premature ventricular contraction by said first signal detector means for timing the interval of such contractions; and said timing means including circuit means causing said generator means to generate stimulating output signals at a rate higher than the normal cardiac cycle for a predetermined number of pulses in an attempt to eliminate a tachycardia condition sensed by said tachycardia direction means.

14. The appartus of claim 7 wherein said timing means includes a second timing circuit means operating independent of said first-mentioned timing circuit means for generating a rate limit enable signal at a predetermined time after the commencement of a caridac cycle and for inhibiting said pulse generator means until said rate limit enable signal has been generated.

15. The apparatus of claim 13 wherein said tachycardia detection means includes programmable means to define the predetermined number of stimulating output signals generated.

16. The apparatus of claim 15 wherein said tachycardia detection means includes event counter means for storing a count representative of the number of times said tachycardia detection means is enabled and for thereafter enabling said cardiac pacing apparatus to enter a different mode of operation.

17. The apparatus of claim 11 wherein said controller circuit means is responsive to the detection of a T wave during said first part of refractory for coupling one of said selection criteria signals from said memory means to said digital filter circuit for detecting one of an R wave, T wave, or Premature Ventricular Contraction during a second part of refractory following said first part; said timing circuit means further comprising reversion counter means for counting detections in said second part of refractory; said controller circuit means being responsive to a predetermined count in said reversion counter circuit means for causing said generator means to generate stimulating pulses at a fixed rate in response to said timing circuit means.

18. The apparatus of claim 14 wherein said cardiac pacing apparatus includes a battery and wherein said first timing circuit means includes a crystal oscillator for generating said timing signals, said second timing circuit means comprising a voltage-controlled oscillator generating said rate limit enable signal having a period depending upon the terminal voltage of said battery.

19. The apparatus of claim 5 wherein said controller circuit means is responsive to the detection of an R wave representing a natural heartbeat during the rate time out period for coupling selection criteria signals during the succeeding refractory time period to said filter means, said selection criteria signals being representative of a predetermined noise level of detection, said controller circuit means being responsive to a first signal detection during said refractory time comprising a second part of refractory for coupling selection criteria signals to said filter means during said second part of refractory period for detecting a PVC signal therein, said timing circuit means further including reversion counter means and means for incrementing said reversion counter means for each PVC
couplet detected and for reverting to fixed rate pacing if a predetermined count of said couplet is reached.

20. The apparatus of claim 19 wherein said controller circuit means couples one set of selection criteria signals to said selection circuit means during a first part of said refractory time period prior to said first signal detection during said refractory period, and a second set of selection criteria signals for the second part of said refractory period.

21. The apparatus of claim 20 wherein said controller circuit means couples selection criteria signals to said selection circuit means for detecting a T wave, an R wave, or a PVC during the first part of a refractory period if said system had detected a natural heartbeat in the previous cardiac cycle and for detecting an R wave or a PVC in the second part of such refractory period.

22. The apparatus of claim 19 wherein said controller circuit means in response to the generation of a stimulating signal by said generator means couples selection criteria signals from said parameter memory means to said selection circuit means during said refractory time period for detecting a T wave, said controller circuit means in response to the detection of a T wave in said refractory period entering a second part of said refractory period couples selection criteria signals to said selection circuit means for detecting a signal of greater magnitude than the T wave during said second part of refractory.

23. The apparatus of claim 21 wherein said timing circuit means includes reversion counter means and PVC
counter means and wherein said controller circuit means couples selection criteria signals to said selection circuit means during said second part of refractory representative of either an R wave or a PVC, said controller circuit means being responsive to the detection of a PVC during said second part of refractory for incrementing said reversion counter circuit means and said PVC counter circuit means, said cardiac pacing apparatus being responsive to a predetermined reversion count for reverting to fixed rate pacing when said predetermined count is reached.

24. The apparatus of claim 22 wherein said controller circuit means is responsive to the detection of an R wave in said second part of refractory for incrementing said reversion counter means.

25. The apparatus of claim 22 wherein said timing circuit means further generates a PVC period signal following said refractory period, said controller circuit means coupling selection criteria signals to said selection circuit means for detecting a PVC signal during said PVC period, said controller circuit means resetting the cardiac cycle time for detecting a further PVC signal durng a refractory period, said controller circuit means continuing to increment said reversion counter means for each detection of a PVC either of said refractory periods and for existing said PVC time period only if a PVC signal fails to be detected in said PVC time period.

26. Cardiac pacer apparatus comprising: electrode means including at least a first electrode adapted to stimulate the heart; control means including timing means which defines a sample time window; signal detector means including sensing means for sensing cardiac signals on said electrode means, filter means including a filter circuit receiving the signal sensed by said sensing means for quantizing said sensed signal and continuously generating digital words representative of the slope of said sensed signal over said sample time window, parameter memory means for storing signals representative of predetermined selection criteria for defining at least one component of a cardiac cycle signal; selection circuit means including a selection-circuit responsive to the quantized output signals of said filter means and said stored selection criteria signals for generating a detection signal if said digital slope words meet said predetermined selection criteria said selection circuit means including first slope detector means for detecting whether said quantized output signals define a first predetermined slope over a first portion of a cardiac cycle; second slope detector means for detecting whether said quantized output signals define a second predetermined slope over a second portion of a cardiac cycle and coincidence detection means responsive to the outputs of said first and second slope detector means for defining a valid detection of said component when said outputs indicate said first and second slope conditions are met; and generator means for generating a stimulating signal and coupling the same to said electrode means if said selection circuit means fails to generate said detection signal within a predetermined time from a previous detection signal or a previous stimulating signal.

27. The apparatus of claim 26 wherein said selection circuit further comprises digital delay means for delaying said digital signals a predetermined time representative of the time difference between said first and second portions of said cardiac signal whereby a valid detection of said component is defined when said first and second slope conditions are met for portions of the same cardiac cycle spaced in time by said predetermined time of said delay means.

28. The apparatus of claim 27 wherein said parameter memory means stores a plurality of digital words, each representative of a desired slope criteria; said filter circuit including slope counter circuit means for counting digital signals to generate a digital word representative of the slope of the cardiac signal from said sensing means; and said control means including controller circuit means for selectively coupling one of said slope criteria words to one of said slope detector means for programming the criteria of slope selection of said one slope detector means.

29. The apparatus of claim 28 wherein said timing means comprises timing circuit means for controlling the time in a cardiac cycle at which said selection parameter word is coupled from said parameter memory means to said slope detection means whereby said component is identified as a function of the timing of a cardiac cycle.

30. The apparatus of claim 28 wherein said digital delay means comprises a shift register and said parameter memory means further stores digital data words representative of a predetermined amount of delay in said shift register between said first and second portions of said cardiac cycle; said controller circuit means selecting one of said digital delay words from said parameter memory means and transmitting the same to said shift register to determine said delay.

31. The apparatus of claim 29 wherein said parameter memory means further stores a plurality of data words representative of different sample rates, and wherein said controller circuit means selectively couples said sample rate data words to said sensing means to define the sample data rate of said incoming cardiac signal.

32. The apparatus of claim 31 wherein said sensing means includes delta modulator circuit means having a gain control circuit responsive to gain-setting inputs and wherein said parameter memory means stores data words representative of different gains for said delta modulator circuit, said controller circuit means selectively coupling said gain data words to said gain control circuit means to define the gain of said delta modulator circuit means.

33. The apparatus of claim 26 wherein one of said slope detector means defines a maximum slope range condition for its associated portion of a cardiac signal and includes counter circuit means for generating a cumulative signal representative of said slope; and further comprising selector circuit means responsive to the output of said counter circuit means for determining whether the contents of said counter circuit means exceeds a predetermined number of counts representing a violation of the error selection criteria of said associated slope detector means.

34. The apparatus of claim 33 wherein said parameter memory means stores a plurality of data words representative of different slope selection criteria for said selector circuit means and said control means includes controller circuit means for selectively coupling one of said slope data words of said parameter memory means to said selector circuit means to define the selection criteria therefor.

35. The apparatus of claim 26 wherein one of said slope detector means includes selector circuit means for defining a mimimum slope range condition for the associated portion of said cardiac signal for a valid detection criteria.

36. The apparatus of claim 35 wherein said sensing circuit means includes delta modulator circuit means generating binary output signals at a predetermined sample clock rate; said filter means including window shift register means clocked at said sample clock rate and receiving the output of said delta modulator for storing said output for a sample window time; and counter circuit means for generating a digital word representative of the count stored in said window shift register; one of said slope detector means comprising high slope selector circuit means for generating an output signal if the contents of said counter circuit means exceeds a predetermined value.

37. The apparatus of claim 36 wherein said parameter memory means stores data words representative of selection criteria for said slope selector circuit means; said control means including controller circuit means for selecting said data words from said parameter memory means and coupling the same to the associated slope detector means.

38. The apparatus of claim 26 wherein said sensing means comprises an intracardial electrode adapted to sense said cardiac signal within the ventricle.

39. The apparatus of claim 26 wherein said sensing means includes an electrode located within the atrium of the heart

40. The apparatus of claim 26 wherein said sensing means includes delta modulator circuit means which samples said oardiac signal at a predetermined sample rate and generates a train of output binary signals, each signal being representative of the slope of the cardiac signal relative to the value of the signal at the previous sample time; said filter circuit means including shift register means receiving the output of the delta modulator circuit means for storing said output signals over a sample window period, and counter circuit means for generating a digital signal representative of the contents of said shift register means; one of said slope detector means being responsive to the contents of said counter circuit means, said other slope detector means including second shift register means for storing signals representative of said counter means' having complied with the selection criteria thereof for a plurality of clock rates of said second shift register.

41. The apparatus of claim 40 wherein said timing means generates first and second clock signals for clocking said first and second shift registers respectively at different rates.

42. The apparatus of claim 41 wherein said parameter memory means stores data words representative of desired clock rates for said first and second shift registers; and said control means comprising controller circuit means for selecting predetermined clock rate data words for said shift registers respectively and for coupling the selected data words to the respective shift registers for clocking the same at the respective selected clock rates.

43. The apparatus of claim 26 characterized in that said first and second portions of said cardiac signal are separated in time for the same cardiac cycle and do not overlap in time.

44. The apparatus of claim 43 characterized in that said first and second portions are separated in time by a predetermined delay period during which the magnitude and slope of said cardiac signal do not affect a valid detection.

45. The apparatus of claim 44 characterized in that said apparatus is reset for detection each cycle of a cardiac signal upon the occurrence of a predetermined portion of an expected cardiac cycle.

46. The apparatus Or claim 26 wherein said parameter memory means stores digital words representative of different criteria for said first and second slope detector means, said control means including a controller circuit means for selecting predetermined data words from said parameter memory means and for coupling the same respectively to said first and second slope detector means at predetermined portions of a caridac cycle, whereby said detection parameters may be changed under control of said controller circuit means for different portions of a cardiac cycle.

47. Cardiac pacer apparatus comprising: electrode means including at least a first electrode adapted to stimulate the heart; control means including timing means which defines a sample time window; signal detector means including sensing means for sensing cardiac signals on said electrode means, filter means including a filter circuit receiving the signal sensed by said sensing means for quantizing said sensed signal and continuously generating digital words representative of the slope of said sensed signal over said sample time window, parameter memory means for storing signals representative of predetermined selection criteria for defining at least one component of a cardiac cycle signal; selection circuit means including a selection circuit responsive to the quantized output signals of said filter means and said stored selection criteria signals for generating a detection signal if said digital slope words meet said predetermined selection criteria; and generator means for generating a stimulating signal and coupling the same to said electrode means if said selection circuit means fails to generate said detection signal within a predetermined time from a previous detection signal or a previous stimulating signal, said timing means including first timing circuit means having a first timing source for gererating timing signals representative of time periods in a cardiac cycle including a rate time out period during which said predetermined component is expected to occur; and second timing circuit means synchronized with said first timing circuit means and having a second timing source independent of said first timing source for generating a rate limit enable signal defining a predetermined minimum period relative to the commencement of a cardiac cycle and ending during a normal cardiac rate time out period; said generator means generating said stimulating signal during said rate time out period and being inhibited from generating said stimulating signal until said rate limit signal is generated by said second timing means.

48. The apparatus of claim 47 wherein said first timing source comprises a crystal oscillator and wherein said generator means generates a stimulating pulse having its width defined by said crystal oscillator.

49. The apparatus of claim 48 wherein said cardiac pacing apparatus includes a battery and wherein said second timing source includes a voltage-controlled oscillator energized by said battery and generating said rate limit enable signal at a period dependent upon the terminal voltage of said battery.

50. The apparatus of claim 49 wherein said rate limit enable signal occurs before the end of said rate time out period if said crystal oscillator is functioning properly and the terminal voltage of said battery has not depleted beyond a predetermined limit; said control means including controller circuit means having rate limit processing circuit means for detecting when said rate limit signal occurs before the end of said rate time out period, each such detection comprising a rate limit event, said rate limit processing circuit means including counter circuit means for counting such rate limit events in successive occurrence and being responsive to a first predetermined number of such rate limit events for increasing said rate time out period of said first timing circuit means.

51. The apparatus of claim 50 wherein said rate limit processing circuit means is further responsive to a second predetermined number of such rate limit events following said first predetermined number of such events for causing said generator means to generate stimulating signals at a fixed rate, and wherein said second timing source derives said timing signals for said generator means and defines the duration of said stimulating signal.

52. The apparatus of claim 49 wherein said rate limit processing circuit means is responsive to a predetermined number of such events occurring in sequence prior to increase in said rate time out period.

53. The apparatus of claim 50 wherein said rate limit processing circuit means is further responsive to said predetermined number of rate limit events for increasing the duration of a stimulating pulse when such predetermined number of rate limit events is detected for increasing the duration of a stimulating signal when such predetermined number of rate limit events is detected.

54. The apparatus of claim 50 wherein said controller circuit means is responsive to the application of an external magnet for substituting said second timing circuit means for said first timing circuit means to define said rate time out period and for shortening said period thereby increasing the rate of the system in an attempt to artificially stimulate the heart.

55. The apparatus of claim 50 wherein said controller circuit means is responsive to the application of an external magnet to define the duration of a stimulating pulse during such application using said first timing circuit means.

56. The apparatus of claim 54 wherein said timing means includes time memory means for storing data words representative of predetermined times in a cardiac cycle, including times for the beginning and end of said rate time out period; comparison circuit means for comparing timing signals derived from said first timing circuit means representative of lapsed time in a given cardiac cycle with data words from said storage means; said controller circuit means coupling data words from said time memory means to said comparison circuit means, said rate limit processing circuit means being responsive to the application of an external magnet for overriding said controller circuit means for coupling a predetermined data word from said time memory means to said comparison means to define the end of said rate time out period during the application of said external magnet.

57. The apparatus of claim 56 wherein said predetermined word selected by said rate limit processing circuit means determines the time out period for said second timing circuit means, said rate limit processing circuit means using said second timing circuit means to determine the rate time out period.

58. The apparatus of claim 57 wherein said word from said time memory means selected by the application of said external magnet is of a duration to interrupt tachycardia, said rate limit processing circuit means further including counter circuit means for counting the number of pulses from said pulse generator means at said tachycardia rate and for limiting the number of pulses applied thereby to a predetermined number.

59. Cardiac pacer apparatus comprising: electrode means including at least a first electrode adapted to stimulate the heart; control means including timing means which defines a sample time window; signal detector means including sensing means for sensing cardiac signals on said electrode means, filter means including a filter circuit receiving the signal sensed by said sensing means for quantizing said sensed signal and continuously generating digital words representative of the slope of said sensed signal over said sample time window, parameter memory means for storing signals representative of predetermined selection criteria for defining at least one component of a cardiac cycle signal; selection circuit means including a selection circuit responsive to the quantized output signal of said filter means and said stored selection criteria signals for generating a detection signal if said digital slope words meet said predetermined selection criteria; and generator means for generating a stimulating signal and coupling the same to said electrode means if said selection circuit means fails to generate said detection signal within a predetermined time from a previous detection signal or a previous stimulating signal, said timing means including first oscillator circuit means for generating a periodic signal at a first repetition rate; first divider circuit means responsive to the output signal of said first oscillator circuit means for generating a digital signal representative of lapsed time; first memory means for storing selectively addressable digital words representative of sequentially occurring predetermined time marks relative to a commencement time; first address means for addressing said time mark words stored in said first memory circuit means; first comparator circuit means responsive to one of said time mark words from said first memory means selected by said first address means representative of a predetermined time in a cardiac cycle for comparing the same with the contents of said first divider circuit means representative of lapsed time in a cardiac cycle; said first comparator circuit means generating an output signal when said lapsed time signal contents of said first divider circuit means is equal to a time mark word addressed and selected from said first memory circuit means; said output signal being representative of the occurrence of a predetermined time in said cardiac cycle as represented by said digital time mark word stored in said first memory circuit means.

60. The apparatus of claim 59 wherein said time mark words in said first memory means represent predetermined lapsed times relative to a reset signal and includes digital words representative respectively of the end of a ventricular refractory period following detection of a natural R wave or stimulated cardiac signal, the end of PVC time period, and the end of a Ventricular Rate Time Out period.

61. The apparatus of claim 59 wherein one of said time mark words in said first memory means represents the end of a Ventricular Rate Time Out period during which a natural heart-beat is expected to occur; and said timing means further comprising: second oscillator circuit means operating independently of first oscillator circuit means for generating a second periodic signal; second divider circuit means responsive to the output signal of said second oscillator circuit means for generating digital signals representative of lapsed time; second memory circuit means for storing an addressable digital word representative of a lapsed time defining a predetermining ventricular rate; second address means for selectively addressing the contents of said second memory circuit means; second digital comparator circuit means responsive to the digital time word of said second memory circuit means and to the contents of said second divider circuit means for generating a rate limit signal when the contents of said divider circuit means representative of lapsed time equal the digital time word selected from said second memory circuit means; said control means including controller circuit means responsive to the output of said first comparator circuit means representative of the end of Ventricular Rate Time Out period for actuating said generator means and for inhibiting the actuation of said generator means until said rate limit signal is generated by said second comparator circuit means, whereby said first oscillator circuit means defines a cardiac-cycle rate during normal operation, and said second oscillator circuit means prevents run away of said first oscillator circuit means.

62. The apparatus of claim 61 wherein said controller circuit means includes means responsive to the occurrence of said signal representative of the end of a Ventricular Rate Time Out period prior to the occurrence of said rate limit signal a predetermined number of times for disabling said first oscillator circuit means and for enabling said second oscillator circuit means to provide timing signals for said pacing apparatus.

63. The apparatus of claim 62 wherein said first oscillator circuit means is a crystal oscillator for deriving primary timing signals and said second oscillator circuit means is a voltage controlled oscillator for deriving secondary timing signals.

64. The apparatus of claim 63 wherein said occurrence of said end of a Ventricular Rate Time Out period prior to a rate limit signal defines a rate limit event and wherein said timing means includes rate limit counter circuit means for counting successive occurrences of rate limit events, said controller circuit means being responsive to a first predetermined count in said rate limit counter circuit means for lengthening said Ventricular Rate Time Out Period by a predetermined amount.

65. The apparatus of claim 64 wherein said controller circuit means extends the end of said Ventricular Rate Time Out period by approximately twelve per cent in response to the detection of rate limit events of said first count.

66. The apparatus of claim 65 wherein said control means further comprises circuit means for generating an elective replacement time signal when said controller circuit detects said first predetermined number of rate limit events to signal battery depletion.

67. The apparatus Or claim 64 wherein said control means further comprises rate limit synchronizer circuit means for synchronizing the output signals of said first and second comparator circuit means.

68. Cardiac pacer apparatus comprising: electrode means including at least a first electrode adapted to stimulate the heart; control means including timing means which defines a sample time window; signal detector means including sensing means for sensing cardiac signals on said electrode means, filter means including a filter circuit receiving the signal sensed by said sensing means for quantizing said sensed signal and continuously generating digital words representative of the slope of said sensed signal over said sample time window, parameter memory means for storing signals representative of predetermined selection criteria for defining at least one component of a cardiac cycle signal; selection circuit means including a selection circuit responsive to the quantized output signals of said filter means and said stored selection criteria signals for generating a detection signal if said digital slope words meet said predetermined selection criteria; and generator means for generating a stimulating signal and coupling the same to said electrode means if said selection circuit means fails to generate said detection signal within a predetermined time from a previous detection signal or a previous stimulating signal, said timing means including timing circuit means responsive to said signal detector means for generating timing period signals for each cardiac cycle including a refractory period signal defining a refractory period, and a Ventricular Rate Time Out signal defining a Ventricular Rate Time Out period signal; said generator means being responsive to said timing signals for generating a stimulating pulse on said electrode means at the end of said Ventricular Rate Time Ou period if a natural heartbeat fails to be detected by said signal detecting means during such period; said signal detector means being responsive to said cardiac signals and said timing signals for detecting a prematuare ventricular contraction during a predetermined portion of said refractory period; and circuit means responsive to said signal detecting means to cause said timing circuit means to reduce said Ventricular Rate Time Out period to a predetermined amount if a premature ventricular contraction is detected during said refractory period; said generator means being operative to generate said stimulating pulse if a natural heartbeat fails to be detected in said reduced Ventricular Rate Time Out period.

69. The apparatus of claim 68 wherein said circuit means is responsive to the detection of a natural heartbeat during said Ventricular Rate Time Out period in one cardiac cycle to cause said timing circuit means to lengthen the Ventricular Rate Time Out period in the next succeeding cardiac cycle to a predetermined time, whereby additional time is given for the detection of a natural heartbeat during the next succeeding cardiac cycle following the detection of a natural heartbeat.

70. The apparatus of claim 68 wherein said electrode means includes first electrode means for stimulating the ventricle and for detecting cardiac signals in said ventricle, and second electrode means for detecting atrial signals representative of atrial contraction; said control means including circuit means responsive to the detection of atrial contraction during said Ventricular Rate Time Out period for establishing a predetermined P-R delay time for the detection of a natural heartbeat irrespective of the time remaining in said Ventricular Rate Time Out period, to thereby synchronize ventricular activity with the detection of atrial contraction.

71. The apparatus of claim 68 wherein said signal detecting means is further responsive to said timing signals and the generation of a stimulating signal for detecting a T wave during said refractory period following the generation of a stimulating signal to verify capture by said stimulating signal.

72. The apparatus of claim 68 wherein said circuit means generates a PVC timing signal defining a PVC period extending for a predetermined time immediately prior to commencement of said Ventricular Rate Time Out period and defining the period for detecting a premature ventricular contraction.

73. Cardiac pacer apparatus comprising: electrode means including at least a first electrode adapted to stimulate the heart; control means including timing means which defines a sample time window; signal detector means including sensing means for sensing cardiac signals on said electrode means, filter means including a filter circuit receiving the signal sensed by said sensing means for quantizing said sensed signal and continuously generating digital words representative of the slope of said sensed signal over said sample time window, parameter memory means for storing signals representative of predetermined selection criteria for defining at least one component of a cardiac cycle signal; selection circuit means including a selection circuit responsive to the quantized output signals of said filter means and said stored selection criteria signals for generating a detection signal if said digital slope words meet said predetermined selection criteria; and generator means for generating a stimulating signal and coupling the same to said electrode means if said selection circuit means fails to generate said detection signal within a predetermined time from a previous detection signal or a previous stimulating signal, control means including status control memory means for storing control data signals representative of a desired status condition; and state controller means responsive to the contents of said status control memory means for selectively enabling or disabling the operation in functioning of a function circuit means in response to the contents stored in an associated word in said status control memory circuit means.

74. The apparatus of claim 73 wherein said function circuit comprises capture verification circuit means including sensing means for determining whether the ventricle has contracted in response to a stimulating signal and for generating a verification signal in response thereto; said status control memory means storing a digital signal representative of whether said capture verification circuit means is to be enabled or disabled;
said state controller means selectively enabling or disabling said capture verification circuit means in response to the contents of said status control memory means.

75. The apparatus of claim 73 wherein said function circuit means comprises automatic tachycardia overdrive circuit means responsive to said timing means for detecting whether a patient is in a state of tachycardia and for generating predetermined signals to stimulate said heart in an attempt to overcome said state of tachycardia; said status control memory means storing digital signals representative of whether said automatic tachycardia overdrive circuit means is to be enabled or disabled; said state controller means selectively enabling or disabling said overdrive circuit means in response to the contents of said status control memory circuit means.

76. The apparatus of claim 73 wherein said pacing apparatus is adapted for total implantation in a patient and wherein said function circuit means is responsive to the application of an external signal for permitting an external source to generate a stimulating signal of predetermined repetition rate to said electrode means;
said function circuit means including means responsive to said external signal for permitting said external source of stimulating pulses to override said timing means and said generator means implanted in said patient, said status control memory means storing data for controlling said pacing apparatus to be responsive to said external signal or nonresponsive thereto.

77. The apparatuse of claim 73 wherein said apparatus is adapted for implantation in a patient, and said timing means generates signals for defining a ventricular rate time out period during which a natural R wave is expected to occur; and wherein said function circuit means includes means responsive to the occurrence of a P wave in said patient during said ventricular rate time out period prior to an R wave for establishing a predetermined P-R interval after the detection of such P wave at the end of which interval said ventricular rate time out period terminates irrespective of the time remaining in said ventricular rate time out period when said P wave was detected, said status control memory means storing digital signals representative of whether said function circuit means is operative.

78. The apparatus of claim 73 wherein said apparatus is adapted for implantation in a patient; said controller means includes switch means responsive to the application of an external signal for communicating said apparatus with an external source of signals; and switch controller means responsive to the state of said switch means for generating an output signal representative thereof and having inverter circuit means for inverting the sense of said output signal; said status control memory means storing signals representative of the operativeness of said inverter circuit means; said state controller means being responsive to the signals stored in said status control memory means for selectively including or overriding said inverter circuit means whereby the signals stored in said status control memory means determine whether the state of said switch means is true or inverted.

79. The apparatus of claim 73 wherein said apparatus is adapted to be implanted in a patient, said controller means comprising switch means responsive to the application of an external signal for generating an internal control signal representative of whether said external signal is present or not; and said function circuit means is responsive to said internal control signal for forcing said pulse generator means to generate a stimulating signal at a predetermined fixed rate when said internal control signal is present; said status control memory means storing signals representative of a state of enablement or disablement for said function circuit means, said state controller means being responsive to said signals stored in said status control memory for selectively enabling or disabling said function circuit means.

80. The apparatus of claim 73 wherein said timing circuit means includes first oscillator means, counter circuit means responsive to the output of said first oscillator circuit means for generating a signal representative of lapsed time; time mark memory means for storing data words representative of predetermined ventricular rate time out periods in a cardiac cycle;
comparator circuit means responsive to the contents of said counter circuit means and a ventricular rate time out data word from said mark memory means for generating an output signal when the same are equal; said state controller means being responsive to the output signal of said comparator circuit means representative of a selected ventricular rate time out time for causing said generator means to generate a stimulating signal if said detector circuit means had not detected an R wave prior thereto; means responsive to the application of an external signal for generating an internal signal in said apparatus; said state controller means being responsive to said internal signal for selecting a predetermined rate time out data word from said time mark memory means representative of a safe pacing condition.

81. The apparatus of claim 73 wherein said timing circuit means comprises a primary oscillator for generating clock signals for said apparatus and wherein said status control memory means stores a standby data word having a first and second states said apparatus being responsive to said first state for inhibiting the transmission of said clock signals for the remainder of said apparatus and being reponsive to said second state for permitting said clock signals to be transmitted to the remaining circuitry of said apparatus, whereby when said stored signal is in said first state, power is fed to said oscillator but the remaining circuitry is not clocked, thereby conserving battery power in a standby mode; said apparatus being responsive to an externally applied signal to change the state of said standby word from said first state to said second state.

82. Cardiac pacer apparatus comprising: electrode means including at least a first electrode adapted to stimulate the heart; control means including timing means which defines a sample time window; signal detector means including sensing means for sensing cardiac signals on said electrode means, filter means including a filter circuit receiving the signal sensed by said sensing means for quantizing said sensed signal and continuously generating digital words representative of the slope of said sensed signal over said sample time window, parameter memory means for storing signals representative of predetermined selection criteria for defining at least one component of a cardiac cycle signal; selection circuit means including a selection circuit responsive to the quantized output signals of said filter means and said stored selection criteria signals for generating a detection signal if said digital slope words meet said predetermined selection criteria; and generator means for generating a stimulating signal and coupling the same to said electrode means if said selection circuit means fails to generate said detection signal within a predetermined time from a previous detection signal or a previous stimulating signal, timing means including first memory circuit means for storing a plurality of first data words, each defining a different duration for said ventricular rate time out period and storing a plurality of second data words, each defining a different time duration for said stimulating signal; said control means further comprising input circuit means responsive to the application of a predetermined external signal for generating an internal signal in said pacing apparatus representative thereof; status memory means storing a first programmable status signal having an enable and a disable state; and temporary mode counter circuit means responsive to said internal signal, and to timing signals for counting a predetermined number of cardiac cycles and including control circuit means responsive to said first status signal's being in an enable state means for selecting one of said first data words from said first memory means to define a predetermined cardiac rate and one of said second data words to define the width of a stimulating pulse, said control circuit means of said temporary mode counter circuit means disabling operation of said apparatus at said programmed rate and pulse width after said counter temporary mode counter circuit means has counted a predetermined number of cardiac cycles,

83. The apparatus of claim 82 wherein said control circuit means is responsive to said first status signal's being in a disabled state for permitting said system to operate in a first magnet phase under program control for as long as an external magnet is applied generating said external signal.

84. The apparatus of claim 83 wherein said status memory means includes a second programmable status signal having an enabled and a disabled state; said control means further comprising state controller circuit means responsive to said second status signal's being in said disabled state for disabling said signal detecting means, thereby causing said apparatus to operate in a fixed rate mode as long as an external magnet is applied.

85. The apparatus of claim 84 wherein said control circuit means is responsive to said apparatus being programmed either at a rate above a predetermined base rate or at a pulse width less than a predetermined safe duration for enabling said temporary mode counter circuit means to terminate operations under one or both of said conditions after predetermined number of cardiac cycles.

86. The apparatus of claim 85 wherein said control circuit means forces said apparatus to operate in an inherently safe mode after said predetermined number of cardiac cycles.

87. The apparatus of claim 86 wherein said control means includes circuit means responsive to said second magnet phase signal for selectively disabling said signal detecting means and thereby causing said apparatus to operate in a fixed rate mode with a ventricular rate time out period determined by said secondary oscillator circuit means.

88. The apparatus of claim 86 wherein said timing means includes timing memory means for storing first and second data words representative respectively of a high and low cardiac pacing rate relative to a normal rate 7 said temporary mode counter circuit means being responsive to said second magnet phase signal for communicating said second data word of said secondary oscillator status memory means to said timing circuit means to define the ventricular rate time out period, said apparatus being further responsive to internally stored signals representative of a desired amplitude and pulse width for said stimulating pulse for effecting the same in response to said second magnet phase signal.

89. The apparatus of claim 86 characterized in that said primary timing circuit means includes a crystal oscillator and said secondary timing circuit means includes a voltage controlled oscillator, and further including means responsive to the application of said external signal to said apparatus to cause said system to operate in said second magnet phase after said predetermined number of cardiac cycles counted by said temporary mode counter circuit means to thereby permit a physician to check out the back-up timing source, rate and pulse width irrespective of the condition of the primary timing source.

90. The apparatus of claim 89 wherein said input circuit means is responsive to the removal of said magnet for generating a signal representative thereof; and wherein said secondary oscillator circuit means generates a rate limit enable signal representative of a desired minimum ventricular rate time out period; said primary timing circuit means defining the end of a ventricular rate time out period during normal operation; and said state controller circuit means is responsive to a rate limit enable signal derived from said secondary oscillator means for disabling the generation of a stimulating pulse until said rate limit enable signal has occurred.

91. The apparatus of claim 90 wherein said apparatus is implanted in a patient, said control means including rate limit means for storing signals representative of the number of sequential occurrences in which the ventricular rate time out period derived from said primary timing circuit means occurs prior to said rate limit enable signal derived from said secondary timing circuit means, such events being rate limit events; said temporary mode counter circuit means further inhibiting the counting of said rate limit events in said counter circuit means during a predetermined time following the generation of said signal represantative of the removal of said external signal.

92. The apparatus of claim 82 wherein said status memory means further includes a second programmable status signal having an enable and a disable state; tachycardia control circuit means responsive to said circuit means that is responsive to the application of a predetermined external signal, and to said second status signal's being in an enable state, for selecting one of said first data words and one of said second data words from said first memory means when said external signal is applied for causing said generator means to generake a predetermined number of pulses at a predetermined repetition rate and pulse width for interrupting a chain of tachycardia;
whereby a patient may generate said external signal if tachycardia is detected, and said apparatus will implement a tachycardia override mode under program control and exit said tachycardia override mode irrespective of further action by the patient.

93. The apparatus of claim 89 wherein said signal detecting means includes a delta modulator and said status memory means stores a second status signal having an enable state of an electrogram generation mode, said state controller means being responsive to said internal signal representative of the application of said external signal for coupling the output of said delta modulator to an output signal transmitter implanted with said apparatus for transmitting externally the output signal of said delta modulator.

94. The apparatus of claim 73 wherein said state controller circuit means increments said temporary mode counter circuit means for each cardiac cycle during which the output of said delta modulator is connected to said output signal transmitter; and wherein said state controller means de-couples the output of the delta modulator from said signal transmitter after a predetermined number of cardiac cycles.

95. The apparatus of claim 94 wherein said filter means comprises ventricular detector circuit means for detecting ventricular cardiac activity and generating the signal representative thereof, and atrial detector circuit means for detecting atrial cardiac activity and for generating the signal representative thereof; and said status memory means being programmable means for selectively energizing one or both of said detector circuits.

96. The apparatus of claim 94 wherein said temporary mode counter circuit means is responsive to an internal signal representative of the removal of said external signal for continuing to couple said signal detecting means to said transmitter for a predetermined number of cardiac cycles following the removal of said external signal; whereby said apparatus reverts to a normal mode of operation wherein cardiac cycle timing is defined by said timing circuit means under normal mode operation.

97. The apparatus of claim 94 wherein said timing circuit means includes primary means and second timing:
sources for generating ventricular rate time out signals, and further including rate limit enable means for inhibiting said generator means until said rate time out signal of said secondary timing source occurs, and for detecting the occurrence of said rate time out signal of said primary source before the occurrence of said rate time out signal of said secondary source to define a rate limit event; said controller circuit means including rate limit event counter circuit means for generating signals representative of the number of successive rate limit events; said temporary mode counter circuit means inhibiting said rate limit counter circuit means from counting said rate limit events for a predetermined number of cycles following the generation of said electrogram under said normal operating mode conditions to thereby provide a recovery time for battery depletion.