CA1171183A - Variable field partial write data merge mask system - Google Patents

Abstract

ABSTRACT

VARIABLE FIELD PARTIAL WRITE
DATA MERGE MASK SYSTEM

A variable field partial write system for merging data bits in a memory word or words upon programmable request is described. The variable blot field can be selected for any m member of bit positions from a single bit up to and including a full data word, where data words are comprised of a predetermined number of bytes each con-taining a predetermined number of bits. A starting bit code defines the location of the start of the bit field to be written and a field length code defines the number of bits that are to be merged and written. The combination of the starting bit code and the field length code define the ending bit control for the bits to be written, and are further utilized to control word boundary crossing into the next sequentially addressed memory word when the, bit field to be written cannot be completed in the addressed word. Mask signals are generated for all bit positions that precede the starting bit code and that follow the ending bit code so that bit positions of data words read from memory that correspond to the mask bits are merged unaltered with the variable field bits that are to be written and the merged data words are thereafter returned for storage in the memory system. Bit mask signals are generated for all like-ordered bits in each byte and byte mask signals are generated to enable setting of mask con-figurations for all bytes in which at least one bit is to remain unaltered, through the use of decode and translator circuits coupled to control bit mask circuits and byte mask circuits.

Description

YARIAB~E ~IE~D PAR~I~L WRITE
DATA ME~GE MA~K SYSTEM

~ACKGROUND OF THE INVEN~ION

In the da-ta processing ar-ts, it has been a consistent goal to achieve ~aster and ~aster computing rates. Coupled with this goal o~ ~aster computing rates is a parallel ~oal o~ providing sys-tem archi-tec-ture that provides ~or a gene~al purpose compu-ting operation. In the past, it has been common for -the da-ta processing system to have system architecture designed for a $ixed data word length. O~ten, -the da-ta word length i~ selected to be compatible wi-th the da-ta word s-torage re~ister capacity in the main memory sys-tem. For example, i:E
a 36-bit memory registers are employed, it was o~ten common that the data processing sys-tems would func-tion on a 36~bit basis. ~t a relatively early time in the development of binary compu-ting systems, it was recognized that a more e~ficient u~ilization o~ the main memory could be accomplished by providing for hal~-word access to the main memory system for reading and writing opeL-ations. Such systems usually opera-ted on a whole-word basis in arithmetic operations, even though access could be made to the memory on a half-word basîs.

- As system architecture and memory systems were

2~ further improved and refined, systems were developed that permitted access ~or reading and writing in the main memory selectively on the basis of quarter-words, third-,~ .

words as well as hal~-words on a ~i~ed bit-arrangement basis. ~'ince -the binary da-ta processing systems were normally arranged wi-th the memory register capaci-ty 'being ~ixed a-t some mul-tiple o~ two or some power o~ -two, these ~ractional arrangements were relatively easy to de~ine and implement.' With the developmen-t o~ -the ~rac~ional-word reading and wri-ting capabili-ty in memory sys-tems, there was developed various types o~ data processing - architectures -tha-t permitted the arithmetic manipula-tion of fractional data words.

~ n the't~-pes o~ da-ta processing systems men--tioned thus ~ar, no provision was made ~or providing'-the capability o~ writing variable length bit-~ields, where the bit-field length could vary anywhere ~rom a single bit in any memory word position, to the extent o~ writing a full memory word. Further, -the systems were limi-ted to fractional recording wi-thin the confines o~ a single addressed memory regis-ter, and word boundary crossing was no-t possible.

~s -the binary data processing sys-tems were developed by various manufac-turers, each manu~ac-turer established individually designed sys-tem architec-tures, including establishmen-t o~ various standards :~or memory register word capacity. For example, one manu~'ac-turer would have developed a product line where a 24-bit memory register word capacity was essentially a standard ~or its equipment, while another manu~acturer wou1d ha~e developed a line o~ equipment where a 36-bit memory register was a standard ~or i~s equipment. ~he various systems that were o~ a general purpose variety would include instruction reper-toires that di~ered in their speci~ic ~unctions, ~rom system -to sys-tem, bu-t collectively often-times could be programmed to accomplish the sarne functions as o-ther systems. As equipment cos-ts became

3~ ever-more expensive, i-t became desireable ~rom a cus-tomer view poin-t -that there be some'~orm o~ compatibility between sys-tems provided by di~eren-t manu~acturers.

- ~t~ 3 One impo~--tan-t elemen-t in providing da-ta processing sys-te~s -tha-t can accomplish per~orrnance of func-tions that are system compatible with o-ther da-ta processing systems, wi-thout limiting the memory regis-ter capacity to a ~ixed memory word capaci-ty, is to provide a memory accessing sys-tem that allows for writing variable data bit-fields that can be u~tilized -to emulate the memory register word capacity of other data processing sys-te~s.
I~ the data processing system is to be u-tilized -to emulate a sys-tem having a data word capaci-ty less than -the emulating system, and the writing of a variable bit-field is limited to a single word in the memory, there would result an ine~ficiency of utilization of -the memory since it is likely that the unused bit positions could be - 15 e~ectively utilized.

As data processing systems became more complex t and the word capaci-ty was increased, -the fractional-word writing resulted in inefficiencies of utili~ation of memory, and failed to provide adequate versatility for many data processing operations where i-t was desireable to manipulate variable-length bit arrangements.

Many logical and data manipulative operations require -the ability to rea~ and write various variable length bit-fields. Such operations are often accomplished by logical instructions coupled with shif-ting of data words -to accomplish -the inser-tion of variable bit-fields in data words -to be recorded. The sequences o~ logical operations coupled with shifting are time consuming and in many systems require additional shi~-ting circuitry.

SUMMARY OF THE INVENTIONS

With the foregoing background af the invention in mind, and in accordance with the present invention, an improvement in digi-tal data processing systems for providing variable ~ield partial wri-te merging of data bits in a memory word or words upon programmable requests is described. The presen-t inven-tion is considered to be a significant improvemen-t in par-tial data word wri-ting in that a variable length bi-t-field can be programmably selected for wri-ting at a predetermined location within a data word s-tored in a main memory register. The system provides for response -to a variable bit-field selec-tion up to a full da-ta word capacity, and provides fur-ther for response to control signals identifying -the location a-t which the variable bit-field is to be wri-tten. In accordance with the invention, the variable bit-field can be selec-ted for any number of bit positions ranging in number from a single bi-t partial write, contin~ously up through and including a full da-ta word. A data word is considered to be a bit~grouping that has a number of ~it posi-tions that is equal to -the number of bit positions in addressable memory loca-tions in -the main memory. A
data word may be considered to be an instruction word for the data processing system, or an operand.

When a variable field partial da-ta word write operation is selec-ted, the word address for the partial write is accessed in the memory system, and -the addressed ! word plus -the next consecu-tive addressed word is made available -to -the variable bi-t-field writing circuitry.
The -two da-ta words thus accessed from -the memory sys-tem will be read ou-t of the memory sys-tem and will be designated as the even address word and -the odd address word. I~ the variable field partial write opera-tion was limited to a single data word in the memory sys-tem, it is likely that the resul-t would be an inefficiency in the utilization of the main memory sys-tem. By providing two addressed memory words simultaneously, the Variable bit-field partial write system can accomplish a word boundary crossing in such a manner that a portion of the variable field appears in the addressed word and second portion o~
the variable field occurs in the next consecu-tive addressed word. ~s -the variable field partial ~ri-te bits are merged or inserted in -the~yords -that are accessed in the memory system, all bit posi-tions that are not included-in the ~L7~ 3 variable length bi~t-field are masked and are returned to the memory system unal-tered. I-t can be seen, then, that -the variable bi-t-field is merged wi-th existing da-ta bits external to the memory systems, and -that the sys-tem operation is transparent to -the memory system and does not require alteration or selec-tion in -the addressing or writing circui-try of the memory sys-tem.

For purposes o~ discussion of this invention, the wri-ting operation -that involves the writing of a data word completely in an addressed memory register, will be referred -to as a full word write. For such an operation, the addressed word is completely written and stored in -the memory sys-tam. ~ny variable field partial da-ta word write tha-t is specified that would result in any bit positions of the addressed word being unaltered or masked, will be determined to be a partial word write even if the variable bit-field specified is o* a capacity that would be equal -to the bi-t capaci-ty of a memory register.

During a partial wri-te opera-tion, the write data~
which is comprised of up to a full data word o~ con-tiguous - bits, to be written is received from a requestor unit, together with a specifica-tion of the address in the memory system at which t~e par-tial write data is -to be mer~ed. The reques-tor also provides a field leng-th 2~ code which defines -the number of contiguous bit that are to be merged with existing data bits during -the partial write operation. The requestor also pro~ides a bit off-se-t code that specifies -the starting bit position of the data bits that are to be written, The bit off-set code specified the bit position number with reference to some positlon o~ the data word, for example, the number o~ bit positions in decreasing order of significance star-ting from -the most significan-t bit position. The bit o~f-set code is referred to hereinaf-ter as -the A-Field, and the fieId leng-th is referred to as the ~-Field~

~he system operates during -the partial write :~7~ 33 func-tion to genera-te mask bi-ts ~or the bi-t positions ~rom the reference bi-t posi-tion o~ -the d~ta word addressed and continuing throughout the contiguous bi-t positions -to, bu-t not including the s-tarting bit. The mask bits func--tion -to main-tain the masked bit positions o~ the data word read ~rom the memory sys-tems in their exis-ting sta-te -to be re-wri-tten in the memory sys-tem as the par-tial write operation is ^ompleted. The contiguous ~it posi-tiors speci~ied by the ~-Field are written in -the memory system .. ..
as the par-tial write ~unction is completed. The combin-ation of the ~-Field and the ~-Field by addition provides a trailing bit control code tha-t specifies where the ~rariable field to be written is -termîna-ted, and specifies where the balance of -the bi-t positions, if any, o~ the word addressed or of the next consecutive word is to commence ha~ing the bit posi-tions masked. ~his trailing bit field will be referred to hereinafter as the B-~ield~ During a partial write opera-tion, the A-Field and -the ~-Field are u-tilized to determine whe-ther the contiguous bits that are to be written will cross the word boundary whereby some of the bi-ts will be wri-tten in -the addressed word and the balance of the bi-ts will be writ-ten in the next sequential word, ~hen -the requestor speci~ies a full word write function, no data bit merging or masking takes place, and the requestor speci~ies.that the A-Field and the ~-Field are each zero, The data word is ~ivided into by-tes, wi-th each byte comprising eight contiguous bit positions, i-t being understood that -the last by-te in a word may have less than eight bitso During a partial write operation,.the variable field data merge mask system of this invention generates two -types of con~trol signals, -these types ~eing a bi-t mask and a by-te maskD The bit mask generation is depend-ent upon -the A-Field for generation of the bit mask -to the starting bi-t, and is dependent upon the B-Field to deter-mi.ne the bit mask for the balance of -the bi-ts in the byte 117~B~

-tha-t conta.ins the -trailing bi-t, The by-te mask is respon-sive to -the A-~`ield for genera-ting masking of the bytes tha-t precede -the S-tarting Bit, and is responsive -to -the B-Field to generate the mask con-trol for the by-tes -that follow the by-te containing -the Trailing Bi-t, The bi-t mask and the byte mask signals are generated by decoder-transla-tor circui-try that will be described in more detail below with reference to a specific embodiment, ~hese decoder-translator circuits of the invention eliminate the need for counters and shi~-t registers thereby providing faster operating rates. Further, the decoder-tranlator circuits involved require fewer circuits -than would be .required for an implementation of a variable field partial wri-te data merge mask u-tilizing counters and shift registers, -thereby resulting in more reliable operation due to reduced failure rates and reduced cost of constructian.

OBJECTS

In view of the foregoing Background of the Invention and the Summary of -the Inven-tion, i-t is -there-fore an objec-t of this invention -to provide an improved system in digital da-ta processing sys-tems ~or providing variable field partial write merging of data bits in a memory word or words upon programmable re~uest~

It is a further objec-t of.this invention to provide an improved system for selectively determining a bit field for writing within one or more data words - while retaining unselected bit positions unaltered in the memory system.

Still ano-ther obaect of this invention is to provide an improved variable field partial wri-te merging o~ da-ta bits whose bit positions are defined by a starting bi-t position wi-thin an addressed memory word together wi-th-the field leng-th -to be writ-ten, all o-ther bi-t positions being masked and unal-tered.

Ye-t a further object of -this inven-tion is to provide a system for v^.riable field partial write merging o~ data bi-ts in memory words where word boundary crossing can occur.

~ f'ur-ther object of -this inven-tion is to provide an improvement in digital data processing sys-tems utilizing da-ta words comprised of a predetermined n~nber of bytes, each byte representing a predetermined number of bi-ts, ~or providing variable fiel~d par-tial wri-te merging of da-ta bits in a memory word or words through the generation of bit masks and byte masks for all bit positions that are to remain unaltered during -the par-tial ~-rite sequence.

Still a further object of this invention is to provide a sys-tem for variable field par-tial wrL-te merging f data bits in a memory word or words -through the gen-eration of bit masks output information -to like-ordered bit positions in all bytes, through the selected activation of byte mask enabling for malntaining all bi-t positions unaltered, other than those bit posi-tions selec-ted, for alteration, S-till a fur-ther object of -this i~ven-tion is -to provide an improved system for variable field par-tial write merging of data bi-ts in a memory word or words wherein the bi-t field to modified is con-tained within a single by-te.

Yet a further object of -this in~ention is to provide an improved sys-tem for variable field partial write merging of data bits in a memory word or words that is transparent to -the memory reading and writing opera-tion and does not add to the access -time for reading and wri-ting opera-tions.

Still a further objéct of -this invention is to provide an improved system for vzriable field par-tial write merging of da-ta bits in a memory word or words upon ~l17~ 3 _9_ programmable reques-t that does no-t require coun-ting circui-try or shi~t regis-ters circui-try, and does no-t require complex programming.

It is a fur-ther object of this inven-tion to provide an improved system :For variable ~ield partial wri-te merging of data bi-ts in a memory word or words upon programmable request that provides for word boundary crossing and minimizes was-ted or unused memory capacity when bit fields of less than a full da-ta word capacity are utilized.

Still a further objec-t of this invention is to provide an improved system ~or providing variable field partial write merging of data bits in a memory word or - words upon programmable request through -the use of decoder and translator circuits utilized to genera-te mask bit configurations ~or re-taining all unselected bi-t positions in the unaltered state.
.
These and other objects and advantages of the invention will become apparent to those having skill in art upon the reading oE -the following detailed descrip-tion when -taken in conjunction wi-th the accompanying drawings in which:

DESCRIPTION OF THE DRA~INGS

FIG. 1 is a simplified block diagram of a data processing system which incorpora~tes the inven~tion for providin~ variable field partial write merg;ng of data bits in a memory word or words;

FIG. 2 illustrates a data flow for a variable field partial write where word boundary is not crossed;

~o ;FIG~ 3 illustrates a variable field partial write operation where a word boundary is crossed;

1 ~1 '7~

-1 0 ~
FIG. 4 illus-trates the ~orma-t of ~he da-ta word utilized in -the embodiment of the inVen-tiQn;

FIG. 5 illustra-tes the format of the Bit Offset designation specified as -the A Con-trol or the A-Fi.eld which specifies -the location in -the data word oi -the S~tarting Bit of the variable field -tha-t is to be wrl-tten;

FIG. 6 illustrates the format of the L Control that defines the Write Bit Field Length, and is designated as the ~-Field;
.
FIG. 7 illustrates the forma-t of -the B-Control, referred to as the B-Field, and defines the start of~-the following bit posi-tions that are to be masked;

FIG. 8 illustrates the inter-relationship of the A-Field, the ~-Field,,and the B~Field;

FIG. 9 is an example that illus-tra-tes writing of a selected variable field wi-thin a da-ta word;

PIG. 10 illus-trates graphlcally -the Bi-t Mask configura-tion for -the Bi-t Offset speci~ied:i.n-the A-Fleld and -the Trailing Bit ~ 1 specified in the B-Field;

FIG. 11 illustrates the By.e Mask outpu-t con~
figuration for the Byte O~fset portion of the A-Fi.eld and the Trailing Byte specified ;in the B-~ield;

FIG. 12a and FIG. 12b, when arranged as iin FIG.
12, is a simplified block diagram of a portion of a data 2~ processing system -tha-t incorporates -the subject inven-tion;

FIG. 13 illustrates the various control and timing signals u-tilized in the func-tioning o~ the improved system for providing variable ~ield par-tial write merging of data bits in a memory word or words upon programmable request;

~ Lt7~

- F~G. 14a through FIG. 14d, when arranged as sho~ in FIG. 14, comprise a block diagrz~ of -the variable field partial write data merge mask system and input eontrol;

FIG, 1~ is the logic block syi.lbol for a ~ow AN~ circuit;

~IG. 16 is the logic block diagram o~ a ~ow OR circui-t;

FIG. 17 is the logic bloek diagram ~or -the High OR cireui-t;

FIG. 18 is the logic block diagram symbol o~
a~ Inverter eireuit;

FIG. 19 is the logie block diagram symbol ~or an Exclusive-OR eircuit;

FIG. 20 is the logic bloek diagram symbol ~or a combined OE and ~MD circuit;

FIG. 21a and FIG. 21b, when arranged as in FIG. 21, is a detailed logie bloek diagram of the Si~gle Byte Par-tial Write Deteetor and Word ~eleet circuitry;
FIG. 22a through FIG. 22b, when arranged as shown in FIG. 22, eomprise the detailed logie arrange~e~t ~or the S-tarting Bit D~ecoder/~ranslator, Trailing Bit Decoder/
Translator, and the Bit Mask eircuitry; and FIG. 23a through FIG. 23c, when arranged as shown 2~ in FIG. 23, comprise the deta.iled logie eircuit diagram o~ the Starting/Trai.ling Byte Decoder/Translator and the By-te ~ask eireuitry.

:~1'7~

DESCRIPTION OF THE PREFERRED EMBODIMENT

~ IG. 1 illus-trates a simpli~ied block diagr~m' of a da-ta processing system which incorporates the invention, and con-templates use of a Processor and Control 10, alternatively referred to as a Requestor, a Memory System 12, Con-trol 14, and the Variable Field Partial Write Da-ta Merge Mask System, hereinafter re~erred to as VFM 16. ~he Processor 10 is characteristically a digital data processor that ~unctions to respond to program instructions for manipula-tion of data words. The Memory System i2 is characteristically a system comprising a plurality of addressable memory registers together with the associated addressing and accessing circui-try, which is no-t shown in detail. It can be selected ~rom directly addressable systems, or can utilize the so-called set-associative memory arrangement ! I-t functions -to store instruction words and operand words ? alternatively collectively re~erred to as ~da-ta words~ e Con-trol 14 operates to control requested reading operations or requested writing opera-tions from the Processor 10 and to correlate the -timing for reading and writing operations iri the Memory lZ. I-t should be unders~tood ~tha-t -there may be several processors or reques-tors a-t-tached -to Con-trol 14. In the event that more -than one requestor is u-tilized, a priority arrangement of the type described in ~the United States Patent No. 3,967,247, to Andersen, e-t al.
would be utili~ed for purposes of illustration of the system operation, it is su~ficient to understand that -the Processor 10 will issue a Read Reques-t on line 18 when data words are required. At -the same time of issuing the Read Request signal9 an Address is transmi-tted on line 20, and an Address ~ 1 will be transmitted on line 22. If -the Memory System 12 is available for accessing, Control 14 will issue a Read Reques-t signal on line 24 for accessing the Address speci~ied on line 26 and the Address ~ 1 specified on line 28~ The Memory 12 will provide the requested addressed read data on line 30 -to Cantrol 14, which in turn wîll transmi-t -the data to the Processor 10 on line 32. For -the writing of data, Processor 10 will provide a ~ri-te Reques-t on line 34 together with the address informa-tion previously described.
The Write Data will be transmitted on line 36. The Control 14 will determine availability of -the Memory 12 for writing by supplying a Wri-te Request on line 38. When the Memory is available for writing, -the data will be -transferred on the Full Word Write data lin 40 to be written at the address specified. The Processor 10 also provides writing ~unction selec-tion signals on line 42 which specifies the selection of full word write or partial word write. In the event that a variable ~ield partial write is specified, a Part Word control signal is transmitted from Control 14 on line 44. In addition to specifying a Partial Write, Processor 10 also specifies the.:Starting Bit position o~ the variable field that is -to be written by signals - transmitted on line 46~ It also supplies a set of control signals that define the variable field length that is to be written by signals on line 48. The VFM 16 responds to timing con-trol signals received on line 50 to genera-te mask signals which are -transmit-ted on line ~2 for defining bit positions in the address memory registers -that will not be altered during the Par-tial Write operation. The mask signals indica-ted by block 54 are combined with the Write Inpu-t signals shown as block 56 and -the Read Data shown as block 58 to comprise the Wri-te Data shown as block 60 which will be transmitted as the Partial Wri-te signals on line 62 to the Memory System 12. The initiation and completion of reading and wri-ting operations 30 between the Processor 10 and Con-trol 14 are signaled by Acknowledges on line 64 and the completion of operations between Control and Memory are signaled by Acknowledges on line 6~.

- In this system environment the VFM 16 will be transparent to the memory references, and due to the speed of the operation of -the VFM in comparison to -the cycle time of the Memory 12, it will in no way impede or slow do~m system operation.

~'7 -14~
FI~. 2 illustra-tes a da-ta flow ~or a variable field partial write, where a word boundary is not crossed.
A data word comprised of J-bits is transmit-ted on line 36 and will be designated as the Write Input 56 ge-nerally.
~he addressed word in storage will have a J-bit capaci-ty as indica~ted by block 68 generally. I-t is arranged for this embodimen-t such that the mos-t signi~icant bit is designated as the O-bit 70 and progressing in order of decreasing significance by increasing bit position des-lQ ignation un~til the least significan-t bit is designated as bit J-1 as indicated by block 72. The Bit ~ffse-t specifies the location o~ the S-tarting Bit of the variable ~ield that is to be written ~rom the referenced point of ~he most significant bit. The Bit Offset is designated as~the A Control and will be shown as block ~4. The Wri^te Data shown as block 76 will be specified as to -the number of contiguous bits of data -that will be wri-tten by -the Write Field ~ength, otherwise referenced asthe L ~on~trol The remaining bi-t positions in the addressed word illus-trated as block 78 following the Wri-tten Da-ta shown as block 80 will be rnasked in -the memory sys~tem and will not be altered during the par~tial write operation~

The so-called following bi-ts following -the ~ritten Data are determined by combining -the Bi-t Offset and the Field ~ength to generate control signals -tha-t will be referenced as the B Control. I-t can be seen, then, that the data word 56 provided by the requestor will have the corresponding bit positions specified by the Bi-t Offse-t and the Field Length written in the address memor~
word 3 ~nd the leading bits shown by block 82 and the following bi-ts shown by block 84 will be ineffec-ti~e to alter the addressed memor~ word due to the leading and following masks that are generated, The mask generation will be described in more detail below.

FIG. 3 illustrates a variable field partial write opera-tion where a word boundary is crossed~ ln this configu;~ation, the word addressed, designated word ~L~'71~;~3 `"- X, comprlsing J-bi-ts, is re~erenced as word 88, and -the address ~ 1 word, designa-ted as word Y, is designa-ted by reference numeral 90. The J-bit da-ta word 56 is received from the wri-te da-ta interf'ace. Again, -the A Control specifies the Bit Offset which results in bi-t positions designated by reference numeral 92 in word X, being masked and no-t writ-ten. The Write Field ~ength in this config-u~ation is specified to be of sufficient magnitude -to exceéd -the capacity of -the remaining bit positions in word X, and requires tha-t the balance of the bit positions to complete the Write Field ~ength extend into the sufficient bi-t positions of~ word Y, Accordingly, i-t can be seen that the start of partial write data bits indicated by arrow 94 defines a par-tial wri-te ~ield X' in the received data word 56 which is transferred to the bit positions in word X following the unal-tered bits 92, as indicated by X'field 96. ~he bit positions corresponding to the Y' field 98 in the input da-ta comprise the balance o~ -the ~rlte Field ~ength, and is -transferred -to the most significant bit positions in word ~ indica-ted by the Y' field 100. The end of the partial write is specified by arrow 102, and defines the start of -the B Con-trol for defining the portion of word Y -that is to be unaltered, as indicated by block 104. ~he bit positions spe~ified by block 1 o6 in -the input data words are ineffective and are no-t utilized for the wri-ting operation, Again, the generation of the leading and trailing mask bits will be described in more detail below.

FIG. 4 illustra-tes the format of the data word utilized in the described embodiment of this inven-tionO
The data word comprises 64 decimal bits with -the 0-bit being t~e most significant bit position and increasing - ordered numbers indicating decreasing bi-t-significance, ~ -to the least significant 63-bit position. ~he 64 decimal bi-t posi-tions are equivalent to 100 octal~bit positions, which can be represented as 0 through 77 octal, and can be represented in 6 binary bit positions. The data word is further divided in-to bytes, where each byte consists 7 3L~L~3 of 8 con-tiguous bi-t positions numbered 0 through 7 for each by-te. In -this arrangemen-t, the mos-t significan-t byte is the 0-byte and the least significan-t by-te is -the 7-byte. It should be unders-tood -tha-t -thls configura-tion for the data word is illustrative only, and -that i-t could utilized more or fewer bi-t positions.

FIG. 5 illustra-tes -the format of -the Bit 0ff2et designation specified as a A Control. The A-Field specifies the location in the data word of -the Star-ting Bit of the variable field that is to be writ-ten. ~he A-Field has -the least significant bit positions des-ignated as ~0 and progresses numericall~ upwardly ln significance. The -three bit positions A0, ~1, and A2 specify the Bit Offset within a by-te. Since each by-te contains 0 through 7 bit positions ! the three bi-ts can -~
designate all possible bit posi-tions within a by-te. ~he A-Field bit positions A3, A4, and A5 speci~iy the B~,te 0ffset of the Star~ing Bit. Again, since there are 0 through 7 bytes in the da-ta word, -the t~l~ee By-te 0ffset bits o~ the ~-Field can specify all possible by-tes.
It is of course apparent that if more bytes would be utilized in a desired configura-tion, -there would have to be added -the ~6 bit position for -the A-Field. The ~-Field can be of a range of 0 -through the numerical value of -the least significant bi-t posi-tion of a da-ta word~ This is essential so -that -the S-tarting Bi-t will occur somewhere within a star~ting word. -~s will be described in more detail below, the A-Field is utilized by the VFM to ~ generate mask bi-ts for bit positions in -the data word that preceed the Starting Bit of the variabIe field tha-t is to be wrîtten.
.
FIG~ 6 illustra-tes the format of -th~ ~ Control that defines the ~rite Bit Field ~eng-th. ~he ~ Control is designated as the ~-Field. For the 64-bit config-3~ uration described, -the ~-Field is comprised of six bi-t posi-tions desigilated as L0 a~ the leas-t significant bit-position and increasing numerically -to ~5 as -the most significant bi-t posi-tion. The six bi-t posi-tions provide su~ficien-t capaci-ty to designate field leng-th of O
through 77 oc-tal bit positions and is su~lcien-t capaci-ty to designa-te up to one complete word capaci-ty of variable field bi-ts -that are to be writ-ten. If the ~-~ield is ~ero, it designates the condi-tion to wri-te a ~ull data word capaci-ty at -the o~fse-t sp@cified by the A-~ield. If the L-Field is designated to be o~ a zero value, and the A-Field is designa-ted -to be a zero, the writing operation .
is a full word write, and the YFM is inoperative. As mentioned previously, i~ the data word capacity exceeds 64 decimal bits, it is necessary to add bi-t position L6 to provide -the additional capacity -to specify the maximum ~-Field. The ~-Field in conjunc-tion with the A-Field designa-tes the bit position in the variable ~ield selection -that are -to be written, and further de~ine -the Trailing Bit of the variable field.

I-t should be noted that the designa-tion Star-ting Bit and Trailing Bit are in-tended ~or purposes o~
identi~ying re~erence points in the variable ~ield, and does no-t indicate -that the variable field is serially written. Once -the variable field is iden-ti~ied and the masks genera-ted as hereinafter described, the writing operation is contemplated to occur wi-th -the varîable field bits being writ-ten parallel.

FIG. 7 illustra-tes the ~ormat of B Control and is utilized to determine the foliowing bit positions that are to be masked. The B Control is designa-ted as the B-Field, and is genera-ted by the binar~ addition o~
the ~-Field and the ~-Field. Bit positions BO, B1, and B2 relate -to the Trailing ~it, and as will be described in more detail below, will designate the bi-t position of the Trailing Bit ~ 1, thereby indicating the ~irst bit in -the following bi-t positions in the data ~ord -that is to be masked. Bit posi-tions B3, B~, and B5 define the numerical byte posi-tion of the byte in which the firs-t bit o~ -the bit positions -to be masked will occur. As 7 ~ 1~ 3 previously described, if -the data word is selec-ted to be larger than 64-bits, an additional bit posi-tion ~6 will be required to provide adequa-te capacity to desi~ha~t~ the additional bytes.

FIG. 8 is an illus-tration of the inter-relation-ship of -the A-Field, -the ~-Field, and the B-Field. If it is assumed that the Starting Bit is -to be the fif-th bi-t in a da-ta word, that is, the 04-bit, it can be seen that the A~Field will be 0 for bi-t posi-tions A3, A4, and A5 thereby indicating the Starting Bit is in the 0-byte ~nd tha-t the binary 100 indica~es the 04-bit posi-tion. The Field ~ength for illustrative purposes is 6-bits which is binary 000110. The process of performing a binary add of the A-Field and the l,-Field results in the B-Field which is binary 001010, that is octal 12. The Trailing Bit, is the 11-bi~ position o~ the word, which is equivalent to the 1-bit position of by-te 1. From the B-Field~ it can be seen that -the first bit position of the ~ollowing bits that are to be masked are defined as the 12-bi-t position of the word~ which is equivalent of -the 2-bit posi-tion of the 1 byte ! -tha-t is -the Trailing Bit ~

FIG. 9 illus-trates a more detailed examp~e -tha-t describes writing a decimal 36-bit variable field~ith-in a data word. Ln this example, the decimal 64-bi-t 2~ word has the bit posi-tions oc-tally numbered from 0 through - 77. The Starting Bit has been selected to be ~the 6-bit in the second byte which is the oc-tal l6-bi-t position ~ of the word. This is equivalent to binary 001110 As stated, the decimal 36-bit Field ~ength is to be wri-tten, which is equivalent to octal 44 and is further equivalent -to bînary 100100. ~he addition of ~the A-Field and the ~-Field yields a binary 110010, which is the equivalent of octal 62 and de~ines the B-Field. For -this example, then, i-t can be seen that bit positions O through 15 are masked and are unchanged and are referred -to as the leading bit positions. ~he Starting Bi-t is the 16-bit posi-tion and bit positions 16 and 17 in -the l-by-te are ~7~1~313 writ-ten. Bytes 2, 3, l~, and 5 are complet~ly writ-ten.
Bit posi-tions 60 and 61 in the 6-by-te are wri-t-ten, and the Trailing Bi-t is the 61-bi-t posi-tion. ~it positions 62 through 67 in the 6-byte are masked and no-t changed, and the en-tire 7-byte is mask~ed and unchanged. The bi-t positions of the word occuring in lower order of significance from the Trailing Bit are referred to as the masked following bits. Again, -the terms "leading"~
"following" and "trailing~' are provided for poin-t of re~erence, and do no-t denote serial operation.

~ IG. 10 illustrates graphically -the Bit Ma`sk configuration for the Bit O~f`set specified as the A-Field and the rrrailing Bit ~ 1 specified as the B-Field. ~rom the example described in FI~. 9, the A-Field would be the 6-bit position of the 1-byte. The binary 110 would result in the mask bits M for the 0, 1, 2, 3, 4, and 5-bit positions. The Trailing Bit * 1 in that example was specified to,be-the 2-bit of the 6-byte. Reading down the B-Field in FIG. 10 to the binary 010 it can be seen -tha-t the mask bits M are generated for the Z, 3. 4, S, 6, and 7-bit positions. The generation of the mask fields for the leading and following bi-t posi-tions will be under timing control that will be described in more de-tail below. It will be made clear -that the Bi-t Masks are OR'ed for providing part of the ~inal merge mask bit config-uration.

FIG. 11 illustrates the Byte Mask output con-figurations for the Byte Offset por-tion of the A-Field and -the Trailing Byte speci~ied as the ~-Field. As just described with regard to the Bit Mask, bytes occurring ahead of -the Starting Bit will be masked, as will the bytes occuring following the 'rrailing Bit. These Byte Mask Bit confi~urations are also OR'ed to form -the ~inal mask con~iguration. Again, the example described with respect to FIG. 9 can be applied to the Byte Mask illus-trztion in FIG. 11, and the By-te Offset will be seen -to be a designation of the 1-byte. Reading across~ -the mask ~7~33 configura-tion will be designated by -the M indications 7 ~nd the P indication represen-ts -the Starting ~y-te which is par-tially masked as de-termined by the appropriate bi-t mask, as determined wi-th reference -to FIG. 10. In this example, then, -the O-by-te will be -to-tally masked and will comprise a Read Data By-te. The 1-by-te will be partially masked in the bit configuration previously selected, and the balance of the bytes will be indica-ted as Write By-tes. This final determination of which bytes will be - -totally written will depend upon the evaluation of theTrailing By-te.

In the example,considered, the Trailing Bit has been found to be located in the 6-by-te. ln FIG. 11, the ~-Field o~ binary 110 gives -the selection of the masking configurations for the Trailing Bits and Trailing By-tes.
For this example, the 7-byte is a Read Data By-te and is totally masked as indica-ted by the M in -the 7-bit position.
Since the Trailing Bi-t occurs in the 6-byte, -the desig-nation P indicates that it is a partial mask and -that -the 6 byte is a Par-tial Write ~ata By-te. ~he masking within the 6-byte will be under control of the bi-t mask as derived from the outpu-t of FIG. 10.

The Byte Mask selected for ou-tput are OR'ed, and in conjunction with the Bit Mask define the -total masking selections. For the variolls positions oi -the S-tarting By-te and Trailing Byte, there will be the partial masking designated b~ the P entries in the mask tables.

The writing of a full 64-bit word in either a direct word location, or offset, gives rise to a special condition that will be described in more de-tail below, it being understood that the ~-Field starts wi-th the numerical 1 and extends numerically through one full bit capacity of a memory word. This provides tha-t 63-bi-ts can be designated in the ~-Field, and leads to the condi-tion -that an ~-Field of all zeros represents a full 64-bit word wri-te, 7~1~33 ~ or systems having word capacity grea-ter than 64-bits, the appropriate number of ex-tra bytes will be added and -the masking system will be -thus expanded to accomplish the variable field par-tial write function, The detailed circuitry and timing for the generation of the Bit Mask and Byte Mask con~igurations will be des-cribed in more de-tail below.

For purposes of further reference, a Read Data Ryte, either leading or following, will be defined as a ~
byte tha-t is to be totally masked. This means that the byte will be read from the memory, totally masked, and unaltered by the partial write opera-tion. A Starting Partial ~rite Data Byte is defined as the byte in which the Starting Bit is located. A Trailin~ Partial Write Data Byte is defined as that byte in which -the Trailing Bit is located. The Starting and Trailing Partial Write Data Bytes will each contain one or more bi-ts tha-t are to be written~ and may or may not include any bi-ts that are to be masked, depending upon -the location of the Starting Bit and the Trailing Bit, respectively. ~ Wri-te Data ~ye is defined as a byte -that is to be totally wri-tten as a par-t of the variable field in partial data write operation~

FIG. 12 is a simplified block diagram of a por-tion of -the data processing system that incorporates the subject invention. The Memory System 12 includes Address' Selection circuitry shown as block 110, and is arranged for receiving the address on line 26 and the address ~ 1 on line 28. ~he Memory reads the even address word on line 30a to the Read Register ~ E 112~
The Memory reads the odd address word over line 30b to the Read Register - 0 114. ~or a reading operation, the data word stored in Read Regis-ter - E 112 is transmit-ted on line 116 to the Read Data Multiplexer 118, and the 3~ outpu-t from Read Register-0 114 is transmi-tted on line 120 thereto. ~he Read Data Multiplexer 118 func-tions -to select the appropriate addressed word for transmission on line 122 to -the Read Da-ta In-terface 124 for -transmission on line 30. The de-tails of this circui-try will not be discussed or shown in de-tail, since i-t does not add materially to an unders-tanding o~ the inven-tion. The data word stored in the ~ead Regis-ter - E 112 is also transrnitted on line 116a to the Wri-te Data Multiplexer -E 126. Similarly, the da-ta word s-tored in ~the Read Regis-ter - 0 114 is transmit-ted on line 120a as one set of input signals to -the Wri-te Data Mul-tiplexer - 0 128. --The da-ta word to~be written is transmitted from a R~questor on line 36 to the Write Da-ta In-ter~ace 130, which transmi-ts the data word on line 132 to the Input Write Data Register 134. The input wri-te da-ta word is transmitted on line 136 - E as a second se-t o~ inpu-t signals to the Write Data Multiplexer - E 126. The in-put write data word is transmi-t-ted over line 136 - 0 to the Wrlte Data Mul-tiplexer - 0 128.

When a Partial Wri-te Mode is selected, the Requestor will transmit the Bit Of~set over line 46 to the A-Regis-ter 138, and will transmi-t the Field ~ength -to the L-Register 140 over line 48, The ~-Field is -transmitted on line 142 as one set o~ inpu-t signal3 -to the Variable Field Partial Write Data Merge Mask con-trol circui-try 144. A-t -the same -time, the A-Field is -transmitted on line 146 as one set o~ parallel input signals -to Adder 148. The second set of input signals to the Adder is provided ~rom the ~-Regis-ter 140 over line 150. The result o~ ^the addition in Adder 148 is the generation of the B-Field which is transmit~ed on line 152 as the second set o~ controlling input signals -to the Y~M 144, The VFM also receives control signals on line 50 ? and a Partial Write Control signal on line 44. The VPM ~unctions -to genera-te mask signals-and con-trol signals on line 154 as a third set of input signals -to -the Write Data Multi-3~ plexer - E 126 and results in the selection of -the Read Data bits that will be masked and the bit posi-tions that will be writ-ten pursuant to Data Bi-ts s-tored in the Input ~l~'7~ 33 Write Data Regis-ter 134. The selected bit configuration is -transferrecl on line 1~6 -to -the ~ri-te Regis-ter - E 158 which in -turn stores the merged word in the Memory 12.
Similarly, -the VFM provides mask signals and control signals on line 160 as the third set of inpu-t signals to the ~ri-te Data Multiplexer - 0 128. These mask signals and control signals selec-t the Read Data bits that will be masked and returned -to -the memory unaltered, and select the inpu-t data bits that will be written.
The bit con~iguration thus genera-ted will be transferred on line 162 to the ~rite Register - O 164, and wili~i-in turn be transferred -to the`Memory 12 ~or s-torage.

Before prbgressing -to descriptinns of the detailedA~circuit operations, the control signal and timing signal arrangements will be described. FIG. 13 illustra-tes the varicus control and timing signals util-ized in the functioning of the VFM. The sequence of the VFM is activated by the occurence of the Enable signals, labeled ENB~. The control signals and timing signals illustra-te signal relationships, and are not related -to speci~ic time intervals, it being understood that -the precise time intervals will depend upon the selec-tion o:~
the circuitry utilized to implemen-t the VFM. Fur-ther, the specific timing will rela-te to the timing o~ the requesl.or and -the memory system.

As pre~iously mentioned, -the genera-tion of the mask signals is divided in-to two portions. The first portion involves the evaluation o~ -the position of the Starting ~it in the address word, and -the determination of the mask signals that must precede the ~-tarting Bit.
The generation of these mask signals will be genera-ted in -the A portion of the VFM sequence. The mask bits that are gene-rated to follow the Trailing Bit are gen-erated in the ~ port~on of the ~M sequence. Since the sequence is divided, the control signal AB Select, labeled AB SEL, illustra-tes the division of -the V~ cycle for providing the A and B control functions.

As men-tioned previously, -two da-ta words are read from the memory yielding an odd addressed word and an even adclressed word, ~ince -the words are addressed in a binary code, the leas-t significan~ digit in the address will indica-te whether ~he address is odd or even.
This will de-termine which of the words should be ini-tially accessed. The least slgnifican-t bit position of -the address, labeled ADR~ 0, will provide a pointing func-tion to select which of the words will be referenced ini-tially, If the least significant bit is a binary 0, the even addressed word will be ini-tially selected, and if a binary 1, -the odd addressed word will be selected.

Sillce a word boundary crossing can occur, an additional control signal for switching the word selection must be utilized, This con-trol signal is the Word Select, labeled WD SEL. In the single word refer-ence situation, wherç a word boundary crossing does not occur, -the Word Select will correlate to the leas-t sig-nificant bit value in -the address, For those si-tua-tions where a word boundary crossing occurs, tha-t is when a carry is generated ~rom the adder, or when the B-Field is 0, the ~ord Select signal will be toggled.

The balance of the signals illustrated in FIG.
13 are timing signals, Table I defines the timing symbols illustrated.

T,...... ..,.... ,,... ~I~ING 0 BT..,,,..,.,..,,BIT
BY.,,,,,.~,,,...BYTE
A,...,.,..,...,,LEADING
BTA..... ,.,.~....... ~EADING 0 T0 7 BIT MA~K
BYA............ ..... LEADING 0 T0 7 BYTE MASK
B.............. ..... TRAILING
BTB~ o~TR~I~ING 0 T0 7 BIT MASK
BYB,.,.. ,........... TRAILING ~ T0 7 BYTE MASK

AB..... ~....... .~EADING OR ~RAIL~NG PER ~B SEL.
BTAB... ~....... ~EAD:LNG OR TRAILING 8-BIT(S) BYAB... ... LEADING OR ~RAILING BYTE

M~....... MASK

TAB~E I

During the A portion of the VFM cycle, -the S-tarting Partial Wri-te Data Byte is evaluated for loca-tion o~ the `~
Starting Bit and the location of the S-tar-ting Byte~ To this end, TB~ provides -the timing signal during which the Starting Byte is identified, and TBTA provides the ` timing during which -the Starting Bi-t is located, and the leading bits are masked.

Following -the Starting Bi-t loca-tion, the TBYAB
and TBTAB signals are generated during the A por-tion of the VFM ~ycle. The TBYAB signal causes the 1eading Read bytes -to be masked and the TBTAB causes the leading bi-ts to be masked. At the swi-tching of -the AB Select in-to -the B portion o~ -the VFM cycle, the circui-try swi-tches to evaluate the.trailing bits that are to be masked.

The T3YB signal provides timing :Eor -the eval-ua-tion o~ the Trailing Partial Wri-te Da~ta ~y~te, and the TBTB signal provides timing o:~ the loca-tion of the Trail-ing Bit.

. During the occurence of the TBYAB and the TBTAB
signals during the B portion of the cycle, the Trailing Read Bytes and -the bi~s. ~ollowing the Trailing Bi-t are masked, FIG. 14a~-through FIG. 14 , when arranged as sho~n in FIG. 14, comprise a block diagram of the variable field partial write data merge mask system and input controls. ~lements that have been previously descri.bed will bear the same reference numerals, .

_ ~ ~ 7 ~ ~ 3 _26_ The A-Field is stored in -the A~Regis-ter 138, and the Field Leng-th is stored in -the ~-Regis-ter 140.
The ~equired inpu-t signals ~or generation o~ the Bit Mask for the Star-ting Bit is per~ormed by -the Starting Bit -5 Decoder/Translator 200. It receives -the ~0 signal on line 142-o, the ~1 signals on line 1~2~1, and the A2 signal on line 142-2. The ~nable signal is applied on line 202~
and is fed on line 202a to the Starting Bit Decoder/Trans-lator 200. This circuit 200 functions to decode ~he three bit input specifying the Star-ting Bit to a signal on one-of-eight possible internal lines. The circuit 200 then ~unctions -to translatè this decoded signal and apply it to all subsequent outpu-t lines. Thus, for -the ~tarting Bit translation, all of the subsequent bits will be identified as bi-ts to be written. Conversely, all bits not selected will be bits that are subject to the leading masking func-tion. The Starting Bit~Decoder/Trans-lator circuit 200 provides output lines labeled BTA0, BTA1, BTA2, ~ , BTA~, Br~A~, and BTA6, all of which are applie~
to the Bit Mask circui-try 204.

The contents of -the A-Register 138 is applied as a parallel input on line 146 to Adder 148. The con-tents of the ~-Regis-ter 140 is applied on line 1~0 as the other set of inputs to Adder 148, As previously described, the result of this addition produces -the B-~ieldl and bits B0, B1, and B2 are represen-ta-tive of the Trailing Bit ~ 1 and are applied on lines 1S2-0, 1~2-1, and 152-2~
respectively, to the Trailing Bit Decoder/Translator 206. ~r This circuit 206 also functions~to decode -the three bi-t input to one-of-eigh-t internal lines, which in turn are translated such that the selected line and all subsequen~
output lines are activated, It pro~ides output signals BTB0, BTB1, BTB2, BTB3, BTB4, BTB5, BTB6, and BTB7 which are all transferred to the Bit Mask circui-try 204. In this configuration, then, it can be seen that the ident-ification of the Trailing Bit ~ 1 and all subsequen-t bi-ts will be identified for masking, which in turn will identify the preceding bi-ts for wri-ting. The speci~ic .

~-- 3~1~7~ 3 circuit configuration and opera-tion :Eor Deooder/Trans-lator circuits 200 and 206 will be described in more de-tail below.

The TBTA signal is applied on line 208, TBTB
is applied on line 210, and TBTAB is applied on line 212 as timing control signals to the Bit Mask circuitry 204, During time TBTA, the decoded and translatecl ou-tpu-t sig-nals from the Starting Bit Decoder./Trc-mslator circuitry --. ~
ZOO are utilized to select the appropriate output lines for establishing. the bi-t mask condition. The outpu-t signals are applied on thè mask ou-tpu-t lines identified as MBTO, MBT1, MBT2, MBT3, MBT4, MB~5, MBT6, and MBT7.
The mask bi-t signals are applied to like-~ordered stages of a pluralit~ OI 8-bit latch circuits, each of v.hich are associated with a specific byte in -the Word O and ~tord 1.
Only three of -the eigh-t latch circuits utilized for ~lord O are shown, with Byte O ~atch - O labeled 214, :By-te 6 :Latch O labeled 216, and Byte 7)Latch - O labeled 218.
The latch circui-ts fGr bytes 1 through 5 o:E the Word O
are similarly arranged but are no-t illus-trated. Similarly, only three of -the -8--bit latc~es :Eor Word. 1 are shown, wi-th Byte O :La-tch - i.labeled 220, By te 6 Latch - 1 labeled 222 J and By-te 7 Latch - 1 labeled 224, wi-th b~tes 1 through 5 of W~rd 1 no-t illustrated, Each o:E -these 8-bits~
latch circuits are selected :~rorn circui-ts available commercially, and function such tha-t vrhen an enable signal is applied, it will receive and -sto~e the se-tting si`gnaIs.
applied there-to. The circuit functions to provide the stored signal combina-tions on the output terminals, which Ior Word O would be the 6l~ lines collectively referenced as line 154, and for Word 1 would be the 64 lines collect-ively ref~erenced as output li.ne 160. The Enable signals utilized to ac-tivate the various la-tch circuits are derived from the By-te Mask circui-try 226 which will be described in more detail. below.

I-t. can be seen, then, that during -time TBTA, that -the Bit Mask circui-try 204 pro~ides the appropriate 7~

_28_ mask bi-t con~igura-tion for -the S~tartin~ Bi-t and applies -the bit configuration to all -the la-tches. The par-ticular latch -that will be se-t will be de-termined by -the appro- -priate enable received from the evaluta-tion o~ -the byte selection. In the A portion of -the cycIe, the applica-tion of TBTAB on line 212 results in -the Bi-t Mask circui-try 204 switching to provide masked bi-ts on all ou-tpu-t lines for application to the 8-bit latches, ~or se-tting the mask configurations for all full Read Bytes, that is all leading bytes -that are not to be written.

During the timing pulse TBTB, which is applied on line 210, the Bit ~ask circui-try 204 responds to the output signals from the Trailing Bi-t Decoder/Translator 206 and functions to set up the mask bit configura-tion for the Trailing Bi-t. These mask signals are again applied -to all like-ordered bit posi-tions ~or all o~ the latch circuits, and the latch -that is appropriately enabled will be set to the mask con~igura-tion es-tablished for the Trailing ~it. During -the B por-tion o~ the cycle, the Bit Mask circu;try 204 will be swi-tched to provide 8 bits of mask output and will be applied -to the la-tches which will select and se-t -the mask configuration ~or all Trailing Read Bytes.

It can be seen, then, that -the g~neration of Bit Mask signals is independent o~ -the word selection.
The special case of a Starting Bit and a Trailin~ Bit occu-rring in the same byte will be described below.
, ' ':
-The evaluation of the S-tarting Byte and Trailing Byte invo]ves the evaluation of the Byte Offset comprising 3o the A3, ~4, and A5 bit positions o~ the A-Register 138, and the Trailing Byte portion o~ the B-Field a-t -the ou-tput o~ the Adder 148, comprising bits B3, B41 and B5. The Starting/Trailing Byte Decoders/Translator 230 receives input signals from the A-Register 138 on lines 142-3, 142-

4, and 1~2-5, and from the Adder 148 on lines 152-3, 152-4, and 152-5. I-t also receives the ~B Selec-t signal on line -:~Ll 71~83 2320 The By-te Decoder/Translator 230 func-tions based upon the s-ta-tus o~ -the AB Select signal -to ei-ther decode the Byte Offset received from the A-Regis-ter 138 or -the Trailing By-te designation received from the Adder 148.
Accordingly, i-t functlons as 2 3-bi-t decoder -to select one of the eigh-t possible condi-tions speci:~ied in these alternative cases. It f'unc-tions f'urther -to -transla-te -the decoded signal to provide the outpu-t signal on -the ~el-ected line 'together with all o-ther subsequen-t output lines, It pro~ides true outpu-t signals on lines labeled consec-utively BYQ through BY7 and complementary ou-tput signals on lines labeled BY0 -through BYo.

The BTB0 signal is applied on line 234 as one of the input signals,~and the Byte Decoder/Translator 230 also provides the ou-tput signals A Selec-t on line - 236 and the B Select on line 238.

During the A portion of' the cycle, as indica-ted by the presence of the A Select signal and during timing pulse TBY~, which is received on line 240, -the By-te Mask circui-try 226 establishes ~the byte in which the Starting Bit occurs and provides the approprnate outpu-t ~or enabling the S-tarti.ng By-te latch se-tting. Dul~ing -the occurence of the -timing signal TBYAB which is recei~ed on line 2~2, the By-te Mask circui-try enables all o~ -the leading lines ~or causing the Read Bytes to be masked. During the B
portion of' the cycle, as established by B Select signal, the timing pulse TB~B, recei~ed on line 244~it enables the appropriate latch circuit for establishing the bit mask configuration for the ~railing Byte. Upon the occurence f TBY~B during -the B portion of' the cycle, all of the following Read Bytes will be enabled and the -total masking -thereof will be accomplished by application of' the outpu-t signals f'rom the Bit Mask circuitry 204.

The Byte Mask circui-try 226 is adapted for controlling -the latches tha-t are applicable both -to -the word 0 and word 1. To ef'~ec-t this con-t:roll -two additional .

- 3~
con-trol signals are necessary, which are -the Word Selec-t 0 signal received on line 246 and -the Word Selec-t 1 signal received on line 248, The Byte Mask circui-t 226 output signals directed to control Word 0 are iden-tified as MBY00 through MBY07, and the mask ou-tput signals to con-trol the ~ord 1 la-tches are iden-ti~ied as MBY10 through MBY17.

The Single Byte Partial Wri-te De-tec-tor and -Word Select 250 func-tions to de-termine whe-ther there is to be a Sin.gle By-te Write, indicated by the SBY signal on line 252 or whether there is to be a ~ul-tiple Byte Write indicated by the MBY signal on line 254. I-t also ~unc-tions to perform the word selection by providing the Word Select 0 signals on line 246 and the Word ~elect 1 signal.on line 248. During -the word boundary crossing, as will be described in detail in the consideration of the detailed circui-try, Word Select circuitry 250 will function -to toggle the word selection during the B portion of the variab~e write cycle. The ini-tial word selec~tion resul-ts from an evaluation of the least significant bi-t position of -the address, received as an inpu-t si.gnal on line 256. When -the least significan~t bi-t position is 0, Word 0 is selected, and when -the leas-t significan-t bi-t is 1, Word 1 is selected.

The word boundary crossing will occur when a Carry signal is provided by Adder 148 on line 258. It will be recalled that it is a system requirement ~tha-t the Starting~Bit occur in the addressed word. When the add-ition of the Field ~ength to the Bit Offset results in the Carry being genera-ted, it indicates that the Trailing Bi-t extends beyond decimal 64 bits, hence occurs in the àddress + 1 word. ~he Word Select 250 also receives the input from the L-Register 140 on line 260, and includes circuitry to detec-t when the con-tents of -the ~-~egister is 0. ~s previously mentioned~ the selec-tion of a full 64-bi-t variable wri-te field will result in stages I.0 through ~ being 0. Therefore, i~ -there.is any displace-~ 7~ ~ ~ 3 men-t o~ -the S-tar-ting Bit, the variable field will ex-tend in-to the next word and -there will be a wordboun~ary crossing. The selec-tion of the -time for -toggling ~the word selection is accomplished by utiliza-tion of the AB Select signal received on line 232a.

~or purposes of evaluating whether the variable ~ield occurs wi-thin a single by-te, or extends over multiple bytes, -the ~ingle Byte Par-tial Write Detector circuitry 250 receives -the inpu-t signals from -the A-Register -_ 138, wherein A3 is received on line 142-3a, A4 is received on line 142-4a, and A5 is received on line 142-5a. It also receives signals from -the B-Field, and receives the signals ~rom stage B3 on line 152-3a, from B4 on line 152-4a, and ~rom B5 on line 152-5a. These inpu-t signals 1~ from the A-Field and ~rom the B-Field are evaluated, and if i-t is de-termined -that bo-th the Starting Bit and -the Trailing Bit are situated in the same byte, the S~Y signal will be generated on line 252, When i-t is de~termined tha~t -the ~~tarting Bit and the Trailing Bi-t occur in different by-tes, the MBY signal will be genera-ted on line 254. These signals SBY and MB~ are u-tilized in the Bit Mask circui-try 204 for controling -the genera-tion of -the bit masks.

Having described the system operation in block diagram ~orm, and having discussed the inter-relationship ~ -the con-trol signals, the timing signals, and the field selections, a-tten-tion will be directed to the discussion and description o~ the detailed logic block diagr~s utilized in the implementation of the pre~erred embodimen-t of -the subject invention. In the logic block diagrams, the various blocks are representative of circuits that are available commercially for performing the logical functions, The flag representation indicates -the dlrec tion o~ data and control .flor~. For purposes of defini-tion, a binary 0 is represented by a lo~ signal, hereinafter 3~ referred -to as ~, and a binary l is a high signal, herein-after referred to as an H signal. The logic symbols utilized in the detail logic block diagrams will be ~lt7~8~

described.

FIG. 15 is the logic block symbol for a ~ow AND circuit wi-th the input signals denoted X and Y. The - true ou-tput terminal is identi~ied as T, and the comple-ment output as C. This circuit will provide a low signal on the T ou-tput when X and Y are both low. This condition will resul-t in a high signal on the C ou-tpu-t. I~ either X or Y or both X and Y are high, the T ou-tput will be high and -the C output will be low.

FIG. 16 is the logic block diagram of a Low OR circuit having input terminals designa-ted as X and Y
and the true output terminal designated T and the comple-ment of it designated C. This circui-t will provide a lo~Y signal on -the T ou-tput when either X or Y or both X
1~ and Y are low. When both X and Y are high, the T ou-tput will be high and the C output will be low.

FIG. 17 is the logic block diagram ~or -the High OR circuit tha-t provides a high signal at the T output -terminal when either or both X and Y input signals are high. The circuit provides a high ou-tpu-t signal at the C outpu-t terminal when both X and Y are low.

FIG. 18 is -the logic block diagram s~llbol o~ ~n Inverter-circuit having input ~ and ou~tpu-t -terminals T and C~ When a low input signal is applied at ~, the True ou~tput signal will be low ~nd the C ou-tput will be hi~h.
When the input signal is high, the T~output will be hi~h and the C output will be low.

FIG. 19 is the logic block diagram symbol ~or an Exclusive-OR circuit having-input signals X and Y with output signals T and C. This circuit operates to provide a low output signal at the T output terminal when either X or Y is high. When X and Y are both low or both high, the T outpu-t signal is high and the C outpu-t signal is low.

~ ~t~ 3 ~33~
FIG. 20 is a logic block diagram symbol for a combined OR and AND circui-t. In this con~igura-tion, each of the AND circui-ts a-t -the inpu-t is coupled to one of the OR inpu-t terminals, but the connection is not illus-tra-ted. The le~-t-most AND circuit receives input signals A and B, the center AND c~rcuit receives input signals C and D, and the right-most AND circui-t receives signals E, F, and G. ~ach of -the AND circuits is a ~ow AND circuit of the type previously described, and requîres low input signals on all of the respectively associa-ted input terminals in order to provide a low ou-tput signal to the OR circui-t. In operation, -then, -this circuit will provide a low signal at -the T output terminal when any or all of the AND circui-ts are sa-tis~ied. Conversely, a high input signal to any line of any AND circuit will disable tha~ AND circuit, and when all AND circui-ts are thus disabled, the OR circuit will provide a high output signal on the T output terminal and a low ou-tput signal on the C output terminal.
.
From the foregoing discussions, -then, it can be seen that the ou-tput terminal flag represen-tation is indicative of ~the anticipa-ted true inpu-t signal combin-ations for the element. These open and closed ~lag representations are intended as an aid in -the understanding 2~ 0~ the detailed logic, and are not intended as a limi-t-ation on the inven-tion or -the ~type of circuitry -that can be u-tilized ~or the embodiment of the inven-tion.

With the foregoing descrip-tion of the logic elements utilized in the implementa~tionj when ~taken in view of the description of the general systems operation, those skilIed in -the art will be readily able to trace through various combinations of events in the detailed logic that will be described. Not every possible combin-ation will be described in detail, since it is ~elt that this will no-t add appreciably to an unders~tanding of the invention.

_3L~_ FIG. 21 is a de-tailed logic block diagram of -the Single Byte Par-tial Wri-te ~etec-tor and Word Selec-t circui-try, and is shown enclosed ~ithin dashed block 2~0.
The word selec-tion is ini-tially de-termined by the least significant bit posi-tion of the address, which is received on line 256 by Inverter 300. ~ pair of XOR circuits 302 and 304 provide the selection signals for -the Word O and Word 1. ~he true output terminal of Inverter 300 is coupled by line 306 to one of the input terminals of XOR
circuit 302, and the complement output terminal is coupled ~-by line 308 to XOR circuit 304, When the least signif-icant address bit is 0, -thereby indica-ting the selection of Word O) a low signal is applied on line 256 which results in a low signal being applied on line 306 and a high signal on line 308, During the ~ portion of the cycle, -the B Select signal on line 232a will be absent, thereby providing a high signal -to AND circuit 310. ~his high signal will result in a low outpu-t signal on line 312 which is applied to XOR circuits 302 and 304. In -this configuration, then, it can be seen tha-t XOR circuit 302 has low input signals applied -to both i.nput terminals resulting in the exclusive OR function not being made with a high signal at its true output termi.nal and a low signal generated on line 246 thereby providing the enable condition for Word Select 0. The combina-tion of low and high signal on -the inpu-t terminals of XOR 304 sa-tis~ies the exclusive OR condition, and it provides a low signal at its true output terminal and a high signal on line 248 at its complement output signal, thereby inhibiting the selection of Word 1 by the high signal on -the Word Select 1 l.ine~ When the B Select signal is applied on line 232a during the B portion of the cycle, and presuming the other input terminal tQ AND circuit 310 is receiving a low signal, AN~ 310 will be switched ~nd will prc-vide a high output signal on line 312. This high si~nalis a~plied to XOR circuits 302 and 304, and results in the reversal of a polarity on output lines 246 and 248 thereby affectively toggling the word selection lines.
If the east significant bi-t posi-tion of the address is - ~ ~ 7 ~ ~ 8 ~35~
initially a binary 1, thereby indica-ting -the selection of the Odd ~ddress Word, the signals levels on lines 306 and 308 will be reversed, and for -the same basic inpu-t conditions, the low signal will be genera-ted on Word Select l output terminal 2~8 and -the high signal will be generated on Word Select O outpu-t select line 246.

The further effect of toggling the word selection involves the determination o~ exis-tence of a Carry signal out of the Adder, as applied on line 258 to OR circu;t 314. When a Carry signal is presen-t, there will be a high signal on line 258 which will cause OR circuit 314 to provide a low signal on line 316 -to AND circuit 310.
Thus, when the .B Select signal is present on line 232a, AND circuit 310 will provide a high signal on line 312 thereby toggling the word selection as previously described.
The true output terminal of OR circuit 314 is u~tilized in the determination of Single Byte Wri-te or Mul-tiple Byte Write by AND circuit 318, by -the application of a true output signal on line 320 thereto. When -the Carry signal is present, OR circui-t 314 will be:provîding a high out-put signal on line 320 which will ef:~ec-tively block AND
circuit 318, and will resul-t in a low output signal on line 254 indicative of the Multiple Byte Write condi-tion.
This also results in the ou-tput si~lal SBY on line ,252 being disabled.

As previously described, i~ -the l-Field is -totally 0, it indicates -that there i~ a full 64-bit word to be written, and when there is any Bit Offset will result in the necessary toggling of -the ~ord selection. It is unders-tood that i~ there is a full word write without Bit Offset, this circuitry is activated such that there is a normal memory wri-ting operation on a word-for-word basis at -the address specifiedD When a Bit Offset is specified and there is to be a full 64-bi-t word, posltion ~0 through ~3 are provided on line 260a as inpu-t signals to ~ND
circuit 32~, and when all are in the binary O state will provide a low signal on line 326 as one o:f -the input 7~33 signals to AND circuit 328. Positions ~4 and ~5 o~ -the ~-Field provided on line 260b as input signals to ~ND
circui-t 328. When all are indicating a binary ~, a high signal will be provided on line~330 as an input signal -to OR circuit 314. Therefore, i-t will be deterrnined that a low signal will be provided on line 316 causing AND
circuit 310 to toggle the selection on line 312, while at the same time providing a high signal on line 320 for effectively determining that there is -the MBY condition present. From the foregoing detailed description, then~
it can be seen tha-t a system for word selection for word boundary crossing has been~described for a 64-bit word - configuration. In the event that it is desired to expand the system -to provide for memory words having capacity 1~ up to 128-bits, it is necessary to add the 6-bi-t position to the A-~ield, -the ~-Field, and the B-Field, as pre-viously described. This expansion would resul-t in the L6 signal being applied on line 260c to AND circuit 32 and -the circuit would function as previously described.
In the word selection circuitry, the Word Select O signal would be applied on line 246a as input signals -to AND
circuit 332 for selecting -the O through 63 bit positions of the Even Address Word by the signal on line 246U, and to AND circuit 334 for sélecting -the bit posi-tions 64 through 127 by the signal on line 246~. Similarly, the Word Select 1 signal applied on line ~48 would be directed on line 248b to AND circuit 336 for selec-ting the bi-t positions O through 63 of the Odd Address Word by the out-put signals on line 248U, and to AND circuit 338 for selecting the 64 thr~ugh 127 bi-t positions by the output signal on line 248~. The A6 signal received on line 142-6a is applied on line 142-6a1 to Inverter 340 which responds thereto in making the word selection.

~he selection o~ SBY condition or the MBY
condition is accomplished by XOR circui-ts 350, 352, and 354, for the 64-bit da-ta word r and with the addition of XOR circuit 3~6 ~or expansion to the 128~bît word format.
The XOP~ circuits are adapted to be responsive -to like-~7~

ordered bit posi-tions o~ the A-Field and ~the B-Field and each functions -to provide a low signal to AND circui-t 318 when the associated bi-t posi-tions are equal, Any comparison of like-ordered bit psi-tions resul-ting in a difference will resul-t in AND circuit 318 being blocked, and the MBY condition will be selected with a low slgnal on line 254, In this regard, XOR circui-t 3~0 receives the A3 and the B3 signals on line 142-3a and 152~3a respectively. When both signals are high, or both signals are low, the exclusive OR condition is not satisfied and the out~-t signal on line 3~8 will be low. When the signals dif~er, the XOR circuit will provide a high signal on line 358 thereby indicating -the MBY condi-tion.
In a similar manner XOR circuit 352 evaluates the A4 and B4 bits received on line 142-4a and 152-4a, respec-tively;
and provides the output signal on line 360. XOR circuit 354 evaluates -the A5 and B5 bit positions received on lines 142-5a and 152-5a respectively, and provides i-ts output signal on line 362. For the 128-bit position data word alternative, XOR 356 will evalua~e -the A6 and B~ signals received on lines 142-6a and 152-6a, respec-t-ively, and provide its output signals on line 364. When all of the XOR circui-ts 3~0, 352, 354, and 356 if used, provide low output signals indica-tive o~ equali-ty o~
like-ordered bit pos;tions, AND circuits 318 will be satis~ied and -the SBY condition will be selec-ted, thereby indicating that all o~ the wri-ting occurs within a single byte.

FIG. 22a through 22 , when arranged as shown in FIG. 22, comprise the detailed logic arrangement ~or the Starting Bit Decoder/Translator 200, the Trailing Bit Decoder/Translator 206, and the Bit MasX circuitry 204~

- The Bit Offset is decoded by AN~ circuits 380, 382, and 384. ~ND 380 receives AO inpu-t signal on line 142-0, AND 382 receives the A1 inpu-t signal on line 142-1, and AND circuit 384 receives A2 on line 142-2. The true ~ ~7~
_38_ and complement ou-tpu-t terminals from -these deco~er AN~ circui-ts are utilized as input signals -to the Transla-tor por-tion o~ the circuit, which is comprised o~
AND circuit ~0 labeled 386, AND circui-t A1 labeled 388, AND/OR circuit A2 labeled 390, INV~RT~R A3 labeled 392, ~ND/OR circuit A4 labeled 394, OR circui-t A5 Iabeled 396, and OR circilit A6 labeled 398. The true output terminal of ~ND 380 is couoled by line 400 as one of the input signals to AND ~0 386, to AND/OR A2 390, and to AND/OR
A4 394. The co~iplement ou-tput terminal o~ AND 380 is coupled through line 402 to OR A6 398, The true output terminal o~ AND 382 is coupled by line 404 as an input to AND AO 386, to AND A1 388, to AND/ORs A2 3~0~ and A4 394.
The complement output terminal of AND 382 is coupled through line 406 as an input to OR A5 396 and OR A6 398. The true outpu-t terminal o~ ~ND 384 is coupled through line 408 -to AND ~0 386, AND A1 388, AND/OR A2 390, INVER~ER A3 392, and -to AND/OP~ A4 394. The complementary output of ArJD 384 is coupIed t.lrough line L~lo as an input to OR As 396 and to OR A6 398. The Enable signal is applied on line 202a as an enabling input to -the decoder AND circui-ts 380, 382, and 384.

For purposes o~ example, one sample Bi-t O~fse-t will be applied to the circuitry. Assuming a Bi-t O~ se-t 2~ o~ six, which is a binary 110, lt will be seen -tha-t AO
will be low7 A1 will be high, and A2 will be high. Since a ~eading Bi-t is being decoded, -the results o~ the trans~
la-tion should result in positions 6 and ~7 lndicating the write condition, and positions O through 5 indicating the mask condition. If the ~eading Bit occurs wi-thin the byte, the 7-bit position must necessarily be written and will be forced -to the write condition withou-t decoding or translation. ~onsidering the 6-bit posi-tion pursuant to the control o~ OR ~6 398, it will be seen tha-t the signal 3~ on line 402 will be high, the signal recei~ed on line 41 will be low, and the signal received on line 406 will be low. This circuit opera-tes such that a high signal on any input terminal -~ill result in a high signal on -the com-plement output and will be indicative -tha-t the wri-ting condi-tion exists, hence -the signal designation -~TA6.
Next considering the 5-bi-t position, as controlled by OR A5 396, i-t will be seen that -the signal provided on line 410 is low and -the signal provided on line 406 is low thereby providing a low signal BTA5, and will be indicative -tha-t a mask condition exists. The 4-bi-t posi-tion is under control o~ AND/OR A4 394, which for this example will receive a low signal on line 400, a high signal on line 404, and a high signal on line 408. It -~
will be seen -that neither of these input AND circuits is sa-tisfied, resulting in a low ~ signal resulting in the 4-bi-t position being masked. The 3-bi-t posi-tion will be de-termined by INVERTER A3 392, which receives a high signal on line 408 resulting in a low output signal BTA3.
The 2-bit position is determined by AND/OR A2 390 which receives a high signal on line 404, a high signal on line 408, and a low signal on line 400. Nei-ther of the input AND circuits is satis~ied, resulting in a low output sig-nal BTA2. The 1-bi-t poaition is con-trolled by AND A1 388, which receives a high signal on line 404 and a high sig-nal on line 408, resul-ting in a low output signal BTA1.
The O-bit position is de-termined by AND AO 386, which receives a high input signal on line 408, a high input signal on lir.ellO4, and a low input signal on line 400, resulting in a low output signal BTAO. For this example, then, it can be seen -tha-t bit position 7 will be forced to the write condition, the 6-bit po~ition has generated a high signal indica-tive of -the w~ite condition, and bi-t positions O through 5 provide the low output signals in-dicative of -the mask condition. Not every combination o~ Bit Offse-t will be described, since those skilled in the art can apply -the -rarious signal combinations -to the illustrated circui-try to achieve the desired results, The Trailing Bit Decoder/Transla-tor 206 described in block diagram ~orm in FIG. 14, is comprised o~ -the decoder AN~ circuit ~20, ~22, and ~24, which recei-re BO
on line 152-0, B1 on line 152-1, and B2 on line 152-2 ~o respec-tively; and the translator circui-ts comprising AND BO 426, ~ND Bl 428, AND/OR B2 ~30, INVERTER B3 432, ~ND/OR ~4 434, OR B5 436, OR B6 438, and INVERTER B7 440.
The Enable signal is applied on line 202a to all o~ -the decoder AND circui-ts 420, 422, and 424 and directly to the INVERTER B7 ~40 resul-ting in the low output signal BTB7. The true output s-~On~l from AND 420 is applied on line 442 to AND BO 426, A~D/OR B2 430, and AND/OR B4 434.
The complementary output signal is applied on line 444 ~o OR B6 438. The -true output signal from AND 422 is applied on line 446 as ~n input to ~ND BO 426, AND Bl 428, AND/OR B2 430, AND,/OR B4 434. The complementary outpu-t signal is applied on line 448 to OR B5 436 and 0~ B6 438.
The -true output signals ~rom AND circuit 424 is applied 1~ on line 450 as an input signal to AND BO 426, AND Bl 428, AND/OR B2 430, INVERTER B3 432, Qnd AND/OR B4 434. The complementary output signal is applied on lin~ 452 as an input to OR B5 436 and OR B6 438.

Applying the example of the Trailing Bit described in combination with FIG. 9, wi-th the Trailing Bi-t occurring in the l-bit posit~on, there should occur high signals ~or the O-bi-t and the l-bit posi-tions indicating writing of these two bits, wi-th low signals ~or bit posi-tions 2 -through 7 indica-ting the mask condition. The result of adding the A-F:ield and -the L~Field results in -the gener-ation o~ the Trailing Bit ~`l in -the B-Field. This will resul-t in the binary OlO being applied as BO, Bl, and B2 respectively. Considering the bit positions in order, it will be seen that the high signal on line 446 will cause AND BO 426 to provide a high outpu-t signal BTBO and AND
circuit Bl 428 to provide a high output signal BTB1, ~or the O-bit and 1-bit positions respecti~ely. For the 2-bit position, the low sign~l applied on line ~50 Qnd the low signal applied on line 442 will res~ t in AND/OR B2 430 providing the low output sîgnal ~TB2~ The low signal applied on line 450 to INVERTER B3 432 will result in the low outpu-t signal BTB3. Similarly, the low signal applied on line 450 to AND/OR B4 434 will cause it to provide -the low output signal BTB4. For -the 5-bit position, the high signal applied on line 452 -to OR B5 will result in it providing the low ou-tpu-t signal BTB5.
Similarly, -the high signal applied on line 452 to the OR B6 438 will resul-t in i-t providing -the low output signal ~TB6. As previously mentioned, the Enable signal causes INVERTER B7 440 to provide the low outpu-t signal BTB7. Further examples of the func-tioning o~ -the cir-cuitry can be readily traced through by -those skilled in the art1 and a-~l possible combinations w~ll no-t be des-cribed in de-tail.

F~om the description -thus ~ar provided~ it can be seen that the decoding and transla-tion of the ~eading Bit and the Trailing Bit ~ l are available substantially simultaneously. The actual ge~eration of the bi-t mask configuration will be-under control o~ ~the timing and control pulses previously ~entioned.

The Bit Mask circui-try 204 described in block form in FIG. 14 is comprised o~` AND/OR circui-ts 204-o, 204-l, 204-2, 204-3, 204-4, 204-5, 204-6, and 204-7.
Each o~ ~these bi-t mask circuits is adap-ted wi-th -three inpu-t AND circui-ts, with the le~t-most AND circuit u-til-ized to genera-te -the ~eading Bi-t mask configuration, -the cen-ter AND circui-t u-tilized -to generate -the 8-bi-t Read Byte mask conditicn, and the righ-t-mos~t AND circui-t u-til-ized to generate the Trailing Bit mask configuration.
~hese circuit arrangements are identical with -the exception of the 7-bit position which does not utilize any inpiAt signals ~or the left-most AND circuit. This absence of a signal results in the output signal MBT7 being forced -to the high outpu-t condition indicating the write condition during the e~aluation of the ~eading Bit as pre-vîously described, each of the output lines MBTO through MBT7 are utilized to drive like-ordered bit positions of all of the 8-bit latches 9 -the latches selec-ted for operation being dependent upon -the byte masks.

The ~enera-tion o~ -the bi-t masks occurs for both partial word write and ~ull word wri-te. When the Bi-t Offse-t is zero and a full word is specified in the L-~ield, the addressed word will be writ-ten, and the en-tire address ~ 1 word will be masked. The par-tial word wri-te bit mask generation occurs in -two steps if the ~ield to be written does not all occur in a single by-te. For the field to be written in a single by-te, -the -timing and control is such that the bi-t mask is generated during -the B
phase, as will be described in more de-tail below.
It will be recalled ~rom the pre~ious discussion tha-t the ~BY signal will be low only when A3 and B3 are identical, and A~ and Bl~ are identical, and A5 and B5 are identical. If ~there is difference in any bit position, 1~ the field to be written extends beyond a single byte.
Then the SB~ signal will not occur and -the~MBY signal will be generated for control. The timing~controls are provided by AND/OR 466 which controls -the timing during the A portion of the cycle, line 476 which controls the timing during the B phase o~ the cycle, and line 212 which controls thè A or B timing for -the generation o~ masks for the Read Bytes. When -the MBY signal on line 254 is low~ and -the TBTA signal on line 208 is low, the outpu-t ~rom circuit 466 on line 472 will 2~ be low, thereby enabling all o~the le:~-t-mos-t AND circui-ts of -the Bi-t Mask circuit 204--o through 204-6, -thereby allowing -the generation o~ the ou-tput signals MBTO through MBT7 in response to the applied input signals AO, A1, and A2. In the event that the MBY signal is high t thereby - indicating that it is not a multiple byte write operation, there will be deactivati~n o~ ~the associa~ed AND circui-t, and the Bi-t Mask circui-ts will be inoperative durîng -the A portion o~ -the timing c-ycle. This is necessary since the ~eading Bi-t and Trailing Bit will be in the same byte, 3~ such that the mask must be generated simultaneously for the ~eading and Trailing ~its, i~ any. The occurrence of the TBTAB signal on line 212 during -the A por-tlon of the ~ ~ 7 ~ ~ ~ 3 cycle, will cause an enabling signal -to all o~ -the cen-ter AND inpu-t -te.rminals o~ -the Bit Mask circui-ts and will generate -the 8-bi-t masks for the Leading Read Bytes.
Similarly, the occurrence o:~ the TBTAB signal during the B portion of the cycle will result in the genera-tion o~ the 8-bit mask signals for -the Trailing Read By-tes.
The occurrence of the TBTB signal on line 210 will cause.
an enabling signal on line 476 -to all of -the right-most AND input circuits of the Bit Mask circuits -thereby enabling the trans~er o~ the translated Trailing Bit ~ 1 mask ~-conditions thereto. In the event i-t has been de-termined that it is ~ single byte write condition, the SBY signal will be present on line 252 as an input -to circuit 466.
During the TBTB time, circui-t l~66 will be enabled and will be providing a low signal on line 472! thereby allowing the setting of -the mask conditions for the - ~eading Bits simultaneously with the se-tting o~ -the Trailing Bi-t mask conditions enabled by the signal on line 476.
, . . .
- 20 From -the foregoing, then, the various mask bit con~igurations and the timing con~trol.for the generation of the Leading Read Data Bytes, the Starting Par-tial Write Data Byte in which -the S-tar-ting Bit is located, -the ~railing Par-tial Write Da-ta By-te in whi.ch -the Trailing Bit is located and -the Trailing Read Da-ta By-te have been described in detail. It remains -to describe -the by-te mask generation in de-tail.

FIG. 23a through 23 , when arranged as shown in FIG. 23~ comprise the detailed logic circuit diagrams 3 of the ~tarting/Trailing Byte Decoder/Translator 230 and the By-te Mask circuitry 226 described in relation -to FIG.
14. The Decoder/Translator portion of the circuitry ~unctions for providing the mask generation cvn-trol signals for both the leading bits to be masked and the trailing bi-ts to be masked in response to the applied timing.and con-trol signals. This functions without dup-lication of circuitry because the Byte Mask signals are utilized ~or :~l'7~1~33 enabling -the 8-bi-t latch circuit and need not be con-cerned abou-t -the single by-te wri-te condition.

The decode portion of -the circuitry is comprised of AND/OR circuit 500 which translates -the A3 signal received on line 142-3 or the B3 signal received on line 152-3, AND/OR 502 which responds to the A4 signal received on line 142-4 or -the B4 signal received on line 152-4, and AND/OR 504 which responds to -the A5 signal received on line 142-5 or the :B5 signa~. received on line 152-5,, The Finable signal is applied on line 202 as an input to all o:E these decode circuits and the ou-tpu-t signals from INVER~ER 506 control whether the :Leading Byte Of:Eset is being decoded or whether the Trailing Byte is being de-coded, INVERTER 506 receives the AB Selec-t signal on line 232, which will be a high signal during -the A portion of -the c~cle. This will result in the complemen-tary output on line 508 being low and will enable the decoding of the signals A3, A4, and A5. During -tha-t -time, -the signal on line 510 will be high and will disable ~he decoding of -the B-Field, When the ~B Select signal switches a-t the change -to -the B portion o~ the cycle, -the ou-tput signals will reverse, and the low output signal on line 510 will then enable the decoding o:f -the B-Field ànd will inhlbit -the A-Field.

The translator portion of the ci.rcuitry is comprised o~ the circuits AND BYO 512, AND BY1 514, AND/OR
BY2 516, TNVERT~R BY3 518, .AND/OR BY4 520 ~ OR :E3Y5 522, OR BY6 524l and IlYVERTER BY7 526~ The true ou-tpu-t o~ AND~
OR 500 is provided on line 528 as an input to ANI~ BYO
512, AND/OR BY2 516, and ~AND/OR BY4 520. The complementary outpu-t is applied on line 530 as one o:E the input signals to OR BY6 524. The true output signals :Erom AND/OR 502 is provided on line 532 as inl~u-t signals -to AND BYO, AND
:BY1, AND/OR B'.2, and ~AND/OR BY4. The complementary ou-tput is provided on line 534 as an input signal to OR
BY5 and OR BY6. The true output s;gna:l. from AND/OR 504 is provided on line 536 as a.n inpu-t signal to ~.NI) :BYO1 ~L~L'7~

AND BYl, AND,/OR BY2, INVERTER BY3, and AND/OR BY4. The complementary output is provided on line 538 as inpu-t signals -to OR BY~ and OR BY6. INVERTER BY7 526 receives the Enable signal and passes i-t through the complemen-tary ou-tput signals ~rom the -translator circuits u-tili~ed for the generation o~ the ~eading By-te Masks, and the com-plementary output signals utilized for the genra-tion o~ the Trailing Byte Mask.

The ~yte Mask generating circuit is comprised o~
eight AND/OR circuits labeled 540, 541, 542, 543, 544, S45. 546, and 547, each having three AND circuits at the input, except ~47 which has -two input AN~ circuits.

The selection of generation o~ ~the ~eading Byte Mask or the Trailing B~te Ma~sk is under the con~trol of AND/OR circuit 550, AND circuit 552, and AND circui-t 554.
The ~n~ble signal is applied to all o~ these control circuits to enable -their ac-tivation. AND 552 receives -the A Select signal on line 236 and the TBYAB siganl received on line 242, The resultant ou-tput control signal on line 556 is directed to -the righ-t-most AND circuit of each of the Byte Mask circuits and functions -to enable the generation of the By-te Mask posi-tions for ~the 1eading Read Byte. AND 554 receives the B 5elec-t signal on line 238 and the TBYAB signal on line 242, wi-th the resultarlt ou-t-put signal applied on line 558 to -the left-most AND cir-cuit of the Byte Mask circuitry. AN~ 554 is enabled during the B portion of the cycle and its output signals functions to enable the generation o~ the ~railing Read Byte. AND/OR circuit 550 receives the ~BYA'signal on line 240 which in combination with the A Select signal received on line 236 results in an enable signal on output line 56Q that enables the selec-tion of the byte in which the 1eading Bit is situatedO The signal being directed -to the center AND circuit of the Byte Mask circuitry. During the 35 - B portion of the cycle, the ~BYB signal received on line 244 and the B Select signal received on line ~38, result in the enable signal being applied on line 560 that provides ~6 for -the identifica-tion of the by-te in which the Trailing Bit is si-tua-ted, The complemen-tary ou-tput signal from each of the -translator circuits is direc-ted to -the righ-t-most ~ND circui-t of the associa-ted s-tage of the Byte Mask circuits and to the center AND circ~i-t of the next higher ordered Byte Mask circuit, with -the exception of ~NVERTER
BY7 526 since -tha-t is the end-condition. ~he true output terminal of each of the transla-tor circui-ts is applied to the left-most AND circui-t and the cen-ter AND
circuit of the associated stage of -the Byte Mask circui-t and to the left most ~ND circuit of the next higher ordered Byte Mask circuit, again wi-th -the exception o~
INVERTE.R BY7 ~26 which has:no higher ordered related Byte Mask circuit. With the exceptions noted, the arrangement is symm'e-trical, and i~.-is not deemed.~n~,cessa~y to identify each connection other than by reference to the drawings, it being clear to those.skil1ed in the art as to how the circui-ts interrela-te and func-tion. The ~0 other end_condition is accommodated by -the applica-tion of the signal BT30 on line 234 to -the lowe~t ordered Byte Mask circuit 540.

When -the Mask By-te circui-try has been ac-tivated as descri'bed,'the si~nals are available ~or enabling the 8-bit la~ch circuits -to be set in response -to the various Mask Bi-t conditions. Since the sys~m..provides ~or a word boundary crossing, as p~eviously described, it is necessary to select which of the two words is presently under consideration. The selection of the output for the even word is accomplished by AND circuits 580, ~81,. 58?1 583, 584, 585~ 586, 587, each of said AND circuits being enabled by the Word Select 0 signal received on line 2~6.
In a similar manner, each of -the mask byte circuits 540 through 547 have their respective ou-tput -terminals coupled to a second set of ~ND circuits 590, 591, 592, 593~ 5g4, 595, 596, and 597. This las-t se~t of AND circuits is enabled by the Word ~elec-t 1 signal applied on line 248.

1~7~ 33 ~47-~` I-t can be seen, then, that the initial word selection -that was accom~lished by the evalua-tion of the word address results in the selec-tion of the outpu-t ~rom the Mask By-te circui-ts, and tha-t -this selec-tion can be altered to the o-ther words by the toggling of -the word select lines as previously described.

From the foregoing detailed description of the embodiment of the invention, it can be seen -that -the varîous s-tate purposes and objectives ha~e been sa-tisfied, In order to provide for the expansion of the capacity of the system, for example to a 128-bit word capacity, it would be necessary -to add -the 6-bit posi-tion to the A-Field, ~-Field, and the ~-Field, as previously described.
~ssuming that -the nurnber of bits within a by-te would no-t be al-tered, tha-t circui-try would continue as illus-trated.
It would, however, require that the By-te Mask circui-try be modified to add -the additiona~ number o~ circui-ts to accommodate -the selected word ca~acity. This would also require the addition of -the necessary 8-bit la-tch cir-cuit~ The addi-tional decoding and -transla-tion for -the extra capacity would follow the same sys-tem as de$cribec~, and would be readily apparent -to -those skilled ln the ar-t.
Accordingly, -the detailed circui-try ~or the addi-t:ional capacity is no-t shown. Of course if lesser capacity is required, the circultry can be simpli~ied by elimina-tion of components, The embodiment shown utilizes the 8-bit latch output circuit for holding the mask configuration. The system could equally work to mix the mask bits with the read da-ta bi-ts during -the reading operation, and u-tilize the resultant bi-t combination as inpu-t signals to the storage device, Having described the embodiment of the invention, what is intended to be protected by ~et-ters Paten-t is set forth in the appended claims, . . ~ .
- What is ola~med is:

.. . .. . . .

Claims (29)

1. In a memory system having an addressable main memory with reading and writing circuitry for reading and writing memory words, a variable field writing control system comprising:
input means for receiving field defining signals indicative of the field of data bits to be read in data words stored in predetermined addressable memory locations;
mask bit generating means coupled to said input means for providing mask signals for all bit positions that are not to be altered in said data words, as des-ignated by said field defining signals; and merging means coupled to said mask bit generating means for merging data bits to be written with data bits in said memory locations corresponding to said mask signals.

2. A variable field writing control system as in claim 1 wherein said input means comprises:
starting bit receiving means for receiving statring bit offset signals indicative of the selected bit position location of a starting bit in a variable bit field to be written in an addressed memory word;
field length receiving means for receiving field length signals indicative of the number of bit positions in a selected variable field, that is to be written;
trailing bit determining means coupled to said starting bit receiving means and said field length receiving means for providing trailing bit signals indica-tive of the last bit in said selected variable field length bit grouping that is to be written.

3. A variable field writing control system as in claim 2 wherein said trailing bit determining means includes adder means for numerically adding starting bit offset signals and said field length signals and providing sum signals indicative of the trailing bit plus one position and a carry signal for said selected variable field;
carry signal output means for providing a carry signal indicative that a selected variable field will extend beyond the bit position limits of the addressed data word and word boundary crossing to the data word stored in the next sequential address will occur;
trailing bit plus one output means coupled to said adder means for providing trailing bit plus one signals indicative of the bit location in a selected byte of the first bit position following said selected variable bit field to be written; and trailing byte output means coupled to said adder means for providing trailing byte signals indicative of the byte location in a selected addressed data word or the next sequential selected data word of the byte in which said trailing bit plus one is located.

4. A variable field writing control system as in claim 3 wherein said starting bit receiving means includes bit offset means for receiving selected first ones of said starting bit signals indicative of the starting bit location in a selected byte of said selected variable bit field to be written; and byte offset means for receiving selected second ones of said starting bit signals indicative of the byte location in a selected data word of the byte in which said starting bit is to be written.

5. A variable field writing control system as in claim 2 wherein said mask bit generating means comprises, leading mask generating means coupled to said starting bit receiving means for generating leading mask signals for all bit positions in said addressed memory word occurring ahead of said starting bit; and trailing mask generating means coupled to said trailing bit determining means for generating trailing mask signals for all bit positions in said addressed memory word occurring after said trailing bit.

6. A variable field writing control system as in claim 5 wherein said leading mask generating means includes leading bit mask generating means coupled to said starting bit receiving means for providing leading bit mask signals for all bit positions preceding starting bit within a starting byte;
leading byte mask generating means coupled to said starting bit receiving means for providing leading byte mask signals for all bytes preceding said starting bit; and leading mask timing receiving means for receiving leading mask timing signals for controlling leading mask bit generation by said leading bit mask generating means and said leading byte mask generating means.

7. A variable field writing control system as in claim 6 wherein said leading bit mask generating means and said leading byte mask generating means includes starting bit decoding and translating means coupled to said starting bit receiving means for providing leading bit mask enabling signals;
bit mask means coupled to said starting bit decoding and translating means and said leading mask timing receiving means for providing said leading bit mask signals;
starting byte decoding and translating means coupled to said starting bit receiving means for providing leading byte mask enabling signals; and byte mask means coupled to said starting bit decoding and translating means and said leading mask timing receiving means for providing said leading byte mask signals.

8. The variable field writing control system as in claim 5 wherein said trailing mask generating means includes trailing bit mask generating means coupled to said trailing bit determining means for providing trailing bit mask signals for all bits following said trailing bit within a trailing byte;
trailing byte mask generating means coupled to said trailing bit determining means for providing trailing byte mask signals for all bytes following said trailing bit; and trailing bit mask timing receiving means for receiving trailing mask timing signals for controlling trailing mask bit generation by said trailing bit mask generating means and said trailing byte mask generating means.

9. A variable field writing control system as in claim 8 wherein said trailing bit mask generating means d said trailing byte mask generating means include trailing bit decoding and translating means coupled to said trailing bit determining means for pro-viding trailing bit mask enabling signals;
bit mask means coupled to said trailing bit decoding and translating means and said trailing mask timing receiving means for providing said trailing bit mask signals trailing byte decoding and translating means coupled to said trailing bit determining means for pro-viding trailing byte mask enabling signals; and byte mask means coupled to said trailing bit decoding and translating means and said trailing timing receiving means for providing said trailing byte mask signals.

10. A variable field writing control system as in claim 5 and further including latch means coupled to said leading mask generating means and said trailing mask generating means for receiving and storing said leading bit mask signals and said trailing bit mask signals.

11. A variable field writing control system as in claim 3 and further including address means for receiving signals indicative of initial selection of a first or second address of a memory word to be accessed:
single byte partial write means coupled to said address means, said carry signal output means, said field length receiving means, said starting bit receiving means, and said trailing byte output means for providing single byte selection signals to said merging means when said starting bit and said trailing bit are located in a single byte.

12. A variable field writing control system as in claim 11 and further including word selection means coupled to said field length receiving means and said carry signal output means and said address means for providing word select signals to said merging means for providing word boundary crossing when a variable bit field to be merged can not be written completely in the addressed data word.

13. In a memory system having an addressable main memory with reading and writing circuitry for reading and writing addressed memory words, and memory addressing selection circuits for use in a data processing system to merge programmable variable data bit fields with recorded data bits at addressed memory locations, a variable field writing control system comprising:
input means for receiving write field defining signals indicative of the location and number of positions of a selected bit field to be written;
leading bit masking means coupled to said input means for providing masking signals for all leading bit positions that precede said bit field to be written in selected data words;
trailing bit masking means coupled to said input means for providing masking signals for all trailing bit positions that follow said bit field to be written in said selected data word;
variable field write receiving means for receiving write signals indicative of a selected field of data bits to be written;
reading means for reading said addressed data words from the memory system;
merging means coupled to said reading means, said variable field write receiving means, said leading bit masking means and said trailing bit masking means for merging said selected field data bits to be written with leading read data bits from said addressed data words as determined by said leading bit masking means and trailing read data bits from said addressed data words as determined by said trailing bit massing means; and writing means coupled to said merging means for writing the merged data words in the memory system.

14. A variable field writing control system as in claim 13 and further including phase control signal receiving means for receiving phase control signals for enabling the leading masking means during a first phase control time and enabling said trailing masking means during a second phase control time;
word select receiving means for receiving word select signals indicative of selection of one of two addressed data words that is to be referenced;
leading timing receiving means for receiving leading timing signals for timing said leading bit masking means; and trailing timing receiving means for receiving trailing timing signals for timing said trailing bit masking means.

15. A variable field writing control system as in claim 14 wherein said leading timing receiving means includes leading bit timing receiving means for receiving leading bit timing signals for controlling selection of a leading bit and masking of all of bits preceding said leading bit within a leading byte; and leading byte timing receiving means for receiving leading byte timing signals for controlling selection and masking of all bytes preceding said leading bit.

16. A variable field writing control system as in claim 15 wherein said trailing timing receiving means includes trailing bit timing receiving means for receiving trailing bit timing signals for controlling selection of a trailing bit and masking of all bits succeeding said trailing bit within a trailing byte; and trailing byte timing receiving means for receiving trailing byte timing signals for controlling selection and masking of all bytes succeeding said trailing bit.

17. A variable field writing control system as in claim 16 and further including word selection switching means coupled to said merging means for switching selection of the word selection provided by said word select signals and word boundary crossing is required to completely accommodate the number of bits in said write signals.

18. A variable field writing control system as in claim 16 wherein said input means comprises:
leading bit receiving means for receiving leading bit offset signals indicative of the selected bit position location of a leading bit in the variable bit field defined by said write signals and to be written in an addressed memory word;
field length receiving means for receiving field length signals indicative of the number of bit positions in said selected variable field that is to be written;
trailing bit determining means coupled to said leading bit receiving means and said field length receiving means for providing trailing bit signals indicative of the last bit in said variable bit field that is to be written.

19. A variable field writing control system as in claim 18 wherein said trailing bit determining means includes adder means for numerically adding said leading bit onset signals and said field length signals and providing sum signals indicative of the trailing bit plus one position and a carry signal for said selected variable field;
carry signal output means for providing a carry signal indicative that a selected variable field will extend beyond the bit position limitations of the addressed data word and word boundary crossing to another data word will occur;
trailing bit plus one output means coupled to said adder means for providing trailing bit plus one signals indicative of the bit location in a selected byte of the first bit position following said selected variable bit field to be written; and trailing byte output means coupled to said adder means for providing trailing byte signals indicative of the byte location in a selected addressed data word or the alternate selected data word of the byte in which said trailing bit plus one is located.

20. A variable field writing control system as in claim 19 wherein said leading bit receiving means includes bit offset means for receiving selected first ones of said starting bit signals indicative of the leading bit location in a selected byte of said selected variable bit field to be written; and byte offset means for receiving selected second ones of said starting bit signals indicative of the byte location in a selected data word of the byte in which the leading bit is to be written.

21. A variable field writing control system as in claim 20 wherein said leading bit mask means includes leading bit mask generating means coupled to said leading bit receiving means for providing leading bit mask signals for all bit positions preceding said leading bit within a leading byte in response to said leading timing signals; and leading byte mask generating means coupled to said leading bit receiving means for providing leading byte mask signals for all bytes preceding said leading timing signals.

22. A variable field writing control system as in claim 21 wherein said leading bit mask generating means and said leading byte mask generating means includes leading bit decoding and translating means coupled to said leading bit receiving means providing leading bit mask enabling signals;
bit mask means coupled to said leading bit decoding and translating means and said leading bit receiving means for providing said leading bit mask signals under control of said leading bit timing signals;
starting byte decoding and translating means coupled to said leading bit receiving means for providing leading byte mask enabling signals; and byte mask means coupled to said leading bit decoding and translating means and said leading byte timing receiving means for providing said leading byte mask signals under control of said leading byte timing signals.

23. A variable field writing control system as in claim 20 wherein said trailing bit masking means includes trailing bit mask generating means coupled to said trailing bit determining means for providing trailing bit mask signals for all bits following said trailing bit within a trailing byte in response to said trailing timing signal; and trailing byte mask generating means coupled to said trailing bit determining means for providing trailing byte mask signals for all bytes following said trailing bit in response to said trailing timing signals.

24. A variable field writing control system as in claim 23 wherein said trailing bit mask generating means and said trailing byte mask generating means include trailing bit decoding and translating means coupled to said trailing bit determining means for providing trailing bit mask enabling signals;
bit mask means coupled to said trailing bit decoding and translating means and said trailing bit timing receiving means for providing said trailing bit mask signals under control of said trailing bit timing signals;
trailing byte decoding and translating means coupled to said trailing bit determining means for pro-viding trailing byte mask enabling signals; and byte mask means coupled to said trailing byte decoding and translating means and said trailing byte timing receiving means for providing said trailing byte mask signals under control of said trailing byte timing signals.

25, A variable field writing control system as in claim 20 and further including latch means coupled to said leading bit masking means and said trailing bit masking means for receiving and storing said leading bit mask signals and said trailing bit mask signals,

26, A variable field writing control system as in claim 20 and further including address means coupled to said word select receiving means for making an initial selection of a first or second address of a memory word to be accessed;
single byte partial write means coupled to said address means, said carry signal output means, said field length receiving means, said leading bit receiving means, and said trailing byte output means for providing single byte selection signals to said leading bit masking means and said trailing bit masking means indicative of that said leading bit and said trailing bit are located in a single byte.

27. A variable field writing control system as in claim 26 and further including word selection means coupled to said field length receiving means and said carry signal output means and said address means for providing word select signals to said merging means for providing word boundary crossing when a variable bit field to be merged cannot be written completely in the addressed data word.

28. In a memory system having an addressable main memory with reading and writing circuitry for reading and writing an even addressed data word and an odd addressed data word during the same memory reference cycle, wherein each stored data word is comprised of a predetermined number of bytes with each byte having a predetermined number of bits, even address and odd address read registers for storing even and odd addressed data words read from the memory, even address and odd address write registers for storing even and odd addressed data words to be stored in memory, a write register for storing a field of data bits to be written, a variable field writing control system for merging a programmably selected field of data bits within a selected one of the even address or odd address data words, or both, while retaining all bits not within the selected variable bit field unaltered as read from the memory, the variable bit field writing control system comprising:
leading bit receiving means, for receiving leading bit signals indicative of the bit position of a leading bit in a variable bit field to be written, said leading bit signals including bit offset signals in a leading byte and byte offset signals in a data word;
field length receiving means for receiving field length signals indicative of the number of bit positions in the bit field that is to be written;
adder means coupled to said leading bit receiving means and said field length receiving means for providing trailing bit signals of the bit position location of the trailing bit in said bit field to be written by locating the first bit position not included in said bit field, said trailing bit signals including trailing bit plus one signals in the trailing byte and trailing byte signals in the data word, said adder means including carry output means for providing carry signals;
leading timing receiving means for receiving leading timing signals for timing generation of leading bit mask signals and leading byte mask signals;
trailing timing receiving means for receiving trailing timing signals for timing generation of trailing bit mask signals and trailing byte mask signals;
phase receiving means for receiving first phase control signals for enabling generation of said leading:
bit mask signals and said leading byte mask signals, and second phase control signals for enabling generation of said trailing bit mask signals and said trailing byte mask signals;
address select receiving means for receiving address select signals indicative of selection of the odd addressed data word or the even addressed data word;
leading bit decoder-translator means coupled to said leading bit receiving means and responsive to said bit offset signals to generate leading bit mask enable signals for all bit positions preceding the bit position indicated by said leading bit signals;
trailing bit decoder-translator means coupled to said adder means and responsive to said trailing bit plus one signals to generate trailing bit mask enable signals for all bit positions following the bit position indicated by said trailing bit signals;
first and second sets of byte latch means, each set including the number of bytes in an addressable memory word, and each having an enable input means and a pre-determined number of latch input terminals matching the number of bits in a byte in an addressable memory word, and a like number of output terminals;
byte decoder-translator means coupled to said phase receiving means, said leading bit receiving means, and said adder means, and responsive to said leading byte offset signals during said first phase to generate leading byte enable signals and responsive to said trailing byte signals during said second phase to generate trailing byte enable signals;
bit mask means having input terminals coupled to said leading bit decoder-translator means and said trailing bit decoder-translator means and said leading timing receiving means and said trailing timing receiving means, and a number of output terminals matching the number of bits in a byte in an addressable memory word, each of said output terminals coupled to all like-ordered ones of said latch input terminals, for generating said leading bit mask signals during first phase and for generating said trailing bit mask signals during second phase;
word select means coupled to said carry output means for providing alternate word selection signals when said variable bit field cannot be completely written in said addressed memory word;
byte mask means having input terminals coupled to said word select means, said byte decoder-translator means, said leading timing receiving means and said trailing timing receiving means, and a number of output terminals matching the number of and coupled to an associated one of the said latch enable input means of said first and second sets of byte latch means, for enabling setting of said leading bit mask signals during said first phase and enabling setting of trailing bit mask signals during said second phase in said first and second sets of byte latch means.

29. A variable field writing control system as in claim 28 and further including single byte partial write means coupled to said leading bit receiving means and said field length receiving means for providing single byte control signals to said bit mask means indicative that said bit field to be written is located totally within a single byte, and multiple byte control signals to said bit mask means indicative that said bit field to be written extends beyond a single byte.