CA1171550A - Field effect transistor and method of manufacturing such a field effect transistor - Google Patents

Field effect transistor and method of manufacturing such a field effect transistor

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Publication number
CA1171550A
CA1171550A CA000387558A CA387558A CA1171550A CA 1171550 A CA1171550 A CA 1171550A CA 000387558 A CA000387558 A CA 000387558A CA 387558 A CA387558 A CA 387558A CA 1171550 A CA1171550 A CA 1171550A
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Prior art keywords
layer
region
substrate
semiconductor
polycrystalline
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CA000387558A
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French (fr)
Inventor
Henricus G.R. Maas
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Koninklijke Philips NV
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Philips Gloeilampenfabrieken NV
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising semiconducting material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate

Abstract

ABSTRACT:

A field effect transistor of which source and drain are realized partly as a semiconductor region in the semiconductor body, partly as a part of a deposited epitaxial layer, while the channel region underlies a recess in the substrate. As a result of this construc-tion the channel length is independent of variations in the thickness of the epitaxial layer and the stray capac-itances from source and drain to the substrate are small.
Moreover, a conductor pattern, separated from the epi-taxial layer by an insulating layer may extend to beyond the connection zones of source and drain, which involves a high packing density. The epitaxial layer moreover comprises extra wiring tracks; this gives a large free-dom in design.

Description

5~

The invention relates to a semiconductor device having at least a field effect transistor, which semi-conductor device comprises a semiconductor body having a substrate of a first conductivity type which, at a sur-face at least at the area of a source region and a drainregion of the field effect transistor, comprises a sur-face region of a second conductivity type opposi-te to the first, while between a source region and a drain region at least a recess is present which extends into the sub-strate and which defines a channel region of the trans-istor and has at least one gate electrode, separated from the channel region by an insulating layer.
The invention relates moreover to a method of manufacturing such a semiconductor device.
Field effect transistors are used in integrated circuits, both in digital circuits (logic circuits, mem-ories) and in analog circuits (for example, operational amplifiers). In these uses it is endeavoured to obtain a highest possible packing density of the various elements such as transistors, diodes, resistors, etc. on one semi-conductor substrate. In order to achieve this it is endeavoured inter alia to give the transistors smaller and smaller dimensions.
A field effect transistor of the above-mentioned
2~ type is disclosed in United States Patent Specification No. 4,003,126 - ~olmes et al - January 18, 1977. The field effect transistor shown in said specification com-prises two parts of a surface region which are separated from each other by a V-groove and which form a source zone and a drain zone, respectively, of the field effect transistor. Between said parts of the surface region and the surrounding substrate in which the surface region is realized, pn-junctions are present. As a result of the capacitance associated with such ~-n junctions the field ~ 7~s~5~) PHN 985~ -2- 1 o-6 - 1 effect transis-tor shown, dependent on the area of the source region and the drain region, has high capacitances between -the source region and -the subs-trate and be-tween the drain region and the substrate, respectively. These capacitances have a detrimental in~luence on the speed of such a -transistor and circuit arrangements manu~actured therewith. The e-ffective surraces of said p-n junctions are restricted to minimum dimensions determined in-ter alia by the minimum dimensions o~ the contact holes in behal r of the source and drain regions and by the tolerances be-tween the mask which de~ines-~aid contact holes and the ; mas~ which defines the groove.
Moreover, in the device shown in the United States Patent Speci~ication No. 4,003,126 the contact metallizations (elec-trodes) in behalf o~ source region, drain region and gate electrodeg are ~ormed from the same metal layer. In order to obtain a good spa-tial eeparation r said connection electrodes, a wide tolerance must be observed, which is at -the cost of the packing density.
It is the objec-t of the invention to provide a field e~fect transistor in which -the switching speed is not influenced or is influenced only to a small e~tent by the capaci-tances be~ween the source region and the drain region, respectively, and -the su~bstrate.
~nother object o r the inven-tion is to provide a -~ield e~fect transistor in which -the source region and the drain region can be provided in a sel:r-registering manner.
Still another object of the invention is -to pro-30 vide a field e~ect ~transistor which permits a large packing density inter al:ia in -that the aligmnen-t tolerances between source region and gate electrode and between drain region and gate electrode, respectively, are not critical.
The inven-tion is based inter ali~-l on -the recognit-ion o r the ~act that the above can be achieved by giving source and drain regions a particular cons truction. In addition it is based on the recognition o~ the fact that ~7~5,~
~ ,., - " P~N 9858 -3~ -1981 ~-.
such a eonstruetion permits a high paelcing density _n-ter alia in that the connection zones o~ source and drain region are manufactured in a process step other than that in which the gate elec-trode is manufactured.
A semicondue-tor devioe according to the invention is characterized in that the surface region of the second conductivity type is separated from the substrate at least over a part of its surface by an insulating layer and com-prises a polycrystalline semiconductor material.
` 10 As a result of this measure, the substrate and the surface region whieh eomprises the source and drain region o~ the field effeet transistor are separated from eaeh ~; other partly by an insulating layer. This has ~or its result that the surfaces of the p-n junctions between the surfaee region, and the substrate and hence the associated eapaeitances may be considerably smaller than in the case in whieh the surface region froms a p-n junction with the substrate o~er its ~hole surface.
A preferred embodiment of a semiconductor device in accordance with the invention is characterized in that the part of the surface region of the second conductivity type separated from the substrate by an insulating layer forms a connection zone for a source region or a drain region of a field effect transistor.
As a result of this, source and drain regions are manu~ac-tured in an entirely self-registering manner. Since in addition the gate electrode is manufac-tured in a step other than that of the connection zones, the minimum dis-tance between the edge o~ the connection zones and the edge of -the gate electrode may be chosen -to be much larger than in known transis-tors. Even a partial overlap is per-mitted so that very high paeking densities can be aehieved with such a transistor.
Sueh a eonnection zone preferably forms part of a 35 wiring layer which is separated from the substrate by an insulating layer and comprises polycrystalline semiconduc-tor material. Said wiring layer may form part of a multi-layer wirin~ system in which a second layer consists of a 5.~

PHN 9858 ~4~

conductor pattern which is provided on a layer of insula-ting material covering the polycrystalline silicon and further parts of the device. Such a multi-layer wiring system provides a large freedom in design.
A method of manufacturing a semiconductor device in accordance with the invention is characterized in that there is started Erom a semiconductor body having a monocrystalline semiconductor substrate of a first con-ductivity type which is covered at a surface with a mask-ing layer of insulating material comprising at least one aperture and in which the semiconductor body with the side of the said surface is then subjected to an epitaxy treatment from the gaseous phase in which an epitaxial ~: layer is deposited of which a part in the apertures on the semiconductor surface grows monocrystalline and a part on the masking layer grows polycrystalline, which layer is doped with impurities causing a second conduc-tivity type opposite to the first, after which at the area of the apertures in the masking layer at least a recess is provided down into the semiconductor substrate after which the walls of the recess are provided with a layer of insulating material on which layer at least one gate electrode is provided while the masking layer remains ~; as a separating layer between the substrate and at least parts of the epitaxial layer which comprise connection ~ zones for the source and drain regions.
: In this method, preferably prior to the epitaxial treatment, at a temperature lower than that at which the epitaxial layer is deposited, an amorphous or polycry-stalline layer is deposited both on the masking layer and on the uncovered semiconductor surface in the apertures in the masking layer, of which the layer portion in the aper-: tures on the uncovered semiconductor body changes into the monocrystalline state by a thermal treatment preceding the deposition of the epitaxial layer.
In this manner it is achieved that the monocry-stalline and polycrystalline parts of the epitaxial layer readily adjoin each other as described in Applicant's '7~5G~

PHN ~$58 -5-Canadian Patent 1,134,061 - issued October 19, 1982.
A preferred embodiment of a method of manufactur-ing a field effect transistor in accordance with the invention is characterized in that at least at the area of the apertures in the masking layer the impurities causing the second conducti~ity type are provided by means of dop-ing down to a depth which is larger than the maximum thickness of the epitaxial layer.
This has for its advantage thatt since the depth of such a doping can very readily be adjusted. Said dop-ing takes place throughout the surface of the device down to substantially the same depth. Variations in the thick-ness of the epitaxial layer which can be provided with a much less great accuracy therefore have no influence on the depth of the p-n junction between the surface region and the substrate. As a result of this such variations do not influence or hardly influence the channel length so that the field effect transistors have a substantially constant channel length throughout the surface area.
~ second advantage consists in that the doped surface region oxidizes more rapidly than the undoped sub-strate. This has for its result that the gate oxide which is grown in a subsequent step is a few times thicker at the area where it covers the source and drain region than it is in the channel region. The stray capacitances between the gate electrode and the source and drain regions are considerably reduced hereby.
~he invention will now be described in greater ~ detail with reference to a few embodiments and the draw-; 30 ing, in which Figure 1 is a plan view of a semiconductor device according to the invention, Figure 2 is a cross-sectional view taken on the line II-II of Figure 1, Figure 3 shows an electric equivalent circuit diagram of the device shown in Figures 1 and 2, Figure 4 shows diagrammatically the current path in a field effect transistor according to the invention, ~7~5~
~` PHN 9858 -6- 1o-6-1981 " ~
Figure 5 shows diagrammatically similar current pa-ths in another cons-truction of a field effec-t transis-tor according to the invention, Figures 6 and 7 show the semiconductor device 5 of Figure 2 during steps in its manufacture, Figure 8 is a plan view of another embodiment of the circuit shown in Figure 3, Figure 9 is a cross-sectional view of this device taken on the line IX-IX of Figure 8, Figure 10 shows an electric equivalent circuit diagram of a part o~ a memory circuit in which a field e~ect transistor according to the invention is used, while Figure 11 is a plan view of a part of such a memory circuit, and Figure 12 is a cross-sectiona~view taken on the line XII-XII of Figure 11.
The Figures are diagrammatic and not drawn to scale in which for clarity especially the dimensions in the direction of thickness are strongly exaggerated in 20 the cross-sectional views. Semiconductor zones of the same conductivity type are generally shaded in the same direct-ion; in the various embodiments corresponding parts are generallyreferred to by -the same reference numerals.
Figure 1 is a plan view of a logic gate of the 25 NAND-type of which the electric equivalent circuit diagram is shown in Figure 3, while Figure 2 is a cross-sectional view taken on the line II-II of Figure 1. The semiconductor device of Figures 1 and 2 comprises in this example a semiconductor body 1 of silicon having a substrate 2 of the 30 p-type, <100~rientsd and with a resistivi-ty of ~-12 ohm.
cm.
A number of field effect transistors T1, T2, T3, T4 is realized at the surface 3 of the substrate 2. These are present at -the area of apertures 4 in a layer 5 of 35 insulating material~, in this example silicon o~ide. A
surface region of the n-type is present on the insulating layer 5 and at the area of the aperture ll. At the area of the aperture 4 said surface region consists of a diffused zone 6 and a monocrystalline epitaxial layer 7a deposited on the surface 3. Beyond the apertures 4 the surface region consists of a polycrystalline 0pitaxial layer 7b depdsited on the oxide.
V-shaped recesses 8 are furthermore present in the apertures 4. Such a recess ~ separates wi-thin an aperture 4 the surface region 6, 7 a in a source region 9 and a drain region 10. The recess 8 extends into the sub-strate 2 and defines there a channel region 11. The channel region 11 is separated from a gate electrode 13 by a thin layer of gate oxide 12, The layer 12 also separates the gate electrode 13 over a part of the walls of the groove 8 from the source region 9 and the drain region 10, respectively.
The polycrystalline layers 7b-comprise connection zones 14 and l5 for the source and drain regions. These connection zones 14, 15 are connected~ via contact holes 16 in an electrically insulating layer of silicon oxide, to a conductor pattern 18 which comprises, for example, doped polycrystalline silicon. This pattern of conductors 20 I 8 contacts in various places via contact holes l6 a wiring pattern which is formed from the polycrys-talline epitaxial layer 7b which is separated from the substrate 2 by the oxide layer 5.
In order to prevent the mutual influencing of various field effect transistors, the device furthermore -comprises channel stopping regions 19.
In such a transistor the source region 9~ the draln region 10 and the associated connection zones 7b form par-t of the same sur~ace region 6, 7. By the measure according to the invention this surface region is separated ~rom the substrate 2 over a large part by the oxide layer 5. The stray capacitance between the substrate 2 and the saurce and drain regions 9 and 10, respectively, is there-fore de-termined subs-tantially exclusively by -the surfaces o~ the p-n ~unctions 20, 21. These surfaces are determined exclusively by the mutual tolerances of -the maslcs which de-termine the aperture l~ and the recess ~, respectively, and may hence ba many times smaller than :in known field .'7:~5S~
PHN 9858 -8- 1 o-6- 1981 effect transistors.
Moreover, since the source and drain regions are defined by the monocrystalline parts 7a of the epitaxial layer, they can be provided in a sel~-registering manner within the aperture L~. The polycrystalline parts 7b ad-joining said monocrystalline parts 7a forrn par-t of a wiring system comprising inter alia the connection zones 14 and 15 of source and drain regions 9 and IO. The gate electrode 13 is manufactured in a separate metallization step; this means that no tolerances need be observed bstween gate electrode and connection zones, which enab~es a further reduction of the dimensions of the field e~fect transistor. As a result of this and due -to the fact that the polycrystalline silicon 7b also serves as an inter-lS connection layer, a very high packing density can be achieved in an integrated circuit manufactured with field effect transistors in accordance with the invention.
For the current through a field effect transistor it holds that:
I = IDSs (1 - VGs) , with VDs _ constant Vp wherein:
; VGs : voltage between gate and source region VDs : voltage between source and drain region Vp : pinch o~ voltage n~2: , whilC IDss~ L
u : mobility of the charge carriers W : channel width L : channel length In the above example the groove has a V-shaped cross-section and the shape o~ an upside down pyramid, see also Figure ~. In this case the constant IDSs is conse-quen-tly no longer determined as such by width and leng-th of the groove since conduction of charge carriers can ta~e 35 place along all four side ~aces 22, 23, 24, 25, as indicated b~ arrows 26 in Figure 4 In ano-ther shape of the groove, as shown in Figure 5, which7 viewed in the direct-ion of current, also has a V-shaped cross-section, the 7~S~

current along the side faces 22, 23 is substantially neg-ligible and IDSs is substantially entirely de-termined by the two side faces 24, 25 along which the charge carriers move (arrows 26).
The semiconductor device shown in Figures 1, 2 can be manufactured as follows (see Figures 6 and 7).
Starting material is a C100~ oriented p-type silicon substrate having a resistivity of 8-12 ohm.cm. On a surface 3 of the substrate 2 an insulating layer 5 is then provided, for example, by oxidation until a layer of silicon dioxide of approximately 0.45 micrometer has grown.
In order to form channel stopping regions between the field effect transistors to be formed, an implantation with boron ions is then carried out all over the sur~ace.
The implantation dose is 1.5.1013 ions/cm2 with an energy of 150 keV. This results in an increased acceptor con-centration in a circuit region 27 immediately below the oxide 5. At the area of the field effect transistors to be provided, an aperture 4 is then provided photolitho-graphically in the oxide 5. Herewith the device shown inFigure 6 is obtained.
An approximately 20 nanometres thick layer of polycrystalline silicon is then deposited at a subatmos-pheric pressure of 0.5 Torr and at a temperature of 625~C
both in the aperture 4 on the silicon surface and on the oxide layer 5. In a subsequent thermal treatment said layer of polycrystalline silicon in the aperture 4 changes into monocrystalline silicon as a result of recrystalliz-ation, while the layer in other places remains polycry-stalline. For further information in this regard refer-ence can be made to Canadian Patent 1,134,061 supra.
The epitaxial layer 7 which is then deposited a-t a temperature of approximately 1050C forms a mono-crystalline part 7a within the aperture 4 and a poly-crystalline part 7b beyond said aperture. The thicknessof said layer which on an average is 0.5 micrometre may PHN 9858 -10- 10_6_1981 -- vary, for example, between 0.4 microme-tre and o.6 micro-metre. In order to form source and drain regions, said layer 7 is then doped, for example, with phosphorus which is provided by means of dif~usion. This diffusion, notably within the aperture 4, is continued do~n to a depth of 0.7 micrometre so that even at a maximunl thickness of the epitaxial layer of 0.6 microme-tre the depth of the p-n junction 20, 21 between substrate 2 and source region 9 and drain region 10, respectively, is determined entirely by the diffusion step ~hich may be done very accurately.
Herewith said depth and hence the channel length of the field e~fect transistor to be formed has become independent of the thickness o~ the epitaxial layer 7.
After patterning the polycrystalline silicon 7b in behalf o~ a first wiring layer (the wiring tracks 28 - in Figure 1) the whole device is covered wi-th a layer 17 of silicon oxide (0.4 micrometre thick). A window 29 (see Figure 1) is provided photolithographically in said layer 17 in behalf o~ providing the recess 8. Herewith the device shown in Figure 7 is obtained.
The recess 8 is then provided within the window 29 by means of anisotropic etching down to a depth of approximately 0.8 micrometre. For -this purpose a potassium hydroxide/isopropanol solution is used at a temperature of approximately 60 C. Said etching treatment takes place down into the substrate 2 do~n to an accurately determined depth from -the surface 3. Since the diffusion with which source and drain regions 9, 10 have been formed have also been carried out down to a substantially uniform depth throughout the semiconductor device, -the channel length is constant over the whole device so that very readily reproducible transistors can be manufactured. The poly-crystalline silicon exposed in the window is also etched away by means of this etching step so that short-circuits, 35 if any,between source and drain region are avoided.
In a subsequent step, the ga-te oxide 12 is gro~n within -the aperture 29 by means of thermal oxidation. .~t the area of the substrate 2 where the actual channel 11 is :~7~55C3 PHN 9858 ~ l0_6-l98l present, s~id oxidation is contimled ~ilntil a thickness of approximately 50 nanometres has been reached. This oxide 12 grows simultaneously on parts 7a of the mono-crystalline silicon exposed within the aperture 29 in which source and drain region 9 and 10, respectively, have been formed. This growth which t-~kes place in a wet nitrogen atmosphere at a temperature of approximately 850C proceeds much more rapidly (4 to 5 times) on the doped silicon 6, 7a than on the undoped substra-te 2.
1D As a result of this, the oxide at the location where it serves as an insulation between the gate electrodes 13 and the source and drain regions g, 10 is considerably thick~r.
than the actual gate oxide 12a at the area of the channel region 11. This results in a decrease of -the stray capaci-tance between source/drain regions 9, 10 and the gateelectrode 13.
In order to obtain an accurate adjustment of the threshold value, the acceptor concentration in the channel region 11 can be increased, i~ desired, by means o~ an ion 20 implantation with, for example, boron ions.
- After providing contact holes 16 in the oxide 17 so as to connect the connection zones 14, 15 and possibly other places of the first wiring pattern 28, a layer of con-ductive material is provided over the assembly. In order to obtain notably in the recesses 8 a good step coatingt polycrystalline silicon is chosen for this purpose which is deposited at low pressure and is then doped. A~ter the conductor pattern 18 has been ~ormed herefrom in genera~y known manner, the device shown in Figure 2 is completed.
Figures ~ and 9 are a plan view and a cross-sectional view, respec-tively o~ another embodiment o~ the circuit arrangement shown in Figure 3. In this embodiment -the transistors T1, T2, T3 are defined in one aperture by providing three recesses 8. The source region 9 of the 35 transistor T1 and the drain region lO of transistor T3 form part :;n the same manner as in the preceding embodiment of the same surface region 6, 7 with the associated advant-ages of a low stray capacitance between said source and '7~55 PHN 9858 _12- 10-6-198 . ~
~ .
'~ -- drain region, respectively, and the substrate.
Since the drain regionsof transistors T1 and T2, ` respectivel~, coincides with the source regionsof transis-tors T2 and T3, respectively, these common regions may be chosen to be very srnall. As a result of this a very high density is obtained. The reference numerals in Figures 8 and 9 have the same meanings as in Figures 1 and 2.
Figure 10 shows diagrammatically a part of a dynamic memory in which a field effect transistor according ; 10 to the invention is used,with word lines WO~ 1~1 and bit lines Bo~ B1~... B4. At the crossings o~ word and bit lines memory cells having one transistor per cell ~re present.
The memory information is stored in storage capacitances -~ formed by the capacitance be-tween the connection zone of lS the drain region of -the transistor and an overyling referen-ce surface from conductive material which are separated from each other by a dielectric.
Figure 11 is a diagrammatic plan view of such a cell and Figure 12 is a cross-sectional view taken on the line XII-XII of Figure 11. The reference surface 3O which in -this example is con~lected to earth forms part of the conductor pat-tern 18, while the dielectric of the capacitor is formed by the oxide layer 17. The word lines WO, W~ also form part of the conductor pattern 18. Each word line connects a number of gate electrodes 13 of transistors which form part of a cell. The number of cells which is driven by a word line determines the number of bits per word. The word line 31 in ~igure 9 also forms part of the conductor pattern 18, while the bit lines 32 are formed by wiring tracks of palycrystalline silicon 7b which are cor~ected to source regions 9 of the transistors. Other~ise, the ~eference numerals in Figures 11 and 12 have the same meanings as in the preceding Figures.
When writing, by means of a voltage at the word line the transistors connected thereto become conductive.
Dependent on the voltage at the bi-t lines which corres-ponds to a given information pattern the capaci-tors are charged or are not charged. During reading information, the PHN 9858 -13 IO_6-1981 transistors are also made conductive so that via the bit lines, i~ desired by means of output ampli~iers, said information can be scanned.
Of course the invention is not restricted to the abo~e embodiments: it will be obvious that numerous v~riations are possible to those skilled in the art without departing from the scope of this invention. For example, recesses other than V-shaped recesses are possible.
They may be, for example, U-shapedO The gate electrode 13, instead of doped polycrystalline silicon, may be manu~actur-ed from aluminium. ~n addition, several gate electrodes may be provided in the groove shown in Figure ~; in this manner, for example, a tetrode-MOST can be realized.
Numerous variations are also possible in the method; for example, -the source and drain regions may be provided by means of a suitable ion implantation instead of by diffusion.
A~ter the gate electrode 13 has been manufactured from polycrystalline silicon in behalf o~ a good step coating, the remaining par-t o~ the conductor pattern 18 may also be manufactured from a different material, ~or example, aluminium.

Claims (15)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOW
1. A semiconductor device having at least a field effect transistor r which semiconductor device comprises a semiconductor body having a substrate of a first conduc-tivity type which, at a surface at least at the area of a source region and a drain region of the field effect transistor, comprises a surface region of a second conduc-tivity type opposite to the first, while between a source region and a drain region at least a recess is present which extends into the substrate and which defines a channel region of the transistor and has at least one gate electrode, separated from the channel region by an insulat-ing layer, characterized in that the surface region of the second conductivity type is separated from the substrate at least over a part of its surface by an insulating layer and comprises polycrystalline semiconductor material.
2. A semiconductor device as claimed in Claim 1, characterized in that the part of the surface region of the second conductivity type separated from the substrate by an insulating layer forms a connection zone for the source region or the drain region of the field effect transistor.
3. A semiconductor device as claimed in Claim 2, characterized in that the connection zone forms part of a wiring layer which is separated from the substrate by an insulating layer and comprises polycrystalline semiconduc-tor material.
4. A semiconductor device as claimed in Claim 1, 2 or 3, characterized in that the field effect transistor comprises one recess and the surface region of the second conductivity type both at the area of the source region and of the drain region is separated from the substrate over a part of its surface by an insulating layer and com-prises polycrystalline semiconductor material.
5. A semiconductor device as claimed in Claim l, 2 or 3, characterized in that between a first source region and a first drain region a plurality of recesses are pre-sent which define channel regions of a plurality of series-arranged field effect transistors, in which the surface region of the second conductivity type, at the area of the first source region and the first drain region, is separ-ated from the substrate over a part of its surface by an insulating layer and comprises polycrystalline semiconduc-tor material.
6. A semiconductor device as claimed in Claim 1, 2 or 3, characterized in that, viewed in the direction from source region to drain region, the recess has a V-shaped cross-section.
7. A semiconductor device as claimed in Claim 1, 2 or 3, characterized in that the layer of polycrystalline semiconductor material is covered with a layer of insulat-ing material which has contact holes for electric con-nections.
8. A semiconductor device as claimed in Claim 1, 2 or 3, characterized in that the semiconductor body com-prises silicon and the insulating layer present on the substrate comprises silicon oxide.
9. A method of manufacturing a semiconductor device as claimed in Claim 1, characterized in that there is started from a semiconductor body having a monocrystal-line semiconductor substrate of a first conductivity type which is covered at a surface with a masking layer of insulating material having at least one aperture and in which the semiconductor body is then subjected with the side of the said surface to an epitaxial treatment from the gaseous phase, in which an epitaxial layer is deposited a part of which grows monocrystalline in the apertures on the semiconductor surface and a part on the masking layer grows polycrystalline, which layer is doped with impuri-ties causing a second conductivity type opposite to the first, after which at least at the area of the apertures in the masking layer at least a recess is provided into the semiconductor substrate, after which the walls of the recess are provided with a layer of insulating material on which layer at least one gate electrode is provided, while the masking layer serves as a separating layer between the substrate and at least parts of the epitaxial layer com-prising connection zones for the source regions and drain regions.
10. A method as claimed in Claim 9, characterized in that, prior to the epitaxial treatment at a temperature lower than that at which the epitaxial layer is deposited, an amorphous or polycrystalline layer is deposited both on the masking layer and on the uncovered semiconductor sur-face in the apertures in the masking layer of which the layer portion in the apertures on the uncovered semicon-ductor surface changes into the monocrystalline state by a thermal treatment prior to the deposition of the epitaxial layer.
11. A method as claimed in Claim 10, characterized in that a subatmospheric pressure of 0.01-10 Torr is used for depositing the amorphous or polycrystalline layer.
12. A method as claimed in Claim 10 or 11, character-ized in that a masking layer of silicon dioxide is formed on a semiconductor body of silicon and the amorphous or polycrystalline layer of silicon is deposited at a temper-ature which is lower than 800°C.
13. A method as claimed in Claim 10 or 11, character-ized in that the amorphous or polycrystalline layer is deposited in a thickness of at least 2 nanometres and at most 100 nanometres.
14. A method as claimed in Claim 9, 10 or 11, charac-terized in that at least at the area of the apertures in the masking layer the impurities causing the secondconduc-tivity type are provided by means of doping down to a depth which is larger than the maximum thickness of the epitaxial layer.
15. A method as claimed in Claim 9, 10 or 11, charac-terized in that an insulating layer which has contact holes in behalf of connection contacts for the semiconduc-tor device is provided over the layer of the second con-ductivity type.
CA000387558A 1980-10-15 1981-10-08 Field effect transistor and method of manufacturing such a field effect transistor Expired CA1171550A (en)

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NL8005673 1980-10-15
NL8005673A NL8005673A (en) 1980-10-15 1980-10-15 FIELD EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING SUCH FIELD EFFECT TRANSISTOR.

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JP (1) JPS5795670A (en)
CA (1) CA1171550A (en)
DE (1) DE3140268A1 (en)
FR (1) FR2492166B1 (en)
GB (1) GB2085656B (en)
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Also Published As

Publication number Publication date
US4825267A (en) 1989-04-25
FR2492166A1 (en) 1982-04-16
FR2492166B1 (en) 1986-06-20
NL8005673A (en) 1982-05-03
GB2085656A (en) 1982-04-28
GB2085656B (en) 1985-05-01
JPS5795670A (en) 1982-06-14
DE3140268A1 (en) 1982-06-16
US4937202A (en) 1990-06-26

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