CA1171930A

CA1171930A - Pcm signal processing apparatus

Info

Publication number: CA1171930A
Application number: CA000390695A
Authority: CA
Inventors: Susumu Hoshimi; Tadashi Kojima
Original assignee: Sony Corp; Tokyo Shibaura Electric Co Ltd
Current assignee: Toshiba Corp; Sony Corp
Priority date: 1980-11-28
Filing date: 1981-11-23
Publication date: 1984-07-31
Also published as: DE3174212D1; JPS5792411A; JPH0221076B2; EP0053474B1; EP0053474A1; US4453250A; AU7772181A; AU542260B2

Abstract

ABSTRACT OF THE DISCLOSURE

A PCM signal processing apparatus adapted to receive successive transmission blocks, each of which comprise time-interleaved PCM data, error correction and error detection words, and which comprises a detecting circuit responsive to error detecting words for detecting if a received transmission block contains an error, error identifying means for identifying as erroneous each of the time-interleaved words included in the received transmission block which has been detected as containing an error, de-interleaving means for time-deinterleaving each received transmission block to recover a de-interleaved block which comprises de-interleaved PCM and error-correction words. Erroneous words of the de-interleaved signal are identified. A syndrome generating device is coupled to the de-interleaving device and generates an error syndrome signal and uses the de-interleaved PCM and error-correction words in the de-interleaved block. An error correcting device is responsive to the error syndrome signal and/or the identification of an error by the error identifying device for correcting an erroneous PCM word in the de-interleaved block as a function of the remaining correct PCM and error-correction words in that de-interleaved block. An error compensating device is responsive to the identification by the error identifying device for compensating at least the erroneous PCM word in the de-interleaved block with a substitute PCM word when the error syndrome indicates the presence of an erroneous PCM
word and the error correction device cannot detect the error or the location of the erroneous word is unknown. An inhibit device for inhibiting the error compensating device during the state when the location of the erroneous word is unknown follows a predetermined number of blocks, and slew rate control device or filter device is coupled to the de-interleaving device for passing the de-interleaved PCM word at a predetermined slew rater and switching device is responsive to the output of the inhibit device and for selecting the slew rate of the control device or the filter device.

Description

~ 17:~L93V
BACKGROUND O~ THE INVENTION
Field of the Invention This invention generally relates to a PC~ Pulse Code Modulation signal processor and particularly to a pcrl signal processor in which an analog signal such as an audio signal is digit~zed f~ recording and reproducing on a recording medium such as tape or a disk.

Description of the Prior Art -There has been proposed a PCM recording and repro-ducing apparatus for modulating an analog audio si~nal such as music to a PCM signal and to add an error correction code and an error detection code thereto so as to convert it to a signal configuration similar to a television signal, which is recorded and reproduced by a VTR (Video Tape Recorder). In the VTR, when dropout is caused by dust and so on the magnetic tape, which is the recording medium, there is a possibility that a burst error will occur in the recorded PCM signal. If such burst error occurs, it becomes quite difficult to error-correct the lost data.
To cope with this the following operation is performed.
In a PCM processor wherein an audio PCM signal is converted to a quasi-video sisnal, upon converting of the audio PCM signal to the video signal, i.e., during recording, the PCM data is separated for each sampled word having a predetermined number thereby to form one block and an error correction code is generated for this one block of PCM data. The PCM data and the error co~rection code are respectively interleaved so as to have dif~erent delay times from each other and the error detection code is further added to the interleaved data, and signalsare then converted to a video signal. I~hen the VTR
reproduces the signal thus recorded, the video signal is con-1~7~930 verted to the audio PCM signal in an operation opposite thatdescribed above, and de-interleaving is performed so as to disperse the burst error and to correct the data. According to such an arrangement, during normal reproduction, all correction capabilities are utilized so that nearly all of the original PCM data can be reproduced.
However, since the error detection function cannot detect or identify the error with absolute reliability, the data is supplied to an error correction circuit where it is not always regarded as erroneous. When the VTR has a dropou~
compensation circuit or the like it can replace a previous block data with the dropped data when the dropout occurs and is utilized by a recording and reproducing apparatus. A data array is converted to an original array by the de-interleaving during reproduction which may become different from the original data. When different data which has already been interleaved are connected to each other so they can be edited, different data may be ~ixed with the data to change it to the correct array by the de-interleaving. In these cases, since the error correcting circuit performs the error correction, the error correcting circuit produces data quite differently from the ori~inal data and when the data is supplied and converted to the audio signal by a D/A (Digital-Analog) converter, such audio signal may be heard as an offensive abnormal sound.
In order to prevent erroneous correction, a method has been proposed where the error decision is performed by employing both the error detection results using an error detection code and syndromes formed from the error correction code and the reproduced PCM data. That is, when an error syndrome indicates the presence of an error although an absence of an error is detected by error detecting means and when the syndrome decides 1~719~0 on the existence of another erroneous word in addition to the erroneous word identified by the error indicator which is the result of the error detection and the position thereof is unknown, the err~r cor~ection thereof is inhibited and instead, all PCM
words within ~he block are compensated. F~r compensation, there are used a front-end hold to interpolate the erroneous word with the correct word occurring prior thereto and a mean value interpolation to interpolate the erroneous word with the mean value between the correct words before and behind thereof.
Further, if such abnormal states occur in succession, the compensating operation becomes impossible so that muting must be appliea.
The method thus described can prevent erroneous correction. In fact, to apply the muting causes the sound to be lost for some periods and when two system inputs are provided for the reproduced input which are switched or when a magnetic tape wherein data of two forms are connected and recorded and is reproduced by a PCM editing apparatus, although the number of errors in data detected by the error detecting signal is small there remains a drawback in that such erroneous data i~ ~tected as an abnormality caused by a mixture of different data into one block after de-interleaving and this results in muting which causes sound to be lost in the proximity of a connecting point of the data for a fixed time period.

SUMMARY OF TH~ INVENTION
An object of this invention is to provide a PCM
signal ~rocessor which can remove the afore-described defects.
Another object of this invention is to provide a PCM signal processor which can prevent erroneous corrections and can eliminate muting as much as possible.

1:~7~l930 -- A further object of this invention is to provide a PCM signal processor in which no sound is lost during cueing of the different audio signals and abnormal sound does not occur.
According to an aspect of the present invention, there is provided a PCM sig~al processing apparatus adapted to receive successive transmission blocks, each comprising time-interleaved PCM data, error correction and error detection words, and comprises a detecting device responsive to the error detecting words for detecting if a received transmission block contains an error, error identifying device for identifying as erroneous , ... . .
each of the time-interleaved words included in the received transmission block which has been detected as containing an error. A de-interleaving device time-deinterleaves each received transmission block to recover a de-interleaved block comprised of de-interleaved PCM and error-correction words, with erroneous ones of the de-interleaved words being respectively identified. A syndrome generating device is coupled to the de-interleaving device for generating error syndrome signals using the de-interleaved PCM and error-correction words in the de-interleaved block. An error correcting device is responsive to the error syndrome signal and/or the identification of the error identifying device for correcting an erroneous PCM word in the de-interleaved block as a function of the remaining non-erroneous PCM and error-correction words in that de-interleaved block. The error compensating device is responsive to the identification of the error identifying device for compensating at least the erroneous PCM word in the de-interleaved block with a substitute PCM word when the error syndrome signal indicates the presence of an erroneous PCM word and the error correction device cannot correct it or the location of the erroneous word is unknown. An inhibit device inhibits the error compensating device when the location 1~73l930 of the erroneous word is unknown and succeeds a predetermined number of blocks. A slew rate control device or filter device is coupled to the de~interleaving device ~or passing the de-interleaved PCPS w~rd with a redetermined slew rate and a switching device is responsive to inhibiting of the inhibit device and f~r selecting the slew rate of the control device or the filter device.
The other objects, features and advantages of the present invention will beco~e apparent from the following description taken in conjunction the accompanying drawings through which the like references designate the same elements and parts.

BRIEF DESCRIPTION OF THE DRAWINGS
Figures lA to lD are diagrams showing a configuration of one block data and waveforms of the recording signal in one embodiment of this invention;
~ igure 2 is a block diagram showing an arrangement of a recording encoder;
Figure 3 is a block diagram showing a reproducing decoder;
Figure 4 is a waveform diagram of one exa~ple of reproduced data useful for explaining one e~bodiment of this invention; and Figures 5A and 5B are schematic diagrams for explaining operati~ D~ o~e e~bodi~ent of this invention.

DESCRIPTION OF THE PREFERP~D EMBODIMENTS
An embodiment of this invention is described which illustrates a case where the invention is applied to an apparatus comprising an audio P~1 recording and reproducing apparatus in which a conventional home rotary two heads type VTR is used and is not modified but an adaptor is connected to it.

1~7~931) The PCM adaptor is arrangea to convert audio PCM data to a signal format similar to a television signal and a standard format such as shown in Figures lA-lD.
~ iau~e lA illustrates a dat~ block which is to be inserted into one horizont~l interv~l (lH) and Figure lB illustrates a control block to be inserted into another lH. Audio signals of two channels are respectively sampled at a sampling frequency fs of 44.056 kHz and are converted to data words Ai and Bi each comprising 14 bits. One block composes a PCM word of six words, parity words Pi and Qi of two words for error correction and a CRC (Cyclic Redundancy Check) code of 16 bits to detect the absence or presence of the aforesaid data having a total of eight words. Accordingly, the length of one block becomes 128 bits. The parity words Pi and Qi for error correction are formed with respect to the PCM word of six words and interleaved word by word. In Figure lA, suffixes attached to each word show the interleaving relationship where a unit delay amount is represented by D (block). The control block seen in Figure lB comprises a cue signal of 56 bits, a content identifying signal of 14 bits, an address signal of 28 bits, a control signal of 14 bits and a CRC code of 16 bits so as to detect errors.
As illustrated in Figure lC, int~ l-H (168 bits) o' the horizontal synchronizing signal HD is inserted one block of 128 bits. A data synchronizing signal is added to the front thereof and a white reference signal is added to the rear thereof. Also, as illustrated in Figure lD, the data interval is ~4~ in one field ~lV~ excluding an equalizing pulse interval and a vertical synchronizing signal (VD) interval having a total of 9H (9.5H for an even-numbered field) and an interval of 7.5H (7H for the even-numbered field) to include the head switching timing. As shown by the cross-hatched section in the il7:1930 Figure, the control block is inserted into the first lH.
Figure 2 shows an arrangement of a recording encoder wherein there is applied to each input terminal la and lb separate ana~og output signa~s of the A and B channels derived from a sample-and-hold circuit (not shown) which is supplied through a multiplexer 2 to an A/D (~nalog and Digital) converter 3 where they are digitized with one word for each sample. The output of the A/D converter 3 is supplied to a serial-parallel converter 4 and is converted to a six parallel words. These six words such as An, Bn, An+l, Bn+l, An~2 and Bn+2 are supplied to a parity generating circuit ~ and to an interleaving delay circuit 6. The parity generating circuit 5 operates as follows:

p = A ~ Bn ~ An+l ~ Bn+l ~ An+2 ~ n+2 Q = T6An Q T5Bn ~ T4An+l ~ T3Bn+l ~ T An+2 Q TBn+2 thereby producing first and second parity words. In the above equation, reference letter n denotes a multiple of either O or 3, + represents a modulo 2 addi~ion of each bit corresponding to each word and T represents a generating matrix. The first and second parity words can correct one word error within one block and if the position of the error word is known, two word ~ rors can also be corrected. A delay circuit 6 is provided to delay the six PCM data series from the serial-parallel converter 4 and the two parity data series from the parity generating circuit 5 by D each of a unit delay time with each differing by D
(O, D, 2D, 3D, 4D, 5D, 6D, 7D) and in practice, a memory RAM a Random Access Memory is utilized for such delay. In other words, the w~ite and read addresses of the memory are controlled so as to perform the interleaving and the frequency of the read clock signal is raised so it is higher than the write clock signal so that the time-base is compressed thereby forming a data 1171g30 blank corresponding to a vertical blanking period. An output of the delay cir~uit 6 is supplied to a parallel-serial converter 7 and c~nverte~ to bit seria~ form and the CRC code is added to it by a CRC code ~enera~or ~ and a switch 9 so as to produce a data output having the form shown in Figure lA.
To this data output are added the synchronizing signal, the e~ualizing pulse and so forth so as to form a recording signal of the same signal configuration as the television signal seen in Figures 1~ and lD, which is then applied to a video input terminal of the VTR.
Figure 3 illustrates an arrangement of a reproducing decoder. From an input terminal 10 is supplied a reproduced signal produced at the video output terminal of the VTR which is connected to a waveform shaping and data extracting circuit 11. The synchronizing signal is separated in a manner not shown from the reproduced signal and is employed to form a timing pulse signal required for data processing in a reproducing system. The reproduced data is applied to a serial-parallel converter 12 and to an error detector 13. The error detector 13 is provided to detect errors in the reproduced data in each block by utilizing the CRC code and produces an error indicator signal EP which is "1" if an error exists and is "O" if no error exists. Eight words appearing in the output of the serial-parallel converter 12 and the error indicator signals EP are applied to a buffer memory 14. The error detector 13 produces the error indicator signal EP with a timing at which all data of one block are input and output to the ~uffer memory 14. The ~ne ~lock data and the error indicator signal EP are made synchronized with each other and with this block. To each of the eight series data appearing at the output of the buffer memory 14 is applied a delay t7D, 6D, 5D, 4D, 3D, 2D, D, O) whi~h is applied in a de-interleaving ~71'~3C~
delay circuit 15 so as to cancel the delay previously obtained by the interlea~ing. In this case, the error indicator signal EP as well as the data ar~ applied to the delay circuit 15 wherein the error data signal EP for one bit is added to each word of the data.
The delay CiICUit 1~ is, in practice, comprised of a memory and is adapted to control addresses thereof so as to apply a predetermined delay as well as to make the frequency of the read clock signal lower than that of the write clock signal thereby performing time-base extension. The data which has been de-interleaved by the delay circuit 15 is supplied to a syndrome generating circuit 16 and the error indicating signal EP accompanying the data is supplied to an error pointer pattern identifying circuit 17. The PCM data derived from the delay circuit 15 is applied, through one block delay circuit 18 to a correcting circuit 19 and to a compensating circuit 20.
To the correcting circuit 19 is supplied the syndrome signal from the syndrome generating circuit 16 and to the compensating circuit 20 is supplied the previous PCM data which has passed through a delay circuit 21 in order to interpolate the mean value. A controller 22 is provided to control whether error correction is done by the correcting circuit 19 or whether error compensation is done by the compensating circuit 20. The controller 22 receives a discrimination result from the error indicator pattern discriminating circuit 17 and a syndrome discrimination result from the syndrome generating circuit 16.
The manner o~ correcting or compensating an erroneous word is as ~ollows. For the PCN data of one block to generate the parity words P and Q, six words Wl to W6 may be considered.
Six words Wl to W6 and the parity words P and ~ are reproduced and supplied to the syndrome generating circuit 16 as follows.

117~93~
Sl = P ~ ~ wn = Pe ~ Wne n=l n=l S2 = Q ~ ~ T7 n Wn = Qe ~ T7-n W
n=l n=l where reference letters Pe and Qe designate error patterns of the parity words P and Q, the error patterns in which, for example, the presence or absence of the error of each bit is respectively represented by "1" or "O" and Wne represents an error pattern o~ the PCM word. Thus syndrome signals Sl and S2 are formed. If no error exists, Sl = O and S2 = O. If the parity word P is only erroneous, Sl ~ O and S2 = O.
If the parity word ~ is only erroneous, Sl = O and S2 ~ O.
Further, if two words of the parity words P and Q are onl~
erroneous or if one word or more of the PCM date words Wl to W6 are in error, Sl ~ O and S2 ~ O. However, since the error correction is not necessarily re~uired for a case where either of the parity word P or Q is only erroneous, a description will hereinafter be given for a case where the PCM word is erroneous.
1. For a one word error of the PCM word:
Can be expressed as:
Wi = Wi + Wie where Wi represents an erroneous word, Wi represents a true value, Wie represents an error pattern.
a. If P is correct and the error position i is speciied by the error indicator EP, since Sl = ~ Wne = Wie n=l thus Wi = Wi ~ Sl b. If P is erroneous but Q is correct and the error position i is specified by the error indicator EP, since S2 = ~ T7-n Wne = T7 i Wie n=l thus Wi = Wi ~3 Wie = Wi ~ T 7S2 c. If P and Q are correct but the erroneous word of a one word error is unknown, the date word is one word error and if it be represented by Wi thus S1 = Wie S2 = T i Wie then i to satisfy ' Sl = T 7 S2 or T i Sl = S2 is searched. If the i is known, thus Wi = Wi ~ Sl

2. If P and Q are correct but two words (Wi, Wj) of the PCM
word are erroneous (where each error pattern is given as Wie and Wje), can be expressed as follows.

Wi = Wi ~ Wie, Wj = Wj ~ Wje ( Sl = Wie ~ Wje S2 = T7 i Wie ~ T7 i Whe ~. ~ , .. ..
Wje = (I ~ Ti j, 1 (Sl ~ Ti 7 S2) (where letter I denotes an unit matrix) Wie = Sl ~ Wje Wi = ~i ~ Wie = Wi ~ Sl ~ (I G~ Ti j) 1 (Sl ~ Ti 7 S2) Wj = ~j ~ Wje = Wj ~ (I ~ Ti j) 1 (Sl ~ Ti 7 S2) The correcting circ~it 19 performs the error corrections described above. In other cases other than the above one, the words regarded as erroneous by the ~.-or indicator EP are concealed by the compensating circuit 20 under control of the controller 22. However, if the error position cannot be detected even when the presence of the error is known as 1~7~930 described below, all words Wl to W6 are concealed.

3. a. For a case wherein both P and Q are correct, but the erroneous word is unknown and also the error position i cannot be detected by the method of l-C, for example, erroneous words of two words or above though not specified by the error indicator EP.
3. b. P is correct, but Q is erroneous. Although the error pointer EP of each word of Wl to W6 does not specify the erroneous word, Sl ~ 0 is established.
3. c. Q is correct, but P is erroneous. Although the error pointer EP of each word of Wl to W6 does not specify the erroneous word, S2 ~ 0 is established.
In this invention, the operation is as follows: If anyone of the cases 3-a to c successively occurs (what is termed a de-interleaving mistake), such successive occurrence is detected by a de-interleaving mistake detector 23 associated with the controller 22 so that the error correction and the compensation of all six words are stopped. At the same time, the controller 22 controls the correcting circuit 19 and the compensating circuit 20 so as to pass the erroneous word which was regarded as without error by the error indicator EP
through the compensating circuit 20 as it is and further controls a selector 24 to select the PCM data passed through a slewing rate controller 25. The slewing rate controller 25 can determine the slewing rate as a predetermined value and the slewing rate value to be determined is selected to be relatively low. It is also possible ~or a digital filter to be provided in place of th~ slewing rate controller 25. The slewing rate controller 25 or the filter may be provided in the stage where the analog signal is produced at an output of a D/A converter.
There is further provided a detector 27 to detect from the error indicator EP if a burst error becomes too long to be ~L~'7i930 corrected and compensated and a terminal 26 receives an overflow detecting signal from the delay circuit 15 (memory) for de-interleaving. Detector 27 produces an output to perform muting.
By way of example, as shown in Figure 4, an editing point X is synchronized with the vertical synchronizing signal VD wh}ch is taken as a border and a reproduced signal wherein different data DATA 1 and DATA 2 are interconnected with each other andare supplied to a reproducing decoder. In a memory area in which the memory comprises the de-interleaving circuit 15, the reproduced data comprising one block are written in turn word by word into addresses spaced apart from each other by D and are sequentially read out word by word with respect ~o the addresses for the same block. As illustrated in Figure 5A, when data An, Bn_3D,... Pn-18D and Qn_21D
block of the DATA 2 after the editing point X is written, data of An, Bn, ... Pn of the DATA 1 are read out together with Qn_21D, i.e., Qn. Accordingly, the de-interleaved output obtained in a period from times to to tl after the D
block, only the parity data Q is included in the DATA 2 and other data are all included in the DATA 1. Therefore, with respect to each block obtained during the period to to tl, if no error exists, Sl = O and S2 ~ O and it can be detected that the parity data is erroneous. The data read out obtained in period from tl to t2 after 5D blocks include di~ferent data of two words or more within one block and even if no error exists, Sl ~ O ana S2 ~ O are established which corresponds to a case of 3, as previously described. Thus, the error position i the~eof cannot be detected. Further, since the data read out obtained during a period t2 to t3 after D block include different data (DATA 1) of one word within one block and ~3~71930 - sl ~ O and s2 ~ O are established when no error exists.
However, since such data is regarded as one word error, a true value can be searched by the error-correction according to the method 1 - c previously discussed.
As ~escr~bed above, the detector 23 detects the de-interleaving mistake during the interval of 5D blocks from tl to t2 wherein the e~roneous words of each block in the de-interleaved output have not yet been detected by the error indicator EP and produces a detecting signal as seen in Figure 5D which goes to a high level in response thereto so as to inhibit the error correction and the compensation of six words and to control the slewing rate controller 25 to produce the output at the selector 24. The output thus produced is, though not shown, converted to an analog output by the D/A
converter and divided into respective channels A and B by a de-multiplexer. The audio signal corresponding to the data i processed in the slewing rate controller 25 is mixed with .
different audio signals and the ratio of the mixture is adapted to be gradually changed.
As is understood from the description of one embodiment mentioned above, according to this invention, since a discontinuity caused by different audio signals is alleviated by the slewing rate controller 25, sound is not lost by using different audio signals as is the case of muting and since erroneous correction is prevented an abnormal sound will not occu~ at the output.
Although the invention has been described with respect to preferred embodiments, it is not to be so limited as changes and modifications can be made which are within the full intended scope of the invention as defined by the appended claims.

Claims

WE CLAIM AS OUR INVENTION:

1. A PCM signal processing apparatus adapted to receive successive transmission blocks each comprising time-interleaved PCM data, error correction and error detection words, said apparatus comprising, detecting means responsive to said error detecting words for detecting if a received transmission block contains an error, error identifying means for identifying as being erroneous each of the time-interleaved words included in the received transmission block which has been detected as containing an error, de-interleaving means for time-deinter-leaving each received transmission block to recover a de-inter-leaved block comprised of de-interleaved PCM and error-correction words with the erroneous ones of said de-interleaved words being respectively identified, syndrome generating means coupled to said de-interleaving means for generating error syndrome signals using said de-interleaved PCM and error-correction words in the de-interleaved block, error correcting means responsive to said error syndrome signals and/or the identification of said error identifying means for correcting an erroneous PCM word in said de-interleaved block as a function of the remaining non-erroneous PCM and error-correction words in such de-interleaved block, error compensating means responsive to the identification of said error identifying means for compensating at least said erroneous PCM word in said de-interleaved block with a substitute PCM word when said error syndrome signal indicates the presence of an erroneous PCM word and the error-correcting means cannor correct it or the location of error is unknown, inhibit means for inhibiting said error compensating means when the state where the location of the erroneous word is unknown succeeds a predetermined number of blocks, slew rate control means or filter means couple to said de-interleaving means and passing said de-interleaved PCM word with a predetermined slew rate, and switching means responsive to the inhibition by said inhibit means and for selecting said slew rate control means or filter means.

2. Means for correcting errors in PCM data which has been encoded as interleaved binary data words for two channels and which also includes error-correction and error-detection words, comprising, an error detecting means receiving said PCM data and indicating from said error-detection words whether an error exists in a data format, a means for de-inter-leaving said PCM data by applying different time delays thereto to produce said binary data words, and said error-correction words and to identify any binary data words in which errors exist, a syndrome signal generating circuit receiving the output of said de-interleaving means to produce error syndrome signals from said binary data words and said error correction words, an error-correcting circuit receiving the outputs of said syndrome signal generating circuit and said means for de-interleaving said PCM data and correcting binary data words in error by using the correct binary data words and the error correction words, a controller, an error signal pattern identifying circuit connected to said controller and receiving an input from said de-interleaving means, an error compensating circuit receiving outputs of said means for de-interleaving and said controller, and a selector means receiving the outputs of said compensating circuit and said correcting circuit.

3. Means for correcting errors in PCM data according to claim 2 including, a de-interleaving mistake detector means receiving an output from said controller and supplying outputs to said controller and to said selector means.

4. Means for correcting PCM data according to claim 3 including a first delay means connected to receive the outputs of said correcting circuit and said compensating circuit and supplying an input to said compensating circuit.

5. Means for correcting PCM data according to claim 4 including a slewing rate controller receiving the outputs of said correcting circuit and said compensating circuit and supplying an input to said selector means.

6. Means for correcting PCM data according to claim 4 including a filter means receiving the outputs of said correcting circuit and said compensating circuit and supplying an input to said selector means.

7. Means for correcting errors in PCM data including a detector connected to said error detector and supplying a muting signal under selected error conditions.

8. Means for correcting errors in PCM data according to claim 3 wherein said means for de-interleaving includes a series to parallel converter, and a buffer memory which receives the outputs of said series to parallel converter and said error detecting means.

9. Means for correcting errors in PCM data according to claim 8 wherein said means for de-interleaving includes a plurality of delay means of different delays connected to the output of said buffer memory.

10. Means for correcting errors in PCM data according to claim 9 wherein said plurality of delay means comprise memory means.

11. Means for correcting errors in PCM data according to claim 9 including a one block delay means receiving the outputs of said plurality of delay means and supplying inputs to said compensating circuit and said correcting circuit.