CA1172331A - Self-clocking data transmission system - Google Patents
Self-clocking data transmission systemInfo
- Publication number
- CA1172331A CA1172331A CA000384151A CA384151A CA1172331A CA 1172331 A CA1172331 A CA 1172331A CA 000384151 A CA000384151 A CA 000384151A CA 384151 A CA384151 A CA 384151A CA 1172331 A CA1172331 A CA 1172331A
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- CA
- Canada
- Prior art keywords
- signal
- binary
- state
- data
- generating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/02—Arrangements for detecting or preventing errors in the information received by diversity reception
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
- H04L25/4904—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using self-synchronising codes, e.g. split-phase codes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L5/00—Arrangements affording multiple use of the transmission path
- H04L5/14—Two-way operation using the same type of signal, i.e. duplex
- H04L5/1423—Two-way operation using the same type of signal, i.e. duplex for simultaneous baseband signals
Abstract
Abstract of the Disclosure A data transmission system is described where data signals are bidirectionally transmitted between a data transmitter and a plurality of data receivers in a self-clocking bit streams carried on true data and complement data signal lines and a non-return-to-zero (NRZ) bit streams on a return data signal line. According to an inventive data transmission scheme, data signals are transmitted by the data transmitter by utilizing the four possible two-bit binary states of the true data and complement data signal lines. Of the four two-bit binary states, a word state is provided before and after the data signal and a one state or zero state followed by a bit state is provided for each bit of the data signal.
The data receivers detect the bit state to recover a bit clock signal and detect the one state and zero state to recover an NRZ data signal. In response to the bit clock signal, the NRZ data signal is serially shifted into a register while a previously parallel loaded return data signal is shifted out of the register and applied to the return data signal line. The inventive data transmission scheme is self-clocking and highly immune to speed and timing variations in the transmission. The inventive data transmission may be advantageously utilized for data transmission in many different data transmission systems, such as computer systems for data transmission between a microprocessor and peripheral units and control systems for data transmission between a central control station and geographically remote stations.
The data receivers detect the bit state to recover a bit clock signal and detect the one state and zero state to recover an NRZ data signal. In response to the bit clock signal, the NRZ data signal is serially shifted into a register while a previously parallel loaded return data signal is shifted out of the register and applied to the return data signal line. The inventive data transmission scheme is self-clocking and highly immune to speed and timing variations in the transmission. The inventive data transmission may be advantageously utilized for data transmission in many different data transmission systems, such as computer systems for data transmission between a microprocessor and peripheral units and control systems for data transmission between a central control station and geographically remote stations.
Description
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SELF-CLOCKING DATA TRANSMISSION SYSTEM
The instant application is related to now pending patent applications, Serial Number 368,042, by Kenneth A. Felix and James A. Pautler, entitled "Improved Method and Apparatus for : Detecting a Data Signal Including Repeated Data Words", and Serial Number 368,037, by John P. Byrns and Michael J. McClaughry, entitled "Phase-Encoded Data Signal Demodulator", both of which were filed on January 7, 1981, and are assigned to the instant ass~gnee .
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Background of the Invention The present invention relates generally to data transmission systems, and more particularly to an improved method and apparatus for the self-cloc~ing transr,lission of digital data signals.
~nong the self-c-locking data transmission techniques in the prior art, one technique commonly referred to as "polar return to zero" utilizes different voltage levels within a bit interval to encode a data signal. For example, a positive voltage level with respect to a reference voltage level indicates a binary one state, while a negative voltage level with respect to the reference volta~e level indicates a binary zero state.
Another technique commonly referred to as Manchester cod-ing provides a transition during each bit interval, where the direction of the transition determines the binary state of the bit. For example, a positive transition duriny a bit interval may represent a binary one bit, while a negative transition may represent a binary zero bit.
Elowever, in order to properly receive data signals transrlitted accordlng to these prior art techniques, it is essential that timing relationships between successive bits of the data signal be accurately maintained at the data transmitter and properly recognized at the data receiver. Further~nore, proper reception at t~he data receiver is also dependent on recovery of the clock signal and precise definition of the bit interval. Thus, transmission systems utilizing these prior art techniques are very sensitive to speed and timing variations in the transmission of the data signals, and require that receiving apparatus include expensive and complex cir-cuitry to compensate for such variations.
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Summary of the Invention Accordingly, it is an object of the present inven-tion to provide an improved method and apparatus for self-clocking data transmission systems that accommodates expansive variations in the speed and timing of the transinission.
It is another object of the present invention to provide an improved self-clocking data transrnission system for provicin~ bidirectional data transrnission between a data translnitter and a pluralit~ of data receivers.
It is a further object of the present invention to provide an improved self-clocking data transmission system for providing data transmission between a data transmitter and a plurality of separately addressable data receivers.
It is a further object of the present invention to provide an improved self-clocking data transmission system for providing data transmission between a data transmitter and a plurality of data receivers each of which may request a data transmission from the trans-mitter .
In practicing the present invention, data signals having a plurality of binary bits are transmitted on two signal lines between a data transmitter and one or more data receivers of a self-clocking data transrnission system. Data signals are transmitted on the two signal lines by utilizing the four possible two-bit binary states of the two signal lines taken together. According to the data transmission scheme of the present invention, a first two-bit binary state of the signal lines is pro-vided both before and after the data signal, and for each bit of the data signal a second two-bit binary state of the signal lines followed by a third two-bit binary state _4~ 7~33~
of the signal lines is generated for a bit having a binary one staite and a fourth two bit binary state of the signal lines followed by a third two-bit binary state of the signal lines is yenerated for a bit having a binary zero state. As a result, the transmitted data signal is not only self-clocking, but also independent of the transmission fre~uency, thereby accommodating expansive variations in the time duration of successive bit inter-vals.
In the data transmission system of the present invention, a data transmitter is coupled to one or more data receivers by two signa:L lines on which data signals are transmitted according to the fore~oin~ data transmis-sion scheme. The data transmitter includes circuitry for 15 generatiny the two-bit binary states of the signal lines for each bit of a data signal to be transmitted. The receiving units include circuitry responsive to the third two-bit binary state of the signal lines for providing a clock signal. The receiving unit also includes first 20 storing circuitry responsive to the second and fourth two-bit binary states of the si~nal lines for storin~ an output signal having a binary one or zero state, respec-tively. Thus, the output signal of the first storing circuitry reflects the binary state of the successive 25 bits of the transmitted data signal. The output signal of the first storing circuitry is then stored into second storin~ circuitry in response to the elock signal. At the end of the transmission, the second storing circuitry holds the received data signal. The received data signal 30 i~ the second storing circuitry may then be ~tilized for accomplishiny any suitable function in the data receiver.
~lore particularly, there is ~rovided:
iA method of ser~ally tr~smittin~ a data signal from a signal source by means of first and second binary signals, 35 the data signal including a plurality of bi~ts each having a binary zero state or a binary one state, said method comprising the step~ of:
i~ (aj generating a first binary state of the first and _~ -4a~
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second signal~ before and after the data signal;
(b) generating for each ~it of the data ~ignal a second binary state of the fir~t si.gnal and the first binary state of the second signal for a bit having a binary zero state, and generating the first binary state of the first signal and the ~econd binary state of the second signal for a bit having a binary one state;
and (c) generating the ~econd binary tate of the first and ~econd signals between successive bits of the data signal.
There is also provided:
A m2thod of ~erially transmittin~ ~n address signal and a d~ta signal from a ~ignal 80urce by means of first and second binary signals, the address slgnal and data signal each including a plurality of bits ha~ing a binary zero state or a binary one state, said method compr~sing the steps of:
(a~ generating a first binary state of the first and second signals before the first b~t of the address signal and after the last bit of the data signal;
(b) generating for each bit of the address signal a seeond binary state of the first signal and the fir~t binary state of the second signal followed by the first binary state of the first and second signals for a bit having a binary zero state, and : ~enerating the first binary state of the first signal and the second binary state of the second signal followed by the first binary state of the first and second signals for a bit having a binary one state;
(c~ generating for each bit of the data signal the second binary tate of the first signal and the first binary state of the second signal for a bit ha~ing a binary zero ~tate, and generating the first binary state of the first signal and the second binary state of the second signal for a bit having a binary ~ne state; and (d) generating the ~econd binary ~tate of the first and 4~ 6econd signals between 6ucce~sive bits of the data signcll.
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-4b-There is also provided-Apparatus for receiving a data signal ~rom first and ~econd binarv signals ~eriall~y tran~mitted by a signal source, the data signal including a plurality of bits each having a binary zero state or a binary one statP, the first and second signals having a first binary state ~efore and after the data signal, the ~irst ~ignal having a ~econd binary ~tate and the second signa:L ~aving a first binary state for data signal bits having a binary zero state, the ~irst signal having a first binary state and the æecond signal having a binary state for data signal bits having a binary one state, and the first and second signals having a second binary state between successive data signal bits, said receiving apparatus comprising:
; 15 first means responsive to the second binary state of the first and second signals for generating a clock signal;
second means coupled to the first and second signals for storing an output signal having a binary zero state in response to a second binary state of the first signal and a first binary state of the second signal, and storing an output signal having a binary one state in response to a first binary state of the first signal and a second binary state of the second signal; and third means coupled to the first means and second means for storing the second means output signal in response to the clock signal.
T~ere is further provided:
A ~ystem ror serially communicating data signals, each including a plurality of bits each having a binary zero state or a binary one state, between a transmitting unit and at least one receiving unit intercoupled by first and second binary signals, said system comprising:
a transmitting unit for transmitting a data signal, including:
a signal source for providing a data signal;
first m~ans for generating a first binary state of the - 'lc -33~
first and second signals before and after the data si~nal;
second means for generating for each bit of the data signal a second binary state of the first signal and a first ~nary state of the second siynal for a bit having a binary zero state, and the first binary sl:ate of the first signal and a second binary state of the second signal for a bit having a binary one state; and said second means generating the second binary state of the first and second signals between successive bits of the 0 data signal; and a receiving unit for receiving a data signal transmit-ted by the transmitting unit, including:
third means responsive to the second state of the first and second signals for generating a clock signal;
fourth means coupled to the first and second signals for storing an output signal having a binary zero state in response to a second binary state of the first signal and a first binary state of the second signal, and a binary one state in response to a first binary state of the first signal 0 and a second binary state of the second signal; and fifth means coupled to the third means and fourth means for storing successive binary states of the fourth ~eans out-put signal in response to thP third means clock signal.
Brief Vescription of the Drawings .
Fig. 1 is a block diagram of a self clocking data transmission system embodying the present invention.
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Fig. 2 is a block diagram of a data transmitter for the data transrnission system in Fig. 1.
Fig. 3 is a block diagram of a data receiver for the data transmission system in Fig. 1.
Fig. 4 is a state diagram illustrating the binary states that may be utilized to encode the data signals transmitted between the data transmitter and data receivers in the data transmission system in Fig. 1.
Fig. 5 is a timing diagram illustrating the wave 'orrns for various blocks of the data receiver in Fig. 3.
Fig. 6 is a block diagram of a different data receiver for the data transmission systern in Fig. 1.
~ 'ig. 7 is a ti;ning diagram of the waveforms for various blocks of the data receiver in Fig. ~.
Detailed Desc-ription of the Preferred Ernbodiment In FIG. 1, there is illustrated a block diagram of a self-clocking data transmission system embodying the present invention. Data transmitter 101 is coupled to data receivers 102-104 by two signal lines, labelled "true data" and "complement data". The data receivers 102-104 may also transmit return data signals to the data transrnitter by rneans of a shared signal line, labelled "return data", as shown for data receivers 103 and 104 or by means of a separate siynal line as for data receiver 102. The return data signals transmitted by the data receivers 102-104 on the return data signal line are transsnitted in synchronism with the data signals received from the data transmitter 101 on the true data and com-plelnent data signal lines. The data transmitter 101 and data receivers 102-104 may be in close proximity with one another or may be separated by great distances because the data transmission is self-clocking and is independent of the transmitting frequency. In the aforementioned -6- ~7~3~
related patent a~plications, the data transmit~er 101 is a microprocessor and the ~ata receivers 102-104 are interface adapters in the control circuitry of a portable radiotelephone.
According to the present invention, data is trans-mitted by the data translnitter 101 to the data receivers 102-lG4 by making use of the four two-bit binary states that can be assw~ed by the true data and complement data signal lines ta~en to~3ether. For example, referring to state dia~3ram of FIG. 4, a first two-bit binary state rnay be referred to as a "~ord state" 401, where the true data si~nal line has a binary one state and the com~lement data signal line has a binary one state. When no data is being transmitted, the word state 401 is provided on the true data and complement data signal lines. 1^1hen a data signal is to be transmitted, a transition is r,lade from the word state 401 to the zero state 402, represented as binary state 01, or to the one state 404, represented as the binary state 10, where the complement data signal line has a binary one state for binary zero bits of the data signal and the true data signal line has a binary one state for binary one bits of the data signal. For all succeeding bits of the data signal to be transmitted, a transition is first made to the bit state 403, repre-sented by the binary state 00, before a transition to theone state 404 or zero state 402. The two-bit binary states of the true data and complement data signal lines are set forth hereinbelow in TABLE I.
TAE~LE I
TRI~E DATA COMPLEMEI~T DATA TWO-BIT STATE
1 1 Word State 0 1 Zero State 1 0 One State 0 0 Bit State . ' ~ ., 3~
Furthermore, transitions between the states 401-404 in FIG. 4 are selected so that onl~ one signal line is changing binary state at a time. Transitions between the word state 401 and bit state 403 and between the one state 404 and zero state 402 are not allowed since the~
would require that the state of both the true clata and complement data signal lines change simultaneously. By limitin~ transitions between the binary states 401-404 to those where only one of the siynal lines is changin~
~inary state at a time, the effects of skewin~ and timin~3 variations are minimized. Moreover, by transmitting data signals as illustrated by the state diagram in FIG. 4, the trans;nission on the true data and complernent data signal lines is both self-clocking and independent of the transmitting frequency. The time duration between each of the state transitions illustrated in FIG. 4 need not be the sanle and may vary dynamically. Thus, according to the data transmission scheme of the present invention, the frequency of the data transmission may be entirely asynchronous with randomly varying time intervals between successive state transitions~
To summarize the transmission sequence, the true data and complement data signal lines have the word state 401 when no data is being transmitted (see waveforms in FIG. 5). For transmission of a data signal, two state transitions occur for each bit. For the first bit of the data si~nal, a transition is made from the word state 401 to the one state 404 or zero state 402, dependiny on the binary state of the bit to be transmitted. ~ext, a state transition is made to the bit state 403. Then, for each succeedin~ bit of the data signal, a transition is made to the one state 404 or the zero state 402 and then back to the bit state 403. Since a transition is Inade to the bit state 403 for each bit of the data si~nal to be transmitted, the bit state 403 can be utilized at the 33~
data receivers to yenerate a clock siynal. For the last bit of the data signal, the last state transition is made from the one state ~04 or zero state ~02 back to the word state 401. Returning to the word state 401, after the last bit of the data signal has been transmitted indi-cates to the data receivers 102-104 that a coMplete data signal has been transmitted.
In order to provide for the bidirectional transmis-sion of data siynals between the data transmitter 101 and the data receivers 102-104 in FIG. 1, another siynal line, referred to as the return data signal line, may be provided for carryin~ non-return-to-zero (~RZ) coded data signals from the data receivers 102-104. The data receivers 102-104`can transmit a return data signal on the return data signal line by utilizing the clock signal developed by detecting the bit state of the true data and compleMent data signal lines. In order to accommodate the transmission of return data slgnals, separate return data siynal lines can be provided to each data receiver, as for data receiver 102, or a number of data receivers, such as data receivers 103-104, can be connected to one return data signal line. If a number of data receivers are connected to the same return data signal line, it will be necessary to selectively address the particular data receiver that is to transmit a return data signal.
Many different addressing schemes can be utilized, such as, for example, utilizing a portion of the data signal transmitted by the data transmitter to provide an address, or transmitting separate address signals and data signals.
Referring to FIG. 2, there is illustrated a block diagram of data transmitter 101 in FIG. 1. When it is desired to transmit data, a data strobe pulse (a momen-tary binary one state) is applied to the strobe input of latch 201 for loadiny a new set of input data, which here ~.7~33~
is represented as an eight-bit binary signal. Latch 201 is transparent durillg data strobe pulse, and is otherilise latched. The data strobe s:ignal via inverting gate 202 also clocks the Q output of flip-flop 208 to a binary one state, which corresponds to a +V voltage level with respect to ground. The binary one state of the Q output or flip-flop 208 is coupled via OR 4ate 204 to produce a binary one state of the busy signal, indicating that the data transmitter is presently busy transmitting a data signal.
The shift clock signal coupled to the clock inputs of flip-flop 209 and reyisters 203 and 211 determines the rate at ~thich data is transmitted on the true data and complement data signal lines to the data receivers. The shift clock signal may be provided by a clock oscillator or by a remote device, such as a microcomputer. Accord-ing to the present invention, the shift clock signal need not be periodic and may vary dynamically in frequency over time and from transition to transition.
Once flip-flop 208 has been clocked by the data strobe signal, the Q output of flip-flop 209 is clocked to a binary one state at the next positive transition of the shift clock signal. The Q output from flip-flop 209 is coupled to the parallel/shift input of register 203 25 and to the D input of register 211. Thus, at the next positive transition of the shift clock signal, register 203 is parallel loaded with the data signal from latch 201 and the first stage of shift register 211 is loaded with a binary one. The binary one state of the Q output of flip-flop 209 is also used to reset flip-flop 208, maintain the busy signal at a binary one state via OR
gates 205 and 204, and apply the shift clock siynal to register 203 via OR gate 205, inverting gate 206 and OR
gate 207.
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For the next eiyht cycle intervals of the shift clock signal, the data signal in register 203 is shifted right applying each bit in succession to inverting yate 216 and ~ND yate 219, while at the same tirne a binary one bit is shifted from stage to stage in shift register 211.
The outputs of shift reyister 211 are combine~ via OR
gate 212 for enabling AND gate 214 and for maintainincj a binary one state of the busy signal via OR gates 2C5 and 20~.
Prior to transmission of the data signal loaded into latch 201, the true data and complei,lent data signal lines were maintained at a binary one state by oR gate 212 via OR (3ate 218 and inverting gate 215. When OR yate 218 changes state from a binary zero state to a binary one state, the state of the true data and complement data signal lines will be determined by each bit of the data signal in reyister 203. During the binary one interval of the first shift clock signal, the true data and cor,l-plement data signal lines are Maintained at a binary one state by AND gate 213. Next, during each succeeding binary zero interval of the shift clock signal, AND gates 217 and 219 are enabled to apply successive bits of the data signal from reyister 203 to OR gates 220 and 221 for the complement data and true data signal lines, respec-tively. The true data signal lines will have a binaryone state for those bits of the data signal that likewise have a binary one state, wllile the complement data signal line will have a binary one state for those bits of the data signal which have a binary zero state. Ty~ical waveforms for the true data and complement data signal lines are illustrated by the wavefonns in FIG. 5.
At the same time that a data signal is being trans-.nitted on the complement data and true data signal lines, a return data signal may be received on the return data signal line, which is coupled to the D input of register 3~
203. Register 203, which is initially parallel loaded with the input data signal from latch 201, serially receives the return data siyllal as it is shifted to transmit the input data signal. Once the last bit of the input data signal has been transr,litted, OR yate 212 changes state from a bi.nary one state to a binary zero state and disables via OR ~ate 205 and inverting gate 206 the shift clock signal to register 203. Also, when the transmission is complete, register 203 provides the return data signal received from a data receiver at its outputs.
Referrin~ to FIG. 3, there is illustrated a detailed circuit diayram for data recéiver 102-104 in ~
haveforms corresponding to labelled blocks in FIG. 3 for a typical data signal transmission are illustrated in FIG. 4, where the transmitted data signal is 11010001 and the return data siynal is 01110101. The data receiver in FIG. 3 includes a data latch formed by NAND gates 305 and 306, which is set by NAND gate 303, which detects the one state (see FIG. 4) of the true data and complement data signal lines, and is reset by NAND gate 304, which detects the zero state of the true data and complement data signal lines. Compleitlents of the true data and complement data signal lines necessary for decoding the two-bit binary states thereon are provided by inverting gates 301 and 302. The output from data latch 305 and 306 is the recovered NRZ data signal and is coupled to the D input and high order parallel input of reyister 312.
The data receiver also includes a last bit latch fonned by NAND gates 309 and 310. The last bit latch 309-310 is set by the bit state of the true data and com-plement data signal lines, as detected by NAND gate 307, and is reset by the word state of the true data and co;n-plement data siynal lines, as detected by NAND (3ate 308.
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The last bit latch output signal is applied to NAND gate 314 and to the parallel/shift input of register 312.
A recovered bit cloc~ signal is provided by NAND
gate 311 in response to the bit state of the true data and complement data signal lines, as detected by NAND
gate 307. The bit clock signal is also forced to a binary one state by the word state of the true data and complement data signal lines, as detected by NAND gate 308.
When a data signal is transmitted to the data receiver in FIG. 3, register 312 is initially parallel loaded in response to the last bit latch outp~t signal and thereafter serially clocked in response to each posi-tive transition of the bit clock signal for shifting in the recovered NRZ data signal. Since the datâ siynals in the preferred embodiment have eight bits, register 312 and latch 31 have eight stages. When eight bits of the recovered NRZ data signal have been shifted into register 312, the frame clock signal provided by NAND gate 308 changes state from a binary zero state to a binary one state causing latch 313 to be transparent, coupling the received NRZ data signal from register 312 to its output.
While register 312 was shifting, latch 313 ~as held in the latched state by the binary zero state of the frame clock signal. Also, the return data signal loaded into register 312 is serially applied by NAND gates 314-316 to the return data signal line while the transmitted data `~signal is being received.
The data receiver of FIG. 3 re~uires a separate return data signal line for each additional data receiver included in the data transmission system. In order to couple a number of data receivers to the same return data signal line, it is necessary to provide capability fGr selectively addressing each data receiverO One way to provide for selectively addressing a number of data -13- ~7~,3~
receivers is to translnit an address signal before the data signal. Many different transmission formats provid-ing for an address signal prior to the data signal can be realized utilizing the data transmission scheme of the present invention. For example, the address signal and data signal may be separated by the word state of the true data and complement data signal lines if the data transr~lission scheme in FIG. 4 is used. According to another scheme, the address signal and data signal may be differentiated by providing the word state of the true data and complement data signal lines between each bit of the address signal and the bit state between each bit of the data signal. By utilizlng this scheme, variable length addresses may be defined while maintaining fixed length data words. The end of the address signal is identified by the bit state of the true data and comple-ment data signal lines occurring after the first bit of the following data signal. A data receiver which receives an eight-bit address signal followed by an eight-bit data signal transmitted according to this scheme is illustrated in FIG. 6.
P~eferring to FIG. 6, the data receiver illustrated there is essentially identical to the data receiver of FIG. 3, with the exception of the additional address register 320, address decoder 321 and gates 322-325.
Waveforms corresponding to labelled blocks in FIG. 6 for a typical address and data signal transmission are illustrated in FIG. 7, where the transmitted address sig-nal is 01010101, the transmitted data siynal is 11010001, and the return data signal is 01110101. In FIG. 6, address register 320 serially receives the NRZ data signal from data latGh 30~-306 in response to the word state of the true data and complement data signal lines, as detected by NAND gate 308 and invertin~ gate 322.
Since the word state is provided between each bit of the .
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address siynal, I~AND gate 30~ and inverting gate 322 provide clock pulses in response to the detected word state. The eight-bit address signal received by address reyister 320 is decoded by address decoder 21 and enables NAND gate 323 if the correct address for this receiver has been received and decoded. The data signal following the address signal is then serially shifted into re~ister 312 as described with reference to FIG. 3. A return data signal previously parallel loaded into register 312 is serially applied by way of inverting gate 324 to I~AND
gate 315 which also is enabled by address decoder 321 if the correct address has been received and decoded. The return data signal is coupled fro~n l~AND gate 315 by way of NAI7D gate 316 to open collector inverting gate 325 for application to the shared return data signal line. The open-collector inverting gate 325 is disabled until the address sic3nal is detected by the decoder 321 which then enables NAND gate 315. Since a number of different data receivers are coupled to the return data signal line, an open collector inverting gate 325 is utilized to inter-face each data receiver to the return data signal line.
Any other suitable tri-state busing devices could also be utilized for interfacing the data receivers to the return data signal line.
When all eight bits of the transmitted data signal have been serially shifted into register 312, NAND gate 323, having been enabled by address decoder 321, clocks the received data signal from register 312 into register 326 in response to the output from last bit latch 309, 30 310.
According to another feature of the present inven-tion, the data receiver in FIG. 6 may alert the data transmitter that a return data signal is available by putting a momentary interrupt signal on the return data signal line. In FIG. 6, NAND yate 314 is enabled to couple the interrupt signal to the return data signal ~L7~ 3~L
line by an output of the last bit latch 309, 310. The output of the last bit latch 309, 310 disables NAND gate 314 only during transmission of the return data siynal.
Thus, an interrupt signal can be coupled to the return data signal line by any receiver at any tirne except during the time interval during which a selected data receiver is transMitting a return data signal. Since the data transmitter has no way of telling which data receiver ~enerated the interrupt signal, the data transmitter will have to poll all data receivers after -receiving the interrupt signal.
The data transmitter in FIG. 2 and the data receiv-ers in FIGS. 3 and 6 can be constructed of conventional integrated circuit devices, such as the C~OS devices described in the CMOS Integrated Circuits Book, published by ~otorola Semiconductor Products, Inc., Austin, Texas, 1978. Furthermore, the electrical circuit devices comprising the data transmitter in FIG. 2 and the data receiver in FIGS. 3 and 6 can be readily integrated into a semiconductive substrate such that a data transmitter and data receiver can be separately, or both, provided in a single integrated circuit device.
The data transmission scheme of the present inven-tion can be advantageously utilized in many different data transmission systems. For example, the inventive data transmission scheme can be used to communicate data between a microprocessor and peripheral devices such as auxiliary memories, keyboards, displays and radio units as described in the aforementioned co-pending applica-tions. Likewise, the inventive data transmission schemecan be used to control a plurality of radio transrnitters located in geographically separated remote stations from a central control station. Delays and skewing due to long distances are not critical to proper transmission since the data transmission scheme is self-clocking and independent of speed and timing variations.
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In sul~nary, the data transmission scheme and apparatus of the present invention provide for reliable, self-clocking, bidirectional data transmission that is hi~hly immune to speed and timing variations. By utiliz-ing two bit binary states of the true data and complementdata signal lines taicen together, the inventive data transmission scheme is capable of uniquely defining the . beginning and end of a data signal and the binary states of the bits of a data signal, while also differentiating bet~een address and data si~nals. The exact two~bit binary states selected can be varied as long as only one signal line changes binary state for each state transi-tion, as illustrated in FIG. 4.
SELF-CLOCKING DATA TRANSMISSION SYSTEM
The instant application is related to now pending patent applications, Serial Number 368,042, by Kenneth A. Felix and James A. Pautler, entitled "Improved Method and Apparatus for : Detecting a Data Signal Including Repeated Data Words", and Serial Number 368,037, by John P. Byrns and Michael J. McClaughry, entitled "Phase-Encoded Data Signal Demodulator", both of which were filed on January 7, 1981, and are assigned to the instant ass~gnee .
.
.' 7Z31~
Background of the Invention The present invention relates generally to data transmission systems, and more particularly to an improved method and apparatus for the self-cloc~ing transr,lission of digital data signals.
~nong the self-c-locking data transmission techniques in the prior art, one technique commonly referred to as "polar return to zero" utilizes different voltage levels within a bit interval to encode a data signal. For example, a positive voltage level with respect to a reference voltage level indicates a binary one state, while a negative voltage level with respect to the reference volta~e level indicates a binary zero state.
Another technique commonly referred to as Manchester cod-ing provides a transition during each bit interval, where the direction of the transition determines the binary state of the bit. For example, a positive transition duriny a bit interval may represent a binary one bit, while a negative transition may represent a binary zero bit.
Elowever, in order to properly receive data signals transrlitted accordlng to these prior art techniques, it is essential that timing relationships between successive bits of the data signal be accurately maintained at the data transmitter and properly recognized at the data receiver. Further~nore, proper reception at t~he data receiver is also dependent on recovery of the clock signal and precise definition of the bit interval. Thus, transmission systems utilizing these prior art techniques are very sensitive to speed and timing variations in the transmission of the data signals, and require that receiving apparatus include expensive and complex cir-cuitry to compensate for such variations.
~7~3~
Summary of the Invention Accordingly, it is an object of the present inven-tion to provide an improved method and apparatus for self-clocking data transmission systems that accommodates expansive variations in the speed and timing of the transinission.
It is another object of the present invention to provide an improved self-clocking data transrnission system for provicin~ bidirectional data transrnission between a data translnitter and a pluralit~ of data receivers.
It is a further object of the present invention to provide an improved self-clocking data transmission system for providing data transmission between a data transmitter and a plurality of separately addressable data receivers.
It is a further object of the present invention to provide an improved self-clocking data transmission system for providing data transmission between a data transmitter and a plurality of data receivers each of which may request a data transmission from the trans-mitter .
In practicing the present invention, data signals having a plurality of binary bits are transmitted on two signal lines between a data transmitter and one or more data receivers of a self-clocking data transrnission system. Data signals are transmitted on the two signal lines by utilizing the four possible two-bit binary states of the two signal lines taken together. According to the data transmission scheme of the present invention, a first two-bit binary state of the signal lines is pro-vided both before and after the data signal, and for each bit of the data signal a second two-bit binary state of the signal lines followed by a third two-bit binary state _4~ 7~33~
of the signal lines is generated for a bit having a binary one staite and a fourth two bit binary state of the signal lines followed by a third two-bit binary state of the signal lines is yenerated for a bit having a binary zero state. As a result, the transmitted data signal is not only self-clocking, but also independent of the transmission fre~uency, thereby accommodating expansive variations in the time duration of successive bit inter-vals.
In the data transmission system of the present invention, a data transmitter is coupled to one or more data receivers by two signa:L lines on which data signals are transmitted according to the fore~oin~ data transmis-sion scheme. The data transmitter includes circuitry for 15 generatiny the two-bit binary states of the signal lines for each bit of a data signal to be transmitted. The receiving units include circuitry responsive to the third two-bit binary state of the signal lines for providing a clock signal. The receiving unit also includes first 20 storing circuitry responsive to the second and fourth two-bit binary states of the si~nal lines for storin~ an output signal having a binary one or zero state, respec-tively. Thus, the output signal of the first storing circuitry reflects the binary state of the successive 25 bits of the transmitted data signal. The output signal of the first storing circuitry is then stored into second storin~ circuitry in response to the elock signal. At the end of the transmission, the second storing circuitry holds the received data signal. The received data signal 30 i~ the second storing circuitry may then be ~tilized for accomplishiny any suitable function in the data receiver.
~lore particularly, there is ~rovided:
iA method of ser~ally tr~smittin~ a data signal from a signal source by means of first and second binary signals, 35 the data signal including a plurality of bi~ts each having a binary zero state or a binary one state, said method comprising the step~ of:
i~ (aj generating a first binary state of the first and _~ -4a~
33~
second signal~ before and after the data signal;
(b) generating for each ~it of the data ~ignal a second binary state of the fir~t si.gnal and the first binary state of the second signal for a bit having a binary zero state, and generating the first binary state of the first signal and the ~econd binary state of the second signal for a bit having a binary one state;
and (c) generating the ~econd binary tate of the first and ~econd signals between successive bits of the data signal.
There is also provided:
A m2thod of ~erially transmittin~ ~n address signal and a d~ta signal from a ~ignal 80urce by means of first and second binary signals, the address slgnal and data signal each including a plurality of bits ha~ing a binary zero state or a binary one state, said method compr~sing the steps of:
(a~ generating a first binary state of the first and second signals before the first b~t of the address signal and after the last bit of the data signal;
(b) generating for each bit of the address signal a seeond binary state of the first signal and the fir~t binary state of the second signal followed by the first binary state of the first and second signals for a bit having a binary zero state, and : ~enerating the first binary state of the first signal and the second binary state of the second signal followed by the first binary state of the first and second signals for a bit having a binary one state;
(c~ generating for each bit of the data signal the second binary tate of the first signal and the first binary state of the second signal for a bit ha~ing a binary zero ~tate, and generating the first binary state of the first signal and the second binary state of the second signal for a bit having a binary ~ne state; and (d) generating the ~econd binary ~tate of the first and 4~ 6econd signals between 6ucce~sive bits of the data signcll.
3.~'7'~3~
-4b-There is also provided-Apparatus for receiving a data signal ~rom first and ~econd binarv signals ~eriall~y tran~mitted by a signal source, the data signal including a plurality of bits each having a binary zero state or a binary one statP, the first and second signals having a first binary state ~efore and after the data signal, the ~irst ~ignal having a ~econd binary ~tate and the second signa:L ~aving a first binary state for data signal bits having a binary zero state, the ~irst signal having a first binary state and the æecond signal having a binary state for data signal bits having a binary one state, and the first and second signals having a second binary state between successive data signal bits, said receiving apparatus comprising:
; 15 first means responsive to the second binary state of the first and second signals for generating a clock signal;
second means coupled to the first and second signals for storing an output signal having a binary zero state in response to a second binary state of the first signal and a first binary state of the second signal, and storing an output signal having a binary one state in response to a first binary state of the first signal and a second binary state of the second signal; and third means coupled to the first means and second means for storing the second means output signal in response to the clock signal.
T~ere is further provided:
A ~ystem ror serially communicating data signals, each including a plurality of bits each having a binary zero state or a binary one state, between a transmitting unit and at least one receiving unit intercoupled by first and second binary signals, said system comprising:
a transmitting unit for transmitting a data signal, including:
a signal source for providing a data signal;
first m~ans for generating a first binary state of the - 'lc -33~
first and second signals before and after the data si~nal;
second means for generating for each bit of the data signal a second binary state of the first signal and a first ~nary state of the second siynal for a bit having a binary zero state, and the first binary sl:ate of the first signal and a second binary state of the second signal for a bit having a binary one state; and said second means generating the second binary state of the first and second signals between successive bits of the 0 data signal; and a receiving unit for receiving a data signal transmit-ted by the transmitting unit, including:
third means responsive to the second state of the first and second signals for generating a clock signal;
fourth means coupled to the first and second signals for storing an output signal having a binary zero state in response to a second binary state of the first signal and a first binary state of the second signal, and a binary one state in response to a first binary state of the first signal 0 and a second binary state of the second signal; and fifth means coupled to the third means and fourth means for storing successive binary states of the fourth ~eans out-put signal in response to thP third means clock signal.
Brief Vescription of the Drawings .
Fig. 1 is a block diagram of a self clocking data transmission system embodying the present invention.
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Fig. 2 is a block diagram of a data transmitter for the data transrnission system in Fig. 1.
Fig. 3 is a block diagram of a data receiver for the data transmission system in Fig. 1.
Fig. 4 is a state diagram illustrating the binary states that may be utilized to encode the data signals transmitted between the data transmitter and data receivers in the data transmission system in Fig. 1.
Fig. 5 is a timing diagram illustrating the wave 'orrns for various blocks of the data receiver in Fig. 3.
Fig. 6 is a block diagram of a different data receiver for the data transmission systern in Fig. 1.
~ 'ig. 7 is a ti;ning diagram of the waveforms for various blocks of the data receiver in Fig. ~.
Detailed Desc-ription of the Preferred Ernbodiment In FIG. 1, there is illustrated a block diagram of a self-clocking data transmission system embodying the present invention. Data transmitter 101 is coupled to data receivers 102-104 by two signal lines, labelled "true data" and "complement data". The data receivers 102-104 may also transmit return data signals to the data transrnitter by rneans of a shared signal line, labelled "return data", as shown for data receivers 103 and 104 or by means of a separate siynal line as for data receiver 102. The return data signals transmitted by the data receivers 102-104 on the return data signal line are transsnitted in synchronism with the data signals received from the data transmitter 101 on the true data and com-plelnent data signal lines. The data transmitter 101 and data receivers 102-104 may be in close proximity with one another or may be separated by great distances because the data transmission is self-clocking and is independent of the transmitting frequency. In the aforementioned -6- ~7~3~
related patent a~plications, the data transmit~er 101 is a microprocessor and the ~ata receivers 102-104 are interface adapters in the control circuitry of a portable radiotelephone.
According to the present invention, data is trans-mitted by the data translnitter 101 to the data receivers 102-lG4 by making use of the four two-bit binary states that can be assw~ed by the true data and complement data signal lines ta~en to~3ether. For example, referring to state dia~3ram of FIG. 4, a first two-bit binary state rnay be referred to as a "~ord state" 401, where the true data si~nal line has a binary one state and the com~lement data signal line has a binary one state. When no data is being transmitted, the word state 401 is provided on the true data and complement data signal lines. 1^1hen a data signal is to be transmitted, a transition is r,lade from the word state 401 to the zero state 402, represented as binary state 01, or to the one state 404, represented as the binary state 10, where the complement data signal line has a binary one state for binary zero bits of the data signal and the true data signal line has a binary one state for binary one bits of the data signal. For all succeeding bits of the data signal to be transmitted, a transition is first made to the bit state 403, repre-sented by the binary state 00, before a transition to theone state 404 or zero state 402. The two-bit binary states of the true data and complement data signal lines are set forth hereinbelow in TABLE I.
TAE~LE I
TRI~E DATA COMPLEMEI~T DATA TWO-BIT STATE
1 1 Word State 0 1 Zero State 1 0 One State 0 0 Bit State . ' ~ ., 3~
Furthermore, transitions between the states 401-404 in FIG. 4 are selected so that onl~ one signal line is changing binary state at a time. Transitions between the word state 401 and bit state 403 and between the one state 404 and zero state 402 are not allowed since the~
would require that the state of both the true clata and complement data signal lines change simultaneously. By limitin~ transitions between the binary states 401-404 to those where only one of the siynal lines is changin~
~inary state at a time, the effects of skewin~ and timin~3 variations are minimized. Moreover, by transmitting data signals as illustrated by the state diagram in FIG. 4, the trans;nission on the true data and complernent data signal lines is both self-clocking and independent of the transmitting frequency. The time duration between each of the state transitions illustrated in FIG. 4 need not be the sanle and may vary dynamically. Thus, according to the data transmission scheme of the present invention, the frequency of the data transmission may be entirely asynchronous with randomly varying time intervals between successive state transitions~
To summarize the transmission sequence, the true data and complement data signal lines have the word state 401 when no data is being transmitted (see waveforms in FIG. 5). For transmission of a data signal, two state transitions occur for each bit. For the first bit of the data si~nal, a transition is made from the word state 401 to the one state 404 or zero state 402, dependiny on the binary state of the bit to be transmitted. ~ext, a state transition is made to the bit state 403. Then, for each succeedin~ bit of the data signal, a transition is made to the one state 404 or the zero state 402 and then back to the bit state 403. Since a transition is Inade to the bit state 403 for each bit of the data si~nal to be transmitted, the bit state 403 can be utilized at the 33~
data receivers to yenerate a clock siynal. For the last bit of the data signal, the last state transition is made from the one state ~04 or zero state ~02 back to the word state 401. Returning to the word state 401, after the last bit of the data signal has been transmitted indi-cates to the data receivers 102-104 that a coMplete data signal has been transmitted.
In order to provide for the bidirectional transmis-sion of data siynals between the data transmitter 101 and the data receivers 102-104 in FIG. 1, another siynal line, referred to as the return data signal line, may be provided for carryin~ non-return-to-zero (~RZ) coded data signals from the data receivers 102-104. The data receivers 102-104`can transmit a return data signal on the return data signal line by utilizing the clock signal developed by detecting the bit state of the true data and compleMent data signal lines. In order to accommodate the transmission of return data slgnals, separate return data siynal lines can be provided to each data receiver, as for data receiver 102, or a number of data receivers, such as data receivers 103-104, can be connected to one return data signal line. If a number of data receivers are connected to the same return data signal line, it will be necessary to selectively address the particular data receiver that is to transmit a return data signal.
Many different addressing schemes can be utilized, such as, for example, utilizing a portion of the data signal transmitted by the data transmitter to provide an address, or transmitting separate address signals and data signals.
Referring to FIG. 2, there is illustrated a block diagram of data transmitter 101 in FIG. 1. When it is desired to transmit data, a data strobe pulse (a momen-tary binary one state) is applied to the strobe input of latch 201 for loadiny a new set of input data, which here ~.7~33~
is represented as an eight-bit binary signal. Latch 201 is transparent durillg data strobe pulse, and is otherilise latched. The data strobe s:ignal via inverting gate 202 also clocks the Q output of flip-flop 208 to a binary one state, which corresponds to a +V voltage level with respect to ground. The binary one state of the Q output or flip-flop 208 is coupled via OR 4ate 204 to produce a binary one state of the busy signal, indicating that the data transmitter is presently busy transmitting a data signal.
The shift clock signal coupled to the clock inputs of flip-flop 209 and reyisters 203 and 211 determines the rate at ~thich data is transmitted on the true data and complement data signal lines to the data receivers. The shift clock signal may be provided by a clock oscillator or by a remote device, such as a microcomputer. Accord-ing to the present invention, the shift clock signal need not be periodic and may vary dynamically in frequency over time and from transition to transition.
Once flip-flop 208 has been clocked by the data strobe signal, the Q output of flip-flop 209 is clocked to a binary one state at the next positive transition of the shift clock signal. The Q output from flip-flop 209 is coupled to the parallel/shift input of register 203 25 and to the D input of register 211. Thus, at the next positive transition of the shift clock signal, register 203 is parallel loaded with the data signal from latch 201 and the first stage of shift register 211 is loaded with a binary one. The binary one state of the Q output of flip-flop 209 is also used to reset flip-flop 208, maintain the busy signal at a binary one state via OR
gates 205 and 204, and apply the shift clock siynal to register 203 via OR gate 205, inverting gate 206 and OR
gate 207.
-10- ~723;3:~L
For the next eiyht cycle intervals of the shift clock signal, the data signal in register 203 is shifted right applying each bit in succession to inverting yate 216 and ~ND yate 219, while at the same tirne a binary one bit is shifted from stage to stage in shift register 211.
The outputs of shift reyister 211 are combine~ via OR
gate 212 for enabling AND gate 214 and for maintainincj a binary one state of the busy signal via OR gates 2C5 and 20~.
Prior to transmission of the data signal loaded into latch 201, the true data and complei,lent data signal lines were maintained at a binary one state by oR gate 212 via OR (3ate 218 and inverting gate 215. When OR yate 218 changes state from a binary zero state to a binary one state, the state of the true data and complement data signal lines will be determined by each bit of the data signal in reyister 203. During the binary one interval of the first shift clock signal, the true data and cor,l-plement data signal lines are Maintained at a binary one state by AND gate 213. Next, during each succeeding binary zero interval of the shift clock signal, AND gates 217 and 219 are enabled to apply successive bits of the data signal from reyister 203 to OR gates 220 and 221 for the complement data and true data signal lines, respec-tively. The true data signal lines will have a binaryone state for those bits of the data signal that likewise have a binary one state, wllile the complement data signal line will have a binary one state for those bits of the data signal which have a binary zero state. Ty~ical waveforms for the true data and complement data signal lines are illustrated by the wavefonns in FIG. 5.
At the same time that a data signal is being trans-.nitted on the complement data and true data signal lines, a return data signal may be received on the return data signal line, which is coupled to the D input of register 3~
203. Register 203, which is initially parallel loaded with the input data signal from latch 201, serially receives the return data siyllal as it is shifted to transmit the input data signal. Once the last bit of the input data signal has been transr,litted, OR yate 212 changes state from a bi.nary one state to a binary zero state and disables via OR ~ate 205 and inverting gate 206 the shift clock signal to register 203. Also, when the transmission is complete, register 203 provides the return data signal received from a data receiver at its outputs.
Referrin~ to FIG. 3, there is illustrated a detailed circuit diayram for data recéiver 102-104 in ~
haveforms corresponding to labelled blocks in FIG. 3 for a typical data signal transmission are illustrated in FIG. 4, where the transmitted data signal is 11010001 and the return data siynal is 01110101. The data receiver in FIG. 3 includes a data latch formed by NAND gates 305 and 306, which is set by NAND gate 303, which detects the one state (see FIG. 4) of the true data and complement data signal lines, and is reset by NAND gate 304, which detects the zero state of the true data and complement data signal lines. Compleitlents of the true data and complement data signal lines necessary for decoding the two-bit binary states thereon are provided by inverting gates 301 and 302. The output from data latch 305 and 306 is the recovered NRZ data signal and is coupled to the D input and high order parallel input of reyister 312.
The data receiver also includes a last bit latch fonned by NAND gates 309 and 310. The last bit latch 309-310 is set by the bit state of the true data and com-plement data signal lines, as detected by NAND gate 307, and is reset by the word state of the true data and co;n-plement data siynal lines, as detected by NAND (3ate 308.
~7;~33~
The last bit latch output signal is applied to NAND gate 314 and to the parallel/shift input of register 312.
A recovered bit cloc~ signal is provided by NAND
gate 311 in response to the bit state of the true data and complement data signal lines, as detected by NAND
gate 307. The bit clock signal is also forced to a binary one state by the word state of the true data and complement data signal lines, as detected by NAND gate 308.
When a data signal is transmitted to the data receiver in FIG. 3, register 312 is initially parallel loaded in response to the last bit latch outp~t signal and thereafter serially clocked in response to each posi-tive transition of the bit clock signal for shifting in the recovered NRZ data signal. Since the datâ siynals in the preferred embodiment have eight bits, register 312 and latch 31 have eight stages. When eight bits of the recovered NRZ data signal have been shifted into register 312, the frame clock signal provided by NAND gate 308 changes state from a binary zero state to a binary one state causing latch 313 to be transparent, coupling the received NRZ data signal from register 312 to its output.
While register 312 was shifting, latch 313 ~as held in the latched state by the binary zero state of the frame clock signal. Also, the return data signal loaded into register 312 is serially applied by NAND gates 314-316 to the return data signal line while the transmitted data `~signal is being received.
The data receiver of FIG. 3 re~uires a separate return data signal line for each additional data receiver included in the data transmission system. In order to couple a number of data receivers to the same return data signal line, it is necessary to provide capability fGr selectively addressing each data receiverO One way to provide for selectively addressing a number of data -13- ~7~,3~
receivers is to translnit an address signal before the data signal. Many different transmission formats provid-ing for an address signal prior to the data signal can be realized utilizing the data transmission scheme of the present invention. For example, the address signal and data signal may be separated by the word state of the true data and complement data signal lines if the data transr~lission scheme in FIG. 4 is used. According to another scheme, the address signal and data signal may be differentiated by providing the word state of the true data and complement data signal lines between each bit of the address signal and the bit state between each bit of the data signal. By utilizlng this scheme, variable length addresses may be defined while maintaining fixed length data words. The end of the address signal is identified by the bit state of the true data and comple-ment data signal lines occurring after the first bit of the following data signal. A data receiver which receives an eight-bit address signal followed by an eight-bit data signal transmitted according to this scheme is illustrated in FIG. 6.
P~eferring to FIG. 6, the data receiver illustrated there is essentially identical to the data receiver of FIG. 3, with the exception of the additional address register 320, address decoder 321 and gates 322-325.
Waveforms corresponding to labelled blocks in FIG. 6 for a typical address and data signal transmission are illustrated in FIG. 7, where the transmitted address sig-nal is 01010101, the transmitted data siynal is 11010001, and the return data signal is 01110101. In FIG. 6, address register 320 serially receives the NRZ data signal from data latGh 30~-306 in response to the word state of the true data and complement data signal lines, as detected by NAND gate 308 and invertin~ gate 322.
Since the word state is provided between each bit of the .
7~
address siynal, I~AND gate 30~ and inverting gate 322 provide clock pulses in response to the detected word state. The eight-bit address signal received by address reyister 320 is decoded by address decoder 21 and enables NAND gate 323 if the correct address for this receiver has been received and decoded. The data signal following the address signal is then serially shifted into re~ister 312 as described with reference to FIG. 3. A return data signal previously parallel loaded into register 312 is serially applied by way of inverting gate 324 to I~AND
gate 315 which also is enabled by address decoder 321 if the correct address has been received and decoded. The return data signal is coupled fro~n l~AND gate 315 by way of NAI7D gate 316 to open collector inverting gate 325 for application to the shared return data signal line. The open-collector inverting gate 325 is disabled until the address sic3nal is detected by the decoder 321 which then enables NAND gate 315. Since a number of different data receivers are coupled to the return data signal line, an open collector inverting gate 325 is utilized to inter-face each data receiver to the return data signal line.
Any other suitable tri-state busing devices could also be utilized for interfacing the data receivers to the return data signal line.
When all eight bits of the transmitted data signal have been serially shifted into register 312, NAND gate 323, having been enabled by address decoder 321, clocks the received data signal from register 312 into register 326 in response to the output from last bit latch 309, 30 310.
According to another feature of the present inven-tion, the data receiver in FIG. 6 may alert the data transmitter that a return data signal is available by putting a momentary interrupt signal on the return data signal line. In FIG. 6, NAND yate 314 is enabled to couple the interrupt signal to the return data signal ~L7~ 3~L
line by an output of the last bit latch 309, 310. The output of the last bit latch 309, 310 disables NAND gate 314 only during transmission of the return data siynal.
Thus, an interrupt signal can be coupled to the return data signal line by any receiver at any tirne except during the time interval during which a selected data receiver is transMitting a return data signal. Since the data transmitter has no way of telling which data receiver ~enerated the interrupt signal, the data transmitter will have to poll all data receivers after -receiving the interrupt signal.
The data transmitter in FIG. 2 and the data receiv-ers in FIGS. 3 and 6 can be constructed of conventional integrated circuit devices, such as the C~OS devices described in the CMOS Integrated Circuits Book, published by ~otorola Semiconductor Products, Inc., Austin, Texas, 1978. Furthermore, the electrical circuit devices comprising the data transmitter in FIG. 2 and the data receiver in FIGS. 3 and 6 can be readily integrated into a semiconductive substrate such that a data transmitter and data receiver can be separately, or both, provided in a single integrated circuit device.
The data transmission scheme of the present inven-tion can be advantageously utilized in many different data transmission systems. For example, the inventive data transmission scheme can be used to communicate data between a microprocessor and peripheral devices such as auxiliary memories, keyboards, displays and radio units as described in the aforementioned co-pending applica-tions. Likewise, the inventive data transmission schemecan be used to control a plurality of radio transrnitters located in geographically separated remote stations from a central control station. Delays and skewing due to long distances are not critical to proper transmission since the data transmission scheme is self-clocking and independent of speed and timing variations.
-16- ~t7~33~
In sul~nary, the data transmission scheme and apparatus of the present invention provide for reliable, self-clocking, bidirectional data transmission that is hi~hly immune to speed and timing variations. By utiliz-ing two bit binary states of the true data and complementdata signal lines taicen together, the inventive data transmission scheme is capable of uniquely defining the . beginning and end of a data signal and the binary states of the bits of a data signal, while also differentiating bet~een address and data si~nals. The exact two~bit binary states selected can be varied as long as only one signal line changes binary state for each state transi-tion, as illustrated in FIG. 4.
Claims (21)
1. A method of serially transmitting a data signal from a signal source by means of first and second binary signals, the data signal including a plurality of bits each having a binary zero state or a binary one state, said method comprising the steps of:
(a) generating a first binary state of the first and second signals before and after the data signal;
(b) generating for each bit of the data signal a second binary state of the first signal and the first binary state of the second signal for a bit having a binary zero state, and generating the first binary state of the first signal and the second binary state of the second signal for a bit having a binary one state;
and (c) generating the second binary state of the first and second signals between successive bits of the data signal.
(a) generating a first binary state of the first and second signals before and after the data signal;
(b) generating for each bit of the data signal a second binary state of the first signal and the first binary state of the second signal for a bit having a binary zero state, and generating the first binary state of the first signal and the second binary state of the second signal for a bit having a binary one state;
and (c) generating the second binary state of the first and second signals between successive bits of the data signal.
2. The method according to claim 1, further including the step of repeating steps (b) and (c) for transmitting subsequent data signals.
3. The method according to claim 1, further including the step of generating a clock signal having a dynamically varying frequency, said step (b) generating the respective binary states of the first and second signals for each bit of the data signal in response to the clock signal.
4. The method according to claim 1, further including the step of generating a clock signal having a frequency varying over a predetermined range of frequencies, said step (b) generating the respective binary states of the first and second signals for each bit of the data signal in response to the clock signal.
5. The method according to claim 1, further including the step of generating a clock signal having a predetermined frequency, said step (b) generating the respective binary states of the first and second signals for each bit of the data signal in response to the clock signal.
6. A method of serially transmitting an address signal and a data signal from a signal source by means of first and second binary signals, the address signal and data signal each including a plurality of bits having a binary zero state or a binary one state, said method comprising the steps of:
(a) generating a first binary state of the first and second signals before the first bit of the address signal and after the last bit of the data signal;
(b) generating for each bit of the address signal a second binary state of the first signal and the first binary state of the second signal followed by the first binary state of the first and second signals for a bit having a binary zero state, and generating the first binary state of the first signal and the second binary state of the second signal followed by the first binary state of the first and second signals for a bit having a binary one state;
(c) generating for each bit of the data signal the second binary state of the first signal and the first binary state of the second signal for a bit having a binary zero state, and generating the first binary state of the first signal and the second binary state of the second signal for a bit having a binary one state; and (d) generating the second binary state of the first and second signals between successive bits of the data signal.
(a) generating a first binary state of the first and second signals before the first bit of the address signal and after the last bit of the data signal;
(b) generating for each bit of the address signal a second binary state of the first signal and the first binary state of the second signal followed by the first binary state of the first and second signals for a bit having a binary zero state, and generating the first binary state of the first signal and the second binary state of the second signal followed by the first binary state of the first and second signals for a bit having a binary one state;
(c) generating for each bit of the data signal the second binary state of the first signal and the first binary state of the second signal for a bit having a binary zero state, and generating the first binary state of the first signal and the second binary state of the second signal for a bit having a binary one state; and (d) generating the second binary state of the first and second signals between successive bits of the data signal.
7. The method according to claim 6, further including the step of repeating steps (d) and (e) for transmitting subsequent data signals.
8. The method according to claim 6, further including the step of generating a clock signal having a dynamically varying frequency, said steps (b) and (d) generating the respective binary states of the first and second signals for each bit in response to the clock signal.
9. The method according to claim 6, further including the step of generating a clock signal having a frequency varying over a predetermined range of frequencies, said steps (b) and (d) generating the respective binary state of the first and second signals for each bit in response to the clock signal.
10. The method according to claim 6, further including the step of generating a clock signal having a predetermined frequency, said steps (b) and (d) generating the respective binary states of the first and second signals for each bit in response to the clock signal.
11. Apparatus for serially transmitting a data signal from a signal source by means of first and second binary signals, the data signal including a plurality of bits each having a binary zero state or a binary one state, said apparatus comprising:
first means for generating a first binary state of the first and second signals before and after the data signal;
second means for generating for each bit of the data signal a second binary state of the first signal and the first binary state of the second signal for a bit having a binary zero state, and generating a first binary state of the first signal and the second binary state of the second signal for a bit having a binary one state, and said second means generating the second binary state of the first and second signals between successive bits of the data signal.
first means for generating a first binary state of the first and second signals before and after the data signal;
second means for generating for each bit of the data signal a second binary state of the first signal and the first binary state of the second signal for a bit having a binary zero state, and generating a first binary state of the first signal and the second binary state of the second signal for a bit having a binary one state, and said second means generating the second binary state of the first and second signals between successive bits of the data signal.
12. The data transmitting apparatus according to claim 11, further including means for generating a clock signal, said second generating means generating the respective binary states of the first and second signals for each bit of the data signal in response to the clock signal.
13. The data transmitting apparatus according to claim 12, further including means for providing a strobe signal and means responsive to the strobe signal for storing a data signal, said second generating means responsive to the data signal stored in the storing means for generating the respec-tive states of the first and second signals.
14. Apparatus for receiving a data signal from first and second binary signals serially transmitted by a signal source, the data signal including a plurality of bits each having a binary zero state or a binary one state, the first and second signals having a first binary state before and after the data signal, the first signal having a second binary state and the second signal having a first binary state for data signal bits having a binary zero state, the first signal having a first binary state and the second signal having a binary state for data signal bits having a binary one state, and the first and second signals having a second binary state between successive data signal bits, said receiving apparatus comprising:
first means responsive to the second binary state of the first and second signals for generating a clock signal;
second means coupled to the first and second signals for storing an output signal having a binary zero state in response to a second binary state of the first signal and a first binary state of the second signal, and storing an output signal having a binary one state in response to a first binary state of the first signal and a second binary state of the second signal; and third means coupled to the first means and second means for storing the second means output signal in response to the clock signal.
first means responsive to the second binary state of the first and second signals for generating a clock signal;
second means coupled to the first and second signals for storing an output signal having a binary zero state in response to a second binary state of the first signal and a first binary state of the second signal, and storing an output signal having a binary one state in response to a first binary state of the first signal and a second binary state of the second signal; and third means coupled to the first means and second means for storing the second means output signal in response to the clock signal.
15. The data receiving apparatus according to claim 14, further including a signal source for providing a return data signal having a plurality of binary bits, and means responsive to the clock signal for generating for successive bits of the return data signal a corresponding binary state of a return signal.
16. The data receiving apparatus according to claim 15, further including means for generating a pulsed binary state of the return signal line to indicate that a return data signal is available for transmission.
17. A system for serially communicating data signals, each including a plurality of bits each having a binary zero state or a binary one state, between a transmitting unit and at least one receiving unit intercoupled by first and second binary signals, said system comprising:
a transmitting unit for transmitting a data signal, including:
a signal source for providing a data signal;
first means for generating a first binary state of the first and second signals before and after the data signal;
second means for generating for each bit of the data signal a second binary state of the first signal and a first binary state of the second signal for a bit having a binary zero state, and the first binary state of the first signal and a second binary state of the second signal for a bit having a binary one state; and said second means generating the second binary state of the first and second signals between successive bits of the data signal; and a receiving unit for receiving a data signal transmit-ted by the transmitting unit, including:
third means responsive to the second state of the first and second signals for generating a clock signal;
fourth means coupled to the first and second signals for storing an output signal having a binary zero state in response to a second binary state of the first signal and a first binary state of the second signal, and a binary one state in response to a first binary state of the first signal and a second binary state of the second signal; and fifth means coupled to the third means and fourth means for storing successive binary states of the fourth means out-put signal in response to the third means clock signal.
a transmitting unit for transmitting a data signal, including:
a signal source for providing a data signal;
first means for generating a first binary state of the first and second signals before and after the data signal;
second means for generating for each bit of the data signal a second binary state of the first signal and a first binary state of the second signal for a bit having a binary zero state, and the first binary state of the first signal and a second binary state of the second signal for a bit having a binary one state; and said second means generating the second binary state of the first and second signals between successive bits of the data signal; and a receiving unit for receiving a data signal transmit-ted by the transmitting unit, including:
third means responsive to the second state of the first and second signals for generating a clock signal;
fourth means coupled to the first and second signals for storing an output signal having a binary zero state in response to a second binary state of the first signal and a first binary state of the second signal, and a binary one state in response to a first binary state of the first signal and a second binary state of the second signal; and fifth means coupled to the third means and fourth means for storing successive binary states of the fourth means out-put signal in response to the third means clock signal.
18. The data communication system according to claim 17, wherein said transmitting unit further includes sixth means for generating a clock signal, said second means generating the respective binary states of the first and second signals for each bit in response to the clock signal.
19. The data communication system according to claim 18 further including a binary return signal between the trans-mitting unit and receiving unit, said receiving unit further including a signal source for providing a return data signal having a plurality of binary hits, and seventh means respon-sive to the third means clock signal for generating for sue-cessive bits of the return data signal a corresponding binary state of the return signal, and the transmitting unit further including eighth means coupled to the return signal for storing in response to the sixth means clock signal successive binary states of the return signal.
20. The data communication system according to claim 19, wherein said receiving unit further includes nineth means for generating a pulsed binary state of the return signal to indicate that a return data signal is available for trans-mission, said transmitting unit including tenth means coupled to the return signal for detecting said pulsed binary state and enabling the transmitting unit to transmit a data signal.
21. The data communication system according to claim 19 or 20, including a plurality of said receiving units each coupled to the first and second signals and the return signal.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/187,303 | 1980-09-15 | ||
| US06/187,303 US4369516A (en) | 1980-09-15 | 1980-09-15 | Self-clocking data transmission system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1172331A true CA1172331A (en) | 1984-08-07 |
Family
ID=22688430
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000384151A Expired CA1172331A (en) | 1980-09-15 | 1981-08-19 | Self-clocking data transmission system |
Country Status (10)
| Country | Link |
|---|---|
| US (1) | US4369516A (en) |
| EP (1) | EP0059724B1 (en) |
| JP (1) | JPH0459819B2 (en) |
| AU (1) | AU544403B2 (en) |
| BR (1) | BR8108793A (en) |
| CA (1) | CA1172331A (en) |
| DK (1) | DK163471C (en) |
| MX (1) | MX151315A (en) |
| SE (1) | SE8203028L (en) |
| WO (1) | WO1982001111A1 (en) |
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-
1980
- 1980-09-15 US US06/187,303 patent/US4369516A/en not_active Expired - Lifetime
-
1981
- 1981-08-14 AU AU75805/81A patent/AU544403B2/en not_active Expired
- 1981-08-14 JP JP56502845A patent/JPH0459819B2/ja not_active Expired - Lifetime
- 1981-08-14 WO PCT/US1981/001094 patent/WO1982001111A1/en active IP Right Grant
- 1981-08-14 EP EP81902354A patent/EP0059724B1/en not_active Expired
- 1981-08-14 BR BR8108793A patent/BR8108793A/en not_active IP Right Cessation
- 1981-08-19 CA CA000384151A patent/CA1172331A/en not_active Expired
- 1981-09-14 MX MX189173A patent/MX151315A/en unknown
-
1982
- 1982-05-14 DK DK217482A patent/DK163471C/en not_active IP Right Cessation
- 1982-05-14 SE SE8203028A patent/SE8203028L/en not_active Application Discontinuation
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57501409A (en) | 1982-08-05 |
| US4369516A (en) | 1983-01-18 |
| EP0059724A4 (en) | 1983-02-09 |
| SE8203028L (en) | 1982-05-14 |
| EP0059724A1 (en) | 1982-09-15 |
| AU544403B2 (en) | 1985-05-23 |
| DK163471C (en) | 1992-07-20 |
| JPH0459819B2 (en) | 1992-09-24 |
| WO1982001111A1 (en) | 1982-04-01 |
| AU7580581A (en) | 1982-04-14 |
| MX151315A (en) | 1984-11-08 |
| BR8108793A (en) | 1982-08-10 |
| DK217482A (en) | 1982-05-14 |
| DK163471B (en) | 1992-03-02 |
| EP0059724B1 (en) | 1985-06-12 |
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