CA1178355A - Local network interface for use in a multi-station word processing system - Google Patents
Local network interface for use in a multi-station word processing systemInfo
- Publication number
- CA1178355A CA1178355A CA000399924A CA399924A CA1178355A CA 1178355 A CA1178355 A CA 1178355A CA 000399924 A CA000399924 A CA 000399924A CA 399924 A CA399924 A CA 399924A CA 1178355 A CA1178355 A CA 1178355A
- Authority
- CA
- Canada
- Prior art keywords
- data
- data processing
- communications
- operatively connected
- processing stations
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000012545 processing Methods 0.000 title claims abstract description 56
- 238000004891 communication Methods 0.000 claims abstract description 103
- 230000006854 communication Effects 0.000 claims abstract description 103
- 230000005540 biological transmission Effects 0.000 claims abstract description 22
- 238000012546 transfer Methods 0.000 claims description 10
- 230000001276 controlling effect Effects 0.000 abstract description 4
- 230000006870 function Effects 0.000 description 7
- 230000003213 activating effect Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000011084 recovery Methods 0.000 description 2
- 230000001010 compromised effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000003455 independent Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Buffering arrangements
- H04L49/9084—Reactions to storage capacity overflow
- H04L49/9089—Reactions to storage capacity overflow replacing packets in a storage arrangement, e.g. pushout
- H04L49/9094—Arrangements for simultaneous transmit and receive, e.g. simultaneous reading/writing from/to the storage element
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
- G06F13/128—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine for dedicated transfers to a network
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
- G06F13/376—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a contention resolving method, e.g. collision detection, collision avoidance
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/407—Bus networks with decentralised control
- H04L12/413—Bus networks with decentralised control with random access, e.g. carrier-sense multiple-access with collision detection (CSMA-CD)
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Buffering arrangements
Abstract
LOCAL NETWORK INTERFACE FOR USE IN A MULTI-STATION WORD PROCESSING SYSTEM
ABSTRACT
A local network interface for use in a network for enabling each of a plurality of data processing stations to communicate with one another via a communi-cations medium. The local network interface is con-nected between the communications medium and the data processing stations. The local network interface includes a processor, a direct memory access (DMA) controller connected to the processor, means for con-trolling communications connected between the communi-cations medium and the processor, and memory means which is connected to the processor, to the means for con-trolling communications, and to the DMA controller.
Data residing in the memory means may be accessed for transmission to, and may be updated from, the communi-cations medium via the local network interface.
ABSTRACT
A local network interface for use in a network for enabling each of a plurality of data processing stations to communicate with one another via a communi-cations medium. The local network interface is con-nected between the communications medium and the data processing stations. The local network interface includes a processor, a direct memory access (DMA) controller connected to the processor, means for con-trolling communications connected between the communi-cations medium and the processor, and memory means which is connected to the processor, to the means for con-trolling communications, and to the DMA controller.
Data residing in the memory means may be accessed for transmission to, and may be updated from, the communi-cations medium via the local network interface.
Description
~7~
The present invention relates to network communi-cation systems and more particularly, to local network interface systems for use in a word processing system.
Description of the Prior Art To allow two or more so-called intelligent terminals to communicate with each other, various co~munication systems, called networks, have been developed. These networks allow terminals, work stations, or data processing stations to share each other's resources when required. A common communication medium is usually employed over which data can be transferred among the stations.
The communication medium most commonly employed i5 a coaxial cable, along which a plurality o~ taps are located. Stations can be connected directly to the coaxial cable via the taps, or stations can be connected to each other via a nodal point or node, which in turn is connected to the coaxial cable via a tap. The tap allows the node to broadcast data to and receive data mg/~ - 1 -
The present invention relates to network communi-cation systems and more particularly, to local network interface systems for use in a word processing system.
Description of the Prior Art To allow two or more so-called intelligent terminals to communicate with each other, various co~munication systems, called networks, have been developed. These networks allow terminals, work stations, or data processing stations to share each other's resources when required. A common communication medium is usually employed over which data can be transferred among the stations.
The communication medium most commonly employed i5 a coaxial cable, along which a plurality o~ taps are located. Stations can be connected directly to the coaxial cable via the taps, or stations can be connected to each other via a nodal point or node, which in turn is connected to the coaxial cable via a tap. The tap allows the node to broadcast data to and receive data mg/~ - 1 -
- 2 -from all other nodes or to and from individually connected stations on the communication network. Any station on the network may initiate a transmission of data on a free channel of the communication medium.
In many systems, nodes are devices specially designed to transfer data between two data processing stations, between two communications channels or between two branches or segments of a communications channel.
Qften these nodes are complex special purpose devices, not required for any function other than for transferring information, which tend to make the communications system or network complicated.
Another problem heretofore inherent in networks having separate intelligent data processing stations connected to each other via a communications medium is data handling and the supervision thereof. In many previous systems, a processor, CPU or microprocessor included in each data processing station controls data transfer between its associated station and the communi-cations channel to which it is connected. The supervisionof this data transfer function can be time consuming for a processor whose time should be better spent performing other tasks. A system in which a great amount of data is transferred among a number of stations at relatively high speed requires an appreciable amount of processor supervision in the aforementioned systems. Clearly, the greater the amount of data transfer, the more processor time must be consumed in performing this function.
SUMMARY OF THE INVENTION
The present invention is intended to simplify network components by allowing any one of a plurality of data processing stations to function both as an indepen-dent work station and as a nodal point for the network between two branches of the communication medium.
The present invention also eliminates the require-ment for speciali~ed components to function as nodal points for the network.
In accordance with one aspect of the present invention, a data communications network for use in a data processing system is provided, which network comprises a plurality of data processing stations adapted to transmit and to receive data via a common communications channel, a common communications channel for transferring data from one of the stations operatively connected to it to another of the stations operatively connected to it. The communications channel has a first segment and a second segment. One of the stations is a nodal point data processing station operatively connected between the first segment and the second segment of the communications channel so that data generated by any one of the stations operatively connected to one of the communications channel segments may be transferred to another of the stations operatively connected to the other communications channel segment via the nodal point data processing station.
The present invention is also intended to minimize or eliminate the time during which a processor must supervise data transfer between its associated data processing station and the communications channel to which it is connected.
In accordance with another aspect of the present invention, there is provided a local network interface for use in a network for enabling each of a plurality of data processing stations to communicate with one another via a communications medium. The local network interface is connected between the communications medium and the data processing stations. The local network interface includes a processor, a direct memory access (DMA) controller connected to the processor, means for control-ling communications connected between the communications medium and the processor, and memory means which is connected to the processor, to the means for controlling communications, and to the DMA controller. Data residing in the memory means may be accessed for transmission to, 7~
and may be updated from, the communications medium via the local network interface.
BRIEF DESCRIPTION OF THE DRAWING
FIGURE 1 is a schematic block diagram in accordance with the present invention;
FIGURE 2 is a block diagram of one embodiment of the configuration of a neiwork; and FIGURE 3 is a flow chart showing the operation of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
The local network interface of the present invention provides a means for attaching two or more word or data processors to a common network so that resources may be shared within the network. Such shared resources can be common disk storage, for example, or common printers. As many as 32 data processing stations or more can be attached to a common co-axial cable which ean be up to one mile in length. Transmission rates in such a network system are on the order of one megahertz.
Referring now to FIGURE 1, the local network interface consists of an Intel Corp. model number 8085 mieroprocessor 10, a model number 8237-5 direct memory aeeess (DMA) eontroller, a Signetics CorpO model number 2652 eommunications controller 14 and at least 16K bytes of dynamic memory 16 which is refreshed by an Intel Corp. model number 8202A dynamie memory controller 18.
The local network interface in this embodiment also includes an interprocessor communieations (IPC) interfaee or eontroller 20 to allow the network to be attached to other proeessors in the system. The use of such an IPC
controller 20 is described in detail in copending Canadian Patent Application Serial No. 383,500 filed August 10, mg/~ - 4 -1981, for 'Communications Systems for a Word Processing System Employing Distributed Processing Circuitry .
An oscillator and timer 22 is connected to the processor 10 via lines which provide a -timing signal called phi (~) and a RESTART (RST) 7.5 signal used for timing out the processor 10 communications operations.
The IPC controller 20 is connected to both the processor 10 and the refresh memory controller 18 via read (RD) and write (WR) lines. The IPC controller 20 is also connected to the processor 10 via input and output lines (SID and SOD respectively) and by a RESTART (RST) 5.5 line. The IPC controller 20 communicates with other processors on the network over a bus, not shown.
Data and address latches shown generally at reference numeral 24 are connected between the DMA
controller 12 and processor 10 and the internal data and address buses 26 and 28 respectively. The internal data bus 26 interconnects the communications controller 14 with the memory 16 via a transceiver 29 and is also connected to an IPC data bus, not shown. Similarly, the internal address bus 28 interconnects the communications controller 14 with the refresh memory controller 18 and is also connected to an IPC address bus, not shown, via an address transceiver 30.
A boot PROM and associated l-ogic 32 is optionally connected between the internal address and data buses 28 and 26, respectively.
An input/output (I/O) decoder 34 is connected to the internal address bus 28 and the communications controller 14. The I/O decoder 34 also interconnects a transmitter state controller 36 which controls data communications of the communications controller 14, and an interrupt controller 38 which is directly connected to the internal data bus 26 and processor 10 via its interrupt (INT) line.
Also connected to the internal data bus 26 is a status register 40 which receives input signals from the I/O decoder 34 and the communications controller 14. A
mg/-~\ 5 -
In many systems, nodes are devices specially designed to transfer data between two data processing stations, between two communications channels or between two branches or segments of a communications channel.
Qften these nodes are complex special purpose devices, not required for any function other than for transferring information, which tend to make the communications system or network complicated.
Another problem heretofore inherent in networks having separate intelligent data processing stations connected to each other via a communications medium is data handling and the supervision thereof. In many previous systems, a processor, CPU or microprocessor included in each data processing station controls data transfer between its associated station and the communi-cations channel to which it is connected. The supervisionof this data transfer function can be time consuming for a processor whose time should be better spent performing other tasks. A system in which a great amount of data is transferred among a number of stations at relatively high speed requires an appreciable amount of processor supervision in the aforementioned systems. Clearly, the greater the amount of data transfer, the more processor time must be consumed in performing this function.
SUMMARY OF THE INVENTION
The present invention is intended to simplify network components by allowing any one of a plurality of data processing stations to function both as an indepen-dent work station and as a nodal point for the network between two branches of the communication medium.
The present invention also eliminates the require-ment for speciali~ed components to function as nodal points for the network.
In accordance with one aspect of the present invention, a data communications network for use in a data processing system is provided, which network comprises a plurality of data processing stations adapted to transmit and to receive data via a common communications channel, a common communications channel for transferring data from one of the stations operatively connected to it to another of the stations operatively connected to it. The communications channel has a first segment and a second segment. One of the stations is a nodal point data processing station operatively connected between the first segment and the second segment of the communications channel so that data generated by any one of the stations operatively connected to one of the communications channel segments may be transferred to another of the stations operatively connected to the other communications channel segment via the nodal point data processing station.
The present invention is also intended to minimize or eliminate the time during which a processor must supervise data transfer between its associated data processing station and the communications channel to which it is connected.
In accordance with another aspect of the present invention, there is provided a local network interface for use in a network for enabling each of a plurality of data processing stations to communicate with one another via a communications medium. The local network interface is connected between the communications medium and the data processing stations. The local network interface includes a processor, a direct memory access (DMA) controller connected to the processor, means for control-ling communications connected between the communications medium and the processor, and memory means which is connected to the processor, to the means for controlling communications, and to the DMA controller. Data residing in the memory means may be accessed for transmission to, 7~
and may be updated from, the communications medium via the local network interface.
BRIEF DESCRIPTION OF THE DRAWING
FIGURE 1 is a schematic block diagram in accordance with the present invention;
FIGURE 2 is a block diagram of one embodiment of the configuration of a neiwork; and FIGURE 3 is a flow chart showing the operation of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
The local network interface of the present invention provides a means for attaching two or more word or data processors to a common network so that resources may be shared within the network. Such shared resources can be common disk storage, for example, or common printers. As many as 32 data processing stations or more can be attached to a common co-axial cable which ean be up to one mile in length. Transmission rates in such a network system are on the order of one megahertz.
Referring now to FIGURE 1, the local network interface consists of an Intel Corp. model number 8085 mieroprocessor 10, a model number 8237-5 direct memory aeeess (DMA) eontroller, a Signetics CorpO model number 2652 eommunications controller 14 and at least 16K bytes of dynamic memory 16 which is refreshed by an Intel Corp. model number 8202A dynamie memory controller 18.
The local network interface in this embodiment also includes an interprocessor communieations (IPC) interfaee or eontroller 20 to allow the network to be attached to other proeessors in the system. The use of such an IPC
controller 20 is described in detail in copending Canadian Patent Application Serial No. 383,500 filed August 10, mg/~ - 4 -1981, for 'Communications Systems for a Word Processing System Employing Distributed Processing Circuitry .
An oscillator and timer 22 is connected to the processor 10 via lines which provide a -timing signal called phi (~) and a RESTART (RST) 7.5 signal used for timing out the processor 10 communications operations.
The IPC controller 20 is connected to both the processor 10 and the refresh memory controller 18 via read (RD) and write (WR) lines. The IPC controller 20 is also connected to the processor 10 via input and output lines (SID and SOD respectively) and by a RESTART (RST) 5.5 line. The IPC controller 20 communicates with other processors on the network over a bus, not shown.
Data and address latches shown generally at reference numeral 24 are connected between the DMA
controller 12 and processor 10 and the internal data and address buses 26 and 28 respectively. The internal data bus 26 interconnects the communications controller 14 with the memory 16 via a transceiver 29 and is also connected to an IPC data bus, not shown. Similarly, the internal address bus 28 interconnects the communications controller 14 with the refresh memory controller 18 and is also connected to an IPC address bus, not shown, via an address transceiver 30.
A boot PROM and associated l-ogic 32 is optionally connected between the internal address and data buses 28 and 26, respectively.
An input/output (I/O) decoder 34 is connected to the internal address bus 28 and the communications controller 14. The I/O decoder 34 also interconnects a transmitter state controller 36 which controls data communications of the communications controller 14, and an interrupt controller 38 which is directly connected to the internal data bus 26 and processor 10 via its interrupt (INT) line.
Also connected to the internal data bus 26 is a status register 40 which receives input signals from the I/O decoder 34 and the communications controller 14. A
mg/-~\ 5 -
3~i CARRIER DETECT signal may also be supplied to the status register 40. The status register 40 is adapted to send a signal to the processor 10 over a RESTART (RST) 6.5 line to indicate the status of the communications cable, as hereinafter descrihed.
A data encoder/decoder is provided at reference numeral 42 to convert data from the communications controller 14 into Manchester non-return-to-zero (NRZ) format for transmission over the co~munications cable.
The Manchester code is a bi-phase code described in detail in '-Encoding Schemes Support High Density Digital Data Recording'', by R. Severt published in ''Computer Design' May 1980.
The local network interface is located on a single printed circuit board positioned within a housing 50 or floor module 60 such as is shown and described, for example, in applicant's copending application Serial No. 383,501, filed August 10, 1981, for Word Processing System Employing a Plurality of General Purpose Processor Circuits . The interface allows the above-identified local system to communicate with the network. Unlike other network communication systems, the present invention requires no complex circuitry for data collision detection as is explained in detail hereinafter.
~ eferring now to FIGURE 2, individual data processing stations 50 can be attached to the communications co-axial cable or channel 52 by means of a tap 54.
The tap only slightly affects the cable 52. Accordingly, the transmission characteristics of the cable 52 are not significantly disturbed. The tap 54 can be located up to 200 feet from its corresponding station 50.
Normally the cable 52 is laid out in a substantially straight line in the ceiling or the floor of a building and users attach their stations 50 to the cable 52 with line lengths 56 of up to 200 feet. The line 56 includes the following signal lines: transmit enable (XMT ENABLE), receive data (RCV DATA) and transmit data (XMT DATA).
mg/~ - 6 -:~7~
The configuration of data processing stations 50 on the network can take a variety of forms. A station - 50 can be directly connected to the communications cable 52 via a tap 54, as shown generall~ at reference numeral 58. A number of work stations 50 can also be connected to a floor module 60 subsystem or cluster, as shown generally at reference numeral 62, which in turn is connected via a tap 54 to the cable 52. Moreover, two local network segments can be interconnected by means of a floor module 60 acting as a nodal point, as shown generally at reference numeral 64. No special modifi-cation to the local network interface is required to adapt a floor module 60 containing a local network interface for use as a nodal point. It should be appreciated that the afore-mentioned three configuration elements provide unlimited flexibility in arranging data processing stations 50 on the network and that the present disclosure is not intended to be limited to the configuration shown and described in FIGURE 2.
Referring also to FIGURE 1, the local network interface functions as follows. Information from the communications channel 52 (the co-axial cable) is transferred via the tap 54 to the local network residing in the data processing station 50 or floor module 60.
Information on the communications channel 52 is encoded by the encoder/decoder 42 using a Manchester code, as described, for example, in the aforementioned "Computer Design" article, which carries both clock and data information. Information from the communications controller 14 is in a non-return-to-zero (NRZ) code format. Information to or from the tap 54 must therefore pass through the Manchester (N~Z) encoder/decoder 42 to change the format of the data. Use of the Manchester code simplifies data recovery logic. The Manchester code carries clock information for every bit cell.
Accordingly, the data recovery scheme used to convert this data to a usable form for the communications controller 14 is greatly simplified.
7~3~
Data from the communications channel 52 is sepa-rated at the tap 54. A common communications channel 52 ; is used for both transmit and receive operations, and ` the tap 54 provides both receive data (RCV DATA) and transmit data (~MT DATA) lines to the local network interface. Information from the tap 54 enters via the receive data line and passes through the Manchester decoder 42. This information is converted into a non-return-to-zero coding format. Tt enters the communi-cations controller 14 and is converted from a serialform to a parallel form usuable by the remainder of the system.
The communications controller 14 formats data required for a protocol known as synchronous data link control (SDLC). The beginning of a transmission is signalled by a leading flag, followed by a terminal address byte, followed by data information. The communi-cations controller 14 monitors the incoming data stream for an address which matches the address of the local terminal. The communications controller 14 interrupts the processor 10 only when an address match occurs.
Accordingly, the throughput of the local processor is not compromised. The local processor 10 is nGt constantly interrupted to analyze the incoming data stream to determine whether the data is intended for the local station 50.
Once an incoming data stream intended for the local station 50 has been detected, a DMA process occurs under control of the DMA controller 12 to transfer information from the communications controller 14 into local memory 16. The processor 10 is then signalled by a XMISSION COMPLETE signal at the end of the receive data stream. It is interrupted by the communications controller 14 via the interrupt controller 3~ to indicate the end of the transmission. The processor 10 can then access the data in its memory 16, analyze the incoming data stream, and react accordingly.
Information that is intended for other processors ~ 7~3~ ~
_ g _ in the system is then passed over the IPC bus via the IPC interface 20 in a fashion similar to that employed em described in copending application Serial , as hereinabove referenced.
For information that is to be transmitted, data is first retrieved across the IPC bus via the IPC
interface 20 and placed into local memory 16. The local network processor 10 then formats the data by storing it in a transmit buffer which resides within the local 16K
memory 16. The data is preceded in the transmit buffer by the address of the station 50 to which the transmis-sion is directed. When the data is formatted or blocked within the memory 16, the processor 10 initializes the DMA controller 12 to point to the first location of the transmit buffer. The DMA controller 12 is also loaded with byte code information to indicate how many bytes are in the present transmission packet.
Once that initialization has been completed, the processor 10 performs an output instruction to the transmitter state controller 36. The transmitter state controller 36 then assumes control of the communications controller 14 and begins a transmission of data onto the network. Transmission begins with a series of opening flags, and then data from the transmit buffer is trans-ferred to the communications controller 14 one byte at atime on a DMA basis. The first byte consists of the destination address for the transmission followed by the data block. Data is passed from the communications controller 14 through the Manchester encoder 42 and to the tap 54 via the transmit data (XMT DATA) line 56.
Information is transferred across the communi-cations channel 52 in packets. A packet consists of one or two opening flags~ a destination address, and at least 256 bytes of data in a block. At the end of the block of data, there are provided two frame check sequence characters used to perform an error check on the data block. A series of closing flags are then provided to indicate the end of the frame.
The local network interface also includes provisions for an optionalboot PROM 32. If the local network interface is used in a remote application without disk storage, program information for the s-tation 50 can be loaded through the communications networ~ (i.e., the internal data and address buses 26 and 28, respectively). When power is applied to the unit, the boot PROM 32 exists in the memory 16 from address 0 to 400 hex, and the processor 10 begins executing instructions from the boot PRO~ 32.
As information is transferred across the local network, it is transferred under control of the program within the boot PROM 32 into main memory 16. The boot PROM 32 is actually a phantom PROM in that although it occupies memory address space from 0 to 400 hex, information from the communications channel 52 can be written into those locations if write operations are performed into the memory 16. Once the boot operation is complete, the boot PROM 32 is ignored by the system, and the entire memory space is occupied by the RAM memory 16 on the board.
The local network interface includes an interrupt controller 38 to generate interrupts to the processor 10.
The interrupt structure for the processor 10 utilizes the model 8085 microprocessor special RESTARTS 5.5, 6.5 and 7.5 as well as the TRAP interrupt. The TRAP interrupt is assigned~to the communications controller 14. Whenever a receiver or a transmitter completes an operation, it signals the processor 10 by activating the TRAP line.
TRAP is a non-maskable interrupt.
X mg/ ~\ - 10 -5~i When the local network interface is a slave across the IPC channel, the master processor in the system can signal the local network interface processor 10 by activating the RESTART 5.5 line. This function is - 5 described in greater detai~ i~ co-pending U.S. patent application Serial No. ~ , as hereinabove referenced.
The RESTART 6.5 line is tied to the CARRIER
DETECT signal. If the state of the CARRIER DETECT
signal changes, the local network interface processor 10 can be signaled. That is a maskable interrupt. The local network interface processor 10 can therefore decide whether to examine that line.
The ~ESTART 7.5 line is assigned to a timer 22.
It is there~ore possible to time out communications operations on the communications channel 52. ~he local network interface originates a transmission and expects an acknowledgement signal from its intended receiver within a certain amount of time. If it does not receive an acknowledgement, it can be assumed that the trans-mission has not been correctly received.
Referring now to FIGU~E 3, a flow chart oftransmission operations is shownO Because the network of the present invention is not intended to operate near its capacity bandwith, the contention scheme is greatly simplified as compared to other systems. Rather than attempting to detect collisions upon transmission, each transmitter with a data packet queued for transmission monitors the activity on the communications channel, step 70. When a potential transmitter in the system detects activity on the channel, it waits until the end of the existing transmission and introduces a random wait 72 at that point. The random wait routine is per-formed by the microprocessor of the transmitting device.
At the end of the random wait, the transmitter begins transmission of data to the cable or channel if it is not currently carrying data 74 and proceeds to the end of the transmission. In the event of a data collision on the network (i.e., two or more stations 50 are - ~7~33~
transmitting over the cable 52 simultaneously) no acknowledgement from the intended receiver is received 78 for the transmission that is sent. The affected transmitter waits for a time out period 76; If, during this time out period, no acknowledgement is received, availability of the channel must again be determined 70.
If, however, an acknowledgement signal has been received by the transmitter, the local network interface is free to transmit another packet of data. The system determines whether the last data packet transmitted was the final data to be sent 80. If so, the system ceases operation 82. If more data remains to be transmitted, however, the system again detects whether the communi-cations channel 52 is being used 70 and the transmissionsequence is repeated.
From the foregoing discussion, it will be evident to those skilled in the art that a novel network apparatus and method of use thereof is herein disclosed. It will also be appreciated that the description of the preferred embodiment should in no way limit the number of possible system configurations which can be utilized as a result of the teaching of this disclosure.
.
A data encoder/decoder is provided at reference numeral 42 to convert data from the communications controller 14 into Manchester non-return-to-zero (NRZ) format for transmission over the co~munications cable.
The Manchester code is a bi-phase code described in detail in '-Encoding Schemes Support High Density Digital Data Recording'', by R. Severt published in ''Computer Design' May 1980.
The local network interface is located on a single printed circuit board positioned within a housing 50 or floor module 60 such as is shown and described, for example, in applicant's copending application Serial No. 383,501, filed August 10, 1981, for Word Processing System Employing a Plurality of General Purpose Processor Circuits . The interface allows the above-identified local system to communicate with the network. Unlike other network communication systems, the present invention requires no complex circuitry for data collision detection as is explained in detail hereinafter.
~ eferring now to FIGURE 2, individual data processing stations 50 can be attached to the communications co-axial cable or channel 52 by means of a tap 54.
The tap only slightly affects the cable 52. Accordingly, the transmission characteristics of the cable 52 are not significantly disturbed. The tap 54 can be located up to 200 feet from its corresponding station 50.
Normally the cable 52 is laid out in a substantially straight line in the ceiling or the floor of a building and users attach their stations 50 to the cable 52 with line lengths 56 of up to 200 feet. The line 56 includes the following signal lines: transmit enable (XMT ENABLE), receive data (RCV DATA) and transmit data (XMT DATA).
mg/~ - 6 -:~7~
The configuration of data processing stations 50 on the network can take a variety of forms. A station - 50 can be directly connected to the communications cable 52 via a tap 54, as shown generall~ at reference numeral 58. A number of work stations 50 can also be connected to a floor module 60 subsystem or cluster, as shown generally at reference numeral 62, which in turn is connected via a tap 54 to the cable 52. Moreover, two local network segments can be interconnected by means of a floor module 60 acting as a nodal point, as shown generally at reference numeral 64. No special modifi-cation to the local network interface is required to adapt a floor module 60 containing a local network interface for use as a nodal point. It should be appreciated that the afore-mentioned three configuration elements provide unlimited flexibility in arranging data processing stations 50 on the network and that the present disclosure is not intended to be limited to the configuration shown and described in FIGURE 2.
Referring also to FIGURE 1, the local network interface functions as follows. Information from the communications channel 52 (the co-axial cable) is transferred via the tap 54 to the local network residing in the data processing station 50 or floor module 60.
Information on the communications channel 52 is encoded by the encoder/decoder 42 using a Manchester code, as described, for example, in the aforementioned "Computer Design" article, which carries both clock and data information. Information from the communications controller 14 is in a non-return-to-zero (NRZ) code format. Information to or from the tap 54 must therefore pass through the Manchester (N~Z) encoder/decoder 42 to change the format of the data. Use of the Manchester code simplifies data recovery logic. The Manchester code carries clock information for every bit cell.
Accordingly, the data recovery scheme used to convert this data to a usable form for the communications controller 14 is greatly simplified.
7~3~
Data from the communications channel 52 is sepa-rated at the tap 54. A common communications channel 52 ; is used for both transmit and receive operations, and ` the tap 54 provides both receive data (RCV DATA) and transmit data (~MT DATA) lines to the local network interface. Information from the tap 54 enters via the receive data line and passes through the Manchester decoder 42. This information is converted into a non-return-to-zero coding format. Tt enters the communi-cations controller 14 and is converted from a serialform to a parallel form usuable by the remainder of the system.
The communications controller 14 formats data required for a protocol known as synchronous data link control (SDLC). The beginning of a transmission is signalled by a leading flag, followed by a terminal address byte, followed by data information. The communi-cations controller 14 monitors the incoming data stream for an address which matches the address of the local terminal. The communications controller 14 interrupts the processor 10 only when an address match occurs.
Accordingly, the throughput of the local processor is not compromised. The local processor 10 is nGt constantly interrupted to analyze the incoming data stream to determine whether the data is intended for the local station 50.
Once an incoming data stream intended for the local station 50 has been detected, a DMA process occurs under control of the DMA controller 12 to transfer information from the communications controller 14 into local memory 16. The processor 10 is then signalled by a XMISSION COMPLETE signal at the end of the receive data stream. It is interrupted by the communications controller 14 via the interrupt controller 3~ to indicate the end of the transmission. The processor 10 can then access the data in its memory 16, analyze the incoming data stream, and react accordingly.
Information that is intended for other processors ~ 7~3~ ~
_ g _ in the system is then passed over the IPC bus via the IPC interface 20 in a fashion similar to that employed em described in copending application Serial , as hereinabove referenced.
For information that is to be transmitted, data is first retrieved across the IPC bus via the IPC
interface 20 and placed into local memory 16. The local network processor 10 then formats the data by storing it in a transmit buffer which resides within the local 16K
memory 16. The data is preceded in the transmit buffer by the address of the station 50 to which the transmis-sion is directed. When the data is formatted or blocked within the memory 16, the processor 10 initializes the DMA controller 12 to point to the first location of the transmit buffer. The DMA controller 12 is also loaded with byte code information to indicate how many bytes are in the present transmission packet.
Once that initialization has been completed, the processor 10 performs an output instruction to the transmitter state controller 36. The transmitter state controller 36 then assumes control of the communications controller 14 and begins a transmission of data onto the network. Transmission begins with a series of opening flags, and then data from the transmit buffer is trans-ferred to the communications controller 14 one byte at atime on a DMA basis. The first byte consists of the destination address for the transmission followed by the data block. Data is passed from the communications controller 14 through the Manchester encoder 42 and to the tap 54 via the transmit data (XMT DATA) line 56.
Information is transferred across the communi-cations channel 52 in packets. A packet consists of one or two opening flags~ a destination address, and at least 256 bytes of data in a block. At the end of the block of data, there are provided two frame check sequence characters used to perform an error check on the data block. A series of closing flags are then provided to indicate the end of the frame.
The local network interface also includes provisions for an optionalboot PROM 32. If the local network interface is used in a remote application without disk storage, program information for the s-tation 50 can be loaded through the communications networ~ (i.e., the internal data and address buses 26 and 28, respectively). When power is applied to the unit, the boot PROM 32 exists in the memory 16 from address 0 to 400 hex, and the processor 10 begins executing instructions from the boot PRO~ 32.
As information is transferred across the local network, it is transferred under control of the program within the boot PROM 32 into main memory 16. The boot PROM 32 is actually a phantom PROM in that although it occupies memory address space from 0 to 400 hex, information from the communications channel 52 can be written into those locations if write operations are performed into the memory 16. Once the boot operation is complete, the boot PROM 32 is ignored by the system, and the entire memory space is occupied by the RAM memory 16 on the board.
The local network interface includes an interrupt controller 38 to generate interrupts to the processor 10.
The interrupt structure for the processor 10 utilizes the model 8085 microprocessor special RESTARTS 5.5, 6.5 and 7.5 as well as the TRAP interrupt. The TRAP interrupt is assigned~to the communications controller 14. Whenever a receiver or a transmitter completes an operation, it signals the processor 10 by activating the TRAP line.
TRAP is a non-maskable interrupt.
X mg/ ~\ - 10 -5~i When the local network interface is a slave across the IPC channel, the master processor in the system can signal the local network interface processor 10 by activating the RESTART 5.5 line. This function is - 5 described in greater detai~ i~ co-pending U.S. patent application Serial No. ~ , as hereinabove referenced.
The RESTART 6.5 line is tied to the CARRIER
DETECT signal. If the state of the CARRIER DETECT
signal changes, the local network interface processor 10 can be signaled. That is a maskable interrupt. The local network interface processor 10 can therefore decide whether to examine that line.
The ~ESTART 7.5 line is assigned to a timer 22.
It is there~ore possible to time out communications operations on the communications channel 52. ~he local network interface originates a transmission and expects an acknowledgement signal from its intended receiver within a certain amount of time. If it does not receive an acknowledgement, it can be assumed that the trans-mission has not been correctly received.
Referring now to FIGU~E 3, a flow chart oftransmission operations is shownO Because the network of the present invention is not intended to operate near its capacity bandwith, the contention scheme is greatly simplified as compared to other systems. Rather than attempting to detect collisions upon transmission, each transmitter with a data packet queued for transmission monitors the activity on the communications channel, step 70. When a potential transmitter in the system detects activity on the channel, it waits until the end of the existing transmission and introduces a random wait 72 at that point. The random wait routine is per-formed by the microprocessor of the transmitting device.
At the end of the random wait, the transmitter begins transmission of data to the cable or channel if it is not currently carrying data 74 and proceeds to the end of the transmission. In the event of a data collision on the network (i.e., two or more stations 50 are - ~7~33~
transmitting over the cable 52 simultaneously) no acknowledgement from the intended receiver is received 78 for the transmission that is sent. The affected transmitter waits for a time out period 76; If, during this time out period, no acknowledgement is received, availability of the channel must again be determined 70.
If, however, an acknowledgement signal has been received by the transmitter, the local network interface is free to transmit another packet of data. The system determines whether the last data packet transmitted was the final data to be sent 80. If so, the system ceases operation 82. If more data remains to be transmitted, however, the system again detects whether the communi-cations channel 52 is being used 70 and the transmissionsequence is repeated.
From the foregoing discussion, it will be evident to those skilled in the art that a novel network apparatus and method of use thereof is herein disclosed. It will also be appreciated that the description of the preferred embodiment should in no way limit the number of possible system configurations which can be utilized as a result of the teaching of this disclosure.
.
Claims (18)
1. For use in a network for enabling each of a plurality of data processing stations to communicate with one another via a communications medium, a local network interface operatively connected between said communications medium and said data processing stations, said local network interface comprising:
a) a processor;
b) a direct memory access (DMA) controller operatively connected to said processor;
c) means for controlling communications operatively connected between said communications medium and said processor; and d) memory means operatively connected to said processor, to said means for controlling communications, and to said DMA controller so that the data residing in said memory means may be accessed for transmission to said communi-cations medium via said local network interface and may be updated therefrom.
a) a processor;
b) a direct memory access (DMA) controller operatively connected to said processor;
c) means for controlling communications operatively connected between said communications medium and said processor; and d) memory means operatively connected to said processor, to said means for controlling communications, and to said DMA controller so that the data residing in said memory means may be accessed for transmission to said communi-cations medium via said local network interface and may be updated therefrom.
2. The local network interface in accordance with claim 1 wherein said means for controlling communi-cations includes a transmitter state controller for allowing said means for controlling communications to be actuated without intervention by said processor.
3. The local network interface in accordance with claim 2 wherein said means for controlling communi-cations includes a communications controller operatively connected to said transmitter state controller.
4. The local network interface in accordance with claim 3 wherein said means for controlling communi-cations includes an encoder operatively connected to said communications controller for encoding data to be transmitted into a standard format.
5. The local network interface in accordance with claim 4 wherein said standard format of encoded data to be transmitted is the Manchester code format.
6. The local network interface in accordance with claim 1 wherein said memory means includes a random access memory (RAM) and refresh circuitry operatively connected thereto for maintaining the data therein.
7. The local network interface in accordance with claim 1 further comprising a programmable read only memory (PROM) operatively connected to said DMA controller and said memory means, said PROM having instructions therein for controlling data transfer over said communi-cations medium.
8. The local network interface in accordance with claim 7 further comprising means for controlling communications among the processors of two or more data processing stations operatively connected to said processor and to said memory means.
9. The local network interface in accordance with claim 8 wherein said means for controlling communi-cations among the processors of two or more data process-ing stations includes an interprocessor communications controller.
10. A data communications network for use in a data processing system comprising:
a) a plurality of data processing stations adapted to transmit and to receive data via a common communications channel;
b) a communications channel having a first segment and a second segment, each of said segments being adapted to transfer data from one of said plurality of data processing stations operatively connected thereto to another of said plurality of data processing stations operatively connected thereto; and c) one of said plurality of data process-ing stations being a nodal point data processing station operatively connected between said first segment and said second segment so that data generated by one of said plurality of data processing stations operatively connected to one of said segments may be transferred to another of said plurality of data processing stations operatively connected to the other of said segments via said nodal point data processing station.
a) a plurality of data processing stations adapted to transmit and to receive data via a common communications channel;
b) a communications channel having a first segment and a second segment, each of said segments being adapted to transfer data from one of said plurality of data processing stations operatively connected thereto to another of said plurality of data processing stations operatively connected thereto; and c) one of said plurality of data process-ing stations being a nodal point data processing station operatively connected between said first segment and said second segment so that data generated by one of said plurality of data processing stations operatively connected to one of said segments may be transferred to another of said plurality of data processing stations operatively connected to the other of said segments via said nodal point data processing station.
11. The data communications network in accordance with claim 10 wherein one of said plurality of data processing stations is directly operatively connected to said first of said segments and another of said plurality of data processing stations is directly operatively connected to said second of said segments.
12. The data communications network in accordance with claim 11 wherein all of said data processing stations, including said nodal point data processing station, are substantially identical.
13. The data communications network in accordance with claim 11 wherein each of said plurality of data processing stations includes at least one terminal operatively connected to a module, said module being operatively connected to said channel.
14. The data communications network in accordance with claim 11 further comprising an independent intelli-gent device operatively connected to one of said segments of said communications channel for exchanging data with any of said plurality of data processing stations operatively connected thereto.
15. The data communications network in accordance with claim 14 wherein said independent intelligent device is a computer.
16. A data communications network for use in a data processing system comprising:
a) a plurality of data processing stations adapted to transmit and to receive data via a common communications channel;
b) a first communications channel adapted to transfer data from one of said plurality of data processing stations operatively connected thereto to another of said plurality of data processing stations operatively connected thereto;
c) a second communications channel adapted to transfer data from one of said plurality of data processing stations operatively connected thereto to another of said plurality of data processing stations operatively connected thereto;
and d) a nodal point data processing station operatively connected between said first communi-cations channel and said second communications channel so that data generated by one of said plurality of data processing stations operatively connected to one of said communications channels may be transferred to another of said plurality of data processing stations operatively connected to the other of said communications channels via said nodal point data processing station.
a) a plurality of data processing stations adapted to transmit and to receive data via a common communications channel;
b) a first communications channel adapted to transfer data from one of said plurality of data processing stations operatively connected thereto to another of said plurality of data processing stations operatively connected thereto;
c) a second communications channel adapted to transfer data from one of said plurality of data processing stations operatively connected thereto to another of said plurality of data processing stations operatively connected thereto;
and d) a nodal point data processing station operatively connected between said first communi-cations channel and said second communications channel so that data generated by one of said plurality of data processing stations operatively connected to one of said communications channels may be transferred to another of said plurality of data processing stations operatively connected to the other of said communications channels via said nodal point data processing station.
17. The data communications network in accordance with claim 16 wherein said nodal point data processing station is one of said plurality of data processing stations.
18. The data communications network in accordance with claim 1 or 10 wherein said communications channel is a coaxial cable.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/256,332 US4441162A (en) | 1981-04-22 | 1981-04-22 | Local network interface with control processor & DMA controller for coupling data processing stations to common serial communications medium |
| US256,332 | 1988-10-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1178355A true CA1178355A (en) | 1984-11-20 |
Family
ID=22971852
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000399924A Expired CA1178355A (en) | 1981-04-22 | 1982-03-31 | Local network interface for use in a multi-station word processing system |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US4441162A (en) |
| EP (1) | EP0064347A1 (en) |
| JP (1) | JPS57187738A (en) |
| AU (1) | AU543489B2 (en) |
| CA (1) | CA1178355A (en) |
Families Citing this family (51)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3374964D1 (en) * | 1982-09-29 | 1988-01-28 | Toshiba Kk | Decentralized information processing system and initial program loading method therefor |
| US4751630A (en) * | 1982-09-30 | 1988-06-14 | Honeywell Information Systems Inc. | Interactive terminal system using a prepoll prior to transferring information from the controller to the work station |
| EP0137804A4 (en) * | 1983-02-07 | 1987-10-12 | American Telephone & Telegraph | Data network interface. |
| US4590468A (en) * | 1983-03-10 | 1986-05-20 | Western Digital Corporation | Token access controller protocol and architecture |
| US4910732A (en) * | 1983-09-20 | 1990-03-20 | Siegfried Schwarz | Onechip-computers as network-controller and computer |
| JPS60237743A (en) * | 1984-05-11 | 1985-11-26 | Nec Corp | Large-capacity data exchange device |
| US4584719A (en) * | 1984-08-24 | 1986-04-22 | System Development Corp. | Fiber optic workstation datalink interface |
| US4736365A (en) * | 1984-10-26 | 1988-04-05 | Dialogic Systems Corporation | Method and apparatus for controlling access to an asynchronous communication network |
| US4703420A (en) * | 1985-02-28 | 1987-10-27 | International Business Machines Corporation | System for arbitrating use of I/O bus by co-processor and higher priority I/O units in which co-processor automatically request bus access in anticipation of need |
| US4731735A (en) * | 1985-09-30 | 1988-03-15 | International Business Machines Corporation | Multilingual processing for screen image build and command decode in a word processor, with full command, message and help support |
| US4680755A (en) * | 1985-11-14 | 1987-07-14 | Hewlett Packard Company | Real-time end of packet signal generator |
| JPS62243057A (en) * | 1986-04-16 | 1987-10-23 | Hitachi Ltd | File transfer managing system |
| US4727538A (en) * | 1986-05-20 | 1988-02-23 | American Telephone And Telegraph Company, At&T Bell Laboratories | Information transfer method and arrangement |
| US4771391A (en) * | 1986-07-21 | 1988-09-13 | International Business Machines Corporation | Adaptive packet length traffic control in a local area network |
| US4750114A (en) * | 1986-07-28 | 1988-06-07 | Honeywell Bull Inc. | Local area network control block |
| US5093910A (en) * | 1986-10-29 | 1992-03-03 | United Technologies Corporation | Serial data transmission between redundant channels |
| US5228129A (en) * | 1987-04-01 | 1993-07-13 | Digital Equipment Corporation | Synchronous communication interface for reducing the effect of data processor latency |
| JP2745521B2 (en) * | 1988-02-23 | 1998-04-28 | 株式会社日立製作所 | Frame transmission method |
| US4916692A (en) * | 1988-03-14 | 1990-04-10 | Racal Data Communications Inc. | TDM bus controller |
| US4949248A (en) * | 1988-07-15 | 1990-08-14 | Caro Marshall A | System for shared remote access of multiple application programs executing in one or more computers |
| US5303236A (en) * | 1988-08-26 | 1994-04-12 | Hitachi, Ltd. | Signalling apparatus for use in an ATM switching system |
| JPH02151926A (en) * | 1988-12-02 | 1990-06-11 | Fujitsu Ltd | Terminal equipment switching system |
| US5319574A (en) * | 1988-12-27 | 1994-06-07 | Fujitsu Limited | Status change monitoring apparatus |
| FR2646539B1 (en) * | 1989-04-27 | 1994-07-29 | Bertin & Cie | COMPUTER SYSTEM FOR ARCHIVING AND CONSULTING DATA, AND INTERFACE CIRCUIT THEREFOR |
| CA2017458C (en) * | 1989-07-24 | 2000-10-10 | Jonathan R. Engdahl | Intelligent network interface circuit |
| US5023891A (en) * | 1989-07-25 | 1991-06-11 | Sf2 Corporation | Method and circuit for decoding a Manchester code signal |
| US5206934A (en) * | 1989-08-15 | 1993-04-27 | Group Technologies, Inc. | Method and apparatus for interactive computer conferencing |
| EP0453863A2 (en) * | 1990-04-27 | 1991-10-30 | National Semiconductor Corporation | Methods and apparatus for implementing a media access control/host system interface |
| US5151895A (en) * | 1990-06-29 | 1992-09-29 | Digital Equipment Corporation | Terminal server architecture |
| GB9019488D0 (en) * | 1990-09-06 | 1990-10-24 | Ncr Co | Local area network having a wireless transmission link |
| CA2060820C (en) * | 1991-04-11 | 1998-09-15 | Mick R. Jacobs | Direct memory access for data transfer within an i/o device |
| CA2128322A1 (en) * | 1992-02-11 | 1993-08-19 | Mark C. Koz | An audiovisual teleservices interface subsystem |
| US5566301A (en) * | 1992-02-11 | 1996-10-15 | Futuretel, Inc. | ISDN audiovisual teleservices interface subsystem |
| AU4245493A (en) * | 1992-05-15 | 1993-12-13 | Connective Strategies, Inc. | Isdn-based high speed communication system |
| DE4221278C2 (en) * | 1992-06-29 | 1996-02-29 | Martin Vorbach | Bus-linked multi-computer system |
| US5550997A (en) * | 1992-11-18 | 1996-08-27 | Canon Kabushiki Kaisha | In an interactive network board, a method and apparatus for preventing inadvertent loading of a programmable read only memory |
| US5394526A (en) * | 1993-02-01 | 1995-02-28 | Lsc, Inc. | Data server for transferring selected blocks of remote file to a distributed computer network involving only single data transfer operation |
| US5692128A (en) * | 1993-06-23 | 1997-11-25 | Microtest, Inc. | Computer network with reliable and efficient removable media services |
| JP3168102B2 (en) * | 1993-06-30 | 2001-05-21 | トヨタ自動車株式会社 | Communication device |
| JP2687860B2 (en) * | 1993-12-28 | 1997-12-08 | 日本電気株式会社 | System start / stop control system for distributed processing system |
| GB2301751B (en) * | 1995-06-02 | 2000-02-09 | Dsc Communications | Control message transmission in telecommunications systems |
| US6219045B1 (en) * | 1995-11-13 | 2001-04-17 | Worlds, Inc. | Scalable virtual world chat client-server system |
| JP4872173B2 (en) * | 2001-08-09 | 2012-02-08 | 大日本印刷株式会社 | Method of manufacturing laminated body having composite unevenness, method of manufacturing mold, and method of forming molded product |
| US20050038946A1 (en) * | 2003-08-12 | 2005-02-17 | Tadpole Computer, Inc. | System and method using a high speed interface in a system having co-processors |
| US7793074B1 (en) * | 2006-04-14 | 2010-09-07 | Tilera Corporation | Directing data in a parallel processing environment |
| US8151088B1 (en) | 2008-07-08 | 2012-04-03 | Tilera Corporation | Configuring routing in mesh networks |
| US8045546B1 (en) | 2008-07-08 | 2011-10-25 | Tilera Corporation | Configuring routing in mesh networks |
| US8050256B1 (en) | 2008-07-08 | 2011-11-01 | Tilera Corporation | Configuring routing in mesh networks |
| US8521963B1 (en) | 2009-09-21 | 2013-08-27 | Tilera Corporation | Managing cache coherence |
| EP2758840B1 (en) * | 2011-09-23 | 2021-06-02 | Videojet Technologies, Inc. | Networking method |
| KR20150095139A (en) * | 2014-02-12 | 2015-08-20 | 삼성전자주식회사 | Direct Memory Access controller and system for accessing to channel buffer directly |
Family Cites Families (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3890471A (en) * | 1973-12-17 | 1975-06-17 | Bell Telephone Labor Inc | Loop data transmission arrangement employing an interloop communication terminal |
| US4063220A (en) * | 1975-03-31 | 1977-12-13 | Xerox Corporation | Multipoint data communication system with collision detection |
| JPS5362945A (en) * | 1976-11-17 | 1978-06-05 | Toshiba Corp | Disc address system |
| GB1570923A (en) * | 1977-02-14 | 1980-07-09 | Gec General Signal Ltd | Data communication apparatus |
| US4296466A (en) * | 1978-01-23 | 1981-10-20 | Data General Corporation | Data processing system including a separate input/output processor with micro-interrupt request apparatus |
| US4334306A (en) * | 1978-06-02 | 1982-06-08 | Texas Instruments Incorporated | Transparent intelligent network for data and voice |
| US4190821A (en) * | 1978-10-02 | 1980-02-26 | Burroughs Corporation | Self-healing loop communications system |
| US4228495A (en) * | 1978-12-19 | 1980-10-14 | Allen-Bradley Company | Multiprocessor numerical control system |
| US4287592A (en) * | 1979-05-23 | 1981-09-01 | Burroughs Corporation | Method and apparatus for interfacing stations in a multiloop communications system |
| US4271507A (en) * | 1979-06-07 | 1981-06-02 | Ford Motor Company | Communication broadcast channel interface |
| US4271505A (en) * | 1979-07-02 | 1981-06-02 | The Foxboro Company | Process communication link |
| US4292197A (en) * | 1979-10-09 | 1981-09-29 | Ppg Industries, Inc. | Method of preparing electrocatalyst for an oxygen depolarized cathode electrolytic cell |
| US4347498A (en) * | 1979-11-21 | 1982-08-31 | International Business Machines Corporation | Method and means for demand accessing and broadcast transmission among ports in a distributed star network |
| US4319338A (en) * | 1979-12-12 | 1982-03-09 | Allen-Bradley Company | Industrial communications network with mastership determined by need |
| US4373183A (en) * | 1980-08-20 | 1983-02-08 | Ibm Corporation | Bus interface units sharing a common bus using distributed control for allocation of the bus |
| US4385382A (en) * | 1980-09-29 | 1983-05-24 | Honeywell Information Systems Inc. | Communication multiplexer having a variable priority scheme using a read only memory |
| US4387441A (en) * | 1981-04-16 | 1983-06-07 | Ncr Corporation | Data processing system wherein at least one subsystem has a local memory and a mailbox memory within the local memory for storing header information |
| US4394726A (en) * | 1981-04-29 | 1983-07-19 | The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration | Distributed multiport memory architecture |
| US4332027A (en) * | 1981-10-01 | 1982-05-25 | Burroughs Corporation | Local area contention network data communication system |
-
1981
- 1981-04-22 US US06/256,332 patent/US4441162A/en not_active Expired - Lifetime
-
1982
- 1982-03-31 CA CA000399924A patent/CA1178355A/en not_active Expired
- 1982-04-16 EP EP82301960A patent/EP0064347A1/en not_active Withdrawn
- 1982-04-20 AU AU82848/82A patent/AU543489B2/en not_active Ceased
- 1982-04-22 JP JP57068009A patent/JPS57187738A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| AU8284882A (en) | 1982-10-28 |
| JPS57187738A (en) | 1982-11-18 |
| EP0064347A1 (en) | 1982-11-10 |
| US4441162A (en) | 1984-04-03 |
| AU543489B2 (en) | 1985-04-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CA1178355A (en) | Local network interface for use in a multi-station word processing system | |
| US4332027A (en) | Local area contention network data communication system | |
| US4337465A (en) | Line driver circuit for a local area contention network | |
| US5247626A (en) | Fddi controller having flexible buffer management | |
| US4608700A (en) | Serial multi-drop data link | |
| US4748617A (en) | Very high-speed digital data bus | |
| US4493021A (en) | Multicomputer communication system | |
| US4641307A (en) | Data packet transmission using shared channel | |
| US4642630A (en) | Method and apparatus for bus contention resolution | |
| JPH0225319B2 (en) | ||
| US4637015A (en) | Packet transmission and reception via a shared DMA channel | |
| EP0064818A1 (en) | Data collision avoidance method | |
| KR0174702B1 (en) | Apparatus and method for intermodular communications using system bus controllers | |
| US4701755A (en) | Data switching system | |
| US5666485A (en) | Software driver for a system bus | |
| CA2145755A1 (en) | Communication bus system and station for use in such system | |
| JPS6054549A (en) | Data transmitting method and device | |
| EP0193305A2 (en) | System interface for coupling standard microprocessor to a communications adapter | |
| US6178177B1 (en) | Data-processing network having non-deterministic access, but having deterministic access time | |
| CA1180075A (en) | Local area contention network data communication system | |
| JP2624265B2 (en) | Data transmission equipment | |
| JPS5822893B2 (en) | Data highway system line control method | |
| Kao | Design of COLAN II, a control oriented local area network | |
| Frese et al. | FPSS-A Fast Packet Switching System | |
| CA1240752A (en) | Packet transmission and reception via a shared dma channel |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEC | Expiry (correction) | ||
| MKEX | Expiry |