CA1184317A - Ultra high-frequency circuit - Google Patents

Ultra high-frequency circuit

Info

Publication number
CA1184317A
CA1184317A CA000401423A CA401423A CA1184317A CA 1184317 A CA1184317 A CA 1184317A CA 000401423 A CA000401423 A CA 000401423A CA 401423 A CA401423 A CA 401423A CA 1184317 A CA1184317 A CA 1184317A
Authority
CA
Canada
Prior art keywords
gold
circuit
silver
mass surface
silk
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA000401423A
Other languages
French (fr)
Inventor
Georges Kersuzan
Michel Picault
Rolland Sourdillon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Gloeilampenfabrieken NV filed Critical Philips Gloeilampenfabrieken NV
Application granted granted Critical
Publication of CA1184317A publication Critical patent/CA1184317A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4061—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in inorganic insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092—Dispersed materials, e.g. conductive pastes or inks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/035—Paste overlayer, i.e. conductive paste or solder paste over conductive layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0388—Other aspects of conductors
    • H05K2201/0391—Using different types of conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/07—Electric details
    • H05K2201/0707—Shielding
    • H05K2201/0715—Shielding provided by an outer layer of PCB
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09981—Metallised walls
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/15—Position of the PCB during processing
    • H05K2203/1572—Processing both sides of a PCB by the same process; Providing a similar arrangement of components on both sides; Making interlayer connections from two sides
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/245—Reinforcing conductive patterns made by printing techniques or by other techniques for applying conductive pastes, inks or powders; Reinforcing other conductive patterns by such techniques
    • H05K3/247—Finish coating of conductors by using conductive pastes, inks or powders
    • H05K3/248—Finish coating of conductors by using conductive pastes, inks or powders fired compositions for inorganic substrates
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S428/00—Stock material or miscellaneous articles
    • Y10S428/901—Printed circuit

Abstract

ABSTRACT:

an ultra-high-frequency circuit realized on an insulating aluminiumoxide substrate according to hybrid technology and by silk screen printing. Silver-palladium is used for the mass surface instead of gold of the prior art circuits. The connection between the conductive gold tracks of the circuit and the mass surface of silver-palladium through the metallized holes is ensured by the intertposition of a gold-platinum alloy metallization.
The gold-platinum alloy interconnection is necessary in order to obtain a stable configuration. avoiding migra-tion of silver into the gold of the circuit. The new configuration provides a considerable reduction of cost with respect to an assembly with total metal appliance of gold.

Description

3~>7 PIIF 81.539 l 1982-03-19 "Ultra high-frecluency circuit".

The invention relates to an ul-tra high-frec~leney circuit manu-faetured according to the "hybrid" technologies and by silk-sereen prin-ting on an insulating aluminiumoxide plate, the first face of -the said plate having to serve as a support for a cireuit comprising conductive eonneetion tKaeks of gold and the second face having to serve as a sup-port for the rnass surfaee of the said eireuit, the connection between the cireuit and the mass surface being ensured by means of wall-metallized holes in the said plate.
In said technique the conduetive eonnection -h-aeks of the eir-lO euit, the metallization of the holes and the mass surfaee are generallyobtained by means of gold deposits by silk-sereen printing~ This em~odi-ment of the proeess-step is particularly onerous. If the cireuit compri-ses optionally resistors, these are also produced by silk screen printing.
The other components are provided on the cireui-t aecording to "hybrid"
15 technology It is the objeet of the invention to produce an ultra high-freclueney eircuit manufaetured aecording to the abovementioned technolo-; gies but in a manner whieh is more eeonomieal by replaeillg gold for the mass surfaee by an alloy on the basis of silver. The said mass surface 20 eonstituting the most important gold deposit, an appreeiable economy maythus be realized. However, a diffieulty presents itself to ensure the eonneetion of the mass surfaee with the eonduetlve eonneetion traeks of the eireuit due to the diffusion of silver in gold, the contaet between said two metals Eorming an unstable eombination from a metallurgie point 25 Of view. In order to mitigate this inconvenience, the ulhra hic~l-frecluency circuit in accordance wlth the invention is characterized in that the said mass surface is realized by means of the deposi-tion of an alloy on the basis of silver, the connection cireuit-mass surface is ensured by interposition in the metallization traek of each of the said holes of an 30 alloy which is eompatible both with the gold of the said eonductive eon~
neetion traeks and with the alloy on the basis of silver of the said mass surfaee.
If the said mass surface is constituted by an alloy of silver-~ , 8~3~
PHF 81.539 2 1982-03-19 palladium and if the said connec-tion circuit-mass surfaee is constituted by an alloy of gold-platinum, the syste~l thus realized is perfectly s-ta-ble from a metallogical point of view due to the gold-platinurn forming a barrier for the cdiffusion of silver in gold.
From the following description, wi-th reference to -the accompany-ing drawings, the whole being glven by way of example, it will be well understoocl hc~ the invention can be realized.
Figures 1 to 4 show the successive stages of the manufacture of an ultra high-frequency circuit in aecordance with the lnvention.
Figures 1a and 1b are a cross-seetional view and a plan view, respee-tively, of an aluminiumoxide plate 3 at the level of a hole 4 made in the said plate. A gold-metallization 5 of the said hole is firs-t ef-fected by means of a deposition by silk-sereen printing on one of the faces 1 of the plate starting from a circumference 6 which is concen-tric 15 with the hole 4, so as to metallize it optimally, the sald gold deposition being suceeeded by drying and firing.
In the following step shown in Figure ~ me-talllzation of gold-platinum 7 of the hole 4 superimposed on the preeeding metallization of gold is obtained by means of a deposition by silk-sereen printing on the 20 other face 2 of the plate starting from a eireumferenee 8 which is con-eentric with the hole 4 so as -to metallize it op-timally, -the deposition of gold-pla-tin~n being suceeedecd b~ drying and flring.
As shown in Figure 3, a deposi-tion is then eclrrled out by silk-sereen printing of silver-palladium of the mass surfaee 9 on the whole 25 surfaee of the faee 2 of the pla-te and in a manner sueh as to obtain a-t the level of eaeh hole 4 a slight eoating with the part of the metalli-zation of gold-platinum 7 which projee-ts on the ou-tside of the hole, -the said deposit of silver-palk~dium beinq sueeeecled by clrying and firing.
Figure 4 shows -the finished deviee complete~d in -the last step of 30 the manufaeture by deposits of gold by silk-sereen printing on the faee 1 of the plate and according to the conductive eonnection traeks 10. At the level of a hole 4, said -traeks are manufac-tured so as to eover entirely -the part of the gold-metallization 5 whieh projects from the outside of the hole, and partially the metallization of gold-platinum 7 on the in-35 side of the hole. Op-tionally, the resistors 11 of the cireui-t are deposi-ted by silk screen printing whieh eireui-t is then ready to reeeive the other -transferred eomponen-ts. The depositions of gold of the eonneetions and of resistive paste are also sueeeeded by drying and firing.

Claims (3)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. An ultra high-frequency circuit manufactured according to the "hybrid" technologies and by silk-screen printing on an insulating aluminiumoxide plate, the first face of the said plate having to serve as a support for a circuit comprising conductive connection tracks of gold and the second face having to serve as a support for the mass surface of the said circuit, the connection between the circuit and the mass surface being ensured by means of holes made in the said plate and being metallized, charac-terized in that the said mass surface is manufactured by means of the deposition of an alloy on the basis of silver, the connection between the circuit and the mass surface being ensured by the interposition in the metallization track of each of the said holes of an alloy which is com-patible both with the gold of the said conductive connec-tion tracks and with the alloy on the basis of silver of the said mass surface.
2. A circuit as claimed in Claim 1, characterized in that the said mass surface is constituted by an alloy of silver-palladium and the said connection circuit-mass surface is constituted by an alloy of gold-platinum.
3. A circuit as claimed in Claims 1 and 2, charac-terized in that each of the said holes is first metallized with gold deposited by silk-screen printing on the said first face from a first circumference which is concentric with the said hole and then of gold-platinum deposited by silk-screen printing on the said second face from a second circumference which is concentric with the said hole, the said mass surface being realized by means of a deposition by silk-screen printing of silver-palladium on the said second face so as to obtain a slight cover with the part of the metallization of gold-platinum projecting from each of the said holes up to the said second circumference, the said conductive connection tracks being obtained by means of depositions of gold by silk-screen printing on the said first face and realized so as to cover entirely the part of the metallization of gold projecting from each of the said holes up to the said first circumference and par-tially the metallization of gold-platinum on the inside of the said holes.
CA000401423A 1981-04-29 1982-04-22 Ultra high-frequency circuit Expired CA1184317A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR8108548 1981-04-29
FR8108548A FR2505094A1 (en) 1981-04-29 1981-04-29 METHOD FOR PRODUCING MICROWAVE CIRCUITS

Publications (1)

Publication Number Publication Date
CA1184317A true CA1184317A (en) 1985-03-19

Family

ID=9257905

Family Applications (1)

Application Number Title Priority Date Filing Date
CA000401423A Expired CA1184317A (en) 1981-04-29 1982-04-22 Ultra high-frequency circuit

Country Status (6)

Country Link
US (1) US4563543A (en)
EP (1) EP0063843B1 (en)
JP (1) JPS57186395A (en)
CA (1) CA1184317A (en)
DE (1) DE3265756D1 (en)
FR (1) FR2505094A1 (en)

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GB2156593B (en) * 1984-03-28 1987-06-17 Plessey Co Plc Through hole interconnections
US5631447A (en) * 1988-02-05 1997-05-20 Raychem Limited Uses of uniaxially electrically conductive articles
US5071359A (en) * 1990-04-27 1991-12-10 Rogers Corporation Array connector
US5245751A (en) * 1990-04-27 1993-09-21 Circuit Components, Incorporated Array connector
DE69233232T2 (en) * 1991-02-22 2004-08-05 Canon K.K. Electrical connector body and manufacturing method therefor
US5227588A (en) * 1991-03-25 1993-07-13 Hughes Aircraft Company Interconnection of opposite sides of a circuit board
DE59108784D1 (en) * 1991-04-01 1997-08-21 Akcionernoe Obscestvo Otkrytog MULTIPLE LAYER BOARD AND METHOD FOR THEIR PRODUCTION
JPH0567869A (en) * 1991-09-05 1993-03-19 Matsushita Electric Ind Co Ltd Method of bonding electric part, module and multilayer board
US5307237A (en) * 1992-08-31 1994-04-26 Hewlett-Packard Company Integrated circuit packaging with improved heat transfer and reduced signal degradation
US5565262A (en) * 1995-01-27 1996-10-15 David Sarnoff Research Center, Inc. Electrical feedthroughs for ceramic circuit board support substrates
FR2735910B1 (en) * 1995-06-20 1997-07-18 Thomson Csf INTERCONNECTION SYSTEM AND IMPLEMENTATION METHOD
FR2740935B1 (en) * 1995-11-03 1997-12-05 Schlumberger Ind Sa METHOD FOR MANUFACTURING AN ASSEMBLY OF ELECTRONIC MODULES FOR ELECTRONIC MEMORY CARDS
US6103992A (en) * 1996-11-08 2000-08-15 W. L. Gore & Associates, Inc. Multiple frequency processing to minimize manufacturing variability of high aspect ratio micro through-vias
DE19910078A1 (en) * 1999-03-08 2000-09-28 Bosch Gmbh Robert Process for increasing the manufacturing reliability of soldered connections
JP3790433B2 (en) * 2001-02-28 2006-06-28 日本無線株式会社 Method for manufacturing printed wiring board
EP1814447A2 (en) * 2004-11-23 2007-08-08 Nessler Medizintechnik GmbH Process for through hole plating an electrically insulating substrate material

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3374110A (en) * 1964-05-27 1968-03-19 Ibm Conductive element, composition and method
US3799802A (en) * 1966-06-28 1974-03-26 F Schneble Plated through hole printed circuit boards
US3981724A (en) * 1974-11-06 1976-09-21 Consolidated Refining Company, Inc. Electrically conductive alloy
US4001146A (en) * 1975-02-26 1977-01-04 E. I. Du Pont De Nemours And Company Novel silver compositions
US4131516A (en) * 1977-07-21 1978-12-26 International Business Machines Corporation Method of making metal filled via holes in ceramic circuit boards
JPS5453267A (en) * 1977-10-05 1979-04-26 Hitachi Ltd Method of manufacturing thick film multilayer wiring board
IT8048031A0 (en) * 1979-04-09 1980-02-28 Raytheon Co IMPROVEMENT IN FIELD EFFECT SEMICONDUCTOR DEVICES

Also Published As

Publication number Publication date
EP0063843B1 (en) 1985-08-28
US4563543A (en) 1986-01-07
JPH035676B2 (en) 1991-01-28
DE3265756D1 (en) 1985-10-03
FR2505094B1 (en) 1984-10-19
EP0063843A1 (en) 1982-11-03
FR2505094A1 (en) 1982-11-05
JPS57186395A (en) 1982-11-16

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