CA1191205A - Repeater station for use in a radio relay system to protect time deviations of time slots - Google Patents
Repeater station for use in a radio relay system to protect time deviations of time slotsInfo
- Publication number
- CA1191205A CA1191205A CA000426287A CA426287A CA1191205A CA 1191205 A CA1191205 A CA 1191205A CA 000426287 A CA000426287 A CA 000426287A CA 426287 A CA426287 A CA 426287A CA 1191205 A CA1191205 A CA 1191205A
- Authority
- CA
- Canada
- Prior art keywords
- station
- time slots
- time
- upward
- downward
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/24—Time-division multiplex systems in which the allocation is indicated by an address the different channels being transmitted sequentially
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/14—Relay systems
- H04B7/15—Active relay systems
- H04B7/155—Ground-based stations
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W56/00—Synchronisation arrangements
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Computer Hardware Design (AREA)
- Radio Relay Systems (AREA)
- Time-Division Multiplex Systems (AREA)
- Mobile Radio Communication Systems (AREA)
Abstract
ABSTRACT
In a repeater station for use in a repeater station to repeat a sequence of downward time slots and a succession of upward time slots, a detector detects a synchronizing signal included in a particular one of the downward time slots. A timing circuit produces a first timing signal when a first predetermined duration lapses after detection of the synchronizing signal.
The first predetermined duration is preferably predictively determined in consideration of a reception time instant of a particular one of the upward time slots that corresponds to the particular downward time slot. Signals included in each upward time slot are memorized in a memory section with reference to the first timing signal. The timing circuit further produces a second timing signal after the first timing signal to transmit the memorized signals to an upward station. The second timing signal is produced in consideration of a deviation with which the upward time slots reach the upward station.
In a repeater station for use in a repeater station to repeat a sequence of downward time slots and a succession of upward time slots, a detector detects a synchronizing signal included in a particular one of the downward time slots. A timing circuit produces a first timing signal when a first predetermined duration lapses after detection of the synchronizing signal.
The first predetermined duration is preferably predictively determined in consideration of a reception time instant of a particular one of the upward time slots that corresponds to the particular downward time slot. Signals included in each upward time slot are memorized in a memory section with reference to the first timing signal. The timing circuit further produces a second timing signal after the first timing signal to transmit the memorized signals to an upward station. The second timing signal is produced in consideration of a deviation with which the upward time slots reach the upward station.
Description
rhis inventioll relates to a repeater station for use in a time di-vision multiple network operable as a raclio relay system.
Such a time division mul-tiple network compr:ises a central station and a plurality oE substations remote -from the central station. A radio relay system serves to carry out communication between the central station and the substations even when the substations are far from a coverage of the central station. For this purpose, at least one repeater station is placed between the central station and the substations in the radio relay system.
Each of conventional repeater stations is operable in response to a time division multiple signal which is arranged :in a succession o:E time slots ass:igllocl to the substatiolls carry:ing out comm~ :i.cati.oll. Sucll a tinlQ cl:ivisioll mu.l.t:i.l):lo s:i.gllcl:l is suL)p.L:iocl to eacll rol)oato:L stat:i.oll Erolll all ~Ipuol s~ut:i.c)ll allcl Irolll a .Lower stat:ioll si.tuatocl upstloam LLIIcLclownstrecLIIl relat:ivo to e.lcll:re,)o.:Lter station through various repeated paths, respectively. The upper station may be either the central station or another repeater station while the lower station, either a further repeater station or one o:E the substations.
As will later be described with re:Eerence to four Eigures of the accompanying drawing, a transmission time of the -time div:ision multiple signal is indiv:idually ancl irregularly variable in each o:E the repeated paths. This ~0 res~.lLts in individLIal var:iatiolls or t:ime devi<Ltlorls o-E the t:i.me slots receivecl at eacll repeater stat:ion. In addit;.on, such a varlation o:E the transmiss:ion time is increased when a plurality o:E the repeater stat:ions are included in the repeated paths.
It is an object of this invention to provide a repeater station which can protect each time slot from being indi.vidually varied :Erom one another.
It is anotller object of this invention to provide a repeater station of the type described which can avoid an increase of a variation of a trans-'. ~
mission linc~.
It is a further object of ~his invention -to provide a repeater station of the type described, wherein an upper station is not subjected to a harmful influence even when each time slot received at the repea-ter station is individually varied from one another.
A repeater station to which this invention is applica~le is for re-peating a first sequence of downward time slots from a first station to a second station as a second sequence of downward time slots and -for transmitting a first succession of upward time slots to the first station in response to a second succession of upward time slots received from the second station. A particular downward time slot in each o:E tlle :Eirst alld the seconcl secluences comprises a syncllrolliz:illg s:ign.l:l. A part:icullr upw.lrcl t:ime slot in e;lCil ot' the :E:i.rst nnd tho SCCOlld SllCCOSS:i.OllS corresl)ollcls to tho part:i.cu:llr clownwcl:rcl t:inllo sloc.. I.',ucll o:E the downward alld the upward time slots has a predetermined lengtll except fo:r the particular downward and upward time slots. The repeater station includes detecting means for detecting the synchronizing signal included in the first seqllence to produce a detection signal. According to this invention, the repeater station comprises timing signal produci]lg means responsive to the cletection signal for prod~lcing a :Eirst and a second timing signal when a :Eirst precle-term:i]led clLIrat:iorl lapses a:Eter cletection o:E the synchronizillg signal in-cluded in the fi.rs-t sequellce ancl when a second preclete:rm:inecl clurat:ioll lapses after product:ion of the :Eirst timing signa:l, respectively, memory means coupled to the timing signal producing means for memorizing in:Eormation carried in the upward time slots o:E the second succession, and reading means responsive to the second timing signal for reading the upward time slot information memorized in the memory means to produce the upward -time slots of the :Eirst succession.
Thus, in accordance with this invention, there is provided a repeater statioll for repeating a first sequence of downward time slots ,Erom a first station to a second station as a second sequence of downward time slots and for transmitting a first succession of upward time slots to said first station in response to a second succession of upward time slots received from said second station, a particular downward time slot in each of said first and said second sequences comprising a synchronizing signal, a particular upward time slot in each of said first and said second successions corresponding to said particular downward time slot, each of said downward and said upward time slots having a predetermined length except for said particular downward and upward time slots, said repeater station including detecting means for detecting the synchronizing signal included in said first se~luence to produce a detection si.gnal, wherein the :iml)rovemerlt compr:ises: t:im:i.ng s:ignal prodl,lc:illg mealls respons:ive to said clete~ctloll s:i.gna:L :Eo:r p~oducillg a. E:i.rst cllld 1 SCCOlld tilllillg S.Lglla'l Whell a i'';ir~t predeterminecl duratioll lapses a:Eter cletection of the synchroni.zing signal in-cluded in said first sequence and when a second predetermined duration lapses after production o:E said first timing signal, respectively; memory means coupled to said timillg signal producing means for memorizing information carried in the upward time slots of said second succession; and reading means responsive to said second timing signal :Eor reading the upward tinle slot information memorized in saicl memory means to produce the upward time slots o:E said :Eirst succession, The invention is described in accordance with the drawings, wherein:
Figure 1 shows, in block, a radio relay system comprising a plurality of repeater stations to each o:E which this invention is applicable;
Figure 2 exempli.fies an arrangement of time slots sent downwardly from a central stati.on illustrated in Figure l;
Figure 3 shows a block diagram of a conventional repeater station for ~ 3~
use in the radio relay system illustrated in Figure l;
Figure 4 shows a time chart -for describing operation of the conven-tional repeater station illustrated in Figure 3;
Figure 5 shows a block diagram of a repeater station according to a preferred embocliment of this invention, which is for use in the radio relay system illustrated in Figure l;
Figure 6 shows a block diagram of a timing circuit for use in the repeater station illustrated in Figure 5;
Figure 7 shows a block diagram of a memory section for use in the repeater station illustrated in Figure 5; and Figure 8 shows a time chart Eor describlng operntiorI oE the repcater stn-tioIl iJ,lustratecl i,n l;igure 5.
I~clorriIlg to I~i,guro I, a radio rolay systom to which tI~is iIlvellt;,on is applicable is Eormed by a timc clivision multiple network Eor carrying out communication by the use of time division mul-tiple signals. Such time division multiple signals will be simply called signals hereinafter. The radio relay system comprises a central station 11 and a plurality of substations 12-1, 12-2, ..., 12-p remote from the central station 11. A plurality of repeater stations 13-1, 13-2, ..., 13-q are placed between the central station 11 and the sub-stations 12-1 - 12-p. TIIe n-lmber oE the substatioTIs 12 (suEEixes omitted) may be diEferent Erom th.-t o-E the repeater stations 13 ~suEEixes omlttccl also).
The signals are repeated in each of the repeater stations 13 to be transmitted from each of the repeater stations 13 in a direction towards the central station ll or towards the substations L2. Tne direction towards the central station 11 will be referred to as "upward" while the direction towards the substations 12, as "downward".
Temporarily referring to Figure 2, a sequence of time slots TSo, TS1, ~ 3S
..., TS is repeated at every frame to carry the signals. The frame lasts a duration to of ~ milliseconds to put a predetermined number of bits therein.
The predetermined number is equal to 2816 by way of example. The illustrated time slot sequence is for transferring the signals from the central station 11 downwards. The leading one of the time slots in each frame has a bit length of 30~ bits and includes a frame synchronizing signal of 16 bits following a preamble signal of 16 bits. Each of the remaining time slots has a predeter-mined bit length of 166 bits differellt from the bit length of the leading time slot. The last one TSn of the time slots is accompanied by guard bits (not shown) of 22 bits.
The frame synchronizing signal is produced by the central station 11 and clelivered to the repeater stations 13 and to the substntions 12. Conscquent-ly, the ropeater stations 13 allCI the substQt:iolls 12 are all operated :in Syll-chrollism with the Eralnc syncllrolli.zillg s:ignal.
Referring to Pigure 1 again and Pigure 3 a:Eresh, a conventional repeater station indicated at 13 is used as each one of the repeater stations 13-1 - 13-q illustrated in Figure 1 and is placed between an upward and a down-ward station which are situated upwarcls and downwards of the repeater station 13, respectively. The upward station may be either the central station 11 or another repeater station while the downward station, either a further repeater station or the substations 12. The upward and the downward stations will be called a first and a second station, respectively, hereinlEter. Por a better understanding of this invention, let the illustrated repeater station 13 be operated as the repeater station 13-1 illustrated in Figure 1. In this event, the central station 11 acts as the first station while each of the substation 12-2 and the repeater stations 13-2 and 13-3, as the second station. The repeater station 13-1 may be referred to as a speciEic repeater station.
The specific repeater station 13-1 serves to repeat a first sequence of downward time slots from the first station to the second station as a second sequence of downward time slots. Each of the :Eirst and the second sequences is similar to that illustrated in Figure 2. Therefo:re, the frame synchronizing signal is included in a particular or a control time slot TSo of each of the first and the second sequences. For convenience of description, the particular time slots TSo in each of the first and the second sequences may be called a downward particular time slot and is represented by TSod~ More particulaTly, the signals are supplied :from the first or upward station to a first reception antenna 16 as the :Eirst sequence of downward time slots and is sent through a f:irst recelver :l7 to a fi.rst demodulator 18 to be demodulated :into a success:i.on o.l`:~i.rst domodLI:Lcltecl bit s:i.gnals. ~rho flrst domodulatecl s:i.gnal :i.s de:l.ayocl a :Elrst predeterminecl delay t:ime tE by a flrst delay circuit 19 and is sent from a first transmisslon antenna 21 to the second station as the second sequence of downward time slots after subjected to modulation and amplification by a first modulator 22 and a first transmitter 23, respectively. At this time, the sig-nals are sent to the second station in synchronism wlth the frame synchronizing s:ignal.
On the other hand, the specific repeater station 13-1 is operable to transmit a :Eirst succession o:E upward time s:Lots to the first stat:ion in response to a second succession of upward time slots received from the second station.
Each of the first and the second successions includes a particular or a control upward time slot TSoU corresponding to the particular downward time slots TS
although somewhat different from each of the first and the second sequences of downward time slots. Anyway, each of the first and the second successions forms a :Erame having a frame length which is common to that illustrated with reference to Figure 2.
More specifically~ the signals are supplied from the second station to a second reception antenna 26 to be sent through a second receiver 27 to a second demodulator 2~. As a result, the second clemodulator 2~ produces a suc-cession of second demodulated bit signals. The second demodulated bit signals are delayed a second predetermined delay time t by a second delay circuit 29 to be supplied to a second transmitter 31 through a second modulator 32 for carrying out modula~ion of the second demodulated bit signals. The second pre-determined de]ay time tS may be equal to the first predetermined delay time tf.
An amplified and modulated signal is sent through a second transmission antenna 33 towards the first or central station in synchronism with the frame synchron-:izing signal.
In r~igure 2, it is to be noted that the spccific repeat,er station 13-'L
is suppLicd with the tinle division miltiple s:ignals through var:io~ls kinds o~
transmission paths and that each time slot is assigned common to the respective substations 12. This means that each time slot received at the specific re-peater station 13-1 is individually variable or fluctuated from one another in dependency on the transmission paths, as will be described in detail.
Referring to Figure ~ discussion will be directed to each of the particular downward time slot TSod and the particular upward time slot TSoU
by way of example. The central station 11 transmits the particular downward time slot TSod at a first titne instant Tl towards the specific repeater station 13-1. After a transmission delay time t between the central and the specific repeater stations 11 and 13-1~ the particular downward time slot TSod is received at the repeater station 13-1 at a second time instant T2 and delayed the first predetermined delay time tf by the first delay circuit 19 as described in con-Junction with ~igure 3 to be sent to the second station at a third time instant T3.
~ 3~
The particular downward time slot TSod transmitted from the repeater static>n 13-1 is returned back to the specific repeater station 13-1 as the par-ticular upward time slot TSo at a fourth time instant T4 after a time interval ty(l). The time interval ty(l) may be called a reception time interval at the specific repeater station 13-1. The particular upward time slot TSoU is delayed the second predetermined delay time ts by the second delay circuit 29 to be transmitted from the repeater station 13-1 to the central station 11 at a fifth time instant T5. Thereafter, the particular upward ~ime slot TSoU is received by the central station 11 at a sixth time instant T6 after the transmission delay time ta between the repeater station 13-1 and the central station 11. Thus, the central station 11 receives the particular upward t:ime slot TSoU after a time interval ty(0~ at the s:ixth time installt '['6 The time interval ty(O~ is de~;necl botweoll procluctiorl oE the particular clownwarcl t:inle slot 'I'S(~c~ and rocot)tioll o~ thc particular upward time slot 'l'Sou and may be named a reception time interval at the central sta~ion 11. As is apparent from Figure 4, the reception time in-terval ty(O~ is given by:
ty(O~ = 2ta + tf -~ ty(l~ -~ tS. (1~
tlowever, it is practically difficult to precisely determine the re-ception time interval ty(O~ because the transmission delay time ta is inevitably variable. In this connection, the reception time interval ty(O~ may be called a theoretical or an ideal reception time interval.
Let a practical transmission delay time and a practical reception time interval be represented by ta' and ty'(O~, respectively. ~nder the circumstances, the practical reception time interval tyl(O~ is given by:
tyl(O~ = 2ta' ~ tf ~ ty(l~ ~ tS- (2) From Equations (1) and (2~, a difference, namely, a time deviation ~ty between the theoretical and the practical reception intervals is given by:
C~
~ty = Ity(O) - ty'(0)1. (3) Equation (3) shows that the practical reception time interval ty'(0) is shifted from the theoretical reception time interval ty(O) by Aty.
As is the case with the reception time interval at the central station 11, the reception time in-terval t (1) which may be theoretically detarmined at the specifi.c repeater station 13-1 is different from a practical reception time interval ty'(l).
Like in Equation (3), a time deviation ~ty(l) between the theoretical and the practical reception time intervals ty(l) and ty'(l) is given by:
~ty(l) = Ity(l) - ty'(l)l. (~) 'I'ak:ing ~qua.t:i.on (~) into cons:icleration, that recept.ion ti.lllC :inter.val at tho centra:l station 1:l wh:i.ch :is represented by ty"(0) :is Inodi.~:ied :i.nto:
ty"(0) = ty(O) -~ ~ty(0) ~ Qty(l}.
As a result, a time deviation ~t from the theoretical reception time interval ty(O) is given by:
~t = ~ty(O) -~ ~ty(l). (5) Likewise, when the particular upward time slot TSoU is suppli.ed to the central station 11 through the repeater stations equal ln number to _, a time dev:iation ~t is represented by:
~t = ~ ~t (q) (6) q=0 Equation (6) also holds with respect to the remaining downward and the remaining upward time slots except the particular downward and the parti-cular upward time slots.
As readily understood from ~'igure 1, each of the upward time slots reaches the central station 11 through various kinds of transmission paths and is, therefore, individually deviated from one another. In order to put the radio relay system into normal operation without a malfunction, the above-mentioned time devia~ion or variatlon should be reduced as little as possible.
Referring to Figure 5, a repeater station 13' according to a preferred embodiment of this invention is assumed to be operated as the specific repeater station 13-1 illustrated in Figure 1 and comprises similar parts designated by like reference numerals. The illustrated repeater station 13' further comprises a detector 40 supplied with the first demodulated bit signal succession from the first demodulator 18. The detector 40 detects the Erame synchronizing sig-nal included in the first sequence of downward time slots and produces a detec-tion signal DS on detection of the frame synchronizing signal. Such a detector 40 may comprisc a shift reglster Eor successively storing the time division muLtiple access signcLls, a reEcrence circuit Eor storing a reEorerlcc signal ro-preselltcltive oE the frcmle synchronlzirlg signal, and a coml)cLrator Eor colnparing the stored si~nals with the reference s;gnal to produce the detection signal when the former coincides with the latter.
Referring to Figure 6 anew and Figure 5 again, the detection signal DS is supp]ied from the detector 40 to a timing circuit 41. The timing circuit 41 comprises a delay member 44 ~Figure 6~ for delaying the detection signal DS
a first predetermined duration. The first predetermlned duratlon is predictive-ly determlned so that the upward partlcular time slot reaches the spec:i~lc re-peater station 13-1 after lapse of the first predetermlned duration. More specifically, the Eirst predetermined duration is decided ln consideration of the first predetermlned delay tlme tf ln the flrst delay circuit 19 (Figure 5) and the ldeal receptlon tlme interval ty(l) at the speclflc repeater station 13-1. In the e~ample belng lllustrated, the flrst predetermlned duration ls equal to that total length of the first predetermlned delay tlme tf and the ideal reception time interval ty(l) from which a duration for the preamble (35 signal of the do~nward particular time slot ls subtracted.
Thus, the delay member 4~1 produces a deLayed detection signal DD de-layed the first predetermined duration relative to the detection signal.
Responsive to the delayed detection signal DD, a flip flop 46 is set to supply an enable signal of a logic "1" level to an AND gate ~8. The enable signal lasts each time slot, as will become clear as the description proceeds.
The AND gate ~8 is given a sequence of clock pulses from a clock generator 50.
The ~D gate 48 therefore allows the clock pulses to pass therethrough during presence of the enable signal.
Supplied with the clock pulses through the AND gate 48, a counter 52 succcssively counts the clock puLses to produce a sequellcc o counts as a se-q~lCllCe of adclress signclls~ respectivoly.
The tlming clrcuit ~1 comprlses a read-only melllory 5~ having a pLural-ity of addresses equal in number to the number ~2816) of bits included in each frame. First and second timing pulses FT and ST each of which takes a logic "1"
level are memorized in each o-f the addresses. The read-only memory 54 produces the first timing pulses FT of whlch a leadlng one appears ln response to the delayed detection slgnal DD. The leadlng timlng pulse may be referred to as a flrst tlmlng slgnal. each of the second tlming pulses ST ls delayed the second predetermlned delay time ts relative to each of the f:irst tlmlng pulses F:T.
Thus, each of the second timing pulses is produced when the second predetermlned delay time t lapses after production of each of the first timing pulses FT.
For example~ a leading one of the second timing pulses ST appears when the second predetermined delay time tS lapses after production of the first timing signal. The leadlng one of the second tlming p~lses ST is referred to as a second timing signal. The second predetermlned delay time tS may be called a second predetermined duration.
In this structure, when a specific one of the addresses is accessed by one of the address signals, one of either the first or the second timing pulses FT or ST is read out of the specific address and lasts during the one address signal. Likewise, each timing pulse is successively read out of the read-only memory 54 by accessing each address by the address signals.
The second timing pulses ST may be produced by delaying the first timing pulses FT the second predetermined duration by the use of a delay element.
When the first timi.ng pulses FT are all read out o-f the read-only memory 5~ together with the second timing pulses ST, a reset signal RS is fed back to the flip flop 46 to reset the same.
Ile:Eerr:ing to F:igure 7 afresll and Figure 5 agaln, the first and thc sccond t:im.i.ng pulses l'T ancl srr' arc sellt :trom tlle t:inling c:ircu:it ~l;l to n Illolnory section 60 between the second clemodulator 28 and the second modulator 32. The memory section 60 is supplied with the second demodulated bit signal succession designated by DM from the second demodulator 28 to produce a succession of memorized signals TR. ~lore specifically, the memory section 60 comprises a random access memory 61 having a plurality of address blocks. Each address block has a plurality of addresses, each having a bit capacity of 8 bits and servcs to memorize the signals included in each time slot. In this st-ructure, each signal of the second democlulated bi.t signal is memorized in each address of 8 bits.
The memory section 60 comprises a write-in address indicator 62 responsive to each of the first timing pulses FP for producing a first address signal ADF and a read address indicator 63 responsive to each of the second tim-ing pulses SP for producing a second address signal ~DS. The first and the second address signals ADF and ADS are selectively supplied through a read/write controller 6~ to the random access memory 61.
On the other hand, the second demodulated bit signal sequence DM is successively and scrially stored in a fiTst shift register section 66. The first shift register section 66 serves to convert the serial demodulated signal DM into a parallel bit signal of 8 bits. For this purpose, the first shift regis~er section 66 comprises a shift register of 8 stages and a counter for producing an enable signal each time when the second demodulated bit signal DM
is counted to 8. Simultaneously with the enable signal, the parallel bit signal is stored in an address specified by the first address signal ADF kept in the write-in address indicator 64. Similar operation is successively carried out with respect to each of the addresses specified by the first address signal ADF.
After production of the first address signal ADF, the second address signcLl ADS speciEy:ing the same address as tlle f:irst address si.gnal AD~ is given to the random access memory 61 frolll the read addre~s indicator 63. As a rcsu;lt, mcmorized dcmodulated signals are read Ollt of the random access mcmory Gl in parallel to be stored in a second shift register 67. The second shift register 67 serves as a parallel-to-serial converter for converting each of the parallel deModulated bit signals to a serial bit signal. The serial bit signal is pro-duced from the second shift register 67 as the memorized s-ignal sequence TR.
At any rate, the random access memory 61 memorizes the signals during the second predetermined duration TS.
Turning back to Figure 5, ~he memorized signal sequence l'R is supplied through the second modulator 32 and the second transmitter 31 to the second transmission antenna 33 and is sent to the central station 11.
Referring to Figure 8, operation of the specific repeater station 13-1 will be described in conjunction with the central station 11 by way of example. When the particular downward time slot l'Sod is produced at the first time instant Tl as described in connection with Figure 4, the time slot TSod is received by the specifi.c repeater station 13-1 at the second time instant T2 after the transmission delay time ta and is transmitted towards the second sta-tion at the third time interval T3 after the first predetermined delay tlme t~
through the first delay circuit 19. After the particular downward time slot TSod is sent from the specific repeater station 13-1 at the third time instant T3, the specific repeater station 13-1 produces the leading one of the first pulses FP at the :Eourth time instant T4 at which the particu:Lar upward time slot TSod is to arrive at the specific repeater station 13-1. The fourth time in-stant T~ appears after a reception time interval ty(l) equal to the predictive time interval. Thus, the predictive time interval is determined in considera-tion of the first predetermined delay time tf and the time :interval ty~l).
The particular upward time slot TSoU is trallslllittecl upwards from the spec:iE1.c rcpeater stat:ion 13-:L to tho celltral station 1:l at the :EiFth t:ime ~nst~mt T5 wh:icll ls determilled by the :leading one o:E the second t:illling pulses SP. The particular upward time slot TSoU reaches the central station 11 from the specific repezter station 13-1 at the sixth time instant T6 after the trans-mission de:Lay time ta.
Herein, let a time interval tx(l) between the third time instant T3 and the fifth time instant T5 be equal to an ideal or a theoretical t.i.me inter-val which is invariable. It is assumed that the particular upward time slot TSoU is sent :Erom the speci:Eic repeater station 13-]. to the central station 11 when the ideal time interva]. tx~l) lapses after transmission of the particular downward time slot TSod from the specific repeater station 13-1 to the second station. Under these circumstances, the central station 11 can receive the particular upward time slot TSo a reception time inte-rval ty(O) after produc-tion of the particular downward time slot TSod~ Such a reception time interval ty~0) at the central station 11 is given by:
)5 ty~O) = 2ta + tf ~ tx~ 7) It is assumed that the transmission delay time ta is varied into ta' and, as a result, the reception time interval is changed to tyt~O). At this time, Equation ~7) is modified into:
ty'(O) = 2ta' + tf + tx~ 8) From Equations (7) and ~8), a time deviation at ~O) between t ~O) and tyl-~O) is given by:
~ty~O) = Ity~O) - ty'~O)I. ~9) When the reception time intervals at the specific repeater station 13-1 are theoretically and pract;.cally represented by ty~l) and tyl(l), respec-t:ively, a timc dev:i.ation Aty~l) betwcen them :is represented by:
Qty(l) = lty(:l) - ty'(l)l. (:lO) As is readily understood from ~quation (8), the sixth time instant T6 at which the particular upward time slot TSo arrives at the central station 11 is irrespective of, namely, :independent of the reception time interval ty(l) at the specific repeater station 13-1 because the ideal time interval tx(l) is invariable. Thus, the time interval Qty(l) indicated by Equation (10) is vari-able only in dependency on the transmission delay time between the central sta-tion 11 and the spec:i:Eic repeater station 13-1. Si.milar rclationship hold between each of the remaining repeater stat:ions and a repeater stat.ion nearest to each remaining repeater station. In other words, each time deviation between one of the stations, such as the central station, the repeater stations, and another station downwardly nearest to the one station is dependent only on a transmission delay time therebetween. Such a transmission delay time is never added to the other transmission delay times between the remaining stations.
Accordingly, the time deviation is never increased even when the particular up-ward time slot is received at the central station 11 through a lot of the re-s peater sta~ions. In order to form thc radio relay system, the first and the second predetermined durations should be varied in their lengths at each of the repeater stations.
Although -the above-mentioned discussion has been directed to the particular downward and the particular upward time slots, this applies to the other time slots. With the repeater station, it is possible to protect each time slot from being individually varied from one another by the use of the memory section for memorizing the slgnals in each address block assigned to each time slot and for reading the memori~ed signals out of each address block. Any-way, the central station 11 can receive the signals without superposition of each time deviati.on occurring between two adjacent stations.
Whlle tllis ;.nventlon }las thus :~ar be~en described in conj~mct:ion with apre:~c:rrcd emboditllent thereof, :it wll:L readily be possible :~or those sk:illed :itl the art to put this invelltion :i.nto p:ractice in various other manners. ~or ex-ample, the substations may be either fixed or moved.
Such a time division mul-tiple network compr:ises a central station and a plurality oE substations remote -from the central station. A radio relay system serves to carry out communication between the central station and the substations even when the substations are far from a coverage of the central station. For this purpose, at least one repeater station is placed between the central station and the substations in the radio relay system.
Each of conventional repeater stations is operable in response to a time division multiple signal which is arranged :in a succession o:E time slots ass:igllocl to the substatiolls carry:ing out comm~ :i.cati.oll. Sucll a tinlQ cl:ivisioll mu.l.t:i.l):lo s:i.gllcl:l is suL)p.L:iocl to eacll rol)oato:L stat:i.oll Erolll all ~Ipuol s~ut:i.c)ll allcl Irolll a .Lower stat:ioll si.tuatocl upstloam LLIIcLclownstrecLIIl relat:ivo to e.lcll:re,)o.:Lter station through various repeated paths, respectively. The upper station may be either the central station or another repeater station while the lower station, either a further repeater station or one o:E the substations.
As will later be described with re:Eerence to four Eigures of the accompanying drawing, a transmission time of the -time div:ision multiple signal is indiv:idually ancl irregularly variable in each o:E the repeated paths. This ~0 res~.lLts in individLIal var:iatiolls or t:ime devi<Ltlorls o-E the t:i.me slots receivecl at eacll repeater stat:ion. In addit;.on, such a varlation o:E the transmiss:ion time is increased when a plurality o:E the repeater stat:ions are included in the repeated paths.
It is an object of this invention to provide a repeater station which can protect each time slot from being indi.vidually varied :Erom one another.
It is anotller object of this invention to provide a repeater station of the type described which can avoid an increase of a variation of a trans-'. ~
mission linc~.
It is a further object of ~his invention -to provide a repeater station of the type described, wherein an upper station is not subjected to a harmful influence even when each time slot received at the repea-ter station is individually varied from one another.
A repeater station to which this invention is applica~le is for re-peating a first sequence of downward time slots from a first station to a second station as a second sequence of downward time slots and -for transmitting a first succession of upward time slots to the first station in response to a second succession of upward time slots received from the second station. A particular downward time slot in each o:E tlle :Eirst alld the seconcl secluences comprises a syncllrolliz:illg s:ign.l:l. A part:icullr upw.lrcl t:ime slot in e;lCil ot' the :E:i.rst nnd tho SCCOlld SllCCOSS:i.OllS corresl)ollcls to tho part:i.cu:llr clownwcl:rcl t:inllo sloc.. I.',ucll o:E the downward alld the upward time slots has a predetermined lengtll except fo:r the particular downward and upward time slots. The repeater station includes detecting means for detecting the synchronizing signal included in the first seqllence to produce a detection signal. According to this invention, the repeater station comprises timing signal produci]lg means responsive to the cletection signal for prod~lcing a :Eirst and a second timing signal when a :Eirst precle-term:i]led clLIrat:iorl lapses a:Eter cletection o:E the synchronizillg signal in-cluded in the fi.rs-t sequellce ancl when a second preclete:rm:inecl clurat:ioll lapses after product:ion of the :Eirst timing signa:l, respectively, memory means coupled to the timing signal producing means for memorizing in:Eormation carried in the upward time slots o:E the second succession, and reading means responsive to the second timing signal for reading the upward time slot information memorized in the memory means to produce the upward -time slots of the :Eirst succession.
Thus, in accordance with this invention, there is provided a repeater statioll for repeating a first sequence of downward time slots ,Erom a first station to a second station as a second sequence of downward time slots and for transmitting a first succession of upward time slots to said first station in response to a second succession of upward time slots received from said second station, a particular downward time slot in each of said first and said second sequences comprising a synchronizing signal, a particular upward time slot in each of said first and said second successions corresponding to said particular downward time slot, each of said downward and said upward time slots having a predetermined length except for said particular downward and upward time slots, said repeater station including detecting means for detecting the synchronizing signal included in said first se~luence to produce a detection si.gnal, wherein the :iml)rovemerlt compr:ises: t:im:i.ng s:ignal prodl,lc:illg mealls respons:ive to said clete~ctloll s:i.gna:L :Eo:r p~oducillg a. E:i.rst cllld 1 SCCOlld tilllillg S.Lglla'l Whell a i'';ir~t predeterminecl duratioll lapses a:Eter cletection of the synchroni.zing signal in-cluded in said first sequence and when a second predetermined duration lapses after production o:E said first timing signal, respectively; memory means coupled to said timillg signal producing means for memorizing information carried in the upward time slots of said second succession; and reading means responsive to said second timing signal :Eor reading the upward tinle slot information memorized in saicl memory means to produce the upward time slots o:E said :Eirst succession, The invention is described in accordance with the drawings, wherein:
Figure 1 shows, in block, a radio relay system comprising a plurality of repeater stations to each o:E which this invention is applicable;
Figure 2 exempli.fies an arrangement of time slots sent downwardly from a central stati.on illustrated in Figure l;
Figure 3 shows a block diagram of a conventional repeater station for ~ 3~
use in the radio relay system illustrated in Figure l;
Figure 4 shows a time chart -for describing operation of the conven-tional repeater station illustrated in Figure 3;
Figure 5 shows a block diagram of a repeater station according to a preferred embocliment of this invention, which is for use in the radio relay system illustrated in Figure l;
Figure 6 shows a block diagram of a timing circuit for use in the repeater station illustrated in Figure 5;
Figure 7 shows a block diagram of a memory section for use in the repeater station illustrated in Figure 5; and Figure 8 shows a time chart Eor describlng operntiorI oE the repcater stn-tioIl iJ,lustratecl i,n l;igure 5.
I~clorriIlg to I~i,guro I, a radio rolay systom to which tI~is iIlvellt;,on is applicable is Eormed by a timc clivision multiple network Eor carrying out communication by the use of time division mul-tiple signals. Such time division multiple signals will be simply called signals hereinafter. The radio relay system comprises a central station 11 and a plurality of substations 12-1, 12-2, ..., 12-p remote from the central station 11. A plurality of repeater stations 13-1, 13-2, ..., 13-q are placed between the central station 11 and the sub-stations 12-1 - 12-p. TIIe n-lmber oE the substatioTIs 12 (suEEixes omitted) may be diEferent Erom th.-t o-E the repeater stations 13 ~suEEixes omlttccl also).
The signals are repeated in each of the repeater stations 13 to be transmitted from each of the repeater stations 13 in a direction towards the central station ll or towards the substations L2. Tne direction towards the central station 11 will be referred to as "upward" while the direction towards the substations 12, as "downward".
Temporarily referring to Figure 2, a sequence of time slots TSo, TS1, ~ 3S
..., TS is repeated at every frame to carry the signals. The frame lasts a duration to of ~ milliseconds to put a predetermined number of bits therein.
The predetermined number is equal to 2816 by way of example. The illustrated time slot sequence is for transferring the signals from the central station 11 downwards. The leading one of the time slots in each frame has a bit length of 30~ bits and includes a frame synchronizing signal of 16 bits following a preamble signal of 16 bits. Each of the remaining time slots has a predeter-mined bit length of 166 bits differellt from the bit length of the leading time slot. The last one TSn of the time slots is accompanied by guard bits (not shown) of 22 bits.
The frame synchronizing signal is produced by the central station 11 and clelivered to the repeater stations 13 and to the substntions 12. Conscquent-ly, the ropeater stations 13 allCI the substQt:iolls 12 are all operated :in Syll-chrollism with the Eralnc syncllrolli.zillg s:ignal.
Referring to Pigure 1 again and Pigure 3 a:Eresh, a conventional repeater station indicated at 13 is used as each one of the repeater stations 13-1 - 13-q illustrated in Figure 1 and is placed between an upward and a down-ward station which are situated upwarcls and downwards of the repeater station 13, respectively. The upward station may be either the central station 11 or another repeater station while the downward station, either a further repeater station or the substations 12. The upward and the downward stations will be called a first and a second station, respectively, hereinlEter. Por a better understanding of this invention, let the illustrated repeater station 13 be operated as the repeater station 13-1 illustrated in Figure 1. In this event, the central station 11 acts as the first station while each of the substation 12-2 and the repeater stations 13-2 and 13-3, as the second station. The repeater station 13-1 may be referred to as a speciEic repeater station.
The specific repeater station 13-1 serves to repeat a first sequence of downward time slots from the first station to the second station as a second sequence of downward time slots. Each of the :Eirst and the second sequences is similar to that illustrated in Figure 2. Therefo:re, the frame synchronizing signal is included in a particular or a control time slot TSo of each of the first and the second sequences. For convenience of description, the particular time slots TSo in each of the first and the second sequences may be called a downward particular time slot and is represented by TSod~ More particulaTly, the signals are supplied :from the first or upward station to a first reception antenna 16 as the :Eirst sequence of downward time slots and is sent through a f:irst recelver :l7 to a fi.rst demodulator 18 to be demodulated :into a success:i.on o.l`:~i.rst domodLI:Lcltecl bit s:i.gnals. ~rho flrst domodulatecl s:i.gnal :i.s de:l.ayocl a :Elrst predeterminecl delay t:ime tE by a flrst delay circuit 19 and is sent from a first transmisslon antenna 21 to the second station as the second sequence of downward time slots after subjected to modulation and amplification by a first modulator 22 and a first transmitter 23, respectively. At this time, the sig-nals are sent to the second station in synchronism wlth the frame synchronizing s:ignal.
On the other hand, the specific repeater station 13-1 is operable to transmit a :Eirst succession o:E upward time s:Lots to the first stat:ion in response to a second succession of upward time slots received from the second station.
Each of the first and the second successions includes a particular or a control upward time slot TSoU corresponding to the particular downward time slots TS
although somewhat different from each of the first and the second sequences of downward time slots. Anyway, each of the first and the second successions forms a :Erame having a frame length which is common to that illustrated with reference to Figure 2.
More specifically~ the signals are supplied from the second station to a second reception antenna 26 to be sent through a second receiver 27 to a second demodulator 2~. As a result, the second clemodulator 2~ produces a suc-cession of second demodulated bit signals. The second demodulated bit signals are delayed a second predetermined delay time t by a second delay circuit 29 to be supplied to a second transmitter 31 through a second modulator 32 for carrying out modula~ion of the second demodulated bit signals. The second pre-determined de]ay time tS may be equal to the first predetermined delay time tf.
An amplified and modulated signal is sent through a second transmission antenna 33 towards the first or central station in synchronism with the frame synchron-:izing signal.
In r~igure 2, it is to be noted that the spccific repeat,er station 13-'L
is suppLicd with the tinle division miltiple s:ignals through var:io~ls kinds o~
transmission paths and that each time slot is assigned common to the respective substations 12. This means that each time slot received at the specific re-peater station 13-1 is individually variable or fluctuated from one another in dependency on the transmission paths, as will be described in detail.
Referring to Figure ~ discussion will be directed to each of the particular downward time slot TSod and the particular upward time slot TSoU
by way of example. The central station 11 transmits the particular downward time slot TSod at a first titne instant Tl towards the specific repeater station 13-1. After a transmission delay time t between the central and the specific repeater stations 11 and 13-1~ the particular downward time slot TSod is received at the repeater station 13-1 at a second time instant T2 and delayed the first predetermined delay time tf by the first delay circuit 19 as described in con-Junction with ~igure 3 to be sent to the second station at a third time instant T3.
~ 3~
The particular downward time slot TSod transmitted from the repeater static>n 13-1 is returned back to the specific repeater station 13-1 as the par-ticular upward time slot TSo at a fourth time instant T4 after a time interval ty(l). The time interval ty(l) may be called a reception time interval at the specific repeater station 13-1. The particular upward time slot TSoU is delayed the second predetermined delay time ts by the second delay circuit 29 to be transmitted from the repeater station 13-1 to the central station 11 at a fifth time instant T5. Thereafter, the particular upward ~ime slot TSoU is received by the central station 11 at a sixth time instant T6 after the transmission delay time ta between the repeater station 13-1 and the central station 11. Thus, the central station 11 receives the particular upward t:ime slot TSoU after a time interval ty(0~ at the s:ixth time installt '['6 The time interval ty(O~ is de~;necl botweoll procluctiorl oE the particular clownwarcl t:inle slot 'I'S(~c~ and rocot)tioll o~ thc particular upward time slot 'l'Sou and may be named a reception time interval at the central sta~ion 11. As is apparent from Figure 4, the reception time in-terval ty(O~ is given by:
ty(O~ = 2ta + tf -~ ty(l~ -~ tS. (1~
tlowever, it is practically difficult to precisely determine the re-ception time interval ty(O~ because the transmission delay time ta is inevitably variable. In this connection, the reception time interval ty(O~ may be called a theoretical or an ideal reception time interval.
Let a practical transmission delay time and a practical reception time interval be represented by ta' and ty'(O~, respectively. ~nder the circumstances, the practical reception time interval tyl(O~ is given by:
tyl(O~ = 2ta' ~ tf ~ ty(l~ ~ tS- (2) From Equations (1) and (2~, a difference, namely, a time deviation ~ty between the theoretical and the practical reception intervals is given by:
C~
~ty = Ity(O) - ty'(0)1. (3) Equation (3) shows that the practical reception time interval ty'(0) is shifted from the theoretical reception time interval ty(O) by Aty.
As is the case with the reception time interval at the central station 11, the reception time in-terval t (1) which may be theoretically detarmined at the specifi.c repeater station 13-1 is different from a practical reception time interval ty'(l).
Like in Equation (3), a time deviation ~ty(l) between the theoretical and the practical reception time intervals ty(l) and ty'(l) is given by:
~ty(l) = Ity(l) - ty'(l)l. (~) 'I'ak:ing ~qua.t:i.on (~) into cons:icleration, that recept.ion ti.lllC :inter.val at tho centra:l station 1:l wh:i.ch :is represented by ty"(0) :is Inodi.~:ied :i.nto:
ty"(0) = ty(O) -~ ~ty(0) ~ Qty(l}.
As a result, a time deviation ~t from the theoretical reception time interval ty(O) is given by:
~t = ~ty(O) -~ ~ty(l). (5) Likewise, when the particular upward time slot TSoU is suppli.ed to the central station 11 through the repeater stations equal ln number to _, a time dev:iation ~t is represented by:
~t = ~ ~t (q) (6) q=0 Equation (6) also holds with respect to the remaining downward and the remaining upward time slots except the particular downward and the parti-cular upward time slots.
As readily understood from ~'igure 1, each of the upward time slots reaches the central station 11 through various kinds of transmission paths and is, therefore, individually deviated from one another. In order to put the radio relay system into normal operation without a malfunction, the above-mentioned time devia~ion or variatlon should be reduced as little as possible.
Referring to Figure 5, a repeater station 13' according to a preferred embodiment of this invention is assumed to be operated as the specific repeater station 13-1 illustrated in Figure 1 and comprises similar parts designated by like reference numerals. The illustrated repeater station 13' further comprises a detector 40 supplied with the first demodulated bit signal succession from the first demodulator 18. The detector 40 detects the Erame synchronizing sig-nal included in the first sequence of downward time slots and produces a detec-tion signal DS on detection of the frame synchronizing signal. Such a detector 40 may comprisc a shift reglster Eor successively storing the time division muLtiple access signcLls, a reEcrence circuit Eor storing a reEorerlcc signal ro-preselltcltive oE the frcmle synchronlzirlg signal, and a coml)cLrator Eor colnparing the stored si~nals with the reference s;gnal to produce the detection signal when the former coincides with the latter.
Referring to Figure 6 anew and Figure 5 again, the detection signal DS is supp]ied from the detector 40 to a timing circuit 41. The timing circuit 41 comprises a delay member 44 ~Figure 6~ for delaying the detection signal DS
a first predetermined duration. The first predetermlned duratlon is predictive-ly determlned so that the upward partlcular time slot reaches the spec:i~lc re-peater station 13-1 after lapse of the first predetermlned duration. More specifically, the Eirst predetermined duration is decided ln consideration of the first predetermlned delay tlme tf ln the flrst delay circuit 19 (Figure 5) and the ldeal receptlon tlme interval ty(l) at the speclflc repeater station 13-1. In the e~ample belng lllustrated, the flrst predetermlned duration ls equal to that total length of the first predetermlned delay tlme tf and the ideal reception time interval ty(l) from which a duration for the preamble (35 signal of the do~nward particular time slot ls subtracted.
Thus, the delay member 4~1 produces a deLayed detection signal DD de-layed the first predetermined duration relative to the detection signal.
Responsive to the delayed detection signal DD, a flip flop 46 is set to supply an enable signal of a logic "1" level to an AND gate ~8. The enable signal lasts each time slot, as will become clear as the description proceeds.
The AND gate ~8 is given a sequence of clock pulses from a clock generator 50.
The ~D gate 48 therefore allows the clock pulses to pass therethrough during presence of the enable signal.
Supplied with the clock pulses through the AND gate 48, a counter 52 succcssively counts the clock puLses to produce a sequellcc o counts as a se-q~lCllCe of adclress signclls~ respectivoly.
The tlming clrcuit ~1 comprlses a read-only melllory 5~ having a pLural-ity of addresses equal in number to the number ~2816) of bits included in each frame. First and second timing pulses FT and ST each of which takes a logic "1"
level are memorized in each o-f the addresses. The read-only memory 54 produces the first timing pulses FT of whlch a leadlng one appears ln response to the delayed detection slgnal DD. The leadlng timlng pulse may be referred to as a flrst tlmlng slgnal. each of the second tlming pulses ST ls delayed the second predetermlned delay time ts relative to each of the f:irst tlmlng pulses F:T.
Thus, each of the second timing pulses is produced when the second predetermlned delay time t lapses after production of each of the first timing pulses FT.
For example~ a leading one of the second timing pulses ST appears when the second predetermined delay time tS lapses after production of the first timing signal. The leadlng one of the second tlming p~lses ST is referred to as a second timing signal. The second predetermlned delay time tS may be called a second predetermined duration.
In this structure, when a specific one of the addresses is accessed by one of the address signals, one of either the first or the second timing pulses FT or ST is read out of the specific address and lasts during the one address signal. Likewise, each timing pulse is successively read out of the read-only memory 54 by accessing each address by the address signals.
The second timing pulses ST may be produced by delaying the first timing pulses FT the second predetermined duration by the use of a delay element.
When the first timi.ng pulses FT are all read out o-f the read-only memory 5~ together with the second timing pulses ST, a reset signal RS is fed back to the flip flop 46 to reset the same.
Ile:Eerr:ing to F:igure 7 afresll and Figure 5 agaln, the first and thc sccond t:im.i.ng pulses l'T ancl srr' arc sellt :trom tlle t:inling c:ircu:it ~l;l to n Illolnory section 60 between the second clemodulator 28 and the second modulator 32. The memory section 60 is supplied with the second demodulated bit signal succession designated by DM from the second demodulator 28 to produce a succession of memorized signals TR. ~lore specifically, the memory section 60 comprises a random access memory 61 having a plurality of address blocks. Each address block has a plurality of addresses, each having a bit capacity of 8 bits and servcs to memorize the signals included in each time slot. In this st-ructure, each signal of the second democlulated bi.t signal is memorized in each address of 8 bits.
The memory section 60 comprises a write-in address indicator 62 responsive to each of the first timing pulses FP for producing a first address signal ADF and a read address indicator 63 responsive to each of the second tim-ing pulses SP for producing a second address signal ~DS. The first and the second address signals ADF and ADS are selectively supplied through a read/write controller 6~ to the random access memory 61.
On the other hand, the second demodulated bit signal sequence DM is successively and scrially stored in a fiTst shift register section 66. The first shift register section 66 serves to convert the serial demodulated signal DM into a parallel bit signal of 8 bits. For this purpose, the first shift regis~er section 66 comprises a shift register of 8 stages and a counter for producing an enable signal each time when the second demodulated bit signal DM
is counted to 8. Simultaneously with the enable signal, the parallel bit signal is stored in an address specified by the first address signal ADF kept in the write-in address indicator 64. Similar operation is successively carried out with respect to each of the addresses specified by the first address signal ADF.
After production of the first address signal ADF, the second address signcLl ADS speciEy:ing the same address as tlle f:irst address si.gnal AD~ is given to the random access memory 61 frolll the read addre~s indicator 63. As a rcsu;lt, mcmorized dcmodulated signals are read Ollt of the random access mcmory Gl in parallel to be stored in a second shift register 67. The second shift register 67 serves as a parallel-to-serial converter for converting each of the parallel deModulated bit signals to a serial bit signal. The serial bit signal is pro-duced from the second shift register 67 as the memorized s-ignal sequence TR.
At any rate, the random access memory 61 memorizes the signals during the second predetermined duration TS.
Turning back to Figure 5, ~he memorized signal sequence l'R is supplied through the second modulator 32 and the second transmitter 31 to the second transmission antenna 33 and is sent to the central station 11.
Referring to Figure 8, operation of the specific repeater station 13-1 will be described in conjunction with the central station 11 by way of example. When the particular downward time slot l'Sod is produced at the first time instant Tl as described in connection with Figure 4, the time slot TSod is received by the specifi.c repeater station 13-1 at the second time instant T2 after the transmission delay time ta and is transmitted towards the second sta-tion at the third time interval T3 after the first predetermined delay tlme t~
through the first delay circuit 19. After the particular downward time slot TSod is sent from the specific repeater station 13-1 at the third time instant T3, the specific repeater station 13-1 produces the leading one of the first pulses FP at the :Eourth time instant T4 at which the particu:Lar upward time slot TSod is to arrive at the specific repeater station 13-1. The fourth time in-stant T~ appears after a reception time interval ty(l) equal to the predictive time interval. Thus, the predictive time interval is determined in considera-tion of the first predetermined delay time tf and the time :interval ty~l).
The particular upward time slot TSoU is trallslllittecl upwards from the spec:iE1.c rcpeater stat:ion 13-:L to tho celltral station 1:l at the :EiFth t:ime ~nst~mt T5 wh:icll ls determilled by the :leading one o:E the second t:illling pulses SP. The particular upward time slot TSoU reaches the central station 11 from the specific repezter station 13-1 at the sixth time instant T6 after the trans-mission de:Lay time ta.
Herein, let a time interval tx(l) between the third time instant T3 and the fifth time instant T5 be equal to an ideal or a theoretical t.i.me inter-val which is invariable. It is assumed that the particular upward time slot TSoU is sent :Erom the speci:Eic repeater station 13-]. to the central station 11 when the ideal time interva]. tx~l) lapses after transmission of the particular downward time slot TSod from the specific repeater station 13-1 to the second station. Under these circumstances, the central station 11 can receive the particular upward time slot TSo a reception time inte-rval ty(O) after produc-tion of the particular downward time slot TSod~ Such a reception time interval ty~0) at the central station 11 is given by:
)5 ty~O) = 2ta + tf ~ tx~ 7) It is assumed that the transmission delay time ta is varied into ta' and, as a result, the reception time interval is changed to tyt~O). At this time, Equation ~7) is modified into:
ty'(O) = 2ta' + tf + tx~ 8) From Equations (7) and ~8), a time deviation at ~O) between t ~O) and tyl-~O) is given by:
~ty~O) = Ity~O) - ty'~O)I. ~9) When the reception time intervals at the specific repeater station 13-1 are theoretically and pract;.cally represented by ty~l) and tyl(l), respec-t:ively, a timc dev:i.ation Aty~l) betwcen them :is represented by:
Qty(l) = lty(:l) - ty'(l)l. (:lO) As is readily understood from ~quation (8), the sixth time instant T6 at which the particular upward time slot TSo arrives at the central station 11 is irrespective of, namely, :independent of the reception time interval ty(l) at the specific repeater station 13-1 because the ideal time interval tx(l) is invariable. Thus, the time interval Qty(l) indicated by Equation (10) is vari-able only in dependency on the transmission delay time between the central sta-tion 11 and the spec:i:Eic repeater station 13-1. Si.milar rclationship hold between each of the remaining repeater stat:ions and a repeater stat.ion nearest to each remaining repeater station. In other words, each time deviation between one of the stations, such as the central station, the repeater stations, and another station downwardly nearest to the one station is dependent only on a transmission delay time therebetween. Such a transmission delay time is never added to the other transmission delay times between the remaining stations.
Accordingly, the time deviation is never increased even when the particular up-ward time slot is received at the central station 11 through a lot of the re-s peater sta~ions. In order to form thc radio relay system, the first and the second predetermined durations should be varied in their lengths at each of the repeater stations.
Although -the above-mentioned discussion has been directed to the particular downward and the particular upward time slots, this applies to the other time slots. With the repeater station, it is possible to protect each time slot from being individually varied from one another by the use of the memory section for memorizing the slgnals in each address block assigned to each time slot and for reading the memori~ed signals out of each address block. Any-way, the central station 11 can receive the signals without superposition of each time deviati.on occurring between two adjacent stations.
Whlle tllis ;.nventlon }las thus :~ar be~en described in conj~mct:ion with apre:~c:rrcd emboditllent thereof, :it wll:L readily be possible :~or those sk:illed :itl the art to put this invelltion :i.nto p:ractice in various other manners. ~or ex-ample, the substations may be either fixed or moved.
Claims (2)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A repeater station for repeating a first sequence of downward time slots from a first station to a second station as a second sequence of downward time slots and for transmitting a first succession of upward time slots to said first station in response to a second succession of upward time slots receive from said second station, a particular downward time slot in each of said first and said second sequences comprising a synchronizing signal, a particular upwardtime slot in each of said first and said second successions corresponding to said particular downward time slot, each of said downward and said upward time sots having a predetermined length except for said particular downward and upward time slots, said repeater station including detecting means for detectingthe synchronizing signal included in said first sequence to produce a detection signal, wherein the improvement comprises:
timing signal producing means responsive to said detection signal for producing a first and a second timing signal when a first predetermined durationlapses after detection of the synchronizing signal included in said first se-quence and when a second predetermined duration lapses after production of said first timing signal, respectively;
memory means coupled to said timing signal producing means for memorizing information carried in the upward time slots of said second succes-sion; and reading means responsive to said second timing signal for reading the upward time slot information memorized in said memory means to produce the upward time slots of said first succession.
timing signal producing means responsive to said detection signal for producing a first and a second timing signal when a first predetermined durationlapses after detection of the synchronizing signal included in said first se-quence and when a second predetermined duration lapses after production of said first timing signal, respectively;
memory means coupled to said timing signal producing means for memorizing information carried in the upward time slots of said second succes-sion; and reading means responsive to said second timing signal for reading the upward time slot information memorized in said memory means to produce the upward time slots of said first succession.
2. A repeater station as claimed in Claim 1, said first succession reach-ing said first station with a variable delay, wherein said first predetermined duration is such that the particular time slot of said succession reaches said repeater station after lapse of said first predetermined duration, said second predetermined duration being determined in consideration of said variable delay.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP66934/1982 | 1982-04-20 | ||
| JP57066934A JPS58182928A (en) | 1982-04-20 | 1982-04-20 | Radio repeating system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1191205A true CA1191205A (en) | 1985-07-30 |
Family
ID=13330315
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000426287A Expired CA1191205A (en) | 1982-04-20 | 1983-04-20 | Repeater station for use in a radio relay system to protect time deviations of time slots |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US4490818A (en) |
| EP (1) | EP0092237B1 (en) |
| JP (1) | JPS58182928A (en) |
| AU (1) | AU553157B2 (en) |
| CA (1) | CA1191205A (en) |
Families Citing this family (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6225523A (en) * | 1985-07-25 | 1987-02-03 | Nec Corp | Radio communication system |
| WO1987006082A1 (en) * | 1986-03-25 | 1987-10-08 | Motorola, Inc. | Method and apparatus for controlling a tdm communication device |
| US4742514A (en) * | 1986-03-25 | 1988-05-03 | Motorola, Inc. | Method and apparatus for controlling a TDM communication device |
| GB8620333D0 (en) * | 1986-08-21 | 1986-10-01 | Uldeco Ltd | Radio communications |
| JPS6374234A (en) * | 1986-09-17 | 1988-04-04 | Nec Corp | Multi-direction multiplex communication system |
| US4912461A (en) * | 1986-11-05 | 1990-03-27 | Cellular Control Systems Corporation | Apparatus and network for transferring packets of electronic signals and associated method |
| JPS63283241A (en) * | 1987-05-15 | 1988-11-21 | Toshiba Corp | Mobile communication system |
| GB8809602D0 (en) * | 1988-04-22 | 1988-05-25 | British Telecomm | Mobile radio systems |
| GB8819501D0 (en) * | 1988-08-17 | 1988-09-21 | British Aerospace | Spacecraft payload |
| JPH02149029A (en) * | 1988-11-30 | 1990-06-07 | Nec Home Electron Ltd | Jitterless single-wire two-way optical transmission equipment |
| EP0515029B1 (en) * | 1991-04-19 | 1996-06-26 | Nec Corporation | Time-division multiplex communication system |
| US5291518A (en) * | 1991-09-06 | 1994-03-01 | Metriplex, Inc. | Link system for radio paging service |
| SE500620C2 (en) * | 1992-12-11 | 1994-07-25 | Televerket | Repeat function for short range radio systems |
| WO1994023504A1 (en) * | 1993-03-31 | 1994-10-13 | British Telecommunications Public Limited Company | Radio repeater |
| US6108364A (en) * | 1995-08-31 | 2000-08-22 | Qualcomm Incorporated | Time division duplex repeater for use in a CDMA system |
| JP3657343B2 (en) * | 1996-04-18 | 2005-06-08 | 富士通株式会社 | Wireless transmission system |
| JP2003087187A (en) * | 2001-09-13 | 2003-03-20 | Kddi Corp | Repeater device and communication control method |
| JP4671385B2 (en) * | 2001-09-13 | 2011-04-13 | 株式会社ウィルコム | Repeater device and communication timing control method |
| US7706745B2 (en) * | 2004-12-03 | 2010-04-27 | M&Fc Holding, Llc | Method, system, apparatus, and computer program product for communications relay |
| JP4682910B2 (en) * | 2006-04-26 | 2011-05-11 | 日本精工株式会社 | Linear motion guide device |
| JP4704469B2 (en) * | 2005-09-28 | 2011-06-15 | エルジー エレクトロニクス インコーポレイティド | Data cooperative relaying method of cellular network for broadcast multicast service |
| GB0616476D0 (en) | 2006-08-18 | 2006-09-27 | Fujitsu Ltd | Communication systems |
| WO2009049683A1 (en) * | 2007-10-19 | 2009-04-23 | Nokia Corporation | A relay, and a related method |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3562432A (en) * | 1966-11-16 | 1971-02-09 | Communications Satellite Corp | Synchronizer for time division multiple access satellite communication system |
| CA1030281A (en) * | 1972-10-31 | 1978-04-25 | Rudolf Debuda | System synchronization for multiple access to a communication satellite |
| FR2479515A1 (en) * | 1980-03-28 | 1981-10-02 | Telecommunications Sa | DIGITAL TRANSMISSION SYSTEM IN THE ALTERNATE |
-
1982
- 1982-04-20 JP JP57066934A patent/JPS58182928A/en active Granted
-
1983
- 1983-04-19 US US06/486,384 patent/US4490818A/en not_active Expired - Lifetime
- 1983-04-19 EP EP83103783A patent/EP0092237B1/en not_active Expired
- 1983-04-20 CA CA000426287A patent/CA1191205A/en not_active Expired
- 1983-04-20 AU AU13685/83A patent/AU553157B2/en not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| EP0092237B1 (en) | 1987-11-04 |
| JPS58182928A (en) | 1983-10-26 |
| JPH0123970B2 (en) | 1989-05-09 |
| EP0092237A2 (en) | 1983-10-26 |
| EP0092237A3 (en) | 1985-01-16 |
| US4490818A (en) | 1984-12-25 |
| AU553157B2 (en) | 1986-07-03 |
| AU1368583A (en) | 1983-10-27 |
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| MKEC | Expiry (correction) | ||
| MKEX | Expiry |