CA1191939A - Video inspection system - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE

A video inspection system comprising a TV camera for producing a digital video image of a subject, an interface, having a direct memory access channel, for structuring the digital data, a high speed random access memory for storing the digital data, a bus oriented processor for performing high speed processing of the digital data in the memory, a digital computer for controlling the operation of the system and an operator terminal for communicating with the system.

Description

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1 1IN THE UNITED STATES PATE~T AND TRADE~RK OFFICE

2 'PATENT OPER~TION

54¦ APPLICATION

RAY E. DAVIS, JR., RICHARD J. BECKER, ROBERT G. FOSTER, 6 I~ICHAEL 3. WESTKA~ER, EARLE J. TIl~OTHY and RIC~ARD H. JOHNSON

8 ¦VIDEO TNSPECTION SYSTEM
9 !i ~BACKGROUND AND BRIEF DESCRIPTION OF ~HE INVENTION
11 !i 12 ,I The present invention relates to a video inspection 13 system and, more particularly, to a real time video inspection 14 Isystem having sixteen levels of grey shade resolution.
15 , 16 Ii. It is known to employ closed circuit television for 17 ;process control. For e~ample, IJ. S. Patent No. 3,243,509 to 18 ¦IHans Sut discloses a system which employs a TV camera to detect 19 the phase boundary between the solid and liquid phases of a 20 ¦I semiconductor rod in a zone melting process. In U. S. Patent 21 IlNo. 4,064,534 to Tung Chang Chen et al a TV camera is employed , -22 Ias part of a quality control system in the manufacture of glass 23 ,jbottles, the outline of the finished bottle being compared with 24 1l that of a reference bottle. In U. S. Patent No. 4,135,204 to 25 jjRay E. Davis, Jr. et al, which is assigned to the assignee of I -26 ~ithe present invention, a TV camera is used to control the growth 27 !'of a thermometer end opening blister in a heated hollow glass 28 lrod by monitoring and iteratively controlling the growth of the 29 ,edges of the bli5ter using edge detection techniques.

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., These prior art systems are directed to situations where the parameter of interest is an edge or boundary which may be compared with a pre-existing reference. There are many applications, however, where edge or boundary detection is totally inadequate. These applications include, for example, pattern recognition and area measurement.
The present invention overcomes the limitations of the prior art systems and comprises a high speed, real time video inspection system having sixteen levels of ~rey shade resolution which is suitable for both pattern recognition and area measurement applications. The video inspection system of the present invention is small, powerful, fast, relati~ely inexpensive and very reliable.
The present invention relates to a video inspection system comprising: a solid state TV camera for producing video images of a sub~ect, the TV camera comprising a two-axis array of picture elements, each picture element having at least sixteen levels of grey scale resolution; an interface connected to the ~V camera for receiving and structuring the video images; a high speed random access memory connected to the interface for storing digital data received from the interface; a computer connected to the interface and the memory for controlling the operation of the system; and a terminal connected to the computer for permitting an operator to communicate with the computer.
In its method aspect, the invention relates to a video inspection method comprising the steps of: producing a first image on a solid state TV camera having a two-axis array of picture elements, each picture element having at least sixteen ,!`. - 2 1, h / cl-~

levels of gray scale resolution; producing a digital representation of the first image; storing the digital representation of the first image in a memory; selecting an inspection algorithm to be employed in an inspection operation; selecting a window to be inspected; selecting a threshold for the window selected; producing a second image on the TV camera; producing a digital representation of the second image; storing the digita:l representation of the second image in a memory; comparing the stored image of the first image with the stored image of the second image within the selected window; and determining whether the result of the comparison exceeds the selected threshold.
In an illustrative embodiment the present invention is employed in a quality control application to compare labels on bottles coming off a high speed fill line with a reference label to determine whether the bottles bear the correct labels and whether the copy on the labels has been smudged or other--wise damaged. In a preferred mode of operation the difference~
if any, between the reference label and the label being in-spected is displayed on a TV monitor for viewing by an operator. The advantages of this application are readi].y apparent since now it is possible to have 100% quality contxol inspection without incurring large labor expenditures.

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In a pre~erred embodiment the present invention employs 2 a solid state TV camera utilizing, for example, a 244 by 236 3 array of elements, each of the 57,584 elements constituting a

4 "pixel" or elemental part of the overall picture. The unstructured Idigital data from the TV camerra goes to an interiace which has a 6 'direct ~emory access (D~) channel. The interface/~MA takes the 7 real time video information and structures the data, using 8 sixteen grey shade levels~ and combines four "pixels" into each g i'word. In addition to the TV camera a,nd interface!DMA, the 10 ;present invention employs a P~I memory, a processor, a computer ll (with an associated operator control terminal) and graphics 12 imaging circuitry (with an associated TV monitor). The interface 13 D~, RAM memory, processor, cornputer and graphics imaging circuitry 14 are all interconnected by means of a "multibus" which carries data, contro7 and address signals. The interface/DMA synchronizes 16 the TV camera with the multibus and transfers the TV image in 17 jreal time to any desired location in the RA~l memory. Once the 18 1 image is in the Rl~I memory, processing occurs on two levels.
~9 j The computer provides the supervisory tasks for serial com~unica- i 20 Il'tion, memory management input/output processing, data acquisition j 2l i,~and display whereas the processor is used for high speed array 22 !lprocessing of the data in the RAM memory. The system software 23 ! is located in the computer l! .
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25 1' As already noted, the video inspection syste~ of the 26 present invention is readily adaptable to numerous applications 27 involving pattern reco~nition and area measurement. Applications 28 involving pc~ttern recogni~ion include the inspection of cornpleted ?.9 printed circui~: boards, the detection of flaws in manufactured itcm8, in~:rudcr detectlon, tl?e analysis of fingerprints, the .

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1 detection of foreign objects in ~ontainers beore they are filled 2 and as part of aircraft landing or collision avoidance systems.
3 Applications involving area measurement: include the measurement 4 of machined parts, the measurement of heart wall thickness, the ,,semi-automated analysis of X-rays and the precision area measure-6 ment of irregular objects. I~ith the acldition o~ positioning 7 inormation, the video inspection system of the present invention 8 can also be used to generate visual sensory signals for robotics.
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ll The video inspection system of the present invention 11 is so versatile because it can acquire and process the full range 12 of data available frorn the sensor. Moroever, by using standard 13 optical components with the TV camera the images available for 14 analysis extend from the micro scale to the macro scale, from images of microelectronic circuitry to images of planetary bodies 16 or star fields. In addition, standard optical filtering 17 technlques may also be employed to enhance or otherwise alter 18 the frequency response of the system and to develop, for eY.ample, 19 ,'specific color sensitivities.

21 ¦I Since the solid state TV camera is sensitive to the 22 1l entire visible spectra and beyond, the video inspection s~stem 23 'lof the present invention may be applied to any task where the 24 visible spectrum is involved. For example, secondary emissions of X-rays via fluoroscopy may be analy~ed. Spectral analysis 26 and colorimetry are also possible. Photographs oE events can 27 also be analyzed in a varicty o ways. In short, the applications;
28 ~or th~ video inspection 5ystem of tlle present invention are 29 lllnited on1y by the resolution o the sensor and the ability to develop appropriate irna~e processing softwarc.

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il ..................... ' I ~_' .,. . i 1 , BRIEF DESCRIPTION OF THE DRAWINGS
2l 3 The present invention is described with reference to 4 , the following drawings ~hich form a part of the specification

5 ', and wherein: '

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7 ll Fig. 1 is a functiona]. block diagram of a preferred

8 embodiment of the video inspection system of the present

9 'I inventio~;

10 11 1

11 , Fig. 2 is a functional block diagram of the

12 l interface/D~ of Fig. l;
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14 ~ Figs. 3A through 3C comprise a schematic diagrarn of the interface/D~ of Fig. 2;
16 ' 17 Fig. 4 is a functional block diagram of the RAM
18 ll memory of Fig. l;

20 ,¦ - Figs. 5A through 5C ccmprise a schematic diagram 21 "' of one "page" of the memory of Fig. 4;
22 li 23 ¦¦ Figs. 6A and 6B comprise a functional block diagram 24 ,l of the processor of Fig. l; and 26 Figs. 7A through 7~1 comprise prograrn flo~/ diagrams 27 for thc embodiment of Fig. 1.

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1 . DETAILED DESCRIPTION

3 The video inspection system of the present in~ention is 4 shown in Fig. 1 and comprises a T.V. camera 10, an interface/DM
5 , 20, a RAM memory 30, a processor 40, a comp~ter S0, an operator 6 1,i control terminal 60, graphics imaging circuitry 70 and a T.V.
7 ' monitor 80. The interface/D~, R~I memory, processor, computer 8 and graphics imaging circuitry are all linked by multibus 90.
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lo ~! T.V. camera 10 is preferably a solid state camera 11 such as the General Electric Co. TN2500 CID (char~e injection 12 device) which has a planar, two axis array of image elements

13 comprising 244 vertical elements by 248 horiz?ntal elements.

14 In the preferred embodiment only 236 of the 248 rows are used.
This produces 57,584 picture elements or "pixels" per frame, e~ch "pixel" measuring 36x46 micrometers. Full frame readout 17 takes 30 milliseconds and each pixel has sixteen levels of grey 1~ shade resolution ~which requires 4 bits). Thus, digital data is 19 , produced by the T.V. camera at a rate of 507,58r pixels x 4 bits ~ I mi liseconds p~r-20 1 ~ 7.68 megabits/sec.
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22 1l Interface/DMA 20 is shown in Fig. 2 in the form of a 23 ~¦functional block diagrarn and is shown schematically in Eig. 3.
24 i!Interface/D~ per~orms two separate functions. It accumulates 25 ll four 4-bit pixels into one 16--bit (2 byte) word and performs the 26 direct memory address to RAM memory 30. It also performs all 27 the synehroni~ation between the video data and multibus 90.
2~ Interface/D~ 20 is capable of addressing up to 1 megabyte of 29 storage, transferring up to 128 thousand bytes in a single 3Q ~ransfer burst, and can operate at up to 10 megabyte per second .
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1 transfer rates. The minim~ transfer rate is 2 megabytes per 2 ` second. Thus, interface/D~ 20 is able to process the full 3 resolution and sensitivity of the sensor.

High speed static ~1 memory 30 is shown in functional 6 block diagram form in Fig. 4 and schematically in Fig. 5. RAM
7 memory 30 has a one megabyte address space so that i~ can receive 8 in real time the full output fror.l TV camera 10. RAM memory 30 ` g , has a worst case storage cycle time of 100 nanoseconds and is able to read/write either 8 or 16 bits per cycle anywhere in 11 the one megabyte address space.

13 High perforrnance bus oriented processor 40 is sho~m in 14 . functional block diagra~ form in Fig. 6 and schematically in Fig. 7. Processor 40 is designed to access prograLn code and 16 data from Multibus 90 and execute the program at ~n eight to ten 17 megahertz clock rate. Processor 40 performs high speed computa-18 tion on the data in memory 30.
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20 '. System computer 50 may be an Intel SBC 86/12 micro- ¦
21 '' computer which is based on the Intel 8086 16-bit micLoprocessor.
22 , Once the image has been stored in memory 30, the bulk of the 23 processing is carried out with computer 50. As noted earlier, 24 ; cornputer 50 provides the supervisory tasks for serial communica-25 '! tion, memory management i.nput/output processing, data acquisition 26 and display. Resident in computer 50 are those pro~ram codes 27 necessary to perform a vari.ety oE video processing functions 28 including pattern recognition and non-contac~ measurement. The 29 soXtware i.s stored in LPROM's forming a part of computer 50.
Figs. 7A through 7H cornprisç program Elow charts for an applica-g~

1 Ij tion of the video inspection system of the present invention 2 ,, involving label inspection.

4 ~l Operator control terminal 60 is shown in Fig. 1 and permits the operator to communicate with computer 50. Operator --- 6 ,~ control terminal 60 may be any standard ~S232C terminal such as I A
7 a Data General Dasher terminal. Operator control terminal 60 8 cor,prises a keyboard and a CRT or a keyboard printer. Operator g 1I control terminal 60 comm~micates with computer 50 and permits, 10 ll for example, parametric changes to be made to the software.
11 ;, 12 ~ Graphics imaging circuitry 70 interfaces with multibus 13 90 and puts data into a format suitable for display on TV
14 monitor ~O-, In the preferred embodiment, graphics imaging circuitry 70 produces a composite video grey scale output.
16 G-aphics imaging circuitry 70 may be a model RGB-256 single 17 board 16 color/grey CRT controller manufactured by Matrox 18 ' Electronic Systems, Ltd., Montreal, Quebec, Canada. The 19 i RGB-256 graphics imaging circuitry is compatible with the 20 l~ standard Intel SBC bus system. T.V. monitor 80 may be any 21 ¦~ standard television monitor. ! - -~2 23 1¦ ` Multibus 90 interiaces with various bus elel~ents, i.e., 24 'I masters, slaves and intelligent-slaves. A bus master is any ~5 I module which has the ability to control the bus. The master 26 exercises this control by acquiring the bus through bus exchange 27 logic and thcn generating command signals, address signals and 28 memory addresses. Many modules may be bus masters. The most 29 basic type of bus masl:cr includes the Intel MD-800 CPU module ~hi.cll includes a procegsor and bus exchange loeic. More complex C~P~

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l ~,masters include the Intel SBC 80/20, the Intel SBC 80/30 and the 2 Intel 86/12 microcomputers. I
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4 l Another type of module which can interface to the multibus is the bus slave. Bus slaves decode the address lines 6 ,land act upon the command signals from the bus masters. The bus 7 slaves are incapable of controlling the multibus. Examples of 8 bus slaves include input/output registe:rs and memories.
9 i1 ! The third type oi module that can interface to the 11 multibus is the intelligent slave. The intelligent slave has all 12 the attributes of a slave module in that it decodes addresses and 13 acts upon commands from master modules. However, the intelligent 14 slave contains a microprocessor which is programmed with software, or firmware and is used to control the on-board memory and the 6 input/output but not the multiblls.

18 l, In terrns of bus elements, interface/D~A 20, RAM memory 19 ,30 and graphics imaging circuitry 70 are slave modules whereas 20 li processor 40 is an intelligent slave module and computer 50 is a 21 !Imaster module.
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23 ~l As shown in Fig. 1, the signals on multibus 90 comprise 24 il data lines, control lines and address and inhibit lines. The data lines comprise sixteen bidirectional data lines, DATO/ through 26 D~TF/ in hexadecimal notation. The control lines cornprise clocks, 27 commands, aclcnowledge and initialize. The clocks are "constant 2~3 c].ock" (CCLK/) and "bus clock" (BCLK/). The cormnands comprise 29 "memory write" (~TC/~, "memory rcad" (I~RDC/), "input/output write" (IO~C/) and "input/output read" (IORC/). lhe ackno~ledge 1 j com~and is "transfsr acknowledge" (XACK/~ while the inltialize 2 jl command- is "initialize" (INIT/). The address lines comprise 3 ,¦ADRO/ through ADR13/ (0-9, A-F, 10-13) while the inhi.bit lines 4 i comprise INHl/and INH2/. Byte control is BHEN/.
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6 Referring to Fig. 2, all DMA control words are accepted on the trailing edge of CCLKl. Commands are implemented 8 or data loaded 30 nanoseconds after address recognition. Start 9 DMA is implemented on the next leading edge of BCLK/. An XACK/
10 is generated by the DMA four CCL~/ pulses following address 11 recognition.
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13 ¦ T.V. camera 10 can be operated in either the "122 14 ¦. sequential" mode or the "244 sequential" mode. In the "122 ¦ .

15 ~! sequentia]." mode only 122 lines of 236 "pixels" each is utilized. i

16 ! In the "244 sequential" mode, ~hich is the highest resolution

17 ~ mode of the camera, 244 line,s of 236 "pixels" each are employed.

18 The mode of camera operation is indicated by an appropriate output~

19 from camera mode logic 216. In the preferred em~odiment the "244 sequential" mode is employed. .,~

22, Interface/DMA utillzes three timing signals from the 23 camera. These are vertical SyllC, sync blanking and 5x clock.
2~ These three signals are shown in Fig. 2 as inputs CO camera sync timing 204. Sync blanking is a logic signal which goes high 26 when valid data is presented at DAT 4 through DAT 7. The 27 1I vertical sync pulse occurs at the beginning of each data field, 28 1, two fields forming one frame. In the "2~4 sequential" mode the 29 jl vertical sync pulse occurs every 33.32 milliseconds. The 5x 30 ~, clock is ,22.5 mc~nhertz and a new ~-bit "pixel" is presented ln , ~ ~,t3~
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1 'on lines DAT 4 through DAT 7 every 5 clock pulses (every 222 2 llnanoseconds). Thus, a 16 bit (2 byte) word is transferred every 3 888 nanoseconds and there are 62 word transfers per line.
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5 ¦1 Interiace/DMA 20 is shown in Fig. 2 in functional block 6 !Idiagram form as comprising input buffer 201, register file 202, 7 Itiming logic 203, camera sync timing 204, nibble count logic 205, 8 read/wri~e equalization 206, read word logic 207, write word g i'logic 208, write tirning logic 209, transfer length register 210, 10 ,,address register 211, interrupt encode logic 212, address decode 11 logic 213, bus driver 214, output buffer 215 and camera mode 12 logic 216. Interface/DMA 20 is also shown schematically in 13 Fig. 3. Although ~mnecessary for a full understanding of the 14 present invention, the relationship between the functional block diagram of Fig. 2 and the schematic diagram of Fig. 3 is set 16 forth below. It will be understood by those skilled in the art 17 that since interface/DI~A is constructed from multifunctional 18 ! integrated circuit "chips," each of which may contain a number 19 l of separate circuits, a given "chip" in Fig. 3 ~ay form part of 2~ ~! several different unctional blocks in Fig. 2.

2'~ ¦ Buffer 201 comprises U14 and U15. Register file 202 23 ¦ comprises U7 through U10. Timîng logic 203 comprises U2, U20 24 ~and U22. Camera sync ti~ing 204 comprises Ul and U2. Nibble 25 " count logie 205 comprises Ul, U3, U4 and Ull. Read/write 26 equaliYation 206 comprises U5, U6 and U70 tnrough U72. Read 27 word logic 207 comprises U5 whereas write word logic 208 comprises, 28 U6. Write timlng logic 209 coMprises U13, U18 through U21, U55, 29 1 1156 an~ U1.0Q. Transfer length .egister 210 comprises U32 through U35. ~dclress register 211 comprises U27 through U31.

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1 I Interrupt encode logic 212 comprises U41 and U16. Address 2 decode logic 213 comprises U38 through U41, U53 and U54.
3 Address bus driver 214 comprises ~45 ~hrough U48. Data buffer ; 4 ' 215 comprises U49 through U52.
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6 ¦1 Interface/D~ 20 is treated as an input/output (I/O) 7 I device by computer 50. The base address is swltch selectable 8 ; from 0000H to 0090H. In operation IO~C/ is buffered and decoded 9 1l by address decode logic 213. The D~ block responds to each 10 I properly decoded address in its instruction set with an XACK/ to 11 ! computer 50. Computer 50 responds to the XACK/ by releasi~g 12 I the IOWC/ and the DMA block is then in condition to operate on !j 13 another IOWC/.
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~ The instruction set for the D~ block comprises the 16 following four I/O write com~ands.
17 11 i 18 ! (1) Reset Interrupt (RST INT) - The reset interrupt i 19 ilcommand is produced by address decode logic 213 in response to

20 I~an IOWC/ to address 00'x'0H from computer 50 via multibus 90.

21 ¦I No data is needed to produce a reset interrupt co~nand.

22 11

23 ;l (2~ Transfer length load (XFER I.NTH LD) ~ The

24 'transfer length load command is produced by address decode logic

25 ' 213 in response to an IOWC/ at address 00'x'2li from computer 50

26 and is prescnted to both transfer length register 210 and

27 1 address register 21;. The transfer length load command causes 2~ , the number of words to be transerred to be read into transfer 29 , len~th regis~er 210.
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CHP-7], I' 1 l (3) Starting Address Load ~STADR l,D) - The starting 2 ,,address loacl command is prod~lced by address decode logic 213 in 3 response to an IOWC/ at address 00'x'41l from computer 50. The 4 starting address load command causes the high order 16 bits of the', 5 ! 20 bit startin~ address to be, read into the address 00'x'4H. This j 6 'laddress is then shifted left 4 bits so that all starting addresses !
7 Iwill be on even 16 byte boundaries.
8 , l g Ij~ (4) Start Transfer (GO) ~- The start transfer command ¦
10 lis produced by address decode logic 213 in response to an IOWC/ at ¦
11 address 00'~'6H. The start transfer co~nand goes to timing logic 12 203 where an "enable" signal is produced which enables interfac,e/-13 ,D~ 20. On the appropriate edge of the bus clock pulse, which is 14 receivecl by timing logic 203 from multibus 90, a BUSY/ signal is produced by timing logic 203 and interface/DMA 20 begins data 16 transfer on the next vertical sync pulse from canera 10.
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18 li The interface block captures the four most significant 19 ¦ibits of data from TV camera 10 and organizes then i.nto 16 bit (2 20 i~byte) words. When a word has been formed a ~TC/ is sent to RAM
21 !I,memory 30 and data is transferred to memory 30 on multibus 90. ¦ . ~
22 llUpon recei.ving an XACK/ from Rl~ memory 30, the interface removes 23 jlthe address and data from multi.bus 90, decrements transfer 24 ,jlen~th register 210 and increments address register 211 twice.
25 ',The interace also keeps track of how many "nibbLes`' (pixels) 26 it has received from 1~ camera 10 in any horizontal line. At the 27 ,end of each line the nuillbeJ. of "nibbles" received rom the camera

28 ,is checked and, i~ necessary, extra transfers made to memory 30 so 2,9 that words-out equals words-in for each line. In the preferred embo~liment the interface block transfers a l6 bit worcl into R~M
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1 memory 30 in 180 ~anoseconds. This includes all "housekeeping"
2 functions on registers and tinting functions required by multibus 3 compatible circuits.
.4 1i l~ The rising edge of the vertical sync pulse, which occurs ¦
6 'lonce each field, is taken as t = o. If an enable signal is .
7 ~presented by timing logic 203 at camera syrtc ~iming 204, then 8 transfer begins. Four bits of data are loaded into one of the : 9 1l4 by 4 registers comprisin~ register.file 202. As pointed out ,Iearlier, register file 202 comprises registers U7 through U10.
11 ;,The first "pixel" (four bits) is loaded, for exa~ple~ in level 0 12 of register U7.-'~he second, third and fourth plxels are loaded 13 in -level 0 of registers U8, U9 and U10, respectively. The 14 ,fifth, sixth, seventh and eighth pixels are loaded in level 1 of registers U7, U8, U9 and U10, respectively. Read word logic 207 16 (counter US) controls which word location will be loaded and is 17 ,incremented after every fourth nibble (pixel).
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19 j'i When data transfer con~lences, the zero levels o~ i 20 ,registers U7, U8, U9 and U10 are read out in parallel to form the 21 'l¦first 16 bit (2 byte) word. The second word is transferred by I .
22 ,Ireading out in parallel level 1 froGt registers U7 through U10. ¦
23 II,The high data transfer rates are obtained by sequentially loading 24 lidata into one level of registers U7 through U10 whlle simttltan-25 lleously readln~ data out in parallel from another level of all 26 four registers.

28 ~1hen the fourth nibble has been loaded into register

29 fi].e 202, a XFUR REQ si~nal is generated witllin ~rit~ ~iming logic 209 (U].3, pin 5) and used to entble .tddress bus driver 214.

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3~1 vHP-71 ., 1 After a suitable delay, an MWTC/ is asserted on multibus 90 by 2 'write timing logic 209. When RAM memory 30 has accepted the data 3 an XACK/ si~nal is asserted on the bus and decoded by write 4 timing logic 209 which causes removal of the address and data 5 1l from the bus as well as ~he MWTC/. Transfer leng~h register 6 ~l210 is decremented and address register 211 is bumped twice 7 to conform with the word transfer mode of operation~

l' At the end of each horizontal line if there are no 1 10 ~words left in regi.ster file 202, eounters U5 and U6 of 1 11 read/~rite equalization 206 will be equal. If the counters 12 are onequal, successive transfers will be made until the counters 13 are equal. At that point, no more transfers will be made for 14 . that line. Transfer of data will continue until a zero length signal is generated by transfer length register 210. At that 16 time bus control is relinqulshed and the interface block 17 1! disabled. Computer 50 issues a RST INT command and reclaims 18 control of the bus.
19 Ij 20 1! Referring to Fig. 4, RAM memory 30 comprises control 21 libus hardware 301, read/write buffers 302, memory array 303, 22 1l address decode logic 304 and address block select jumpers 305.
23 ''Memory array 303 preferably comprises a series of 64 "pages", each 24 l,page having 16K 8-bit bytes of storage. Control bus hardware 301 25 ,lsynchronizes between the bus and memory array 303. Address decode 26 logic 304 determines whether the address on the bus corresponds 27 to one i.n memory array 303. Address bloc~ select jumpcrs 305 28 determi.ne the basc address for each page (16K byte block) of 29 address space in memory array 303. Read/~rite bufEers 302 buffer data bet~een memory array 303 and the bus in rcsponse to an enable ,' ' ''' ;'''' ' .;-7~ 3~

1 signal produced by address decode logic 304.
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3 Referring briefly to Fig. 5, which is a schematic 4 `diagram of one "page" of R~l memory 30, U53 through U58 are 5 Iread/write buffers whereas ~2 through U3, U10 through U17, ,- 5 ~U20 through U27 and U28 through U35 comprise 32 Intel 2147-3 1 -7 l,4K by 1 bit logic chips providing for 16K 8-bit bytes of storage.
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10 .¦ Referring to Fig. 6, bus oriented processor 40 11 comprises microprocessor (CPU) 401 which is preferably an 12 ,.Intel 8086 16-bit microprocessor. Processor 40 also comprises 13 clock generator 402, status decoder 403, address latch 404, 14 bus arbiter 405, address bus driver 406, data bus driver 407, bus command decoder 408, interrupt jumpers 409, programmable 16 interrupt controller (PIC) 410, remote I/0 decoder 411, mailbox 17 register file 412, interrupt control register 413, local Il0 18 ~address decoder 414, memory address decoder 415, data buffer 416, 19 high speed ~ ~ memory 417 and high speed PROM memory 418.
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21 ll Bus oriented processor 40 is itself a complete computer I -22 l~in the sense that it has an I.SI microprocessor central processing 23 ilunit, memory, interrupt priority resolution circuitry and bus 24 'jarbitration. Processor 40 resides on the multibus and acts as 2S an asynchronous computing resource. In rmultibus terminology, 2~ processor 40 is an intelligent slave. The configuration of ' 27 processor 40 perrnits microprocessor 401 to operate on program 28 code and data at its maximum compu~ing speed. In addition 2~ cor,lpu~er 50, which in mul~ibus ~erminology is a m~ster module, ~o can address processor 40 and down-load and/or up-load program `~IP-71 ~ 3~

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1 code and/or data for asynchronous processing by bus oriented 2 processor 40. The central component of processor 40 which 3 permits this type of operation is the mailbox register file 412.

The implementation of a significant portion of the ~ S design of processor 40 is identical to the implementation of the 7 Intel SBC 86tl2 which, as previously noted, also employs an 8 Intel 8036 16-bit microprocessor. Accordingly, only those areas 9 , will be described where there exist significant departures from standard design.
11, 12 CPU 401 normally operates at an 8 megahertz clock 13 frequency, although it can be made to operate at up to 10 14 megahertz. All timing functions operate at the Eull clock frequency without any "wait" states.

17 The memory of processor 40 has been organized into 18 two separate address spaces. Addresses zero to 4095 comprise 19 very high speed static random access memory 417 which may, for !`
, example, comprise Intel 2147-3 devices. Addresses 1,019,904 to 21 1,024,000 comprise high speed EPROM memory 418 which may, for 22 ,l example, comprise Intel 2716-1 devices. ~Iemory address decoder 23 il 415 forces on board access for the two above-identified groups of 24 addresses and forces bus access for all other addresses.
2S ~, Communication for initiali~ation and norrnal operation oE
26 processor 40 is accornplished by means oE dual ported mailbox 27 register file 412 which responds to I/O commands, through jumper 28 selectable addresses, from cornputer 50 as well as I/O cornmands 29 from CPU 401. Thus, computer-to-computer col~nunications are accomplished tllrou~l~ mailbox register file 412 which may, for e:;al;lplc, comprise our 74I,S170 4 by 4 rcgiscer Eiles.

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1 ~ Progra~med I/0 i9 also decoded as on-board or off-board 2 addresses. Ho~ever, the on-board I/0 device address are jurnper 3 selectable so as to avoid I/0 address conflicts with other 4 devices. Processor 40 comprises three I/0 devices, viz:
prograrnmable interrupt controller 410; interrupt control 6 ! register 413; and mailbox register file 412. Each I/0 device is 7 allocated a block of four addresses, each address being an even 8 offset from a base address. For exar~ple, if the base address for ~` 9 ' programmable interrupt controller 410 were hexadecimal 40, then the succeeding addresses would be 42, 44, 46 and 4~ in 11 hexadecirnal.

13 All I/0 accesses not directed on-board are directed to 14 the rnultibus. All bus oriented memory and I/0 accesses are directed through "normal" bus arbitration. It should be noted, .. . i 16 ho~ever, that CPU 401 May, under firlmware control, "lock" the 17 ,, bus once it has cornpleted arbitration and perform subsequent 18 accesses without suffering any additional arbitration. This 19 , per~nits the fullest throughput performance to and from the bus, . when necessary.
21 ~
22 I, Processor 40 can also be made to operate as a slave 23 l~ processor. Under these conditions, upon initial power up and/or 24 a hardware RE~SET, the firmware resident in processor 40 perfor~s ' the initia]. configuration of programmable interrupt controller 26 410 and initialization of the memory, registers and stack 27 poi.nter. The f.irmware then halts processor 40. Computer 50 on 28 the rnultibus addresses mai.lbox register file 412 and loads a 29 ].6-bit vector into the rnailboY. register. Once the vector is loaded, an intcrrupt is generated to CPU 40L. The firn~iare ~ .
._ /y _ .
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,HP-71 .. I
resident in processor 40 exits the HALT state and performs an 2 l/O read to the mailbox register file. The l6-bit vector 3 address is read and used as the most significant 16 bits in a 4 20-bit off-board memory address. This memory location is the first word in a processor control block (PCB). The firmware 6 j`resident in pr~cessor 40 then accesses the PCB and reads and 7 operates on processor control words (PCWs) contained within 8 this PCB. The PCWs direct processor 40 to perform one of g the following three functions: ¦
10 ~
11 (1) Send Status - form and place a processor 12 status word (PSW) in a designated location in ~emory.

14 (2) I~ove Words - move words of program and/or data either from the memory of processor 40 to off-board 16 memory (e.g., RAM memory 30) or vice versa.

1?3 ,' (3) Execute - execute program code starting 19 at a designated address.

21 I The PCB contains a list of PCWs in a chain. Each PCW
22 ,' ~ay be followed by appropriate data words. Once a PCW has been 23 I decoded and executed, an interrllpt response will be sent, iE
24 so coded. The interrupt response is generated by interrupt control register 413. CPU 401 sets the appropriate interrupt 26 level into interrupt control register 413 and this level is 27 coupled to the multibus by means of an I/O write command to 28 the in~errupt control register.

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CilP-71' ~193~ :

l This scheme of comrnanding processor 40 and utilizing 2 ! the parallel interrupt mechanism permits high performance, 3 asynchronous computation with a minim~m of supervision and 4 maximum flexibility. In operation, image processing algorithms are down-loaded into RAM memory 417 of processor 40. These 6 l algorithms are executed on "pixell' data stored in R~5 memory 30 7 and provided to processor 40 via multibus 90. Thus, processor 40 8 performs high speed, asynchronous "array processing" of data 9 I stored in rnemory array 303 (Fig. 4).
10 ", ', 11 , The program llow charts for an application of the 12 present invention to label inspection are shown in Figs. 7A
13 through 7H. First a master label is placed before TV car~era 10.
14 The output from the TV camera is then structured by interface/DMA
20 and stored in ~M memory 30. Next the master label is display-16 ed on TV monitor 80 using graphics imaging circuitry 70. Alter-17 j natively, the master label could be displayed by a printer at 18 operator control terminal 60. The particular inspection l9 algorithm to be employed is then selected by the operator. The 20 1 algorith~ may, Eor example, involve an area calculation.
21 11 Alternatively, the algorithm may involve Q ~7eighted line I -22 1 computation. The operator next sets the "window" (portion of 23 ,, the 244 x 236 a~ray to be inspected) and "merit" (threshhold) 24 to be employed Eor the particular inspection operation.

26 The system is now set to inspect labels on, for 27 exclmple, bottles as they come o~f a high speed fill line. As 28 in thc case oE the master labei, the subject label is imaged by 29 TV camera 10 and the ou~put from the TV camera is structured by interface/D`5A 20 and stored.in I~AM rnemory 30. The window is . . .

--D?O

~ 71 ~ 3~
,, - i . .
.

l selected and a high speed image processin~ routine employed using , 2 ~us oriented processor 40. The routine selected ~ay, for example, 3 involve area or weighted line calculations. In both routines 4 corresponding pixels from the master and subject labels stored S in ~ memory 30 are selected and transferred to processor 40 ~ 6 ,where the absolute value of the difference in intensity is 7 computed. From this value is subtracted the selected noise 8 offset, which compensates for background interference.
9 ,;
; In the case of the weighted line routine, the weighte~
11 differences are accumulated across a ~iven line. The result of 12 the accumulation is then compared with the "merit" or threshhold 13 chosen for this window. If the accumulated result is greater than:
14 the merit, then an error is indicated. Assuming no error, ~successive lines of pixels are processed until the window has been 16 completed at which time the system is ready to inspect the 17 next subject label or the next window for this label.

.-19 , In the case of the area routine, all non-zero differences for the whole window are accumulated and compared 21 'jwith the merit for the window. It will be appreciated that ~he 22 ''meri~ for the area routine will normally be different from 23 (greater than) the merit for the weighted line routine. If the 24 accumulated differences for the window are greater than the ~erit for that wi.ndow, an error is indicated. If not, the system ls 26 ready to process the next label or the next window for this 27 label.

29 In both the area and weighted line routines the differ- i ences bet~7cell corresponding pixcls n~ay be presented to an 3~
;.IP-71 1 operator by a printer at ten~inal 60 or on TV monitor 80 so that, 2 in the event of an error indication, the operator can see the 3 cause of the error and, depending on its severity, accept or .4 reject the label.

~ 6 l,l The invention disclosed and claimed herein is not 7 limited to the preferred embodiment sho-~n or to the exemplary 8 application of that embodiment to label reading since g j modifica~ions will undoubtedly occur to persons s~illed in the art. Hence, departures may be made from the form of the 11 present invention without departing from the principles thereof.

13 ~hat ~7e clai~ is:

. . .

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,

Claims (18)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A video inspection system comprising:
(a) a solid state TV camera for producing video images of a subject, said TV camera comprising a two-axis array of picture elements, each picture element having at least sixteen levels of grey scale resolution;
(b) an interface connected to said TV camera for receiving and structuring said video images;
(c) a high speed random access memory connected to said interface for storing digital data received from said interface;
(d) a computer connected to said interface and said memory for controlling the operation of said system;
and (e) a terminal connected to said computer for permitting an operator to communicate with said computer.

2. A video inspection system according to Claim 1 further including a processor connected to said interface and said memory for performing high speed processing of the digital data stored in said random access memory.

3. A video inspection system according to Claim 1 wherein said two-axis array comprises over fifty thousand picture elements.

4. A video inspection system according to Claim 1 further comprising:

(a) graphics imaging circuitry connected to said interface, said memory and said computer; and (b) a TV monitor connected to said graphics imaging circuitry for displaying information produced by said video inspection system.

5. A video inspection system according to Claim 3 wherein said random access memory comprises means for storing at least on the order of one million bytes of digital data.

6. A video inspection system according to Claim 3 wherein said interface comprises means for transferring digital data to said random access memory at rates of on the order of ten megabytes per second.

7. A video inspection system according to Claim 1 wherein said computer comprises a 16-bit microprocessor and wherein said terminal comprises an RS232C terminal.

8. A video inspection system according to Claim 1 wherein said interface comprises means for monitoring how many picture elements have been received from said camera in any horizontal line and how many of those picture elements have been transferred to said random access memory and for ensuring that the number of picture elements received from said camera corres-ponds to the number of picture elements transmitted to said memory, for each horizontal line.

9. A video inspection system according to Claim 1 wherein said interface, said random access memory and said computer are linked by a multibus arrangement and wherein said interface comprises a direct memory access channel.

10. A video inspection method comprising the steps of:
(a) producing a first image on a solid state TV camera having a two axis array of picture elements, each picture element having at least sixteen levels of gray scale resolution;
(b) producing a digital representation of said first image;
(c) storing said digital representation of said first image in a memory;
(d) selecting an inspection algorithm to be employed in an inspection operation;
(e) selecting a window to be inspected;
(f) selecting a threshhold for the window selected;
(g) producing a second image on said TV
camera;
(h) producing a digital representation of said second image;
(i) storing said digital representation of said second image in a memory;
(j) comparing the stored image of said first image with the stored image of said second image within the selected window; and (k) determining whether the result of the comparison exceeds the selected threshhold.

11. A video inspection method according to Claim 10 including the additional steps of:

(a) displaying said first image; and (b) displaying said second image.

12. A video inspection method according to Claim 11 including the additional step of displaying any difference between said first and second images.

13. A video inspection method according to Claim 10 including the additional step of setting off an alarm if the result of the comparison exceeds the selected threshhold.

14. A video inspection method according to Claim 10 wherein the determination of whether the threshhold has been exceeded occurs at the end of each horizontal line-within the selected window.

15. A video inspection method according to Claim 10 wherein the determination of whether the threshhold has been exceeded occurs after inspection of the selected window has been completed.

16. A video inspection method according to Claim 10 wherein said digital representation of said first image is produced at a rate of at least seven megabits per second.

17. A video inspection method according to Claim 10 wherein siad two-axis array comprises at least fifty thousand picture elements.

18. A video inspection method according to Claim 10 wherein said first and second images are images of labels.