CA1198831A - Nondestructive dimensional detection system - Google Patents
Nondestructive dimensional detection systemInfo
- Publication number
- CA1198831A CA1198831A CA000441260A CA441260A CA1198831A CA 1198831 A CA1198831 A CA 1198831A CA 000441260 A CA000441260 A CA 000441260A CA 441260 A CA441260 A CA 441260A CA 1198831 A CA1198831 A CA 1198831A
- Authority
- CA
- Canada
- Prior art keywords
- layer
- targets
- pattern
- layers
- target
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4638—Aligning and fixing the circuit boards before lamination; Detecting or measuring the misalignment after lamination; Aligning external circuit patterns or via connections relative to internal circuits
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
- H05K1/0269—Marks, test patterns or identification means for visual or optical inspection
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09918—Optically detected marks used for aligning tool relative to the PCB, e.g. for mounting of components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
- H05K2201/10204—Dummy component, dummy PCB or template, e.g. for monitoring, controlling of processes, comparing, scanning
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0008—Apparatus or processes for manufacturing printed circuits for aligning or positioning of tools relative to the circuit board
Abstract
ABSTRACT OF THE DISCLOSURE
An inspection system for use in the fabrication of circuit boards of multiple, precisely registered layers. Each layer that is to be precisely registered within the circuit board is formed with at least two targets, each target corresponding in position to a target of another layer, and the targets of each layer defining a pattern that is unique to that layer. Radiography techniques allow a viewing of the registration of each target of a layer relative to a test target pattern. The test target pattern may be carried on a master template for the testing of individual layers for dimensional stability prior to stacking of the layers for lamination. Alternatively, the multiple layers may be stacked in their desired order, in which case the test target pattern for the targets of one layer are formed by the targets of at least two other layers. Layer registration of the multiple layers may be viewed prior to lamination, with adjustment or replacement of any mis-registered layer, or after lamination and prior to further processing. The targets may be formed in positions that define a pattern that is unique to a layer or in configuration that defines a pattern that is unique to a layer, or both.
An inspection system for use in the fabrication of circuit boards of multiple, precisely registered layers. Each layer that is to be precisely registered within the circuit board is formed with at least two targets, each target corresponding in position to a target of another layer, and the targets of each layer defining a pattern that is unique to that layer. Radiography techniques allow a viewing of the registration of each target of a layer relative to a test target pattern. The test target pattern may be carried on a master template for the testing of individual layers for dimensional stability prior to stacking of the layers for lamination. Alternatively, the multiple layers may be stacked in their desired order, in which case the test target pattern for the targets of one layer are formed by the targets of at least two other layers. Layer registration of the multiple layers may be viewed prior to lamination, with adjustment or replacement of any mis-registered layer, or after lamination and prior to further processing. The targets may be formed in positions that define a pattern that is unique to a layer or in configuration that defines a pattern that is unique to a layer, or both.
Description
MULTI-LAYER CIRCUIT BOARD INSPECTION SYSTEM
BAC~GROUND OF THE IN~ENTION
1. ~ield of the Invention.
The present invention relates to multi-layer circuit boards and, particularly, to the inspection of such boards during their fabrication.
Multi-layer circuit boards h~ve been defined as an interconnect package Whic}l con-tains more than two layers of circuitry. E~aving gro~l out of space and military applications in the early 60s, multi-layer boards are now used in many commercial applications. The various types of multi-layer boards fall into several categories, all sharing common problems, to varying degrees.
BAC~GROUND OF THE IN~ENTION
1. ~ield of the Invention.
The present invention relates to multi-layer circuit boards and, particularly, to the inspection of such boards during their fabrication.
Multi-layer circuit boards h~ve been defined as an interconnect package Whic}l con-tains more than two layers of circuitry. E~aving gro~l out of space and military applications in the early 60s, multi-layer boards are now used in many commercial applications. The various types of multi-layer boards fall into several categories, all sharing common problems, to varying degrees.
2. Description of the Prior Art.
One problem encountered in the fabrication of multi-layer boards is dimensional stability, or the lack of it, as the individual layers are processed. That is, each layer is designed in anticipation of precise registratiorl with the other layers that form the multi-layer board. Ho~ever, unless each of the layers undergoes identical dimensional alterations during its individual processing, precision that existed in the original artwork may be lost. This could result in a critical misalignlllent in the multi-layer board and result in its re~ection. In other instances, misregistration may be compensated for after lamination, and during drilling, by providing a compensating ofset within the drilling operation.
One problem encountered in the fabrication of multi-layer boards is dimensional stability, or the lack of it, as the individual layers are processed. That is, each layer is designed in anticipation of precise registratiorl with the other layers that form the multi-layer board. Ho~ever, unless each of the layers undergoes identical dimensional alterations during its individual processing, precision that existed in the original artwork may be lost. This could result in a critical misalignlllent in the multi-layer board and result in its re~ection. In other instances, misregistration may be compensated for after lamination, and during drilling, by providing a compensating ofset within the drilling operation.
3~ ~
SUMMARY OF THE INVENTION
The present invention ~rovides an inspection system for use in the fabrication of circuit boards of multiple, precisely registered layers. At least t~o targ~ts are formed on each layer, to be precisely registered during layer fabrication. Each target corresporlds in position to a target of at least one other layeL, with the targe-ts of each layer defining a pattern that is unique to that layer. During fabrication, the registration of each target of a layer may be viewed relative to a test target pattern via radioyraphy techniques. ~lus, the dimensional stability of each individual layer may be determined during and after their fabrication, while the relative registration of stacked layers may be determined through the relative registration of their target patterns to a test target pattern. In stacked relation, the test target pattern for the targets of one layer may be formed by the targets of at least two other layers.
As noted above, each layer may be inspected during and after its fabrication and be discarded if it is out of tolerance. After stacking, and before lamination, the relative registration of the stacked ~5 layers may be inspected, with a corresponding adjust~ent or replacement of misregistered layers, before lamination. After lamination, the relative registration of the layers may be determined and further fabricating costs saved, or compensating allowances made in the completion of the fabrication process.
3~
BRIEF D~SCRIPTION OF T~IE D}~WINGS
Figure 1 illustrates multiple layers that may form a multi-layer circuit board and the concept underlying the present invention.
Figure 2 illustra-tes the manner by which misregistration may be detected within multiple layers of a multi-layer circui-t board.
Figure 3 illustrates multiple target patterns that may be employed within the scope of the present invention and the manner by which they indicate misregistration.
Figure 4 illus-trates further alternative patterns that may be employed within the scope of the present invention.
DETAILED DESCRIPTION OE' THE PREFER~D E~IBODIMENTS
The present invention provides an inspection system for use in the fabrication of circuit boards of multiple, precisely registered layers. At least two targets are formed on each layer that will be ; 20 precisely registered relative to the targets of other layers, with each target corresponding in position to a target of at least one other layer and the targets of each layer defining a pattern that is unique to that layer. As will be explained more fully below, ~5 the uni~ue target pattern of each layer may be established by the positions of the targets of that layer, the configurations of the targets of that layer, or both. The targets are formed in such a way that they may be viewed by known radiography techniquesO Pxeferably, the targets are formed with the other printed circuit elements on the layer on which they are carried.
SUMMARY OF THE INVENTION
The present invention ~rovides an inspection system for use in the fabrication of circuit boards of multiple, precisely registered layers. At least t~o targ~ts are formed on each layer, to be precisely registered during layer fabrication. Each target corresporlds in position to a target of at least one other layeL, with the targe-ts of each layer defining a pattern that is unique to that layer. During fabrication, the registration of each target of a layer may be viewed relative to a test target pattern via radioyraphy techniques. ~lus, the dimensional stability of each individual layer may be determined during and after their fabrication, while the relative registration of stacked layers may be determined through the relative registration of their target patterns to a test target pattern. In stacked relation, the test target pattern for the targets of one layer may be formed by the targets of at least two other layers.
As noted above, each layer may be inspected during and after its fabrication and be discarded if it is out of tolerance. After stacking, and before lamination, the relative registration of the stacked ~5 layers may be inspected, with a corresponding adjust~ent or replacement of misregistered layers, before lamination. After lamination, the relative registration of the layers may be determined and further fabricating costs saved, or compensating allowances made in the completion of the fabrication process.
3~
BRIEF D~SCRIPTION OF T~IE D}~WINGS
Figure 1 illustrates multiple layers that may form a multi-layer circuit board and the concept underlying the present invention.
Figure 2 illustra-tes the manner by which misregistration may be detected within multiple layers of a multi-layer circui-t board.
Figure 3 illustrates multiple target patterns that may be employed within the scope of the present invention and the manner by which they indicate misregistration.
Figure 4 illus-trates further alternative patterns that may be employed within the scope of the present invention.
DETAILED DESCRIPTION OE' THE PREFER~D E~IBODIMENTS
The present invention provides an inspection system for use in the fabrication of circuit boards of multiple, precisely registered layers. At least two targets are formed on each layer that will be ; 20 precisely registered relative to the targets of other layers, with each target corresponding in position to a target of at least one other layer and the targets of each layer defining a pattern that is unique to that layer. As will be explained more fully below, ~5 the uni~ue target pattern of each layer may be established by the positions of the targets of that layer, the configurations of the targets of that layer, or both. The targets are formed in such a way that they may be viewed by known radiography techniquesO Pxeferably, the targets are formed with the other printed circuit elements on the layer on which they are carried.
4--For the purpose of this Specifica-tion and Claims, the "position" of a target on a layer is the position of that target relative to the other circuit elements on that layer such that registration of the targets in a multi-layer board indicates registration of the circuit elements carried by those layers.
In carrying our the inspection techniques of the present invention, any suitable radiographic system may be employed. One that may be employed, with minor modification to accommodate the size of the multi-layer circuit boards to which the present invention is directed, is that sold under the trademark MIKROX by Nicolet XRD Corporation, a subsidiary of Nicolet Instrument Corporation. A
related device is disclosed in U. S. Patent No. 4,159,436, issued January 26, 1979 to Raymond V.
Ely and entitled "Electron Beam Focussing for X-Ray Apparatus," which is commonly owned with the present invention. The advan-tage of these radiographic systems is that they provide an X-ray source that is essentially a "point source" and which allows a magnification of the part being inspected. The use of an X-ray-sensitive TV camera and monitor allows a real-time viewing of the inspected part. For the purpose of this Specification and Claims, however, the term "viewing" is intended to embrace both a real-time display on a TV monitor as well as a film exposure and its subsequent review.
Referring now to Figure 1, there are shown six layers, 10-15, which may be laminated to form a ~' :l`
18~ ~
~ulti-layer circuit board. For the sake of clarity, the circuit elements of the se~eral layers are not illustrated. ln the lower left corner oF each layer is a tar~et pattern, the targets being illustrated as S solid figures which must be formed in a manner so as to be detectible by the particular viewing technique employed. In the case of radiography techni~ues, the targets axe radiopaque and may be forllled during the ~ormation of the circuit elements on the several layers, and in a defined relationship therewith.
This defined relationship allows a registration determination be~ween the targets of the several layers to determine the registrat`ion of the circuit elen~ents of the several layers.
In Figure 1, the several targets are each o~
the same configuration (square), while occupying pre-determined positions. For example, layer 10 has targets in positions that may be identified as positions 1 and 2, while layer 11 has targets in positions 1, 2 and 3. Each of the layers 12-lS has a target i~l position 1, with layer 12 having additional targets in positions 3 and 4, layer 13 in positions 4 and 5, layer 14 in positions 5 and 6, and layer lS in positions 6 and 7.
With the layers 10 through 15 in stacking relation to each ot~er in what is believed to ~e proper registration, a radiographic viewing will establish whether proper registration is, in fact, present. This i5 illustrated in Figure 2, where a regular pattern of six taryets is illustrated, with misregistered targets being illustrated at positions 1, 4 and 5. With reference to Figure 1, it can be seen that the targets of the stacked layers forJn a test target pattern, with the itargets of layer 13 being out of registration with that test target pattern. Thus, layer 13 is misreyistered. Fiyure 2 also illustrates the way by which the degree o~
~nisregistration can be estimated. For example, if eac~l of the targets has a known dimension and one oE
the layers is misregistered so as to overlie the test target pattern formed by the other layers by half of the target dimension, the misreyistered layer is ~nisreqistered by an amount app~oxin~ately one-half the dimension of the targets. As seen in Figure 2, the direction of misregistration can also be determined.
Figure 3 illustrates alternative patterns that may be employed to identify different layers of a multi-layer circuit board. The patterns of Figure 3 are dependent not orlly on position of the targets but also their configuration. For example, the pattern indicated generally at 20 i5 a three-target pattern having a diamond in the firstposition, a square in the second position, and a diamond in the tenth position. Pattern 21 is formed with a circle in the second position and a dia~ond in the third position. The other patterns ~ay be as shown.
A nine-layer circuit ~oard employing the patterns illustrated in the upper poxtion of Figure 3 will produce a pattern illustrated at li~e 29 of E`igure 3 when all of the layers are in proper reyistraton. Line 30 illustrates what would be viewed if the layer of pattern 24 were out o~
registration upwardly and to the left and with the layer of pattern 26 misregistered downwardly and to the right. Line 31 illustrates ~ha-t would he viewe~
if the layer of pattern 28 were misregistered to the left as viewed in E'igure 3.
Figure 4 illustrates patterns 35-37, which may be employed on a three-la~er board with the patterns differing only by their configuration. ~ha~
i5, in terms of positions as discusse~ with reference to E'igures 2 and 3, each of patterns 35-37 is formed 0 with taryets in the first and second position, with the patterns differing from each other by a difference in the configuration of the targets that fsrm the~. Misregistration of patterns 35-37, when the layers that carry them are laid in stacking relation to each other, will give an indication of a misregistration of those layers.
In addition to giving an indication of misregistration between layers, the present invention may be employed to determine the dimensional stability, or lack thereof, of a single layer. In a multi-layer context, a test target pattern for each layer is formed by the targets of at least two other layers. Alternatively, a master template may be employed, the templa-te carrying a test target pattern corresponding to the pattern of the layer it is wished -to inspect. By properly overlaying the layer with the template, and viewing i-t as described above, the registration of the layer pattern relative to the test target pattern may be employed to establish the dimensional stability or instability of the layer being processed.
~ 3~ ~
O`bviously, many modifications and variations of the present invention are poqsible in light of the above teachings. For ex~mple, the present inventior may be employed for inspection during any stage of multi-layer circuit board fabrication, includlrlg:
During and after processing of each layer, the relative registration of stacked layers prior to lamination and the relative reyistration of the layers of a laminated circuit board.
The pre-lamination registration oE stacked layers may be inspected while those layers are within the laminating caul plates, ~as by providing inspection ports in those plates, with suitable closures for those ports.
Many target patterns may be employed within the scope of the present invention, which is not limited to the patterns disclosed herein. Indeed, the individual targets may be solid or outline figures, and may be positioned along one or more sides of each layer. ~hile it is anticipated that the target patterns will be contained within the border of each layer, where practical, they may be positioned within the "artwork" of the circuitry carried by each layer. It is therefore to be understood that, witllin the scope of the apended claims, the invention may be practiced otherwise than as specifically described.
In carrying our the inspection techniques of the present invention, any suitable radiographic system may be employed. One that may be employed, with minor modification to accommodate the size of the multi-layer circuit boards to which the present invention is directed, is that sold under the trademark MIKROX by Nicolet XRD Corporation, a subsidiary of Nicolet Instrument Corporation. A
related device is disclosed in U. S. Patent No. 4,159,436, issued January 26, 1979 to Raymond V.
Ely and entitled "Electron Beam Focussing for X-Ray Apparatus," which is commonly owned with the present invention. The advan-tage of these radiographic systems is that they provide an X-ray source that is essentially a "point source" and which allows a magnification of the part being inspected. The use of an X-ray-sensitive TV camera and monitor allows a real-time viewing of the inspected part. For the purpose of this Specification and Claims, however, the term "viewing" is intended to embrace both a real-time display on a TV monitor as well as a film exposure and its subsequent review.
Referring now to Figure 1, there are shown six layers, 10-15, which may be laminated to form a ~' :l`
18~ ~
~ulti-layer circuit board. For the sake of clarity, the circuit elements of the se~eral layers are not illustrated. ln the lower left corner oF each layer is a tar~et pattern, the targets being illustrated as S solid figures which must be formed in a manner so as to be detectible by the particular viewing technique employed. In the case of radiography techni~ues, the targets axe radiopaque and may be forllled during the ~ormation of the circuit elements on the several layers, and in a defined relationship therewith.
This defined relationship allows a registration determination be~ween the targets of the several layers to determine the registrat`ion of the circuit elen~ents of the several layers.
In Figure 1, the several targets are each o~
the same configuration (square), while occupying pre-determined positions. For example, layer 10 has targets in positions that may be identified as positions 1 and 2, while layer 11 has targets in positions 1, 2 and 3. Each of the layers 12-lS has a target i~l position 1, with layer 12 having additional targets in positions 3 and 4, layer 13 in positions 4 and 5, layer 14 in positions 5 and 6, and layer lS in positions 6 and 7.
With the layers 10 through 15 in stacking relation to each ot~er in what is believed to ~e proper registration, a radiographic viewing will establish whether proper registration is, in fact, present. This i5 illustrated in Figure 2, where a regular pattern of six taryets is illustrated, with misregistered targets being illustrated at positions 1, 4 and 5. With reference to Figure 1, it can be seen that the targets of the stacked layers forJn a test target pattern, with the itargets of layer 13 being out of registration with that test target pattern. Thus, layer 13 is misreyistered. Fiyure 2 also illustrates the way by which the degree o~
~nisregistration can be estimated. For example, if eac~l of the targets has a known dimension and one oE
the layers is misregistered so as to overlie the test target pattern formed by the other layers by half of the target dimension, the misreyistered layer is ~nisreqistered by an amount app~oxin~ately one-half the dimension of the targets. As seen in Figure 2, the direction of misregistration can also be determined.
Figure 3 illustrates alternative patterns that may be employed to identify different layers of a multi-layer circuit board. The patterns of Figure 3 are dependent not orlly on position of the targets but also their configuration. For example, the pattern indicated generally at 20 i5 a three-target pattern having a diamond in the firstposition, a square in the second position, and a diamond in the tenth position. Pattern 21 is formed with a circle in the second position and a dia~ond in the third position. The other patterns ~ay be as shown.
A nine-layer circuit ~oard employing the patterns illustrated in the upper poxtion of Figure 3 will produce a pattern illustrated at li~e 29 of E`igure 3 when all of the layers are in proper reyistraton. Line 30 illustrates what would be viewed if the layer of pattern 24 were out o~
registration upwardly and to the left and with the layer of pattern 26 misregistered downwardly and to the right. Line 31 illustrates ~ha-t would he viewe~
if the layer of pattern 28 were misregistered to the left as viewed in E'igure 3.
Figure 4 illustrates patterns 35-37, which may be employed on a three-la~er board with the patterns differing only by their configuration. ~ha~
i5, in terms of positions as discusse~ with reference to E'igures 2 and 3, each of patterns 35-37 is formed 0 with taryets in the first and second position, with the patterns differing from each other by a difference in the configuration of the targets that fsrm the~. Misregistration of patterns 35-37, when the layers that carry them are laid in stacking relation to each other, will give an indication of a misregistration of those layers.
In addition to giving an indication of misregistration between layers, the present invention may be employed to determine the dimensional stability, or lack thereof, of a single layer. In a multi-layer context, a test target pattern for each layer is formed by the targets of at least two other layers. Alternatively, a master template may be employed, the templa-te carrying a test target pattern corresponding to the pattern of the layer it is wished -to inspect. By properly overlaying the layer with the template, and viewing i-t as described above, the registration of the layer pattern relative to the test target pattern may be employed to establish the dimensional stability or instability of the layer being processed.
~ 3~ ~
O`bviously, many modifications and variations of the present invention are poqsible in light of the above teachings. For ex~mple, the present inventior may be employed for inspection during any stage of multi-layer circuit board fabrication, includlrlg:
During and after processing of each layer, the relative registration of stacked layers prior to lamination and the relative reyistration of the layers of a laminated circuit board.
The pre-lamination registration oE stacked layers may be inspected while those layers are within the laminating caul plates, ~as by providing inspection ports in those plates, with suitable closures for those ports.
Many target patterns may be employed within the scope of the present invention, which is not limited to the patterns disclosed herein. Indeed, the individual targets may be solid or outline figures, and may be positioned along one or more sides of each layer. ~hile it is anticipated that the target patterns will be contained within the border of each layer, where practical, they may be positioned within the "artwork" of the circuitry carried by each layer. It is therefore to be understood that, witllin the scope of the apended claims, the invention may be practiced otherwise than as specifically described.
Claims (8)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. An inspection method for use in the fabrication of circuit boards of multiple, precisely registered layers comprising the steps of:
forming at least two targets on each layer to be precisely registered, each target corresponding in position to a target of at least one other layer and the targets of each layer defining a pattern that is unique to that layer;
viewing the registration of each target of a layer relative to a test target pattern via radiography techniques.
forming at least two targets on each layer to be precisely registered, each target corresponding in position to a target of at least one other layer and the targets of each layer defining a pattern that is unique to that layer;
viewing the registration of each target of a layer relative to a test target pattern via radiography techniques.
2. The method of Claim 1 wherein the step of viewing comprises the steps of:
positioning a layer in stacking relation to a master template, the master template carrying a test target pattern including targets corresponding to the pattern of that layer in stacking relation to the master template; and viewing the registration of each target of that layer in stacking relation to the master template with the corresponding target of the test target pattern of the master template via radiography techniques.
positioning a layer in stacking relation to a master template, the master template carrying a test target pattern including targets corresponding to the pattern of that layer in stacking relation to the master template; and viewing the registration of each target of that layer in stacking relation to the master template with the corresponding target of the test target pattern of the master template via radiography techniques.
3. The method of Claim 1 wherein the step of viewing comprises the steps of:
positioning multiple layers, in their desired order, in stacking relation to each other, the test target pattern for the targets of one layer being formed by the targets of at least two other layers; and viewing the registration of each target of each stacked layer with the test target pattern formed by the targets of the other stacked layers via radiography techniques.
positioning multiple layers, in their desired order, in stacking relation to each other, the test target pattern for the targets of one layer being formed by the targets of at least two other layers; and viewing the registration of each target of each stacked layer with the test target pattern formed by the targets of the other stacked layers via radiography techniques.
4. The method of Claim 3 wherein the step of positioning comprises the step of assembling said multiple layers in caul plates for lamination thereof and the step of viewing comprises the step of viewing the registration of each target of each stacked layer with the test target pattern formed by the targets of the other stacked layers via radiography techniques after said assembling step.
5. The method of Claim 3 further comprising the step of laminating said multiple layers in their desired order, said viewing step being performed after said laminating step.
6. The method of Claim 1 wherein said forming step comprises the step of forming targets in positions that define a pattern that is unique to a layer.
7. The method of Claim 1 wherein said forming step comprises the step of forming targets in target configurations that define a pattern that is unique to a layer.
8. The method of Claim 1 wherein said forming step comprises the step of forming targets in positions and configurations that define a pattern that is unique to a layer.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/514,624 | 1983-07-18 | ||
| US06/514,624 US4536239A (en) | 1983-07-18 | 1983-07-18 | Multi-layer circuit board inspection system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1198831A true CA1198831A (en) | 1985-12-31 |
Family
ID=24048011
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000441260A Expired CA1198831A (en) | 1983-07-18 | 1983-11-16 | Nondestructive dimensional detection system |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US4536239A (en) |
| JP (1) | JPS6022333A (en) |
| CA (1) | CA1198831A (en) |
| DE (1) | DE3342564A1 (en) |
| FR (1) | FR2549677B1 (en) |
| GB (1) | GB2143379B (en) |
Families Citing this family (33)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4617160A (en) * | 1984-11-23 | 1986-10-14 | Irvine Sensors Corporation | Method for fabricating modules comprising uniformly stacked, aligned circuit-carrying layers |
| JPS61125712A (en) * | 1984-11-26 | 1986-06-13 | Matsushita Electric Works Ltd | Method for drilling hole of multi-layer printing wiring board |
| US4809308A (en) * | 1986-02-20 | 1989-02-28 | Irt Corporation | Method and apparatus for performing automated circuit board solder quality inspections |
| US4790694A (en) * | 1986-10-09 | 1988-12-13 | Loma Park Associates | Method and system for multi-layer printed circuit board pre-drill processing |
| DE3640616A1 (en) * | 1986-11-27 | 1988-06-09 | Standard Elektrik Lorenz Ag | ADJUSTMENT DEVICE |
| US4899440A (en) * | 1986-12-31 | 1990-02-13 | Systems Analysis And Integration | Method and apparatus for locating targets on a panel and performing work operations thereon |
| GB2212333A (en) * | 1987-11-11 | 1989-07-19 | Gen Electric Co Plc | Method of fabricating multi-layer circuits |
| US4938600A (en) * | 1989-02-09 | 1990-07-03 | Interactive Video Systems, Inc. | Method and apparatus for measuring registration between layers of a semiconductor wafer |
| US4940633A (en) * | 1989-05-26 | 1990-07-10 | Hermansen Ralph D | Method of bonding metals with a radio-opaque adhesive/sealant for void detection and product made |
| JPH03123010A (en) * | 1989-10-05 | 1991-05-24 | Murata Mfg Co Ltd | Manufacture of laminated electronic part |
| US5111406A (en) * | 1990-01-05 | 1992-05-05 | Nicolet Instrument Corporation | Method for determining drill target locations in a multilayer board panel |
| US5010449A (en) * | 1990-04-04 | 1991-04-23 | Eastman Kodak Company | Multi-layer printed circuit board and a method for assuring assembly in a selected order |
| US5206820A (en) * | 1990-08-31 | 1993-04-27 | At&T Bell Laboratories | Metrology system for analyzing panel misregistration in a panel manufacturing process and providing appropriate information for adjusting panel manufacturing processes |
| US5048178A (en) * | 1990-10-23 | 1991-09-17 | International Business Machines Corp. | Alignment--registration tool for fabricating multi-layer electronic packages |
| EP0698084B1 (en) * | 1993-05-14 | 1998-06-24 | Minnesota Mining And Manufacturing Company | Method for rapid quantification of microorganism growth |
| GB2307352A (en) * | 1995-11-16 | 1997-05-21 | Marconi Gec Ltd | Manufacture of multi-layer printed circuit boards |
| NO308630B1 (en) * | 1996-09-19 | 2000-10-02 | Norske Stats Oljeselskap | Pipeline inspection system |
| US5788802A (en) * | 1996-10-22 | 1998-08-04 | Preco Industries, Inc. | Vacuum drum feed and alignment apparatus for multiple layer laminator |
| WO1998033366A1 (en) | 1997-01-29 | 1998-07-30 | Kabushiki Kaisha Toshiba | Method and device for manufacturing multilayered wiring board and wiring board |
| GB2343399B (en) * | 1997-03-28 | 2001-04-18 | Preco Ind Inc | Web or sheet-fed apparatus having high-speed positioning mechanism |
| US7640836B1 (en) | 1997-03-28 | 2010-01-05 | Preco Industries, Inc. | Method for simultaneous x, y and θ registration of segment of continuous web with a processing station |
| JP4322402B2 (en) | 2000-06-22 | 2009-09-02 | 大日本印刷株式会社 | Printed wiring board and manufacturing method thereof |
| US7433509B1 (en) * | 2001-10-09 | 2008-10-07 | Nanometrics Incorporated | Method for automatic de-skewing of multiple layer wafer for improved pattern recognition |
| DE102004049439A1 (en) * | 2004-10-08 | 2006-04-13 | Feinfocus Gmbh | Drilling device for drilling contacting bores for connecting contacting surfaces of multilayer printed circuit boards |
| AT12737U1 (en) * | 2010-09-17 | 2012-10-15 | Austria Tech & System Tech | METHOD FOR PRODUCING A CONDUCTOR PLATE COMPOSED OF MULTIPLE PCB SURFACES AND PCB |
| EP2566306A4 (en) * | 2011-05-27 | 2013-07-03 | Huawei Tech Co Ltd | Multi-layer circuit board and manufacturing method thereof |
| CN102998309B (en) * | 2011-09-09 | 2015-07-15 | 深南电路有限公司 | Multilayer printed circuit board contraposition detection method |
| CN104582331B (en) * | 2014-12-31 | 2017-10-17 | 广州兴森快捷电路科技有限公司 | The internal layer off normal detection method of multilayer circuit board |
| CN107278020A (en) * | 2017-06-30 | 2017-10-20 | 上达电子（深圳）股份有限公司 | Circuit board and locating tool |
| CN108260305A (en) * | 2018-01-11 | 2018-07-06 | 郑州云海信息技术有限公司 | A kind of automatic lamination oxide method of pcb board |
| CN110691475B (en) * | 2018-07-06 | 2021-01-08 | 深南电路股份有限公司 | PCB (printed circuit board) layer deviation detection feedback system and detection device thereof |
| CN108925066B (en) * | 2018-08-28 | 2020-01-31 | 深圳市景旺电子股份有限公司 | multilayer board interlayer offset detection method and detection system |
| CN112654141B (en) * | 2020-12-25 | 2022-10-11 | 天津普林电路股份有限公司 | Method for checking alignment of mechanical hole and inner layer pattern |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1046853A (en) * | 1962-05-17 | 1966-10-26 | Atomic Energy Authority Uk | Improvements in or relating to the identification of circuit cards |
| GB1597841A (en) * | 1977-01-19 | 1981-09-09 | Nicolet Xrd Corp | Electron beam focussing |
| US4193687A (en) * | 1978-06-05 | 1980-03-18 | Rockwell International Corporation | High resolution alignment technique and apparatus |
| US4327292A (en) * | 1980-05-13 | 1982-04-27 | Hughes Aircraft Company | Alignment process using serial detection of repetitively patterned alignment marks |
| DE3031103C2 (en) * | 1980-08-16 | 1982-08-19 | Bodenseewerk Gerätetechnik GmbH, 7770 Überlingen | Procedure for checking the positional misalignment in multi-layer printed circuit boards |
| DE3045433A1 (en) * | 1980-12-02 | 1982-07-01 | Siemens AG, 1000 Berlin und 8000 München | MULTI-LAYER CIRCUIT BOARD AND METHOD FOR DETERMINING THE CURRENT POSITION OF INTERNAL CONNECTION AREAS |
| US4343878A (en) * | 1981-01-02 | 1982-08-10 | Amdahl Corporation | System for providing photomask alignment keys in semiconductor integrated circuit processing |
-
1983
- 1983-07-18 US US06/514,624 patent/US4536239A/en not_active Expired - Lifetime
- 1983-11-16 CA CA000441260A patent/CA1198831A/en not_active Expired
- 1983-11-25 DE DE19833342564 patent/DE3342564A1/en active Granted
- 1983-12-07 FR FR8319596A patent/FR2549677B1/en not_active Expired
- 1983-12-23 JP JP58243644A patent/JPS6022333A/en active Pending
-
1984
- 1984-01-27 GB GB08402265A patent/GB2143379B/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| GB2143379A (en) | 1985-02-06 |
| FR2549677B1 (en) | 1988-11-25 |
| DE3342564A1 (en) | 1985-02-07 |
| US4536239A (en) | 1985-08-20 |
| DE3342564C2 (en) | 1988-12-29 |
| FR2549677A1 (en) | 1985-01-25 |
| GB2143379B (en) | 1986-04-09 |
| GB8402265D0 (en) | 1984-02-29 |
| JPS6022333A (en) | 1985-02-04 |
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