CA1200616A - Method for producing integrated mos field effect transistors with an additional interconnect of metal silicides - Google Patents
Method for producing integrated mos field effect transistors with an additional interconnect of metal silicidesInfo
- Publication number
- CA1200616A CA1200616A CA000428109A CA428109A CA1200616A CA 1200616 A CA1200616 A CA 1200616A CA 000428109 A CA000428109 A CA 000428109A CA 428109 A CA428109 A CA 428109A CA 1200616 A CA1200616 A CA 1200616A
- Authority
- CA
- Canada
- Prior art keywords
- layer
- regions
- silicide
- utilized
- phosphorus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
ABSTRACT
A method of producing integrated MOS field effect tran-sistors is provided wherein an additional interconnect consisting of a metal silicide is utilized. All contacts to the active MOS
regions and polysilicon regions for the metal silicide level and for the metal interconnect - silicide mushroom contacts - as well, are opened before the deposition of the metal silicide layer. In order to achieve an overlapping contact, a layer comprised essenti-ally of a silica-phosphorus glass layer is utilized as an insula-tion layer between the polysilicon level and the silicide level.
This layer is of such a nature as to effect a high selectivity of an etching agent by itself, relative to the thermally generated oxide regions positioned on the substrate, relative to the poly-silicon regions and relative to the substrate, when producing the contact holes. In preferred embodiments, a HF/NH4F etching mix-ture is utilized as the etching agent. The method is useful in production of complementary MOS field effect transistor circuits in VLSI technology.
A method of producing integrated MOS field effect tran-sistors is provided wherein an additional interconnect consisting of a metal silicide is utilized. All contacts to the active MOS
regions and polysilicon regions for the metal silicide level and for the metal interconnect - silicide mushroom contacts - as well, are opened before the deposition of the metal silicide layer. In order to achieve an overlapping contact, a layer comprised essenti-ally of a silica-phosphorus glass layer is utilized as an insula-tion layer between the polysilicon level and the silicide level.
This layer is of such a nature as to effect a high selectivity of an etching agent by itself, relative to the thermally generated oxide regions positioned on the substrate, relative to the poly-silicon regions and relative to the substrate, when producing the contact holes. In preferred embodiments, a HF/NH4F etching mix-ture is utilized as the etching agent. The method is useful in production of complementary MOS field effect transistor circuits in VLSI technology.
Description
~ACKGROUND OF TIIE INV~NTION
Field of the Invention The invention relates to integrated MOS field effect transistors and somewhat more particularly to an improved method of producing complementary MOS
field effect transistor circuits (CMOS-FT's) having an additional interconnect of metal silicides.
Prior Art A known technique for producing integrated MOS field effect transistor circuits includes providing a layer structure composed of hmp (high melting point) metal silicides, such as silicides of Mo, W, Ta or Ti, -for use as an additional interconnect level. Such metal silicide layer structures are applied after :Eabrication of a polysilicon level, generation of active MOS regions, application of an insulating oxide and opening of contact holes to the active MOS and polysilicon regions for the metal silicide interconnect. In this manner, direct contacts to the metal silicide level as well as indirect contacts to the metal interconnect or conductor path are attained in the form of silicide mush-room contacts. A silicon oxide layer containing phosphorus is utilized as the intermediate oxide between the metal silicide interconnect and the metal inter-connect. Structuring of the metal silicide layer occurs in such a manner that p -regions of the circuit otherwise lying uncovered, remain covered by the metal silicide layer when the phosphorus glass (phosphorus-containing silicon oxide) functioning as the intermediate oxide is allowed to flow-spread (at a temperature of about l,000C for rounding the contact hole regions).
With decreasing structural size in integrated circuits, packing density of circuit components is determined with an increasing degree by the wiring grid and the type of possible contacts.
l6 An increase of componen-t packing density in integrated circuits can be attained by utilizing a second metal wiring level or silicide wiring level, for example, as described in Applicant's Wes-t German OLS 3,027,954, published February 25th, 1982. The use of a silicide level is particularly suitable for saving space within individual gates because of its smaller grid in comparison to a second metal wiring level and because of its grea-ter contact-ing possibilities.
A further increase of component packing density is produced by overlapping contact (see V.L. Rideoutl IBM Technical Disclosure Bulletin, Vol. 17, No. 9, 1975, page 2802~. Overlapping contacts on n -silicon are problematic because of the danger of substrate shorts at edges of the field oxide regions generated on the substrate by thermal oxidation. Moreover, additional wiring levels generally require two additional photolithographic processes and thus increase the defect density.
A method u-tilizing silicide mushroom contacts is described and claimed in co-pending Canadian Patent Application 409,650 and assigned to the instant assignee. The main goal of tha-t method is to achieve contact holes which exhibi-t very little underetching. As a result of using a phosphorus glass layer as an intermediate oxide, the contac-t holes can be rounded during glass flow becuase of the silicide intermediate layer (mushroom) in the contacts, without the p -regions of -the circuit being uncovered.
J~ L6 SUMMARY OF TH:E INVENTION
The invention provides an improved method for manufac-ture of integrated MOS field effect transistor circuits which combines the advantages of utiliziny a silicide wiriny ]evel and silicide mushroom contacts with the advantayes of utiliziny overlapping contac-ts so as to ~Eurther increase the packing density of an integrated circui-t. The invention also enables the yeneration of the over-- 2a -120(~6~6 lapping con-tacts with as little added technological outlay as pos-sible upon utilization of -the silicide wiring level in the manu-facturing process for MOS circui-ts.
In accordance with the principles of the invention, the earlier described technique is improved by, depositing a layer essentially comprised of a silica phosphorus glass layer as an insulation layer between the polysilicon level and the silicide level, after a surface-wide removal of an oxide layer generated on the doped regions of a substrate~ This silica-phosphorus glass layer is of such a nature that a high selectivity of an etching agent, relative to thermally generated oxide regions located on the substrate and separating the active regions of the circuit, relative to the polysilicon regions and relative to the substrate, is effected by itself when etching the overlapping contact hole to the active MOS and polysilicon regions.
In certain aspects of this invention, it is possible to use a SiO2 layer generated at a pressure of less than about l00 Pa and at a temperature in the range of abou-t 300 through 450C (a so-called low pressure/low temperature oxide -LPT-oxide) as the basis of the insulating layer between the polysilicon level and the silicide level, and is etched with a hydrofluoric acid (HF)/
ammonium fluoride (NH4F) etching mixture.
In this embodiment of the invention, the low pressure/
low temperature SiO2 (LPT-oxide) layer contains an amount of phos-phorus which is less than about 8% and the HF/N~14F etching mixture is adjusted so as to contain the two constituents thereof at a mix-ing ratio of about 7:l.
~2~3~
In practicing the principles of the inven-tion, contact holes overlapping the field oxide region edges (LOCOS) or, respec-tively, polysilicon edges, are etched through this LPT-oxide insulation layer. A prerequisite for reliably avoiding substrate shorts is, therefore, a combination of an insulation layer and an etching agent wi-th as high as possible selectivity of such etching agent, relative to silicon, as is the case with a phosphorus-containing LPT-SiO2 layer and a HF/NH~F 7:1 SiO2 etching mixture.
BRIEF DESCRIPTION OF THE DRAWINGS
Figures 1 3 are partial, cross-sectional, elevated schematic views illustrating various stages of an exemplary struc-ture undergoing fabrication in accordance with the principles of the invention; and Figure 4 is a schematic layout of an exemplary N-MOS
inverter with overlapping contacts and silicides produced in accor-dance with the principles of the invention.
DESCRIPTION OF PREFERRED E~BODIMENTS
In the drawings, identical reference numerals are uti-lized to designate identical structures, except where otherwise noted.
Figure 1 As an exemplary embodiment, the production of a n-channel MOS field effect transistor will be explained hereinbelow.
A monocrystalline, p-doped (100)-oriented silicon sub-strate 1 having a specific resistance in the range of about 2 through 50 Ohm/cm is subjected to a field implantation and the field oxide regions 2 (doX--700 nm) and active regions (wi-thout :12(~6~
oxide) are defined therein with the assistance of the known LOCOS
technique. A gate oxide 3 is produced as a 40 nm thick layer by oxidation in the active regions. A 500 nm thick polysilicon layer 4 is thereafter deposited surface-wide by a CVD process (chemical vapor deposi-tion), is n -doped and structured as shownn An arsenic ion implantation is then executed to produce n -doped regions 5.
- 4a -The first essential step according to the principles o-f the invention now occurs, whereby the oxide present on the substrate in a thickness of 40 nm is removed surface-wlde (where not protected by the polysi.licon layer 4). The resultant structure is i].lustrated in Figure 1.
Figure 2 The overall arrangement ls now yrovided with a LPT-SiO2 layer 6 con-taining about 4% phosphorus and having a thickness of about 50 mrl. The layer 6 is produced from a gaseous phase at a temperature of about 430C and a pres-sure of about 27 Pa (a so-called LPT-deposition). Next, this insulation oxide layer 6 is opened (etched) for both~ the contacts for the additional level 11, preferably composed of tantalum silicide, for the tantalum si].icide polysilicon level 7, for the tantalum silicide n -regions 10, as well as for the mushroom contacts for the interconnect 12 (best seen in Figure 3), preferably composed of aluminum/silicon, to the polysilicon and the n -regions.
A secondessential step according to the principles of the invention is executed in this contact hole etching by application of a selective etching mixture consisting, for example, of HF (49% purity) and NH4F (40% purity) in a mixing ratio of about 7:1. With this etching mix~ure, a ratio of etching rates from 3 through 7 arises, relative to the thermal oxide layer 2, i.e. with a 4%
phosphorus content, the phosphorus-containing SiO2 layer is etched faster by a factor of 7 than is the thermal oxide (field oxide) layer 2. After conclusion of the first contact hole etching (7, 10), a second interconnect level 11, pre-:Eerably composed of tantalum silicide, is deposited in a layer thickness of about 200 through 500 nm and is structured such that an oversize tantalum silicide spot (mushroom) remains over all contact (7, 10). The resultant struc-ture is illustrated in Figure 2.
5 _ ~(36~6 The region identified with bracket 9 encompasses the "buried contact" equivalent, a-t-tained by following the principles of the invention. As can be seen from Figure 2, noticeable space is saved as a result of the inventive overlapping contacts.
Figure 3 An intermediate oxide composed of a phosphorus-silicate glass is now deposited from a gaseous phase (with LPT-deposition parameter), having a phosphorus content of about 4% in a layer -thickness ranging from about 500 throuyh 1,500 nm. Then, a second contact hole etching occurs for the contacts 14 of the aluminum/silicon interconnect level 12 to the tantalum silicide level 11. This is followed by a flow-spread (via application of heat at a temperature of about l,000C) of the phosphorus glass layer in order to round-off the contact hole regions, whereby the p+-regions of the p-channel -transis-tor of a CMOS circuit are now masked or covered by portions of the tantalurrl silicide layer 11 positioned thereabove. This structuring is not illustrated in detail, however, further details can be derived from West German OLS 30 27 954 (see page 2). For sake of greater clarity, the overall oxide layer, consisting of gate oxide 3, insulation oxide 6 and the intermediate oxide is referenced in Figure 3 with reference numeral 13. Finally, the interconnection level 12, composed of aluminum/silicon, is generated in a known manner.
With the foregoing process sequence, a polysilicon/
diffusion contact (see Figure 2) which saves space in comparison ~o~
to an otherwise standa.rd "buried contact", occurs, in addition to the general advantage of having a second ~Jiring or inter~
connec-t level.
Contacts for the polysilicon level, not only -to the n -silicon, but also to the p -silicon as wel.l are possible as a result of the silicide connec-~2~ 6 tion, This provides a new avenue in CMOS design. Slnce the "buried contact"
mask can now be eliminated, the additional wiring or interconnect level, at most, requires an additional photoli*hographic step. No addition~l photolithogra-phic step is required with CMOS processes having a "buried contact" and a "switch capacitor" because the silicide connection can be simultaneously util-ized as the electrode of the "switch capacitor". Thus, an increase of packing density and the advantages of a second, independent wiring level is attained with relatively little added technological outlay.
Figure 4 ]0 The layout of an N-MOS inverter as a use example is illustrated on a scale of lOOO:l. The same reference numerals as in Figures 1 - 3 are utili~ed to designate identical structures.
The advantages of this layout, produced by following the principles of the invention, lie in the two space-saving, overlapping silicide mushroom con-tacts at the left and right side ~10, 11 and 12, 14), as well as in the new polysilicon/diffusion contacts (4, 9 and 11, 5) which can be placed between the two gates in a space-saving manner without the self-adjusting character of a depletion transistor (left-hand region 4) being lost.
As is apparent from the foregoing specification, the present invention is susceptible of being embodied with various alterations and modifications which may differ particularly from those that have been described in the pre-cedings specification and description. For this reason, it is to be fully understood that all of the foregoing is intended to be merely illustrative and is not to be construed or interpreted as being restrictive or otherwise limitingof the present invention, excepting as it is set forth and defined in the hereto-appended claims.
Field of the Invention The invention relates to integrated MOS field effect transistors and somewhat more particularly to an improved method of producing complementary MOS
field effect transistor circuits (CMOS-FT's) having an additional interconnect of metal silicides.
Prior Art A known technique for producing integrated MOS field effect transistor circuits includes providing a layer structure composed of hmp (high melting point) metal silicides, such as silicides of Mo, W, Ta or Ti, -for use as an additional interconnect level. Such metal silicide layer structures are applied after :Eabrication of a polysilicon level, generation of active MOS regions, application of an insulating oxide and opening of contact holes to the active MOS and polysilicon regions for the metal silicide interconnect. In this manner, direct contacts to the metal silicide level as well as indirect contacts to the metal interconnect or conductor path are attained in the form of silicide mush-room contacts. A silicon oxide layer containing phosphorus is utilized as the intermediate oxide between the metal silicide interconnect and the metal inter-connect. Structuring of the metal silicide layer occurs in such a manner that p -regions of the circuit otherwise lying uncovered, remain covered by the metal silicide layer when the phosphorus glass (phosphorus-containing silicon oxide) functioning as the intermediate oxide is allowed to flow-spread (at a temperature of about l,000C for rounding the contact hole regions).
With decreasing structural size in integrated circuits, packing density of circuit components is determined with an increasing degree by the wiring grid and the type of possible contacts.
l6 An increase of componen-t packing density in integrated circuits can be attained by utilizing a second metal wiring level or silicide wiring level, for example, as described in Applicant's Wes-t German OLS 3,027,954, published February 25th, 1982. The use of a silicide level is particularly suitable for saving space within individual gates because of its smaller grid in comparison to a second metal wiring level and because of its grea-ter contact-ing possibilities.
A further increase of component packing density is produced by overlapping contact (see V.L. Rideoutl IBM Technical Disclosure Bulletin, Vol. 17, No. 9, 1975, page 2802~. Overlapping contacts on n -silicon are problematic because of the danger of substrate shorts at edges of the field oxide regions generated on the substrate by thermal oxidation. Moreover, additional wiring levels generally require two additional photolithographic processes and thus increase the defect density.
A method u-tilizing silicide mushroom contacts is described and claimed in co-pending Canadian Patent Application 409,650 and assigned to the instant assignee. The main goal of tha-t method is to achieve contact holes which exhibi-t very little underetching. As a result of using a phosphorus glass layer as an intermediate oxide, the contac-t holes can be rounded during glass flow becuase of the silicide intermediate layer (mushroom) in the contacts, without the p -regions of -the circuit being uncovered.
J~ L6 SUMMARY OF TH:E INVENTION
The invention provides an improved method for manufac-ture of integrated MOS field effect transistor circuits which combines the advantages of utiliziny a silicide wiriny ]evel and silicide mushroom contacts with the advantayes of utiliziny overlapping contac-ts so as to ~Eurther increase the packing density of an integrated circui-t. The invention also enables the yeneration of the over-- 2a -120(~6~6 lapping con-tacts with as little added technological outlay as pos-sible upon utilization of -the silicide wiring level in the manu-facturing process for MOS circui-ts.
In accordance with the principles of the invention, the earlier described technique is improved by, depositing a layer essentially comprised of a silica phosphorus glass layer as an insulation layer between the polysilicon level and the silicide level, after a surface-wide removal of an oxide layer generated on the doped regions of a substrate~ This silica-phosphorus glass layer is of such a nature that a high selectivity of an etching agent, relative to thermally generated oxide regions located on the substrate and separating the active regions of the circuit, relative to the polysilicon regions and relative to the substrate, is effected by itself when etching the overlapping contact hole to the active MOS and polysilicon regions.
In certain aspects of this invention, it is possible to use a SiO2 layer generated at a pressure of less than about l00 Pa and at a temperature in the range of abou-t 300 through 450C (a so-called low pressure/low temperature oxide -LPT-oxide) as the basis of the insulating layer between the polysilicon level and the silicide level, and is etched with a hydrofluoric acid (HF)/
ammonium fluoride (NH4F) etching mixture.
In this embodiment of the invention, the low pressure/
low temperature SiO2 (LPT-oxide) layer contains an amount of phos-phorus which is less than about 8% and the HF/N~14F etching mixture is adjusted so as to contain the two constituents thereof at a mix-ing ratio of about 7:l.
~2~3~
In practicing the principles of the inven-tion, contact holes overlapping the field oxide region edges (LOCOS) or, respec-tively, polysilicon edges, are etched through this LPT-oxide insulation layer. A prerequisite for reliably avoiding substrate shorts is, therefore, a combination of an insulation layer and an etching agent wi-th as high as possible selectivity of such etching agent, relative to silicon, as is the case with a phosphorus-containing LPT-SiO2 layer and a HF/NH~F 7:1 SiO2 etching mixture.
BRIEF DESCRIPTION OF THE DRAWINGS
Figures 1 3 are partial, cross-sectional, elevated schematic views illustrating various stages of an exemplary struc-ture undergoing fabrication in accordance with the principles of the invention; and Figure 4 is a schematic layout of an exemplary N-MOS
inverter with overlapping contacts and silicides produced in accor-dance with the principles of the invention.
DESCRIPTION OF PREFERRED E~BODIMENTS
In the drawings, identical reference numerals are uti-lized to designate identical structures, except where otherwise noted.
Figure 1 As an exemplary embodiment, the production of a n-channel MOS field effect transistor will be explained hereinbelow.
A monocrystalline, p-doped (100)-oriented silicon sub-strate 1 having a specific resistance in the range of about 2 through 50 Ohm/cm is subjected to a field implantation and the field oxide regions 2 (doX--700 nm) and active regions (wi-thout :12(~6~
oxide) are defined therein with the assistance of the known LOCOS
technique. A gate oxide 3 is produced as a 40 nm thick layer by oxidation in the active regions. A 500 nm thick polysilicon layer 4 is thereafter deposited surface-wide by a CVD process (chemical vapor deposi-tion), is n -doped and structured as shownn An arsenic ion implantation is then executed to produce n -doped regions 5.
- 4a -The first essential step according to the principles o-f the invention now occurs, whereby the oxide present on the substrate in a thickness of 40 nm is removed surface-wlde (where not protected by the polysi.licon layer 4). The resultant structure is i].lustrated in Figure 1.
Figure 2 The overall arrangement ls now yrovided with a LPT-SiO2 layer 6 con-taining about 4% phosphorus and having a thickness of about 50 mrl. The layer 6 is produced from a gaseous phase at a temperature of about 430C and a pres-sure of about 27 Pa (a so-called LPT-deposition). Next, this insulation oxide layer 6 is opened (etched) for both~ the contacts for the additional level 11, preferably composed of tantalum silicide, for the tantalum si].icide polysilicon level 7, for the tantalum silicide n -regions 10, as well as for the mushroom contacts for the interconnect 12 (best seen in Figure 3), preferably composed of aluminum/silicon, to the polysilicon and the n -regions.
A secondessential step according to the principles of the invention is executed in this contact hole etching by application of a selective etching mixture consisting, for example, of HF (49% purity) and NH4F (40% purity) in a mixing ratio of about 7:1. With this etching mix~ure, a ratio of etching rates from 3 through 7 arises, relative to the thermal oxide layer 2, i.e. with a 4%
phosphorus content, the phosphorus-containing SiO2 layer is etched faster by a factor of 7 than is the thermal oxide (field oxide) layer 2. After conclusion of the first contact hole etching (7, 10), a second interconnect level 11, pre-:Eerably composed of tantalum silicide, is deposited in a layer thickness of about 200 through 500 nm and is structured such that an oversize tantalum silicide spot (mushroom) remains over all contact (7, 10). The resultant struc-ture is illustrated in Figure 2.
5 _ ~(36~6 The region identified with bracket 9 encompasses the "buried contact" equivalent, a-t-tained by following the principles of the invention. As can be seen from Figure 2, noticeable space is saved as a result of the inventive overlapping contacts.
Figure 3 An intermediate oxide composed of a phosphorus-silicate glass is now deposited from a gaseous phase (with LPT-deposition parameter), having a phosphorus content of about 4% in a layer -thickness ranging from about 500 throuyh 1,500 nm. Then, a second contact hole etching occurs for the contacts 14 of the aluminum/silicon interconnect level 12 to the tantalum silicide level 11. This is followed by a flow-spread (via application of heat at a temperature of about l,000C) of the phosphorus glass layer in order to round-off the contact hole regions, whereby the p+-regions of the p-channel -transis-tor of a CMOS circuit are now masked or covered by portions of the tantalurrl silicide layer 11 positioned thereabove. This structuring is not illustrated in detail, however, further details can be derived from West German OLS 30 27 954 (see page 2). For sake of greater clarity, the overall oxide layer, consisting of gate oxide 3, insulation oxide 6 and the intermediate oxide is referenced in Figure 3 with reference numeral 13. Finally, the interconnection level 12, composed of aluminum/silicon, is generated in a known manner.
With the foregoing process sequence, a polysilicon/
diffusion contact (see Figure 2) which saves space in comparison ~o~
to an otherwise standa.rd "buried contact", occurs, in addition to the general advantage of having a second ~Jiring or inter~
connec-t level.
Contacts for the polysilicon level, not only -to the n -silicon, but also to the p -silicon as wel.l are possible as a result of the silicide connec-~2~ 6 tion, This provides a new avenue in CMOS design. Slnce the "buried contact"
mask can now be eliminated, the additional wiring or interconnect level, at most, requires an additional photoli*hographic step. No addition~l photolithogra-phic step is required with CMOS processes having a "buried contact" and a "switch capacitor" because the silicide connection can be simultaneously util-ized as the electrode of the "switch capacitor". Thus, an increase of packing density and the advantages of a second, independent wiring level is attained with relatively little added technological outlay.
Figure 4 ]0 The layout of an N-MOS inverter as a use example is illustrated on a scale of lOOO:l. The same reference numerals as in Figures 1 - 3 are utili~ed to designate identical structures.
The advantages of this layout, produced by following the principles of the invention, lie in the two space-saving, overlapping silicide mushroom con-tacts at the left and right side ~10, 11 and 12, 14), as well as in the new polysilicon/diffusion contacts (4, 9 and 11, 5) which can be placed between the two gates in a space-saving manner without the self-adjusting character of a depletion transistor (left-hand region 4) being lost.
As is apparent from the foregoing specification, the present invention is susceptible of being embodied with various alterations and modifications which may differ particularly from those that have been described in the pre-cedings specification and description. For this reason, it is to be fully understood that all of the foregoing is intended to be merely illustrative and is not to be construed or interpreted as being restrictive or otherwise limitingof the present invention, excepting as it is set forth and defined in the hereto-appended claims.
Claims (6)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A method for the production of an integrated MOS
field effect transistor which comprises:
providing a substrate having doped ion implantation generated regions in preselected areas thereon together with a doped, structured polysilicon gate electrode, spaced active regions and field oxide regions separating said active regions and covered with an oxide layer, removing the oxide layer over said doped, ion implantation generated regions and over said field oxide regions separating said active regions, depositing a silica-phosphorus glass layer over the result-ing surface, forming contact holes in said silica-phosphorus glass layer to provide space for an additional interconnect level by selective etching with an etchant which exhibits a high etching selectivity to silica-phosphorus as compared with thermal silicon dioxide and produce contact areas which overlap the edges of said field oxide regions, depositing and structuring a high melting point metal silicide layer to produce a mushroom contact over all said contact holes and provide said additional interconnect level, depositing a second silica-phosphorus glass layer over the resulting surface to form an insulation layer, forming contact holes in said insulation layer down to said silicide layer, and applying a metal conductor over the exposed silicide layer to form an outer interconnect level.
field effect transistor which comprises:
providing a substrate having doped ion implantation generated regions in preselected areas thereon together with a doped, structured polysilicon gate electrode, spaced active regions and field oxide regions separating said active regions and covered with an oxide layer, removing the oxide layer over said doped, ion implantation generated regions and over said field oxide regions separating said active regions, depositing a silica-phosphorus glass layer over the result-ing surface, forming contact holes in said silica-phosphorus glass layer to provide space for an additional interconnect level by selective etching with an etchant which exhibits a high etching selectivity to silica-phosphorus as compared with thermal silicon dioxide and produce contact areas which overlap the edges of said field oxide regions, depositing and structuring a high melting point metal silicide layer to produce a mushroom contact over all said contact holes and provide said additional interconnect level, depositing a second silica-phosphorus glass layer over the resulting surface to form an insulation layer, forming contact holes in said insulation layer down to said silicide layer, and applying a metal conductor over the exposed silicide layer to form an outer interconnect level.
2. In a method as defined in claim 1 wherein an SiO2 layer generated at a pressure of less than about 100 Pa and at a temperature in the range of about 300 through 500°C is utilized as said insulation layer and a hydrofluoric acid/ammonium fluoride etching mixture is utilized to etch said SiO2 layer.
3. In a method as defined in claim 2 wherein said SiO2 layer contains phosphorus in an amount up to 8% and said HF/NH4F etching mixture contains the constituents thereof in a mixing ratio of about 7:1.
4. In a method as defined in claim 3 wherein said SiO2 layer contains about 4% phosphorus therein.
5. In a method as defined in claim 1 wherein said insulation layer is deposited in a thickness in the range of about 50 through 500 nm.
6. In a method as defined in claim 1 wherein a tantalum silicide layer having a thickness in the range of about 200 to 500 nm is utilized as the metal silicide layer.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DEP3218309.7 | 1982-05-14 | ||
| DE19823218309 DE3218309A1 (en) | 1982-05-14 | 1982-05-14 | METHOD FOR PRODUCING INTEGRATED MOS FIELD EFFECT TRANSISTORS WITH AN ADDITIONAL CIRCUIT LEVEL, MADE OF METAL SILICIDES |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1200616A true CA1200616A (en) | 1986-02-11 |
Family
ID=6163676
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000428109A Expired CA1200616A (en) | 1982-05-14 | 1983-05-13 | Method for producing integrated mos field effect transistors with an additional interconnect of metal silicides |
Country Status (5)
| Country | Link |
|---|---|
| EP (1) | EP0094559B1 (en) |
| JP (1) | JPS58209145A (en) |
| AT (1) | ATE32805T1 (en) |
| CA (1) | CA1200616A (en) |
| DE (2) | DE3218309A1 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6037743A (en) * | 1983-08-11 | 1985-02-27 | Nec Corp | Semiconductor device |
| JPS62126632A (en) * | 1985-11-27 | 1987-06-08 | Toshiba Corp | Manufacture of semiconductor device |
| GB2186423A (en) * | 1985-11-29 | 1987-08-12 | Plessey Co Plc | Integrated circuit transistor and method for producing same |
| GB9219268D0 (en) * | 1992-09-11 | 1992-10-28 | Inmos Ltd | Semiconductor device incorporating a contact and manufacture thereof |
Family Cites Families (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3844831A (en) * | 1972-10-27 | 1974-10-29 | Ibm | Forming a compact multilevel interconnection metallurgy system for semi-conductor devices |
| JPS5311356B2 (en) * | 1973-06-30 | 1978-04-20 | ||
| JPS5034488A (en) * | 1973-07-31 | 1975-04-02 | ||
| DE2445594A1 (en) * | 1974-09-24 | 1976-04-08 | Siemens Ag | METHOD OF MANUFACTURING INTEGRATED CIRCUITS |
| US4125427A (en) * | 1976-08-27 | 1978-11-14 | Ncr Corporation | Method of processing a semiconductor |
| US4052253A (en) * | 1976-09-27 | 1977-10-04 | Motorola, Inc. | Semiconductor-oxide etchant |
| JPS583380B2 (en) * | 1977-03-04 | 1983-01-21 | 株式会社日立製作所 | Semiconductor device and its manufacturing method |
| JPS6047749B2 (en) * | 1977-03-15 | 1985-10-23 | 富士通株式会社 | Manufacturing method of semiconductor device |
| US4102733A (en) * | 1977-04-29 | 1978-07-25 | International Business Machines Corporation | Two and three mask process for IGFET fabrication |
| JPS5488779A (en) * | 1977-12-26 | 1979-07-14 | Cho Lsi Gijutsu Kenkyu Kumiai | Method of fabricating complementary mos transistor |
| JPS5568675A (en) * | 1978-11-17 | 1980-05-23 | Toshiba Corp | Fabrication of complementary mos transistor |
| DE2949198A1 (en) * | 1979-12-06 | 1981-06-11 | Siemens AG, 1000 Berlin und 8000 München | Integrated MOS circuit prodn. by silicon gate technology - with self-aligning overlapping source-drain contact using silicon nitride masking |
| DE3027954A1 (en) * | 1980-07-23 | 1982-02-25 | Siemens AG, 1000 Berlin und 8000 München | MOS integrated circuit with supplementary wiring plane - of silicide of high melting metal completely independent of metal wiring plane |
| JPS5780739A (en) * | 1980-11-07 | 1982-05-20 | Hitachi Ltd | Semiconductor integrated circuit device and manufacture thereof |
| DE3132809A1 (en) * | 1981-08-19 | 1983-03-10 | Siemens AG, 1000 Berlin und 8000 München | METHOD FOR PRODUCING INTEGRATED MOS FIELD EFFECT TRANSISTORS, ESPECIALLY COMPLEMENTARY MOS FIELD EFFECT TRANSISTOR CIRCUITS WITH AN ADDITIONAL CIRCUIT LEVEL CONSTRUCTED FROM METAL SILICIDES |
-
1982
- 1982-05-14 DE DE19823218309 patent/DE3218309A1/en not_active Withdrawn
-
1983
- 1983-05-04 DE DE8383104402T patent/DE3375860D1/en not_active Expired
- 1983-05-04 AT AT83104402T patent/ATE32805T1/en not_active IP Right Cessation
- 1983-05-04 EP EP83104402A patent/EP0094559B1/en not_active Expired
- 1983-05-11 JP JP58082454A patent/JPS58209145A/en active Pending
- 1983-05-13 CA CA000428109A patent/CA1200616A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| EP0094559A1 (en) | 1983-11-23 |
| DE3375860D1 (en) | 1988-04-07 |
| DE3218309A1 (en) | 1983-11-17 |
| EP0094559B1 (en) | 1988-03-02 |
| ATE32805T1 (en) | 1988-03-15 |
| JPS58209145A (en) | 1983-12-06 |
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