CA1204827A - Method of and arrangement for demodulating a frequency-modulated input signal - Google Patents
Method of and arrangement for demodulating a frequency-modulated input signalInfo
- Publication number
- CA1204827A CA1204827A CA000431052A CA431052A CA1204827A CA 1204827 A CA1204827 A CA 1204827A CA 000431052 A CA000431052 A CA 000431052A CA 431052 A CA431052 A CA 431052A CA 1204827 A CA1204827 A CA 1204827A
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- Canada
- Prior art keywords
- input
- output
- stage
- signal
- zero
- Prior art date
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D3/00—Demodulation of angle-, frequency- or phase- modulated oscillations
- H03D3/006—Demodulation of angle-, frequency- or phase- modulated oscillations by sampling the oscillations and further processing the samples, e.g. by computing techniques
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D2200/00—Indexing scheme relating to details of demodulation or transference of modulation from one carrier to another covered by H03D
- H03D2200/0041—Functional aspects of demodulators
- H03D2200/006—Signal sampling
- H03D2200/0062—Computation of input samples, e.g. successive samples
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D2200/00—Indexing scheme relating to details of demodulation or transference of modulation from one carrier to another covered by H03D
- H03D2200/0041—Functional aspects of demodulators
- H03D2200/0064—Detection of passages through null of a signal
Abstract
ABSTRACT:
For determining the half-cycle durations of the input signal which is presented as a sequence of sampled values, its zero crossings are approximated too by lines which interconnect the from sampled values of different sign on both sides of the zero crossing. The half-cycle duration is derived from the number of sampled values within a period, i.e. between two consecutive zero cross-ings, and from the time intervals at the beginning and end of each half-cycle determined by the intersection of the approximation line with the axis. The time intervals at the beginning and end of each period are corrected for a more accurate determination of the duration and the time intervals during which the values of the individual half-cycle durations are stored, are made to approximate to these half-cycle durations. The instantaneous frequency of the input signal is determined from the values of the half-cycle durations which have thus been shifted in time by forming the reciprocal.
For determining the half-cycle durations of the input signal which is presented as a sequence of sampled values, its zero crossings are approximated too by lines which interconnect the from sampled values of different sign on both sides of the zero crossing. The half-cycle duration is derived from the number of sampled values within a period, i.e. between two consecutive zero cross-ings, and from the time intervals at the beginning and end of each half-cycle determined by the intersection of the approximation line with the axis. The time intervals at the beginning and end of each period are corrected for a more accurate determination of the duration and the time intervals during which the values of the individual half-cycle durations are stored, are made to approximate to these half-cycle durations. The instantaneous frequency of the input signal is determined from the values of the half-cycle durations which have thus been shifted in time by forming the reciprocal.
Description
B~7 n 82.071 l 3.6. 1983 "MethoA of and arrangement for demodulating a fr0quency-modulated input signal".
The invention relates -to a method of demodulating a frequency-modulated periodic input signal by determining the duration of each half-cycle between every two adjacent zero crossings of the input signal, which signal appears in the form of a sequence of digitized samples taken from the input signal at regular intervals, and by generating the reciprocals of the duration of the half-cycles. The invention also relates to an arrangement for carrying out the method.
A similar method for input signals in purely analog form is known in which the duration of each half-cycle between every two adjacent zero crossings is deter-mined by counting a reference clock signal whose frequency is high in comparison with the highest frequency of the input signal. The number reference~clock pulses counted between two adjacent zero crossings constitutes a digital representation of the duration of -the half-cycle. If the half-cycle duration must be determined with a high reso-lution the frequency of the reference cloch signal must be increased proportionally relative to the input-signal fre-quency. In the case of high-frequency input signals, such as the frequency modulated luminance signal in a colour video signal read from a magnetic -tape, the reference clock fre-quency must be so high that the counting circuits required for this are impracticable or become too intricate and expensive.
It is the object of the inven-tion -to provide a method of the -type mentioned in the opening paragraph in which the frequencies of the required clock or other auxi-liary signals are of the order of magnitude of the fre-quency with which the sequence of samples of the input sig~nal recurs 9 SO that digital electronic circuits with a , ' , .
The invention relates -to a method of demodulating a frequency-modulated periodic input signal by determining the duration of each half-cycle between every two adjacent zero crossings of the input signal, which signal appears in the form of a sequence of digitized samples taken from the input signal at regular intervals, and by generating the reciprocals of the duration of the half-cycles. The invention also relates to an arrangement for carrying out the method.
A similar method for input signals in purely analog form is known in which the duration of each half-cycle between every two adjacent zero crossings is deter-mined by counting a reference clock signal whose frequency is high in comparison with the highest frequency of the input signal. The number reference~clock pulses counted between two adjacent zero crossings constitutes a digital representation of the duration of -the half-cycle. If the half-cycle duration must be determined with a high reso-lution the frequency of the reference cloch signal must be increased proportionally relative to the input-signal fre-quency. In the case of high-frequency input signals, such as the frequency modulated luminance signal in a colour video signal read from a magnetic -tape, the reference clock fre-quency must be so high that the counting circuits required for this are impracticable or become too intricate and expensive.
It is the object of the inven-tion -to provide a method of the -type mentioned in the opening paragraph in which the frequencies of the required clock or other auxi-liary signals are of the order of magnitude of the fre-quency with which the sequence of samples of the input sig~nal recurs 9 SO that digital electronic circuits with a , ' , .
2~
PIID ~2.071 ~ 3,6.1983 lo-~er operating speed may be used.
~ ccording to the invention thi.s object is achieved in that th0 duration '~ of each half-cycle is de-rived from the sum of the time intervals T corresponding to the number n of samples between the adjacent zero crossings -and the time intervals tn, tm between each zero crossing and the sample which directly precedes it, using the following relationship:
(T tn~ + nT + tm tm t}l + (n + l)T
the time intervals tn and tm each being derived from two consecutive samples an, an+l and am, am~l respec-tively of different signs at the location of the zero crossings, using the following relationship:
¦ a 1 1 n T la l-a ¦a m-l m¦
In this way the duration of each half-cycle is derived from full periods T of the samples and from fractions there-of, which are obtained fro~ the t~o adjacent samples by a linear approximation to the input signal at the location of the zero crossings. The resolution of determining the durat-ion of` each half-cycle then does not depend on a high-fre-quency c:Lock signal but on the :resolution, i.e. the pre-cision, of the samples~ The required comp~ltation can be effected within the time intervals between two consecutive samples, or in the case of a plurality of computing operations within a multiple thereof, if a pipeline struc-ture is used for carrying out the method. ~hen calculating the duration of the next half-cycle the second time inter-val t may be used as the first time interval tn.
It is obvious that the accuracy of the linear approximation to a sinusoidal input signal at the locat-ion of the zero points increases as the number of` samples ~PI[D ~2.07-l 3 3.6.1983 ~iithin one half-cycle increases. llowever~ if only a few samples, for example less than t-ro, occur within one half-cycle of` the input signal, a distinct error will arise owing to the linear approximation. In such a case it is effective to use a variant of the method in accordance with the invention in which prior to the determination of the half-cycle clura-tion each time interval tn, tm is corrected by a correction value which depends on -the value of said time interval. Moreover, a further correction is possible using the value of the duration of the preceding half-cycle, because in general it is assumed that the frequency con-tained in the input signal does not change abruptly from one half-cycle to -the next.
The duration of each half-cycle is determined lS with the first sample after the end of this half-cycle, i _ after the zero crossing with which this half-cycle terminates. The value thus determined is preserved until the duration of the next half-cycle has been determined.
This means that the value of the duration of a half-cycle remains available for the length of the next half-cycle whose duration may differ from that of the preceding half-cycle, so tha-t values of short half-cycle durations are maintained too long and those of long half-cycle durations too shor-t, resulting a shift relative to the correct de-~5 modulated signal. In order to preclude this, it ic effect-ive in accordance with a ~urther variant if the duration determined for each half-cycle is stored for a time interval equal to the interval between a number of samples which is 1 higher than the nurnber of samples between the first of the two adjacent zero crossings and the preceding zero crossing. Such a method can simple be carried out by means of a delay device, as rill be explained hereinafter.
The above variant of the method in accordance with the invention still gives rise to small errors as a result of time shifting, because the value of the duration of a half-cycle always coincides -with or has constant shift relative to the instant at which a sample appears 9 whilst PIID ~2.071 L~ 3.6.1983 the actual zero crossing occurs at an arbitrary instant between -two samples. In order to minimize the effect of this sta-tis-tically varying time error it is ef~ective, in accordance with a further variant of the inventive method, if a period ~ k is assigned to the time interval between the consecutive samples a 5 an 1 at the location of the first one of the two zero crossings which period, depending on the time interval tn between this zero crossing and the preceding sample, is situated between the perlod ~n 1 de-termined berore this zero crossing and the last period de-termined ~n in conformity with the following relationship:
~nk tn ( n-l n) + n-In this way an intermediate value is inserted at the location of the zero crossing during the change from the value o~ one half-cycle duration to that of the next half-cycle, so tha-t a smoother -transition between the values is obtained, which results in a better approximation to the variation of the frequency of the input signal.
An arrangement for carrying out the method in accordance with the invention and two embodiments thereo~
are defined in the other sub-claims.
~ mbodiments of the invention will now be des-cribed in more de-tail, by way of example, with reference to the dra~ings. In the drawings:
Fig~ 1 is a timing diagram which illustrates how the half-cycle duration of a frequency-modulated sinusoidal input signal is determined by a linear approximation to the zero crossings, Fig. 2 is a diagram which illustrate the errors which then occur, F~g. 3 shows the effects of maintaining the value of -the duration of a half~cycle for the length of the next half-cycle and the result of` a correction for this effect, Fig, 4 is a block diagram of a circuit arrangement in accordance with the invention, PIID S2.O7l 5 3,6.1983 ~ig, 5 is the block diagram of a modification to the circuit arrangement shown in Fig. L~
~ig, 6 shows the basic arrangement of specific delay stages.
Fig. 1 shows a full period of a sinewave signal whose half-cycle ~ is -to be determined by digital means.
For this purpose the input signal is available in the fornn of a sequence of samples, of which the samples a 1' a , a , a are shown. If the samples are situated closer to m-1 m each other in relation to the signal, i.e. if the signal ~requency is low relative to the sample frequency 1/T (T
is the period of the samples, i.e. the distance between two consecutive samples), further samples will be situated between the samples an and am l~ However, this is not essential ~or the following explanation.
The zero crossings of the signal determine the half-cycle duration and thus its frequency. However, since the sampled values are discrete in time the zero-crossings are approximated tooby a straight connecting line between the two sampled values and from the time intervals defined by the intersections of this approximation line with the axis an approximated value ~' of the desired period is de-rived. From the time intervals tn and tm be-tween an inter-section with an approximation line and the preceding sampled value an~l from the number n of samples between two adjacent zero crossings the approximated value for thehalf-cycle duration can then be derived as follows in con-formity with Fig. 1:
~t = (T - tn) + n-T + tm = tm ~ tn + (n+1)T (1) The duration of the time interval t~ can be derived from the values a 1 and an of the two adjacent samples and from their distance T in accordance with the set of radii in the following manner: 5 n _ T
¦ n~ n-1 n~
tn = I n-1L_ T (2) n_ 1 an I
8~7 PIID ~2.071 6 3.6.1983 In a similar way the duration of the tl-ne interval tm can be derived. These time intervals can be cl0termined after each other, the previously determined time interval tn being stored temporarily, and the approxima-ted value ~ of the half-cycle duration is derived from the buffered time interval t and the instantaneously compu-ted time interval tm in accordance with equation (1).
As will be seen in Fig. 1, the deviation of intersection of -the approximation line which extends -through the two adjacent sampled values with the axis from the actual zero crossing of the signal corresponds to an error F. This error, as is evident from Fig. 1, depends on the positions of the two sampled values relative to the zero crossing and hence it depends directly on the value of the time interval tn. If a sampled value happens to coincide with a zero crossing, i.e. if t = O or t = T, the error n n is also equal to O. If the two sampled values are disposed e~actly s~nmetrically relative to the zero crossing, i.e.
if -tn = O.5, the error is also O in the case of a purely sinusoidal signal, the errors on both sides o~ this value for tn having different signs.
The variation of the error F depending on the ratio of the time interval tn to the perîod T of the sampled values is plotted in Fig. 2. ~s the sampled values 1ie closer to the signal period, i.e. as the value ~/t in-creases~ the maxin1um value o~ the error F decreases, thebasic variation depending on the position of the sampled values relative to the zero crossing being the same. For a very accurate correction of the time intervals t~ and tm respectively the instantaneous frequency or period of the signal must be known, which may be approximated -too by the values last determined assuming that no abrupt change in signal frequency occurs between two half-cycles. In prac-tice, for example for the demodulation of the frequency-modulated luminance signal contained in a video signal which has been read from a magnetic tape, it is found that the correction o~ the time intervals tn and tm depending PIID ~2 07l 7 3.6.1983 on these values is adequate only for an average fre-quency of the signal equal to a quarter of the sample fre-quency. If by means of the -time in-tervals -thus correc-ted the duration ~ of a half-cycle of the signal and from this duration -the signal frequency is determined, the resulting values are sufficiently accurate.
~ Iowever, this only yields the values of the durations of the individual half=cycles, but these need not directly constitute a correct representation of the periods of the signal frequency~ as will be explained with reference to Fig. 3. In this Figure a) shows an input signal whose frequency changes at an exaggerated fast rate~ On line b) the zero-crossing signal is shown, which is generated if immediately after a sampled value a new sampled value with an opposite sign occurs, and this signal is maintained until the next sample. The variation of the zero-crossing signal is also important for the description of the block diagram given hereinafter.
By means of the first zero-crossing signal shown on line b in Fig. 3 the value of the duration of the half cycle a of the input signal is determined. This value is stored until the second zero-crossing signal appears, upon which the value of the duration of the half-cycle b is de termined This applies also to the half-cycles c and d. The values ~n of the durations of these individual half-cycles and the periods of time during which these values are stored are represented in Fig. 3 on line c), the beginning of the value for the duration of the half-cycle a being indicated by a short vertical line, because the preceding half-cycle of the input signal and hence its duration is not shown.
It will be seen that the values for the durations of the individual half-cycles are stored for time inter-vals whose lengths are not in conformity with the durations of the corresponding half-cycles. For a more accurate approximation the time during which the value of the dura-t-ion of each half-cycle is stored must be changed, which is PlID 82.071 8 3,6.1983 possible by de:Laying these values by several sampling clock periods. Different values then have to be delayed to a different extent in some cases. The control signal for the delay may be derived from the zero-crossing signal.
The values ~~ which have been delayed to obtain the cor-rect dura-tion are shown on line d) in Fig. 3. This se-quence of values constitu-tes a substantially better approxi-mation to the actual variation of the periods of the inpu-t signal.
On line e) in Fig. 3 the sequence of values for the individual half cycle durations a to e has been shifted so that the value for the duration of a hal~-cycle begins with the first samples value in this half-cycle.
I-t will be appreciated that each value of a half-cycle lS duration is still shifted to some extent relative to the exact position of this half-cycle, because in the present example the zero crossings are each time situated be~
tween -two sampled values. The shift of the beginning of each new value relative to the first of the two associated adjacent zero crossings depends on the input signal and varies statistically with this signal, so that any arbi-trary other shift (which shift is purely arithmetical and corresponds to an arbitrary constant shift between the in-put signal and the output signal) can never bring the se-quence of values completely into conformity with the input signal.
For a further improvement of the approximation an intermediate value betweenthe old and the new value is formed before every new valuel i.e. in the drawing between the two sampled values on both sides of the zero crossing9 which intermediate value depends as follows on the position of the zero crossing between the instants of the samplecl values and thus on the values of the time intarvals tn and tm respectively in determining the half-cycle durations~
~2 = tn' ~n-1 + (1-t~) ~
= t (~ 1 ~ n) +1~ (3) Thus, if a zero crossing is situated near the second one of ~263~7 PIID ~2.071 9 3.6.1983 the two consecutive sampled values, the preceding half-cycle has extended f`ar into -this interval, ancl the inter-mediate value ~ is therefore also situa-ted near the value for the duration of the preceding half-cycle and is in-verted accordingly. These intermediate values are indi-cated by a solid line at the relevant points in Fig. 3e), the uncorrected values being represented by broken lines.
The solid line in Fig. 4e) therefore represents the cor-rected variation of the values 1~Vk of the durations of the half-cycles of the input signal and even in the cases in which only a few sampled values are situated in each half-cycle and the half-cycle durations vary rapidly they con-stitute a good approximation to the actual variation of the half-cycle durations.
Hereinafter the block diagram is described of a circuit arrangement which determines the corrected values of the half-cycle durations obtained in the manner des-cribed above, from which values the frequency of an input signal is derived, Fig. 5 showing the arrangement for generating the values plotted in Fig. 3c) and Fig. 5 show-ing the block diagram of a circuit arrangement for gene-rating the values which are situated correctly in time and ~hose transitions have been corrected.
The sequence of sampled values corresponding to the input signal to be modulated is applied to the input 2 of the circuit arrangement in Fig. 4. The sampled values are presented in the form of, for example, multi-bit binary words, whose individual bits are processed in pa-rallel, so that the input 2 in fact comprises a number of parallel inputs for -the individual bits of a data word.
Therefore, the connection 1 from the input 2 and the other lines shown in Fig. 4 and Fig. 5 also comprise a number of parallel lines corresponding to the number of bi-ts of each data word, except for the lines carrying the zero-crossing signal and signals derived therefrom~ such as the lines 17 and 19, Via connection 1 input 2 is connected to a re-8~7 PlID 82.071 10 3.6.1983 gister 4 which stores a data word upon each clock signal This clock signal, no-t shown, which is also applied -to other registers, is correlated to the application of -the sampled values to input 2, i.e. each time that a new sampled value is applied a pulse of the clock signal appears.
Connection 1 is also connected to a subtractor 6, whose other input is connected to the output of the re-gister 4 and forms the difference between the two values.
The output of the subtractor stage 6 is connected to a value-generating stage 8 which generates the absolute value o~ the difference. For example for the representation of the sampled values and the binary values derived there-from this requires a specific processing of the applied values. The output of the register is also connected via connection 3 to a value-generating stage 10 of a similar type. It follows from equation (2) that only positive values are permissible ~or the time intervals t and in order to simplify division it is preferred to divide only the absolute values.
This division is per~ormed in the divider stage 12 to which the values generated by the stages 8 and 10 are applied. The multiplication in equation (2) by the duration of the period of the sampled values or the clock signal may be omitted, because this value is a constant scaling factor~
The quotients formed by the divider stage 12 are applied to a correction stage 14 which comprises a read-only memory to which the quotients ~ormed by the divider stage 12 are applied as addresses. ~t each address, which corresponds to a specific value of the time interval tn, the time interval corrected by the error F for a specific average frequency of the input signal in accordance with Figs. 1 and 2 is stored and is output via connection 150 This connection 15 leads to the input of a fur-ther register 20, which stores the value on -the colmection 15 at the end of a zero-crossing signal. This zero-crossing signal shown in Fig. 3b) is generated by an exclusive-OR
.~, PIID ~2.071 11 3.6.l983 logic net-~ork l6, wllich receives the 9~gn bits of the undela~ved sampled value applied to -the input 2 and the delayed samplecl value supplied by the register L~ and which produces an output signal on the line 17 if the two sign bits are different. If during processing of the sampled values in -the stages 6 to 1L~ a delay of more than one clock period occurs, which may happen in particular if the divider stage 12 is a pipeline divider, said zero-crossing signal is applied to a time-delay stage 18, which has a delay time equal to said delay. The zero-crossing signal, which may have been delayed, on the output line 19 corres-ponds in time to the data word applied to the input of the register 20. This register 20 therefore contains a value corresponding to the length of the time interval tn after each end of the zero-crossing sig~nal, i.e~ ~ithout a delay after the second sampled value which follows a zero crossing.
This value is applied to the subtraction input of an arithmetic stage 22, whose other input is connected to the output of the correction circuit 14 and receives a value corresponding to the time interval t in accordance with Fig. 1 upon the appearance of the next zero crossing.
The line 19 l~hich carries the zero-crossing sig-nal is also connected to the reset input of a counter 24, which receives the clock signal, n~t shown, as counting clock signal. The output of the counter 2L~ is connected to an output counting register 26, into ~hich the count is loaded upon each clock signal and consequently upon the appearance of a zero-crossing signal on the line 19. Thus, during each zero-crossing signal the output counting re~
gister 26 contains a value corresponding to the number of sampled values~ incremented by "1", between the directly preceding two zero crossings of the input signals 7 assuming that the counter 24 is set -to "1" by -the zero~crossing sig-nal and the count reached directly before a clock signalis loaded into the register 26 under con-trol of the clock signal edges only. ~lternatively, to set the counter 2L~ to -the initial position "1" at the end of the zero-crossing PI-ID 82.07l 12 3.6.1983 signal, so that the regist0r 26 may be dispensed with or a delay by one clock period is provided in the output line of the ari-thmetic stage 22 as well as the line 19 and the connec-tion 15.
The outputs of the output counting register 26 and the arithmetic stage 22 in the form of a sub-tractor are connected to the inputs of an adder 28, whose output 28 supplies values corresponding to the duration of each half-cycle of the input signal applied to the input 2, which durations do not always appear at the correct in-stant as is illustrated in Fig. 3c). Moreover, it is to be noted that in the present circuit arrangement the stages 6 to 14 and consequently the stages 22 and 28 not only process the values corresponding to two consecutive sampled values on both sides of a ~ero crossing but also all the other sampled values, so that between two correct values which represent the duration of the last half-cycle erroneous or useless values appear on output 29.
However, this is taken into account during the further processing of these values in the circuit arrangement shown in Fig. 5, which ~orms the correctly timed durations of the values as shown in Fig. 3e).
The values appearing on the connection 29 are applied to a delay circuit 40 in Fig. 5, which is construct-ed as a shi~t register comprising the series-connected register stages 402, 404~ 406 and 408. The value appearing on the connection 29 is loaded into the register stage 402 only at the end of the zero-crossing signal on the line 19, whilst the register stages store the value on the input upon each clock signal. Thus, in general several consecutive stages contain the same values, which is necessary for generating the sequence of values with the correct durat-ions as shown in Fig. 3d). The tappings 40l, 403, 405 and 407 of the delay circuit, which are connected to the out-35 puts of the stages 402, L~o4, 406 and 408, are connected to the individual position connections of a ch.ange-over switch 46, which is suitably constructed as an electronic multi-ple~er.
2~
PIID S2.071 13 3.6.1983 The zero-crossing signal on tho line 14 is applied to a delay circuit 42 corresponding to the delay circuit 40, which also comprises a number of series-con-nected stages 422, 424, 426 and 428, which are controlled by the clock signal. Each of these stages contains only one bit in contradistinction to the stages 402 to 408 of the delay circuit 40~ which each contain a data word. The tappings 421, 423, 425 and 427 o~ the delay circui-t 42 are connected to the outputs of the corresponding stages 422 to 428 and thus correspond to the tappings of the delay circuit 42.
The tappings 421 to 427 of the delay circuit 42 are connected to the inputs of a processing circuit 44 in -the form of a read-only memory, the inputs being the address inputs of the memory. Each address of the memory is thus assigned to a specific combination of signals on the tappings 421 to 427, i.e. a speci~ic pattern of -the zero-crossing signal on the line 45, and contains a bit combination which appears on output line 45 and which sets the switch 46 to a well-defined position. As the switch 46 in the present embodiment has ~our positions, two bits on each address of the read-only memory are sufficient in the selection circuit 44, so that the line 45 in fact comprises two lines. The content of -the read-only memory 25 for various signal combinations on the tappings 421 to 427 is specified in the following Table.
~;Zl)~8~7 PTID 82.07l 14 3.6.1983 TABL~
421 _ ~ _ _ _ 45 ~1 _ _ _ In the Table the value "O" on the line 45 means that the switch 46 is connected to the output 4O1, -the other values being assigned to the other outputs in the same sequence. The bit combina-tion yielding the value ~
cannot occur for -the relevant ~requencies or means such a low frequency relative to the clock frequency that the delay circuits 4O and 42 would become too long.
By controlling the switch 46 in accordance with the Table the sequenceo~ values for the durations of the cons0cutive hal~-cycles is obtained with the correct timing~
as shown in Fig. 3d), on the output connection 47 of the switch 46.
The intermediate values o~ Fig. 3e) are generated by means o~ the other elements shown in F~g,5. O~ these elements the input o~ a register 48 is connecte~ -to the tapping 4O7 of the delay circuit 4O and upon each clock signal the value appearing on this tapping is loaded into ~L2~8~7 PIID 82.071 15 3.6.1983 the register 48. 'I`his value is -the value of the period for which the corresponding zero crossin.g signal appears simultaneously on the outpu-t 427 of the delay circuit 42.
I~hen this value has been loaded in-to the register 48 the value of -the next period appears simultaneously on -the connection 47 as a result ~ an appropriate change-over of the switch 46. The output of the register 48 is con-nected to the adding input of a subtractor 50, whose subtract input is connected to -the connection 47, so that I0 at an instant corresponding to the delay caused by the register ~8 the difference between the values of the durations of two consecutive half-cycles appears on the output connection 51. The correspondingly delayed zero-crossi.ng signal is taken from the output 59 of a delay I5 s-tage 60, which is connected to the tapping or output 427 of the delay circuit 42, and th.is signal actua-tes a switch whose function will be explained hereinaf-ter.
The connection 51 is connected to one input of a multiplier 54, whose other input is connected to the switch 58. In the absence of a zero-crossing this switch 58 transfers the value "0" to the multiplier 54, so that the value "0" appears on said output connection. When a zero-crossing signal appears the switch 58 connects the relevant input of the multiplier 54 to the output of a de-lay circuit 52, which has a delay time equal -to tle sum of the delays of the register 48 and the delay circuit 40 and which may for example be constructed as a shift re-gister with a sui-table number of stages. The inpu-t of the delay circuit 52 is connected to the connection 15, which carries the value of the time interval t , which corres-ponds to the value of the half-cycle duration which appears simultaneously on the connection 47 as a result of -the delay produced by the delay circuit 52.
This value is applied to one input of an adder 56, whose other input is connected to the connection 55 of the multiplier 54. Thus, upon a change from the value of the duration of one half cycle to that of the next half-cycle intermediate value be-tween these two values is genera-ted ~2~ 327 PHD 82.071 16 3.o.1983 on lts ou-t~ut connection 57. The corrected values of the individual half-cycle durations thus produced on the out-put conncction 57 are applied to the input of the recipro-cal-~alue generator 30, which suitably comprises a read-only memory, whose address lines are connected to the in-put of the reciprocal-value generator 30 and which trans-fers the data on these addresses to the output 32 of the arrangement. These values appearing on the output 32 represent the sequence of the instantaneous frequencies of the input signal corresponding to the sampled values applied to the input 2, with a constant time delay, which in the present example is mainly caused by the delay cir-cuit 40. The time delay of the delay circuit L~o and conse-quently that of the delay circuit 42 depends on the durat-ion of the longest half-cycle occurring in the input sig-nal, and strictly speaking on the difference bet-reen the smallest and the longest duration of the actually occurr-ng half~cycles of the input signal. The shift in time between the input signal and the output signals on output 32 which represent its instantaneous frequency may increase of in particular the individual arithmetic stages are followed by delay stage, in which case care must be taken that the delays introduced in all the pa-rallel signal paths are the same, in order to compensate for the propagation delays of the signals ln the indivi-dual arithmetic stages, so that said delay can be sub-stantially equal to the period of the clock signal.I-Towever, for the sake of clarity such additional delay stages are not shown.
~uitably, the register stages and delay stages used in the present example and, as the case may be addit-ional stages, are constructed as accumulator registers, which are all operated with the clock signal, i.e. which take up the input value and transfer it -to the output upon each clock pulse. This is particularly favourable if the complete circuit arrangement is constructed as an inte~
grated circuit in dynamic MOS-tech~ology. In order -to 1'~1D 82.071 l7 3.6.1983 enable the registsr stages and delay s~ ges, which must take over a value only when a zero-crossing signal appears, to be constructed in the same way, it is eI'fective to use -the arrangement shown in Fig. 6. This arrangement com-prises a register 64 which is operated with the generalclock signal. 'rhe input of this register 64 is preceded by a switch 62, which under con-trol of the zero-crossing signal via the line 63 connects the input 61 of the stage to the input of the register 64. In the absence of a zero-crossing signal on the line 63 the input of the re-gister 64 is connected to its output 65, so that its con-tents is not changed upon the next clock signals.
PIID ~2.071 ~ 3,6.1983 lo-~er operating speed may be used.
~ ccording to the invention thi.s object is achieved in that th0 duration '~ of each half-cycle is de-rived from the sum of the time intervals T corresponding to the number n of samples between the adjacent zero crossings -and the time intervals tn, tm between each zero crossing and the sample which directly precedes it, using the following relationship:
(T tn~ + nT + tm tm t}l + (n + l)T
the time intervals tn and tm each being derived from two consecutive samples an, an+l and am, am~l respec-tively of different signs at the location of the zero crossings, using the following relationship:
¦ a 1 1 n T la l-a ¦a m-l m¦
In this way the duration of each half-cycle is derived from full periods T of the samples and from fractions there-of, which are obtained fro~ the t~o adjacent samples by a linear approximation to the input signal at the location of the zero crossings. The resolution of determining the durat-ion of` each half-cycle then does not depend on a high-fre-quency c:Lock signal but on the :resolution, i.e. the pre-cision, of the samples~ The required comp~ltation can be effected within the time intervals between two consecutive samples, or in the case of a plurality of computing operations within a multiple thereof, if a pipeline struc-ture is used for carrying out the method. ~hen calculating the duration of the next half-cycle the second time inter-val t may be used as the first time interval tn.
It is obvious that the accuracy of the linear approximation to a sinusoidal input signal at the locat-ion of the zero points increases as the number of` samples ~PI[D ~2.07-l 3 3.6.1983 ~iithin one half-cycle increases. llowever~ if only a few samples, for example less than t-ro, occur within one half-cycle of` the input signal, a distinct error will arise owing to the linear approximation. In such a case it is effective to use a variant of the method in accordance with the invention in which prior to the determination of the half-cycle clura-tion each time interval tn, tm is corrected by a correction value which depends on -the value of said time interval. Moreover, a further correction is possible using the value of the duration of the preceding half-cycle, because in general it is assumed that the frequency con-tained in the input signal does not change abruptly from one half-cycle to -the next.
The duration of each half-cycle is determined lS with the first sample after the end of this half-cycle, i _ after the zero crossing with which this half-cycle terminates. The value thus determined is preserved until the duration of the next half-cycle has been determined.
This means that the value of the duration of a half-cycle remains available for the length of the next half-cycle whose duration may differ from that of the preceding half-cycle, so tha-t values of short half-cycle durations are maintained too long and those of long half-cycle durations too shor-t, resulting a shift relative to the correct de-~5 modulated signal. In order to preclude this, it ic effect-ive in accordance with a ~urther variant if the duration determined for each half-cycle is stored for a time interval equal to the interval between a number of samples which is 1 higher than the nurnber of samples between the first of the two adjacent zero crossings and the preceding zero crossing. Such a method can simple be carried out by means of a delay device, as rill be explained hereinafter.
The above variant of the method in accordance with the invention still gives rise to small errors as a result of time shifting, because the value of the duration of a half-cycle always coincides -with or has constant shift relative to the instant at which a sample appears 9 whilst PIID ~2.071 L~ 3.6.1983 the actual zero crossing occurs at an arbitrary instant between -two samples. In order to minimize the effect of this sta-tis-tically varying time error it is ef~ective, in accordance with a further variant of the inventive method, if a period ~ k is assigned to the time interval between the consecutive samples a 5 an 1 at the location of the first one of the two zero crossings which period, depending on the time interval tn between this zero crossing and the preceding sample, is situated between the perlod ~n 1 de-termined berore this zero crossing and the last period de-termined ~n in conformity with the following relationship:
~nk tn ( n-l n) + n-In this way an intermediate value is inserted at the location of the zero crossing during the change from the value o~ one half-cycle duration to that of the next half-cycle, so tha-t a smoother -transition between the values is obtained, which results in a better approximation to the variation of the frequency of the input signal.
An arrangement for carrying out the method in accordance with the invention and two embodiments thereo~
are defined in the other sub-claims.
~ mbodiments of the invention will now be des-cribed in more de-tail, by way of example, with reference to the dra~ings. In the drawings:
Fig~ 1 is a timing diagram which illustrates how the half-cycle duration of a frequency-modulated sinusoidal input signal is determined by a linear approximation to the zero crossings, Fig. 2 is a diagram which illustrate the errors which then occur, F~g. 3 shows the effects of maintaining the value of -the duration of a half~cycle for the length of the next half-cycle and the result of` a correction for this effect, Fig, 4 is a block diagram of a circuit arrangement in accordance with the invention, PIID S2.O7l 5 3,6.1983 ~ig, 5 is the block diagram of a modification to the circuit arrangement shown in Fig. L~
~ig, 6 shows the basic arrangement of specific delay stages.
Fig. 1 shows a full period of a sinewave signal whose half-cycle ~ is -to be determined by digital means.
For this purpose the input signal is available in the fornn of a sequence of samples, of which the samples a 1' a , a , a are shown. If the samples are situated closer to m-1 m each other in relation to the signal, i.e. if the signal ~requency is low relative to the sample frequency 1/T (T
is the period of the samples, i.e. the distance between two consecutive samples), further samples will be situated between the samples an and am l~ However, this is not essential ~or the following explanation.
The zero crossings of the signal determine the half-cycle duration and thus its frequency. However, since the sampled values are discrete in time the zero-crossings are approximated tooby a straight connecting line between the two sampled values and from the time intervals defined by the intersections of this approximation line with the axis an approximated value ~' of the desired period is de-rived. From the time intervals tn and tm be-tween an inter-section with an approximation line and the preceding sampled value an~l from the number n of samples between two adjacent zero crossings the approximated value for thehalf-cycle duration can then be derived as follows in con-formity with Fig. 1:
~t = (T - tn) + n-T + tm = tm ~ tn + (n+1)T (1) The duration of the time interval t~ can be derived from the values a 1 and an of the two adjacent samples and from their distance T in accordance with the set of radii in the following manner: 5 n _ T
¦ n~ n-1 n~
tn = I n-1L_ T (2) n_ 1 an I
8~7 PIID ~2.071 6 3.6.1983 In a similar way the duration of the tl-ne interval tm can be derived. These time intervals can be cl0termined after each other, the previously determined time interval tn being stored temporarily, and the approxima-ted value ~ of the half-cycle duration is derived from the buffered time interval t and the instantaneously compu-ted time interval tm in accordance with equation (1).
As will be seen in Fig. 1, the deviation of intersection of -the approximation line which extends -through the two adjacent sampled values with the axis from the actual zero crossing of the signal corresponds to an error F. This error, as is evident from Fig. 1, depends on the positions of the two sampled values relative to the zero crossing and hence it depends directly on the value of the time interval tn. If a sampled value happens to coincide with a zero crossing, i.e. if t = O or t = T, the error n n is also equal to O. If the two sampled values are disposed e~actly s~nmetrically relative to the zero crossing, i.e.
if -tn = O.5, the error is also O in the case of a purely sinusoidal signal, the errors on both sides o~ this value for tn having different signs.
The variation of the error F depending on the ratio of the time interval tn to the perîod T of the sampled values is plotted in Fig. 2. ~s the sampled values 1ie closer to the signal period, i.e. as the value ~/t in-creases~ the maxin1um value o~ the error F decreases, thebasic variation depending on the position of the sampled values relative to the zero crossing being the same. For a very accurate correction of the time intervals t~ and tm respectively the instantaneous frequency or period of the signal must be known, which may be approximated -too by the values last determined assuming that no abrupt change in signal frequency occurs between two half-cycles. In prac-tice, for example for the demodulation of the frequency-modulated luminance signal contained in a video signal which has been read from a magnetic tape, it is found that the correction o~ the time intervals tn and tm depending PIID ~2 07l 7 3.6.1983 on these values is adequate only for an average fre-quency of the signal equal to a quarter of the sample fre-quency. If by means of the -time in-tervals -thus correc-ted the duration ~ of a half-cycle of the signal and from this duration -the signal frequency is determined, the resulting values are sufficiently accurate.
~ Iowever, this only yields the values of the durations of the individual half=cycles, but these need not directly constitute a correct representation of the periods of the signal frequency~ as will be explained with reference to Fig. 3. In this Figure a) shows an input signal whose frequency changes at an exaggerated fast rate~ On line b) the zero-crossing signal is shown, which is generated if immediately after a sampled value a new sampled value with an opposite sign occurs, and this signal is maintained until the next sample. The variation of the zero-crossing signal is also important for the description of the block diagram given hereinafter.
By means of the first zero-crossing signal shown on line b in Fig. 3 the value of the duration of the half cycle a of the input signal is determined. This value is stored until the second zero-crossing signal appears, upon which the value of the duration of the half-cycle b is de termined This applies also to the half-cycles c and d. The values ~n of the durations of these individual half-cycles and the periods of time during which these values are stored are represented in Fig. 3 on line c), the beginning of the value for the duration of the half-cycle a being indicated by a short vertical line, because the preceding half-cycle of the input signal and hence its duration is not shown.
It will be seen that the values for the durations of the individual half-cycles are stored for time inter-vals whose lengths are not in conformity with the durations of the corresponding half-cycles. For a more accurate approximation the time during which the value of the dura-t-ion of each half-cycle is stored must be changed, which is PlID 82.071 8 3,6.1983 possible by de:Laying these values by several sampling clock periods. Different values then have to be delayed to a different extent in some cases. The control signal for the delay may be derived from the zero-crossing signal.
The values ~~ which have been delayed to obtain the cor-rect dura-tion are shown on line d) in Fig. 3. This se-quence of values constitu-tes a substantially better approxi-mation to the actual variation of the periods of the inpu-t signal.
On line e) in Fig. 3 the sequence of values for the individual half cycle durations a to e has been shifted so that the value for the duration of a hal~-cycle begins with the first samples value in this half-cycle.
I-t will be appreciated that each value of a half-cycle lS duration is still shifted to some extent relative to the exact position of this half-cycle, because in the present example the zero crossings are each time situated be~
tween -two sampled values. The shift of the beginning of each new value relative to the first of the two associated adjacent zero crossings depends on the input signal and varies statistically with this signal, so that any arbi-trary other shift (which shift is purely arithmetical and corresponds to an arbitrary constant shift between the in-put signal and the output signal) can never bring the se-quence of values completely into conformity with the input signal.
For a further improvement of the approximation an intermediate value betweenthe old and the new value is formed before every new valuel i.e. in the drawing between the two sampled values on both sides of the zero crossing9 which intermediate value depends as follows on the position of the zero crossing between the instants of the samplecl values and thus on the values of the time intarvals tn and tm respectively in determining the half-cycle durations~
~2 = tn' ~n-1 + (1-t~) ~
= t (~ 1 ~ n) +1~ (3) Thus, if a zero crossing is situated near the second one of ~263~7 PIID ~2.071 9 3.6.1983 the two consecutive sampled values, the preceding half-cycle has extended f`ar into -this interval, ancl the inter-mediate value ~ is therefore also situa-ted near the value for the duration of the preceding half-cycle and is in-verted accordingly. These intermediate values are indi-cated by a solid line at the relevant points in Fig. 3e), the uncorrected values being represented by broken lines.
The solid line in Fig. 4e) therefore represents the cor-rected variation of the values 1~Vk of the durations of the half-cycles of the input signal and even in the cases in which only a few sampled values are situated in each half-cycle and the half-cycle durations vary rapidly they con-stitute a good approximation to the actual variation of the half-cycle durations.
Hereinafter the block diagram is described of a circuit arrangement which determines the corrected values of the half-cycle durations obtained in the manner des-cribed above, from which values the frequency of an input signal is derived, Fig. 5 showing the arrangement for generating the values plotted in Fig. 3c) and Fig. 5 show-ing the block diagram of a circuit arrangement for gene-rating the values which are situated correctly in time and ~hose transitions have been corrected.
The sequence of sampled values corresponding to the input signal to be modulated is applied to the input 2 of the circuit arrangement in Fig. 4. The sampled values are presented in the form of, for example, multi-bit binary words, whose individual bits are processed in pa-rallel, so that the input 2 in fact comprises a number of parallel inputs for -the individual bits of a data word.
Therefore, the connection 1 from the input 2 and the other lines shown in Fig. 4 and Fig. 5 also comprise a number of parallel lines corresponding to the number of bi-ts of each data word, except for the lines carrying the zero-crossing signal and signals derived therefrom~ such as the lines 17 and 19, Via connection 1 input 2 is connected to a re-8~7 PlID 82.071 10 3.6.1983 gister 4 which stores a data word upon each clock signal This clock signal, no-t shown, which is also applied -to other registers, is correlated to the application of -the sampled values to input 2, i.e. each time that a new sampled value is applied a pulse of the clock signal appears.
Connection 1 is also connected to a subtractor 6, whose other input is connected to the output of the re-gister 4 and forms the difference between the two values.
The output of the subtractor stage 6 is connected to a value-generating stage 8 which generates the absolute value o~ the difference. For example for the representation of the sampled values and the binary values derived there-from this requires a specific processing of the applied values. The output of the register is also connected via connection 3 to a value-generating stage 10 of a similar type. It follows from equation (2) that only positive values are permissible ~or the time intervals t and in order to simplify division it is preferred to divide only the absolute values.
This division is per~ormed in the divider stage 12 to which the values generated by the stages 8 and 10 are applied. The multiplication in equation (2) by the duration of the period of the sampled values or the clock signal may be omitted, because this value is a constant scaling factor~
The quotients formed by the divider stage 12 are applied to a correction stage 14 which comprises a read-only memory to which the quotients ~ormed by the divider stage 12 are applied as addresses. ~t each address, which corresponds to a specific value of the time interval tn, the time interval corrected by the error F for a specific average frequency of the input signal in accordance with Figs. 1 and 2 is stored and is output via connection 150 This connection 15 leads to the input of a fur-ther register 20, which stores the value on -the colmection 15 at the end of a zero-crossing signal. This zero-crossing signal shown in Fig. 3b) is generated by an exclusive-OR
.~, PIID ~2.071 11 3.6.l983 logic net-~ork l6, wllich receives the 9~gn bits of the undela~ved sampled value applied to -the input 2 and the delayed samplecl value supplied by the register L~ and which produces an output signal on the line 17 if the two sign bits are different. If during processing of the sampled values in -the stages 6 to 1L~ a delay of more than one clock period occurs, which may happen in particular if the divider stage 12 is a pipeline divider, said zero-crossing signal is applied to a time-delay stage 18, which has a delay time equal to said delay. The zero-crossing signal, which may have been delayed, on the output line 19 corres-ponds in time to the data word applied to the input of the register 20. This register 20 therefore contains a value corresponding to the length of the time interval tn after each end of the zero-crossing sig~nal, i.e~ ~ithout a delay after the second sampled value which follows a zero crossing.
This value is applied to the subtraction input of an arithmetic stage 22, whose other input is connected to the output of the correction circuit 14 and receives a value corresponding to the time interval t in accordance with Fig. 1 upon the appearance of the next zero crossing.
The line 19 l~hich carries the zero-crossing sig-nal is also connected to the reset input of a counter 24, which receives the clock signal, n~t shown, as counting clock signal. The output of the counter 2L~ is connected to an output counting register 26, into ~hich the count is loaded upon each clock signal and consequently upon the appearance of a zero-crossing signal on the line 19. Thus, during each zero-crossing signal the output counting re~
gister 26 contains a value corresponding to the number of sampled values~ incremented by "1", between the directly preceding two zero crossings of the input signals 7 assuming that the counter 24 is set -to "1" by -the zero~crossing sig-nal and the count reached directly before a clock signalis loaded into the register 26 under con-trol of the clock signal edges only. ~lternatively, to set the counter 2L~ to -the initial position "1" at the end of the zero-crossing PI-ID 82.07l 12 3.6.1983 signal, so that the regist0r 26 may be dispensed with or a delay by one clock period is provided in the output line of the ari-thmetic stage 22 as well as the line 19 and the connec-tion 15.
The outputs of the output counting register 26 and the arithmetic stage 22 in the form of a sub-tractor are connected to the inputs of an adder 28, whose output 28 supplies values corresponding to the duration of each half-cycle of the input signal applied to the input 2, which durations do not always appear at the correct in-stant as is illustrated in Fig. 3c). Moreover, it is to be noted that in the present circuit arrangement the stages 6 to 14 and consequently the stages 22 and 28 not only process the values corresponding to two consecutive sampled values on both sides of a ~ero crossing but also all the other sampled values, so that between two correct values which represent the duration of the last half-cycle erroneous or useless values appear on output 29.
However, this is taken into account during the further processing of these values in the circuit arrangement shown in Fig. 5, which ~orms the correctly timed durations of the values as shown in Fig. 3e).
The values appearing on the connection 29 are applied to a delay circuit 40 in Fig. 5, which is construct-ed as a shi~t register comprising the series-connected register stages 402, 404~ 406 and 408. The value appearing on the connection 29 is loaded into the register stage 402 only at the end of the zero-crossing signal on the line 19, whilst the register stages store the value on the input upon each clock signal. Thus, in general several consecutive stages contain the same values, which is necessary for generating the sequence of values with the correct durat-ions as shown in Fig. 3d). The tappings 40l, 403, 405 and 407 of the delay circuit, which are connected to the out-35 puts of the stages 402, L~o4, 406 and 408, are connected to the individual position connections of a ch.ange-over switch 46, which is suitably constructed as an electronic multi-ple~er.
2~
PIID S2.071 13 3.6.1983 The zero-crossing signal on tho line 14 is applied to a delay circuit 42 corresponding to the delay circuit 40, which also comprises a number of series-con-nected stages 422, 424, 426 and 428, which are controlled by the clock signal. Each of these stages contains only one bit in contradistinction to the stages 402 to 408 of the delay circuit 40~ which each contain a data word. The tappings 421, 423, 425 and 427 o~ the delay circui-t 42 are connected to the outputs of the corresponding stages 422 to 428 and thus correspond to the tappings of the delay circuit 42.
The tappings 421 to 427 of the delay circuit 42 are connected to the inputs of a processing circuit 44 in -the form of a read-only memory, the inputs being the address inputs of the memory. Each address of the memory is thus assigned to a specific combination of signals on the tappings 421 to 427, i.e. a speci~ic pattern of -the zero-crossing signal on the line 45, and contains a bit combination which appears on output line 45 and which sets the switch 46 to a well-defined position. As the switch 46 in the present embodiment has ~our positions, two bits on each address of the read-only memory are sufficient in the selection circuit 44, so that the line 45 in fact comprises two lines. The content of -the read-only memory 25 for various signal combinations on the tappings 421 to 427 is specified in the following Table.
~;Zl)~8~7 PTID 82.07l 14 3.6.1983 TABL~
421 _ ~ _ _ _ 45 ~1 _ _ _ In the Table the value "O" on the line 45 means that the switch 46 is connected to the output 4O1, -the other values being assigned to the other outputs in the same sequence. The bit combina-tion yielding the value ~
cannot occur for -the relevant ~requencies or means such a low frequency relative to the clock frequency that the delay circuits 4O and 42 would become too long.
By controlling the switch 46 in accordance with the Table the sequenceo~ values for the durations of the cons0cutive hal~-cycles is obtained with the correct timing~
as shown in Fig. 3d), on the output connection 47 of the switch 46.
The intermediate values o~ Fig. 3e) are generated by means o~ the other elements shown in F~g,5. O~ these elements the input o~ a register 48 is connecte~ -to the tapping 4O7 of the delay circuit 4O and upon each clock signal the value appearing on this tapping is loaded into ~L2~8~7 PIID 82.071 15 3.6.1983 the register 48. 'I`his value is -the value of the period for which the corresponding zero crossin.g signal appears simultaneously on the outpu-t 427 of the delay circuit 42.
I~hen this value has been loaded in-to the register 48 the value of -the next period appears simultaneously on -the connection 47 as a result ~ an appropriate change-over of the switch 46. The output of the register 48 is con-nected to the adding input of a subtractor 50, whose subtract input is connected to -the connection 47, so that I0 at an instant corresponding to the delay caused by the register ~8 the difference between the values of the durations of two consecutive half-cycles appears on the output connection 51. The correspondingly delayed zero-crossi.ng signal is taken from the output 59 of a delay I5 s-tage 60, which is connected to the tapping or output 427 of the delay circuit 42, and th.is signal actua-tes a switch whose function will be explained hereinaf-ter.
The connection 51 is connected to one input of a multiplier 54, whose other input is connected to the switch 58. In the absence of a zero-crossing this switch 58 transfers the value "0" to the multiplier 54, so that the value "0" appears on said output connection. When a zero-crossing signal appears the switch 58 connects the relevant input of the multiplier 54 to the output of a de-lay circuit 52, which has a delay time equal -to tle sum of the delays of the register 48 and the delay circuit 40 and which may for example be constructed as a shift re-gister with a sui-table number of stages. The inpu-t of the delay circuit 52 is connected to the connection 15, which carries the value of the time interval t , which corres-ponds to the value of the half-cycle duration which appears simultaneously on the connection 47 as a result of -the delay produced by the delay circuit 52.
This value is applied to one input of an adder 56, whose other input is connected to the connection 55 of the multiplier 54. Thus, upon a change from the value of the duration of one half cycle to that of the next half-cycle intermediate value be-tween these two values is genera-ted ~2~ 327 PHD 82.071 16 3.o.1983 on lts ou-t~ut connection 57. The corrected values of the individual half-cycle durations thus produced on the out-put conncction 57 are applied to the input of the recipro-cal-~alue generator 30, which suitably comprises a read-only memory, whose address lines are connected to the in-put of the reciprocal-value generator 30 and which trans-fers the data on these addresses to the output 32 of the arrangement. These values appearing on the output 32 represent the sequence of the instantaneous frequencies of the input signal corresponding to the sampled values applied to the input 2, with a constant time delay, which in the present example is mainly caused by the delay cir-cuit 40. The time delay of the delay circuit L~o and conse-quently that of the delay circuit 42 depends on the durat-ion of the longest half-cycle occurring in the input sig-nal, and strictly speaking on the difference bet-reen the smallest and the longest duration of the actually occurr-ng half~cycles of the input signal. The shift in time between the input signal and the output signals on output 32 which represent its instantaneous frequency may increase of in particular the individual arithmetic stages are followed by delay stage, in which case care must be taken that the delays introduced in all the pa-rallel signal paths are the same, in order to compensate for the propagation delays of the signals ln the indivi-dual arithmetic stages, so that said delay can be sub-stantially equal to the period of the clock signal.I-Towever, for the sake of clarity such additional delay stages are not shown.
~uitably, the register stages and delay stages used in the present example and, as the case may be addit-ional stages, are constructed as accumulator registers, which are all operated with the clock signal, i.e. which take up the input value and transfer it -to the output upon each clock pulse. This is particularly favourable if the complete circuit arrangement is constructed as an inte~
grated circuit in dynamic MOS-tech~ology. In order -to 1'~1D 82.071 l7 3.6.1983 enable the registsr stages and delay s~ ges, which must take over a value only when a zero-crossing signal appears, to be constructed in the same way, it is eI'fective to use -the arrangement shown in Fig. 6. This arrangement com-prises a register 64 which is operated with the generalclock signal. 'rhe input of this register 64 is preceded by a switch 62, which under con-trol of the zero-crossing signal via the line 63 connects the input 61 of the stage to the input of the register 64. In the absence of a zero-crossing signal on the line 63 the input of the re-gister 64 is connected to its output 65, so that its con-tents is not changed upon the next clock signals.
Claims (13)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A method of demodulating a frequency-modulated periodic input signal by determining the duration of each half-cycle between every two adjacent zero crossings of the input signal, which signal appears in the form of a sequence of digitized samples taken from the input signal at regular intervals, and by generating the reciprocals of the durations of the half-cycles, characterized in that the duration ? of each half-cycle is derived from the sum of the time intervals T corresponding to the number n of samples between the adjacent zero crossings and the time intervals tn, tm between each zero crossing and the sample which directly precedes it, using the following relation-ship:
?= (T - tn) + nT + tm = tm - tn + (n + 1)T
the time intervals tn and tm each being derived from two consecutive samples an, an+1 and am, am+1 respectively of different signs at the location of the zero crossings, using the following relationship:
?= (T - tn) + nT + tm = tm - tn + (n + 1)T
the time intervals tn and tm each being derived from two consecutive samples an, an+1 and am, am+1 respectively of different signs at the location of the zero crossings, using the following relationship:
2. A method as claimed in Claim 1, characterized in that prior to the determination of the half-cycle duration each time interval tn, tm is corrected by a correction value which depends on the value of said time interval.
3. A method as claimed in Claim 1, characterized in that the duration determined for each half-cycle is stored for a time interval equal to the interval between a number of samples which is 1 higher than the number of samples between the first of the two adjacent zero crossings and the preceding zero crossing.
4. A method as claimed in Claim 3, characterized in that a period ?nk is assigned to the time interval between the consecutive samples an, an+1 at the location of the first one of the two zero crossings which period, depending on the time interval tn between this zero crossing and the preceding sample, is situated between the period ?n-1 determined before this zero crossing and the last period determined ?n in conformity with the following relation-ship:
5. An arrangement for carrying out the method as claimed in Claim 1, which arrangement comprises an input, to which the digital samples are consecutively applied in the rhythm of a clock signal, and an output which supplies data words in the same rhythm, which represent the instan-taneous frequency of the input signal represented by the applied sampled values, characterized by a first delay stage (4) which delays each digital sample applied to the input (2) by one period of the clock signal, an exclusive-OR logic circuit (16), which receives the sign signal of each sampled value which has been delayed and applied to the input (2) of the arrangement and which generates a zero-crossing signal if the two sign signals are different, a first arithmetic stage (6), which is coupled to the input (2) of the arrangement and to the output of the first delay stage (4) and which supplies the difference between two consecutive sampled values, a divider stage (12), whose inputs are coupled to the output of the first arithmetic stage (6) and the output of the delay stage (4) and which forms the quotients of the values supplied by said stages, a second delay stage (20), whose input is coupled to the output of the divider stage (12) and which under control of the zero crossing signal stores the quotients of the sampled values of different signs before a new quotient appears, a counter (24) having an output counting register (26), which receives the clock signal a counting signal and upon the zero-crossing signal loads the count into the output count-ing register (26) and is rest to an initial position, a second arithmetic stage (22, 28), of which a first input is coupled to the output of the divider stage (12), of which a second input is coupled to the output of the second delay stage (20) and of which a third input is coupled to the output of the output counting register (26), and which stage forms the difference between the value applied to the second input and the sum of the values applied to the first and the third input, and a reciprocal-value generator (30), whose input is coupled to the output of the second arith-metic stage (20, 28) and whose output is connected to the output (32) of the arrangement.
6. An arrangement as claimed in Claim 5, character-ized in that the divider stage (12) is followed by a cor-rection circuit (14), which corrects each quotient supplied by the divider stage (12) by a correction value which depends at least on said quotient.
7. An arrangement as claimed in Claim 6, character-ized in that the correction circuit (14) is a read-only memory whose address inputs are coupled to at least the output of the divider stage (12) and whose data outputs are coupled to the input of the second delay stage (20) and one input of the second arithmetic stage (22, 28).
8. An arrangement as claimed in Claim 5, character-ized in that there is provided a first delay stage (40) for delaying a plurality of data words, which circuit comprises a plurality of tappings (401...407), which has its input coupled to the output of the second arithmetic unit (22, 28) and which upon each zero-crossing signal takes over a data word, said tappings (401...407) being connected to the inputs of a multi-position switch (46), there is provided a second delay circuit (42) which has tappings (421...427) corresponding to those of the first delay circuit, which receives the zero-crossing signal and which has its tap-pings (421...427) connected to a processing circuit (44), which depending on the combination of signals on the tap-pings (421...427) generates a control signal which sets the switch (46) to a position assigned to said combination, and the input of the reciprocal-value generator (30) is coupled to the output of the switch (46).
9. An arrangement as claimed in Claim 8, character-ized in that the first and the second delay circuit (40, 42) are constructed as a shift register comprising a plural-ity of stages (402...408; 422...428) which are controlled by the clock signal, each stage in the first delay circuit (40) storing a data word, and the tappings (401...407;
421...427) are the outputs of the individual stages (402...408; 422...428) and the input of the second delay circuit (42).
421...427) are the outputs of the individual stages (402...408; 422...428) and the input of the second delay circuit (42).
10. An arrangement as claimed in Claim 8, character-ized in that the output of the switch (46) is connected to a third arithmetic unit (50), which has another input coupled to the last tapping (407) of the first delay cir-cuit (40) via a third delay stage (48) which delays each data word applied by one clock period, and which supplies the difference between the values applied to the two inputs on its output, the output of the third arithmetic stage (50) is coupled to a first input of a fourth arithmetic stage (54, 56), which has a second input coupled, via a fourth stage (52) whose delay time is equal to the sum of the delay times of the first or the second delay circuit (40, 42) and the third delay stage (48), to the output of the divider stage (12) or the correction circuit (14) following it and which has a third input coupled to the output of the switch (46) and under control of zero-cross-ing signal which has been delayed by the delay of the first or second delay circuit (40, 42) in the clock period before the application of a new value to the output of the switch (46) adds the product of the values applied to the first and the second input of the fourth arithmetic stage (54, 56) and in the other clock periods adds the value "0" to the output signal of the switch (46) and supplies the sum to the reciprocal-value generator (30).
11. An arrangement as claimed in Claim 10, character-ized in that at least there is provided at least one switch (58) which is arranged before the first or the second input of the fourth arithmetic stage (54, 46) and which is con-trolled by the zero-crossing signal, which switch applies a data word of the value "0" to the relevant input in the absence of a zero-crossing signal.
12. An arrangement as claimed in Claim 5, 6 or 7, characterized in that the reciprocal-value generator (30) is a read-only memory, whose address input is connected to the output of the second (22, 28) or the fourth arithmetic stage (54, 56) and whose data output is connected to the output (32) of the arrangement.
13. An arrangement as claimed in Claim 5, 6 or 7, characterized in that the second delay stage (20) and/or the first stage (402) of the first delay circuit (40) com-prise a register stage (64) which is controlled by the clock signal and a second switch (62) which is controlled by the zero-crossing signal, for the storage of values appearing simultaneously with the zero-crossing signal, which switch connects the output of the register stage (64) to its input in the absence of a zero-crossing signal.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DEP3223345.0 | 1982-06-23 | ||
| DE19823223345 DE3223345A1 (en) | 1982-06-23 | 1982-06-23 | METHOD AND ARRANGEMENT FOR DEMODULATING A FREQUENCY-MODULATED INPUT SIGNAL |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1204827A true CA1204827A (en) | 1986-05-20 |
Family
ID=6166595
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000431052A Expired CA1204827A (en) | 1982-06-23 | 1983-06-23 | Method of and arrangement for demodulating a frequency-modulated input signal |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US4570126A (en) |
| EP (1) | EP0099142B1 (en) |
| JP (1) | JPS5937714A (en) |
| AT (1) | ATE56325T1 (en) |
| CA (1) | CA1204827A (en) |
| DE (2) | DE3223345A1 (en) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3373392D1 (en) * | 1983-12-24 | 1987-10-08 | Itt Ind Gmbh Deutsche | A digital demodulator for digitized frequency-modulated signals |
| BE901232A (en) * | 1984-12-07 | 1985-06-07 | Itt Ind Belgium | RADIOCOMMUNICATION SYSTEM. |
| DE3579919D1 (en) * | 1985-07-27 | 1990-10-31 | Itt Ind Gmbh Deutsche | FREQUENCY DEMODULATION CIRCUIT WITH ZERO CONTINUOUS PAYMENT. |
| US4777487A (en) * | 1986-07-30 | 1988-10-11 | The University Of Toronto Innovations Foundation | Deterministic access protocol local area network |
| USRE33650E (en) * | 1986-07-30 | 1991-07-30 | University Of Toronto Innovations Foundation | Deterministic access protocol local area network |
| US5067140A (en) * | 1989-08-16 | 1991-11-19 | Titan Linkabit Corporation | Conversion of analog signal into i and q digital signals with enhanced image rejection |
| US5283815A (en) * | 1991-05-21 | 1994-02-01 | General Electric Company | Tangental type differential detector for pulse shaped PI/4 shifted differentially encoded quadrature phase shift keying |
| US5202901A (en) * | 1991-05-21 | 1993-04-13 | General Electric Company | Digital discriminator for pulse shaped π/4 shifted differentially encoded quadrature phase shift keying |
| JPH08500942A (en) * | 1991-11-20 | 1996-01-30 | ヌマ テクノロジーズ インコーポレイテッド | Digital demodulator |
| US5239273A (en) * | 1991-11-20 | 1993-08-24 | Numa Technologies, Inc. | Digital demodualtor using signal processor to evaluate period measurements |
| US6810112B1 (en) * | 1999-10-06 | 2004-10-26 | Fujitsu Limited | Method and apparatus for testing an information notification service |
| US7339985B2 (en) * | 2003-01-08 | 2008-03-04 | National Instruments Corporation | Zero crossing method of symbol rate and timing estimation |
| US7298423B1 (en) * | 2004-11-29 | 2007-11-20 | Cirrus Logic, Inc. | Time based digital FM demodulator |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| IT1037127B (en) * | 1975-03-18 | 1979-11-10 | Sits Soc It Telecom Siemens | FREQUENCY MODULATED WAVES DEMODULATOR |
| DE2809418C2 (en) * | 1978-03-04 | 1989-08-31 | ANT Nachrichtentechnik GmbH, 7150 Backnang | Method for demodulating a phase-shift-free, multiple frequency modulated (FSK) signal |
| IT1119943B (en) * | 1979-11-05 | 1986-03-19 | Cselt Centro Studi Lab Telecom | RECEIVER OF MUTLIFREQUENCY KEYBOARD SIGNALS CODED IN PCM |
| JPS56140706A (en) * | 1980-04-04 | 1981-11-04 | Nippon Telegr & Teleph Corp <Ntt> | Fm demodulator |
| DE3027053A1 (en) * | 1980-07-17 | 1982-02-11 | Robert Bosch Gmbh, 7000 Stuttgart | METHOD FOR THE CORRECTIVE CORRECTION OF DIGITAL SWITCHING SIGNALS |
| CA1137632A (en) * | 1980-09-25 | 1982-12-14 | Claude J.J. Champagne | Pulse code demodulator for frequency shift keyed data |
| US4412339A (en) * | 1981-09-24 | 1983-10-25 | Advanced Micro Devices, Inc. | Zero-crossing interpolator to reduce isochronous distortion in a digital FSK modem |
-
1982
- 1982-06-23 DE DE19823223345 patent/DE3223345A1/en not_active Withdrawn
-
1983
- 1983-06-20 AT AT83200894T patent/ATE56325T1/en not_active IP Right Cessation
- 1983-06-20 EP EP83200894A patent/EP0099142B1/en not_active Expired - Lifetime
- 1983-06-20 DE DE8383200894T patent/DE3381862D1/en not_active Expired - Lifetime
- 1983-06-23 CA CA000431052A patent/CA1204827A/en not_active Expired
- 1983-06-23 JP JP58113598A patent/JPS5937714A/en active Granted
- 1983-06-23 US US06/507,202 patent/US4570126A/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| DE3223345A1 (en) | 1984-01-05 |
| EP0099142A3 (en) | 1985-08-21 |
| JPS5937714A (en) | 1984-03-01 |
| EP0099142B1 (en) | 1990-09-05 |
| ATE56325T1 (en) | 1990-09-15 |
| EP0099142A2 (en) | 1984-01-25 |
| JPH0576203B2 (en) | 1993-10-22 |
| US4570126A (en) | 1986-02-11 |
| DE3381862D1 (en) | 1990-10-11 |
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