CA1209716A - Semiconductor component and method of manufacture - Google Patents

Semiconductor component and method of manufacture

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Publication number
CA1209716A
CA1209716A CA000451170A CA451170A CA1209716A CA 1209716 A CA1209716 A CA 1209716A CA 000451170 A CA000451170 A CA 000451170A CA 451170 A CA451170 A CA 451170A CA 1209716 A CA1209716 A CA 1209716A
Authority
CA
Canada
Prior art keywords
contact
metallised
raised
electronic component
component according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA000451170A
Other languages
French (fr)
Inventor
Ricardo S. Sussmann
Robert C. Goodfellow
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Plessey Overseas Ltd
Lumentum Technology UK Ltd
Original Assignee
Plessey Overseas Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Plessey Overseas Ltd filed Critical Plessey Overseas Ltd
Application granted granted Critical
Publication of CA1209716A publication Critical patent/CA1209716A/en
Expired legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/58—Optical field-shaping elements
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4204—Packages, e.g. shape, construction, internal or external details the coupling comprising intermediate optical elements, e.g. lenses, holograms
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4219—Mechanical fixtures for holding or positioning the elements relative to each other in the couplings; Alignment methods for the elements, e.g. measuring or observing methods especially used therefor
    • G02B6/4228—Passive alignment, i.e. without a detection of the degree of coupling or the position of the elements
    • G02B6/423—Passive alignment, i.e. without a detection of the degree of coupling or the position of the elements using guiding surfaces for the alignment
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4249—Packages, e.g. shape, construction, internal or external details comprising arrays of active devices and fibres
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0203—Containers; Encapsulations, e.g. encapsulation of photodiodes
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4219—Mechanical fixtures for holding or positioning the elements relative to each other in the couplings; Alignment methods for the elements, e.g. measuring or observing methods especially used therefor
    • G02B6/4236—Fixing or mounting methods of the aligned elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01049—Indium [In]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01056—Barium [Ba]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10158—Shape being other than a cuboid at the passive surface
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
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    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12043—Photo diode
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
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    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
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    • H01L2924/30107—Inductance

Abstract

ABSTRACT A Semiconductor Component and Method of Manufacture An electronic component comprises a mounting substrate (13) having a surface provided with a plurality of spaced contact pads (15) and a semiconductor chip (10) having at least one active element (11) and a surface provided with metallised contact regions (14). The metallised contact regions (14) are superimposed on and electrically conductively bonded to a different one of the mounting substrate contact pads (15). The method comprises the forming on a surface of a semiconductor chip at least one active device having a raised metallised contact region and at least one additional raised contact region spaced from the active device contact region. A metallised contact pad for each of the raised contact regions is provided on a mounting substrate their spacing corresponding to the spacing of the raised contact regions. The contact pad for each active device is arranged to form part of a conductor connection. The chip is positioned on the mounting substrate with the associated raised contact regions and contact pads in mutual contact and they are electrically conductively bonded together.

Description

" ~2~71i~

A SF.MICO~lDUCTOR CO~qPOlilE~T AND METHOD OF ~ANUFACTURE
The invention relates to a semiconductor component mounted on a substrate and to a me~hod of manufacturing such a component.
This invention has resulted from a study of the problems involved in the manufacture of substrate entrance detectors. Such detectors are normally mounted on relatively complex packages with an entrance hole for incident illumination. Wire bonding is employed to effect connection to the active mesas. Wire bonding is a common source of device degredation due to both the introduction of additional parasitic capacitances and conductances and enhanced leakage currents. Also yield is low with wire bondin~ due to high localised pressures involved. It is also difficult to wire bond to mesas smaller than SO micron diameter imposing restrictions to the reduction in capacitance possible to achieve.
The present invention seeks to provide a construction in which wire bonding to the chip is avoided which is suitable for fabrication of substrate entrance detsctors but which has application to other semiconductor devices.
According to one aspect vf the invention there is provided, an electronic component comprising a mounting substrate having a surface provided with a plurality of spaced contact pads; and a semiconductor chip having at least one active element in the orm of a photodiode on a substrate of light transmissive semiconductor materiai, said active element having a metallised contact re~ion, and a plurali~y of projectin~ metallised contact regions, wherein said metallised contact reKion of said active element is electrically conductively bonded to one of said spaced contact pads of said mounting substrate, and each one of said plurality of projecting metallised contact regions is electrically conductively bonded to a different one of said spaced contact pads of said mounting substrate.

~1 PAT 10072-1 - l -` , ~X~7~6 By making connection between the chip and mounting substrate by bonding, small area active regions can be employed thereby permitting a reduction in capacitance of the device itself and also obviating the parasitic capacitance and inductance introduced by wire bonding~
The contact pads and associated contact regions may be electrically bonded by thermal compression bonding or by soldering.
A group of the projecting metallised contact regions and associated electrically bonded contact pads may be distributed around the or each active element to support the chip on the substrate. Alternatively, for each ac~ive element there may be provided a metallised contact region and associated electrically bonded contact pad which extends at least partially around the element to support the chip on the substrate.
The contact pad(s) associated with an active device may form part of an extended conductor connection. The extended conductor connection may extend to an enlarged connection pad or pads. The mounting substrate may be an integrated circuit with the active element(s) connected into the circuit via the electrical bonding.
The electrical contact regions may be provided on mesas on the chip. A metallised contact region may be provided on the outer face of the semiconductor chip.
The active device may be in the form of a photodiode, e.g. a PIN diode, or a light emitting diode, formed on a æ~7 ~

substrate of light transmissive semiconductor material. In a particularly advantageous application the diode is a PI~ diode and the mounting substrate is part of an integrated circuit including for instance a field effect transistor to which the diode is connected via said electrical bonding. The device may be provided with a cavity in its substrate face opposite the diode junction for receipt of a microlens or optical fibre. A contact pad may be provided on the substrate face of the chip which pad surrounds the cavity.
According to another aspect of the invention there is provided, a method of manufacturing a semiconductor device, comprising formin~ on a surface of a semiconductor chip substrate at least one active device in the form of a photodiode on a substrate of light transmissive semiconductor material, said active device having a raised metallised contact region, formin~ a plurality of additional raised metallised contact re~ions spaced from said active device contact re~ion, formin~ on a surface of an insulating or semi-insulating mounting substrate a metallised contact pad for each of said raised contacts regions of spacing correspondin~ to the spacin& of said raised contact regions, the contact pad for each said active device formin~ part of a conductor connection, positioning the chip on the mounting subs~rate with the associated raised contact re~ions and contact pads in mutual contact and electrically conductively bondin~ the raised con~act regions to the contact pads.
In the constructional method, there may be provided, for each active device, an additional raised metallised , . ~

3~

contact region and associated pad shaped to extend at least partially around the element to reduce the load on the active device during bonding and provide mechanical stability and support. Alternatively, for each active device, a group of said additional raised metallised contact regions and associated pads are provided distributed around the active element to reduce the load on the active device during bonding and provide mechanical stability and support.
In order that the invention and its various other preferred features may be understood more easily, embodiments thereof will now be described, by way of example only, with reference to the drawings, in which:~
Figure 1 is a cross sectional view of a substrate entrance detector constructed in accordance with the invention;
Figure 2 is a plan view of the mesa side of a semi-conductor chip forming part of the device of Figure l;
Figure 3 is a plan view of the opposite side of the - 20 semicondu~tor chip of Figure 2, and Figure 4 is a cross sectional view taken on the line x-x of Figure l showing in dotted lines the position of other elements.
Referring now to Figures 1 to 4 there is shown an indium phosphide semiconductor chip substrate 10 onto which there is grown an active device in the form of a PIN

``` ` ~ g6~7~

detector 11. The detector is produced as a diffused or implanted mesa structure on either a ternary ~GaInAs) or quaternary (GaInAsP) compound grown lattice matched onto the chip substrate by for example liquid phase epitaxy.
Additional mesas 12 are formed which may be identical to the central active mesa or may not have been diffused or implanted so that there is no diode junction at these mesas.
The additional mesas 12 are distributed around the pin detector 11 and form an array of supporting legs which provide mechanical stability and support of the chip when mounted on a mounting substrate or carrier block 13. Each of the mesas is provided with a gold metallised contact region 14.
The carrier block 13 can be formed from any insulating material e.g. alumina, ceramics or silica or from a semi-insulating material e.g. gallium arsenide or indium phosphide. The carrier block 13 is provided with gold plated contact pads 15, as can be seen in greater detail in Figure 4, which are spaced to correspond with the positions of the mesas on the chip 10 so that the chip can be positioned on the block 13 with the metallised contact regions 14 in contact with the contact pads 15. Electrical bonding of the r0gions 14 to th~ pads 15 is then effected b~
thermal compression bonding and the additional mesas 12 serve to reduce the load on the active mesa 11 during the bonding operation.
The pad 15 for the detector 11 is extended to one side of the chip where an enlarged region 15a is provided for ~6--lead connection. The pads 15 for the other mesas may also be similarly extended as shown in chain lines in Figure 4 to provlde connection to the chip substrate. If the mesas 12 are provided with a diode, a connection to the substrate may be optionally made by "punching through" the diode i.e. by short circuiting the diode by means of an overcurrent.
The substrate of the chip 10 illustrated is formed from a light transmissive ~emiconductor material and on the opposite side to the mesas it is provided with an etched well or recess 16 which reduces the thickness and improves light transmission. The recess 16 is in alignment with the detector 11 and enables insertion of a microlens 17 for focusing light onto the detector to increase the light collecting area, or a monomode or lens-tipped multimode optical fibre. Such an arrangement overcomes the disadvantage of existing techniques where an optical fibre in the form of a "pigtail" is permanently attached to the device mounting and which introduces di~ficulties in integrating the detector into a hybrid package. Also the carrier package can be designed so that parasitic capacitances are only a small fraction of the capacitance of the detector. A gold contact pad 18 is formed on the same side of the chip as the recess 16 and surrounds the recess.
This pad permits direct connection to the substrate by wire bonding if required.

A particularly advantageous technique that we have devised to provide a thick gold metallisation on the mesa~
of the chip is as follows:-1. Provide a thin coating of gold over the entire surface of the chip .
2. Deposite a ring of a delectric material of 2000 Angstrom thickness, e.g. silox, silicon nitride, polyamide, silicon monoxide, to define the required mesa and metal contact dimension.
3. Apply a photoresist and provide a window to expose the inside of the ring.
4. Gold plate to 8 - 10 micron thickness to provide a projecting contact.
5. Dissolve the photoresist.
6. Apply a gold etch for long enough to remove the thin gold coating but to leave the projecting gold contact substantially intact.
7. Etch the chip to leave a mesa defined by the exterior of the dielectric ring.
- 20 An alternative is to deposit the ring onto the chip substrate prior to depositing gold. A similar procedure can be employed using a planar structure with windows for the contacts being provided after production of the active devices by for example diffusion.
In the embodiment described a group of additional mesas 12 are provided around the detector 10. For some applications a slngle additional mesa may suffice and it will be appreciated that different configurations or patterns of mesa may be employed to suit particular purposes. Examples of suitable patterns are four supporting mesas disposed at the corners of a square configuration with the active mesa disposed centrally within the square or three supporting mesas disposed at the corners of an equilateral triangle with the active mesa disposed centrally within the triangle or where the active mesa is disposed at the centre of a circular pattern of supporting mesas.
Examples of suitable configurations of mesa are a single horseshoe shaped pedestal extending part way round the active mesa.
Instead of effecting electrical bonding by thermal compression bonding, the connection may be effected by soldering e.g. employing a low melting point solder and exposing the chip, when positioned on the substrate, to a temperature sufficient to melt the solder.
Although the embodiment described is a diode detector, a light emitting diode could be provided using a similar construction. The concept of the invention is applicable not only to optical devices but to any semiconductor chip devices where direct bonding enables small area devices or small contact areas to be connected onto a support structure.
Although the embodiment described relates to the provision of a chip on a support block for subsequent wiring to for example a header, the support block 13 may comprise an integrated circuit structure in which case the active device or a number of active devices on the chip 10 are directly electrically bonded to the integrated circuit to form a hybrid circuit. Such an arrangement is considered to fall within the scope of this invention. A particular application of this type is in the manufacture of hybrid PIN
- FET circuits for use in receiver circuits. In this case a pin diode would be formed on the chip 10 and an integrated amplifier on the substrate 13. Other applications are possible in integrated optical/electrical devices, avalanche detectors and in transferred electron devices.

Claims (18)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. An electronic component comprising:
a mounting substrate having a surface provided with a plurality of spaced contact pads; and a semiconductor chip having at least one active element in the form of a photodiode on a substrate of light transmissive semiconductor material, said active element having a metallised contact region, and a plurality of projecting metallised contact regions, wherein said metallised contact region of said active element is electrically conductively bonded to one of said spaced contact pads of said mounting substrate, and each one of said plurality of projecting metallised contact regions is electrically conductively bonded to a different one of said spaced contact pads of said mounting substrate.
2. An electronic component according to claim 1, wherein said metallised contact region of said active element and said plurality of projecting metallised contact regions are electrically conductively bonded to said spaced contact pads by thermal compression bonding.
3. An electronic component according to claim 1, wherein said metallised contact region of said active element and said plurality of projecting metallised contact regions are electrically conductively bonded to said spaced contact pads by a solder.
4. An electronic component according to claim 1, wherein said one of said spaced contacts pads to which said metallised contact region of said active element is electrically conductively bonded forms part of an extended conductor connection.
5. An electronic component according to claim 4, wherein said extended conductor connection extends to an enlarged connection pad.
6. An electronic component according to claim 1, wherein said mounting substrate is an integrated circuit.
7. An electronic component according to claim 1, wherein said projecting metallised contact regions are provided on mesas on said semiconductor chip.
8. An electronic component according to claim 1, wherein said semiconductor chip has a metallised contact region on its outer face.
9. An electronic component according to claim 1, wherein said photodiode is a PIN diode and said mounting substrate is an integrated circuit to which said PIN diode is connected thereby to provide an optical receiver equivalent to a PIN receiver.
10. An electronic component according to claim 1 or claim 9, wherein said substrate of said semiconductor chip is provided with a cavity in its outer face opposite said photodiode for receipt of a microlens or optical fibre.
11. An electronic component according to claim 10, wherein a contact pad is provided on said outer face of said semiconductor chip, which contact pad surrounds said cavity.
12. A method of manufacturing a semiconductor device, comprising forming on a surface of a semiconductor chip substrate at least one active device in the form of a photodiode on a substrate of light transmissive semiconductor material, said active device having a raised metallised contact region, forming a plurality of additional raised metallised contact regions spaced from said active device contact region, forming on a surface of an insulating or semi-insulating mounting substrate a metallised contact pad for each of said raised contacts regions of spacing corresponding to the spacing of said raised contact regions, the contact pad for each said active device forming part of a conductor connection, positioning the chip on the mounting substrate with the associated raised contact regions and contact pads in mutual contact and electrically conductively bonding the raised contact regions to the contact pads.
13. A method as claimed in claim 12, wherein the electrically conductive bonding is effected by thermal compression bonding.
14. A method as claimed in claim 12, wherein the electrically conductive bonding is effected by soldering.
15. A method as claimed in claim 12, claim 13 or claim 14, wherein, for each active device, an additional raised metallised contact region and associated pad are provided shaped to extend at least partially around the element to reduce the load on the active device during bonding and provide mechanical stability and support.
16. A method as claimed in claim 12, wherein each active device a group of said additional raised metallised contact regions and associated pads are provided distributed around the active element to reduce the load on the active device during bonding and provide mechanical stability and support.
17. A method as claimed in claim 12, wherein the raised metallised contact regions are formed on individual mesas on the chip.
18. A method as claimed in claim 12, wherein at least one of said additional raised metallised contact regions is provided on a diode structure formed in the chip and connection to the substrate is completed by punch through burning out the diode.
CA000451170A 1983-04-05 1984-04-03 Semiconductor component and method of manufacture Expired CA1209716A (en)

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GB08309131A GB2137807B (en) 1983-04-05 1983-04-05 A semiconductor component and method of manufacture
GB8309131 1983-04-05

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JP (1) JPS6024048A (en)
AT (1) ATE54776T1 (en)
CA (1) CA1209716A (en)
DE (1) DE3482719D1 (en)
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GB2137807B (en) 1987-08-12
EP0121402A2 (en) 1984-10-10
DE3482719D1 (en) 1990-08-23
US4752816A (en) 1988-06-21
GB2137807A (en) 1984-10-10
JPS6024048A (en) 1985-02-06
ATE54776T1 (en) 1990-08-15
EP0121402B1 (en) 1990-07-18
EP0121402A3 (en) 1986-12-17

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