CA1210159A - Multiple redundant clock system comprising a number of mutually synchronizing clocks, and clock circuit for use in such a clock system - Google Patents
Multiple redundant clock system comprising a number of mutually synchronizing clocks, and clock circuit for use in such a clock systemInfo
- Publication number
- CA1210159A CA1210159A CA000438592A CA438592A CA1210159A CA 1210159 A CA1210159 A CA 1210159A CA 000438592 A CA000438592 A CA 000438592A CA 438592 A CA438592 A CA 438592A CA 1210159 A CA1210159 A CA 1210159A
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- 238000012937 correction Methods 0.000 claims description 3
- 238000001514 detection method Methods 0.000 claims description 3
- 238000005065 mining Methods 0.000 claims description 3
- 230000009849 deactivation Effects 0.000 claims description 2
- 230000000306 recurrent effect Effects 0.000 claims description 2
- 230000000875 corresponding effect Effects 0.000 description 4
- 230000014509 gene expression Effects 0.000 description 4
- 239000000306 component Substances 0.000 description 2
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- DNXHEGUUPJUMQT-UHFFFAOYSA-N (+)-estrone Natural products OC1=CC=C2C3CCC(C)(C(CC4)=O)C4C3CCC2=C1 DNXHEGUUPJUMQT-UHFFFAOYSA-N 0.000 description 1
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1604—Error detection or correction of the data by redundancy in hardware where the fault affects the clock signals of a processing unit and the redundancy is at or within the level of clock signal generation hardware
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
- G06F11/187—Voting techniques
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
Abstract
ABSTRACT:
"Multiple redundant clock system comprising a number of mutually syn-chronizing clocks, and clock circuit for use in such a clock system".
A multiple redundant clock system comprises at least n=4 clocks and is self-synchronizing and fault tolerant against the failure of at the most ?(n-1) clocks. Each clock comprises an oscillator cir-cuit which activates a dividing circuit at the end of each period in order to form its own clock signal on the output of the dividing circuit.
Each clock furthermore comprises a deviation-determining device which compares the own clock signal with the clock signals originating from the other clocks in the system. When an excessively large number of the other clock signals deviate during the first half of the (own) period, the own oscillator circuit is decelerated. When an excessively large num-ber of the other clocks signals deviate during the second half of the own period, the own oscillator circuit is accelerated.
"Multiple redundant clock system comprising a number of mutually syn-chronizing clocks, and clock circuit for use in such a clock system".
A multiple redundant clock system comprises at least n=4 clocks and is self-synchronizing and fault tolerant against the failure of at the most ?(n-1) clocks. Each clock comprises an oscillator cir-cuit which activates a dividing circuit at the end of each period in order to form its own clock signal on the output of the dividing circuit.
Each clock furthermore comprises a deviation-determining device which compares the own clock signal with the clock signals originating from the other clocks in the system. When an excessively large number of the other clock signals deviate during the first half of the (own) period, the own oscillator circuit is decelerated. When an excessively large num-ber of the other clocks signals deviate during the second half of the own period, the own oscillator circuit is accelerated.
Description
~2~
The invention relates to a multiple redundant clock sys-tem, comprising a number of n ~4 mutually synchronizing clocks, each of which comprises a respective clock output for a bivalent clock signal, said system comprising an interconnection network for applying the clock signal of each clock to each of the other clocks, each clock comprising an oscillator circuit and a deviation-determining device to an input of which the oscillator circuit is connected via an interconnection and which comprises further in-puts for receiving the clock signals of the other clocks. A clock system of this kind is known from US-PS 4,239,982 in the name of T. Basil Smith et al. Such a clock system is used, for example, in a digital device which is composed of a number of stations which must operate in synchronism, for example in a multiprocessor com-puter system in which each processor comprises its own clock. The number n of processors provides a system redundancy so that a cor-rectly operating system is obtained even with a smaller number of correctly operating processors, for example ~n-l~. There are also other applications for such a clock s~stem. It is the object of the known system to indicate a desynchronized state of one of the clocks, while the other clocks of the system can continue in a mutually synchronized state.
It is an object of the invention to provide a self-synchronizing multiple clock system which is composed of simple clocks and in which a feedback is formed between the actual state of the oscillator circuit and the deviation-determining device in order to render the clock system self-synchronizing as well as fault tolerant: the clock system first of all attempts to maintain a mutually synchronized state between a majority of the clocks.
~;
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~2~01~;9 -la-The object is achieved in that in accorda.nce with the invention each clock comprises, as a par-t of said interconnection, a two-state dividing circuit which is switched over~ each time under the control of a period signal of the local oscillator circuit, at a recurrent series of switching points and which continuously outputs the associated signal value of its "own" clock ,~ ,.. ....
i%~C~lS9
The invention relates to a multiple redundant clock sys-tem, comprising a number of n ~4 mutually synchronizing clocks, each of which comprises a respective clock output for a bivalent clock signal, said system comprising an interconnection network for applying the clock signal of each clock to each of the other clocks, each clock comprising an oscillator circuit and a deviation-determining device to an input of which the oscillator circuit is connected via an interconnection and which comprises further in-puts for receiving the clock signals of the other clocks. A clock system of this kind is known from US-PS 4,239,982 in the name of T. Basil Smith et al. Such a clock system is used, for example, in a digital device which is composed of a number of stations which must operate in synchronism, for example in a multiprocessor com-puter system in which each processor comprises its own clock. The number n of processors provides a system redundancy so that a cor-rectly operating system is obtained even with a smaller number of correctly operating processors, for example ~n-l~. There are also other applications for such a clock s~stem. It is the object of the known system to indicate a desynchronized state of one of the clocks, while the other clocks of the system can continue in a mutually synchronized state.
It is an object of the invention to provide a self-synchronizing multiple clock system which is composed of simple clocks and in which a feedback is formed between the actual state of the oscillator circuit and the deviation-determining device in order to render the clock system self-synchronizing as well as fault tolerant: the clock system first of all attempts to maintain a mutually synchronized state between a majority of the clocks.
~;
~ ,, .
~2~01~;9 -la-The object is achieved in that in accorda.nce with the invention each clock comprises, as a par-t of said interconnection, a two-state dividing circuit which is switched over~ each time under the control of a period signal of the local oscillator circuit, at a recurrent series of switching points and which continuously outputs the associated signal value of its "own" clock ,~ ,.. ....
i%~C~lS9
-2-signal on its output in each state, the deviation-determining device comprising a comparator for comparing the number of clock signals received from other clocks and deviating from its own clock signal with a permissible upper limit which at the most equals the largest integer that is not greater than ~(n-11 and to generate, in the case of a larger number, a deceler-ation signal in a first period which directly succeeds a switch-over point but an acceleration signal in a second period which directly preceeds a switch-over point in order to readjust the frequency of the oscillator circuit. Isochronously is to be understood to mean herein the relation pattern in which charac-teristic phenomena of a first element ~so in this case -the state changes of the dividing circuit) always occur at corres-ponding points of the cycle of the second element (so in this case the oscillator circuit). Therefore, the dividing circuit can be set at the same point of the oscillator circuit cycle, but possibly also at another point. The durations of the first and the second periods may be the same, but they may also be dif-ferent. Thus, for a value n=4 the pexmissible upper limit is l;
for a value n=5, the upper limit equals l or 2, and so on for higher values of n. The system is also fault tolerant in many cases: a given number of clocks may be completely out of step and will be ignored. The specific differences with respect to and the advantages ovex the present state of the art will be described hereinafter.
Preferably, said upper limit at the most equals the largest integer that is not greater than l/3(n-l). For n=4, s~
-2a-the permissible upper limit then equals 1, likewise for n=5 and 6. For n=7, the permissible upper limit then equals 2. It has been found that this more severe requirement offers protec-tion against practically all feasible fault configurations which are limited to a number of clock circuits which does not ecceed the upper limit, including inter alia interruptions in the output line for the clock signal of the faulty clock.
Preferably, the end of a said firs-t period is consecu-tive with the beginning of a said second period. This results in a simple organization and quick synchronization (by way of a large "pull-in" range for the synchronization).
Preferably, between a said first period and a directly subsequent second period there is situated a third period, there being provided an error detection circuit in a clock for supply-ing an error signal in said third period when said upper limit is exceeded due to another clock. After termination of switch-on phenomena, such an error signal -` ~21~
P~ 10.470 3 19.9.1983 clearly indicates that the relevant clock circuit is out of step so that more likely it is faulty.
Preferably, -there is provided a deactivation control element for deactivating, under the control of said error signal, the clock tnus deemed faulty. A faulty clock circuit can thus ~e deactivated, subject to the condition that said switch-on phenomena have terminated.
Preferably, said dividing circuit is a two-divider which is controlled in synchronism with the pericd of the oscillator circuit. This offers a simple implementation.
rrhe oscillator circuit in a preferred embodim~ent comprises a circuit loop which includes an EXCLUSIVE-OR-gate, a low-pass filter and an oscillator, the dividing circuit ~eing connected to an output of the oscillator while the output of the deviation-determining device is con-nected to an input of the EXCLUSIVE-OR-gate in order to apply thereto, when said upper limit is exceeded, a first logic value during said first period and a second logic value during said second period, but otherwise the second logic value and the first logic value, respectively. Thus, a simple implementation is achieved, allowing the use of standard compo-nents.
The oscillator circuit in another preferred ernbcdi~ent compri-ses an oscillator and a counter which is fed by the oscillator and which counts from a start count state to a maximum count state, there also ~eing provided a logic circuit which forms, under the control of an output signal of the deviation-determining device, a hold signal in the case of a low count but an acceleration signal in the case of a high count. This is a completely digital solution, so that an arbitrary ad-justment accuracy can be achieved.
Preferably, said acceleration signal emulates a mc~ximum count signal. This results in accelerated self-synchronization.
Preferably, for n=4 the cleviation-determining device comprises a majority decision device for the clock signals of the other clocks and a comparison circuit which receives an output signal of the majority decision device and its own clcck signal. The foregoing results in a sunple implementation and, moreover, -this number of clocks already suf-fices in many cases.
The inven-tion also relates to a clock circui-t which is intended for use in a multiple redundant clock system of the kind descri~ed and which comprises (n-1~ external connections for receiving externally for-~2~1S9 med clock signals, and which also comprises an oscillator sir-cuit, a dividing circuit and a deviation-de-termining device of the kind described. Such a clock circuit forms an attractive module in which n and said upper limit may be adjustable, if desired.
The invention also relates to a multiprocessor computer system eomprising n computer modules, eaeh eomputer module eompri-sing a eloek so that the n clocks together constitute a multiple redundant clock system of the kind described, each computer module also comprising a processor module for the processing of a data word, a reducing encoder which is connected to the proces-sor module in order to form a code symbol from the data word so that the n code symbols formed from a data word form a code word of a symbol error correction code, a memory moduIe which is con-nected to the reducing encoder in order to store a code symbol per data word, and a data word reeonstruetion module, the data word reeonstruetion modules of all eomputer modules being eonnected to the relevant eomputer modules by way of a seeond intereonnec-tion network in order to reeeive the relevant code symbols of a eode word and to reeonstruet therefrom a data word for presenta-tion to the processor module of the relevant computer module, thevarious data proeessing operations being synehronized by the eloek system. A computer system of this kind, without the present clock system, has already been partly disclosed in Canadian Patent No.
1,163,373 in the name of Applieant. The clock system is thus also rendered redundant, so that the system is eapable of dealing with a failure of the eloek seetion as well as with a failure of the data processing section of a number of modules in as far as this .~
S~9 number does not ex~eed the upper limit of the fault tolerance capacity.
Brief description of the figures The invention will be described in detail hereinafter with reference to some Eigures.
Figure 1 is a simple block diagram of a multiprocessor computer system comprising a multiple redundant clock system.
Figure 2 shows a clock system in accordance with the invention.
Figures 3 and 4 show the logic expressions for figure 2.
Elgures 5 and 6 show two embodiments of a clock circuit.
Figure 7 illustrates the content of a read-only memory.
Description of a multiprocessor computer system Figure 1 is a simple block diagram of a multiprocessor computer system comprising a multiple redundant clock system.
The computer system comprises four computer modules. Each computer module comprises a processor module, its own clock, and a data word reconstruction module. There are four processor modules 200-206. Each clock 220-226 applies clock signals to the associated processor. Each clock also applies clock signals to all other clocks, and hence indirectly to the other processor modules. Each processor module outputs its output data to all four data word reconstruction modules 210-216 which together form a data word reconstruction device. In each data word reconstruction module given data errors can b~ detected and/or corrected: the correct data is applied to the associated processor in which data proces-sing can take place. A computer system divided into a number of -5a-modules has already been disclosed in Canadian Patent No. 1,163,373;
therein, a code word consisting of code symbols is formed on the basis of a data word consisting of data symbols. After encoding, each computer module processes only a part of the code word, for example one code symbol. This operation concerns, for example, memory storage, followed by a read operation and regeneration of the code symbol. In order to reconstruct the entire data woxd for an arithmetic operation, all code symbols are applied to all computer modules. It has been found that the operation can be correctly performed even in the case of complete failure of, for example, one computer module. Such a system can be synchronized by a master clock. In the set-up shown in figure 1, the various operations in the various computer modules are synchronized by the clock system consisting of the clocks 220-226. The operation of the data word reconstruction modules can also be synchronized in this manner, bu-t this is not shown. Should one of the computer modules, for example the module comprising the blocks 202-212, 222, become defective (data or clock), the other three modules can continue to operate in the usual manner. In accordance with Canadian Patent No. 1,163,373, the system requires only a two-fold storage capacity in the memory for a four-Eold processing capacity in the arithmetic and logic (ALU) unit in comparison with a single-non-redundant processor (in the terminology used, the processor thus also comprises the foreground memory; the back-ground memory and Eurther peripheral apparatus are not considered herein). Similarly, another multiple ~01~
data processing system (for example, a communication system, a word processing system and the like) can also comprise such a multiple redundant clock system.
Preferred embodiments of the invention Figure 2 shows a self-synchronizing clock system for four single clocks in accordance with the invention. The number of clocks connected may be arbitrarily large and the degree of redundancy may also be increased. The first single clock is shown in detail in block 122. This clock is driven by an inter-nal oscillator haviny a frequency which is, for example, from20 to 100 times higher than the required operating frequency:
the latter frequency is formed by the counter 108 which acts as a frequency divider in conjunction with element 116. The oscil-lator frequency is not subject to very severe constraints.
The oscillator may be, for example, an oscillator which is adjus-ted by means of an external RC-network. This oscillator alter-nately supplies an odd clock pulse 01 and an even clock pulse 02, thus synchronizing the operation of the logic circuits 106 and 114 and the latch circuits 100, 104, 118 and 120. The rele-vant clock signals can also be formed by positive and negativeedges, respectively, of a single clock signal.
Each clock unit 122, 124, 130, 136 produces an external clock signal by way of the relevant toggle flip-flop 116, 128, 134, 140, respectively. The clock unit 122 receives the exter-nal clock signals of the clock units 124, 130, 136 in the mul-tiple latch circuit 100. The further clock units comprise cor-responding multiple latch circuits 126, 132, 138. Counter 108, ~0~59 -6a-which is in this case formed as a five-bit counter, counts the clock pulses ~1 subject to the condition that the latch cir-cuits 104 and 120 both contain a "1", because the AND-gate 106 is then conductive. In this respect reference is already made to figures 3 and 4 which show the logic relations OII which the operation of the counter 108, the majority circuit 102 and the toggle flip-flop 116 is based. The statements are expressed as so-called "guarded commands'l as based on a paper by E.W.
Dijkstra, in D. Gries, ed., Programming methodology, Springer 1978, pp 166-175 and also E~W. Dijkstra, A discipline of program-ming, Prentice Hall, 1976, p 24 ff. The guard preceeds the arrow and consists of a ~oolean expression. The command proper follows the arrow. The little blocks chain the commands within the do/od subroutine. The do/od indicates a loop. The commands are executable in parallel for then attaining a new system state.
For figure 3 an arbitrary number of clock units is assumed to be present. When the counter 108 has not tyet) reached its maximum count, p~ N, the latch circuit 120 receives a logic "1"
which is stored under the control of an even clock pulse. When the counter 108 has reached its maximum count, the latch cir-cuit 120 receives a logic "0" for storage. In that case, how-ever, the logic circuit 112 applies a "1" to the latch circuit 118, which "1" is stored under the control of an even clock pulse.
Under the ., ~
~ 121~:~59 P~ 10.470 7 19.9.1983 control of the next odd elock pulse, the AND-gate 11a then outputs a "1". As a resul-t, the countex 108 is reset to its startiny state and the state of the toggle flip-flop 116 changes. The value of the "own" clock signal on line 117 then ehanges.
s If the numbex of othex eloek units supplying an external signal different from that from the cloek unit 122 is not excessively laxge, the latch cixcuit 1oa~ reeeives a "1". For a redundaney degxee or error tole-ranee degree F, this means at the most F of the other elock circuits are allowed to supply a signal whieh deviates from the "o~n" eloek. F'or an extx~mely high reliability, notably when exclusively digital elements axe used (as in figures 2 and 6), the number n oE cloek units must be larger than or equal to 3F + 1. Usually a smaller num~er of cloek cix-cuits, such as is given by n~ 2F + 1, suffices notably for the solution shown in figure 5 which involves a phase-locked loop. The detection of the number of signals deviating from the "own" cloek ls performed in the logic eixeuit 102. When both lateh eireuits 1oa and 120 have stored a "one" (under the contxol of an even cloek pulse), the AND-gate 106 con-duets the odd cloek pulses until this situation is terminated; the counter 108 thus each time reaches its maximum eount and is subsequently reset to zero. In the ease of a ring eountex, xesetting would even be superfluous. The seeond line of figure 3 is thus implemented.
The output of the logie eixeuit 102 is also applied to the lo-gie eircuit 112. When the circuit 102 outputs a "0" (too many other clocks deviate), gate 106 is subsequently bloelced. The logic eireuit 112 now, however, implements the first line and the first part (up to or) of the third line of figure 3. When the signal on line 113 indieates that the counter 108 is in a low coun-t state (p~ m, for example, p< N/2), nothing happens so that the incrementation of eounter 108 is thereupon bloeked (first line of fi.gure 3). When the sicJnal on line 113 indieates that-the eolmter 108 is in a high coun-t state (for example, p~ N/2), -the maximum count state of this counter 108 is direetly emulated (third line, first part of figure 3). The indications do and od in ~igure 3 in-dieate that this proeedure is cyclically reprea-ted; the bloeks indicate chaining of the expressions; the logic ~ND-f~mc-tion has priority over the logie "O~"-funetion. In -the four-fold sys-tem deseribed, one of the eloclc units m-~y have an arbitrary synehronization condi-tion: in that case self-synehronizing always occurs. Thisholdsgood regardless of the ou-tput signal of this one deviating cloek unit. Notably the following s99 situations are accommodated:
a) the deviating clock unit outputs a static signal which, how-ever, is stored in a different manner by the various latch cir-cuits 100, 126, 132, 138 (in some as 10-l and in some as a "1").
b) an arbitrary noise signal is superposed on the signal of the deviating clock unit so that the counter of this clock unit may be in an arbitrary state at any instant. In the figure equal intervals are chosen for a "high" and a "low" count state.
The intervals need not be equal. It is alternatively possible to separate these intervals by a third interval, for example in that the condition in the first line is: p <N/4, in the third line is p~ 3N/4, and in that an additional line is inserted:
~-`D (s)> F and N/4~ p ~ 3N/4 ~ ERR.
Thus, in that case a fault indication occurs. An additional restriction can, for example, be imparted to this fault indica-tion, i.e. the start has to have taken place a given period of time previously: until that instant the operation "skip" i5 implemented. The latter period of time is determined simply by means of a monostable element which blocks the AND-gate which serves to supply the signal ERR. The condition of the count state is decoded by means of a decoder. The signal ERR can control a "clear mode" during which the output signals "clock"
and "data" of the relevant computer module (figure 1) are ignored by the other computer modules. Each module which detects a deviating signal from another module treats said other module as being faulty. This can be achieved by means of a switch (not shown for the sake of simplicity) which isolates the clock signal of the faulty module from the detecting module and replaces it ~2~0~S~
-8a-by the clock signal of the own clock. Any changes in the symbol correction code can be performed as described in Canadian Patent No. 1,163,373. Input signals having the value "terminated by a high impedance" are then treated as "O" in the data word recon-struction module in order that they will be ignored. Alter-natively, such a switch-off mechanism may be omitted, but in that case the decoding in the data word reconstruction modules is controlled selectivelyu The expressions of figure 4 correspond to those oE
figure 3 but serve notably for a situation involving four co-operating clocks. "S" represents the "own" clock signalO "V"
represents the majority of the other clock signals. The figures
for a value n=5, the upper limit equals l or 2, and so on for higher values of n. The system is also fault tolerant in many cases: a given number of clocks may be completely out of step and will be ignored. The specific differences with respect to and the advantages ovex the present state of the art will be described hereinafter.
Preferably, said upper limit at the most equals the largest integer that is not greater than l/3(n-l). For n=4, s~
-2a-the permissible upper limit then equals 1, likewise for n=5 and 6. For n=7, the permissible upper limit then equals 2. It has been found that this more severe requirement offers protec-tion against practically all feasible fault configurations which are limited to a number of clock circuits which does not ecceed the upper limit, including inter alia interruptions in the output line for the clock signal of the faulty clock.
Preferably, the end of a said firs-t period is consecu-tive with the beginning of a said second period. This results in a simple organization and quick synchronization (by way of a large "pull-in" range for the synchronization).
Preferably, between a said first period and a directly subsequent second period there is situated a third period, there being provided an error detection circuit in a clock for supply-ing an error signal in said third period when said upper limit is exceeded due to another clock. After termination of switch-on phenomena, such an error signal -` ~21~
P~ 10.470 3 19.9.1983 clearly indicates that the relevant clock circuit is out of step so that more likely it is faulty.
Preferably, -there is provided a deactivation control element for deactivating, under the control of said error signal, the clock tnus deemed faulty. A faulty clock circuit can thus ~e deactivated, subject to the condition that said switch-on phenomena have terminated.
Preferably, said dividing circuit is a two-divider which is controlled in synchronism with the pericd of the oscillator circuit. This offers a simple implementation.
rrhe oscillator circuit in a preferred embodim~ent comprises a circuit loop which includes an EXCLUSIVE-OR-gate, a low-pass filter and an oscillator, the dividing circuit ~eing connected to an output of the oscillator while the output of the deviation-determining device is con-nected to an input of the EXCLUSIVE-OR-gate in order to apply thereto, when said upper limit is exceeded, a first logic value during said first period and a second logic value during said second period, but otherwise the second logic value and the first logic value, respectively. Thus, a simple implementation is achieved, allowing the use of standard compo-nents.
The oscillator circuit in another preferred ernbcdi~ent compri-ses an oscillator and a counter which is fed by the oscillator and which counts from a start count state to a maximum count state, there also ~eing provided a logic circuit which forms, under the control of an output signal of the deviation-determining device, a hold signal in the case of a low count but an acceleration signal in the case of a high count. This is a completely digital solution, so that an arbitrary ad-justment accuracy can be achieved.
Preferably, said acceleration signal emulates a mc~ximum count signal. This results in accelerated self-synchronization.
Preferably, for n=4 the cleviation-determining device comprises a majority decision device for the clock signals of the other clocks and a comparison circuit which receives an output signal of the majority decision device and its own clcck signal. The foregoing results in a sunple implementation and, moreover, -this number of clocks already suf-fices in many cases.
The inven-tion also relates to a clock circui-t which is intended for use in a multiple redundant clock system of the kind descri~ed and which comprises (n-1~ external connections for receiving externally for-~2~1S9 med clock signals, and which also comprises an oscillator sir-cuit, a dividing circuit and a deviation-de-termining device of the kind described. Such a clock circuit forms an attractive module in which n and said upper limit may be adjustable, if desired.
The invention also relates to a multiprocessor computer system eomprising n computer modules, eaeh eomputer module eompri-sing a eloek so that the n clocks together constitute a multiple redundant clock system of the kind described, each computer module also comprising a processor module for the processing of a data word, a reducing encoder which is connected to the proces-sor module in order to form a code symbol from the data word so that the n code symbols formed from a data word form a code word of a symbol error correction code, a memory moduIe which is con-nected to the reducing encoder in order to store a code symbol per data word, and a data word reeonstruetion module, the data word reeonstruetion modules of all eomputer modules being eonnected to the relevant eomputer modules by way of a seeond intereonnec-tion network in order to reeeive the relevant code symbols of a eode word and to reeonstruet therefrom a data word for presenta-tion to the processor module of the relevant computer module, thevarious data proeessing operations being synehronized by the eloek system. A computer system of this kind, without the present clock system, has already been partly disclosed in Canadian Patent No.
1,163,373 in the name of Applieant. The clock system is thus also rendered redundant, so that the system is eapable of dealing with a failure of the eloek seetion as well as with a failure of the data processing section of a number of modules in as far as this .~
S~9 number does not ex~eed the upper limit of the fault tolerance capacity.
Brief description of the figures The invention will be described in detail hereinafter with reference to some Eigures.
Figure 1 is a simple block diagram of a multiprocessor computer system comprising a multiple redundant clock system.
Figure 2 shows a clock system in accordance with the invention.
Figures 3 and 4 show the logic expressions for figure 2.
Elgures 5 and 6 show two embodiments of a clock circuit.
Figure 7 illustrates the content of a read-only memory.
Description of a multiprocessor computer system Figure 1 is a simple block diagram of a multiprocessor computer system comprising a multiple redundant clock system.
The computer system comprises four computer modules. Each computer module comprises a processor module, its own clock, and a data word reconstruction module. There are four processor modules 200-206. Each clock 220-226 applies clock signals to the associated processor. Each clock also applies clock signals to all other clocks, and hence indirectly to the other processor modules. Each processor module outputs its output data to all four data word reconstruction modules 210-216 which together form a data word reconstruction device. In each data word reconstruction module given data errors can b~ detected and/or corrected: the correct data is applied to the associated processor in which data proces-sing can take place. A computer system divided into a number of -5a-modules has already been disclosed in Canadian Patent No. 1,163,373;
therein, a code word consisting of code symbols is formed on the basis of a data word consisting of data symbols. After encoding, each computer module processes only a part of the code word, for example one code symbol. This operation concerns, for example, memory storage, followed by a read operation and regeneration of the code symbol. In order to reconstruct the entire data woxd for an arithmetic operation, all code symbols are applied to all computer modules. It has been found that the operation can be correctly performed even in the case of complete failure of, for example, one computer module. Such a system can be synchronized by a master clock. In the set-up shown in figure 1, the various operations in the various computer modules are synchronized by the clock system consisting of the clocks 220-226. The operation of the data word reconstruction modules can also be synchronized in this manner, bu-t this is not shown. Should one of the computer modules, for example the module comprising the blocks 202-212, 222, become defective (data or clock), the other three modules can continue to operate in the usual manner. In accordance with Canadian Patent No. 1,163,373, the system requires only a two-fold storage capacity in the memory for a four-Eold processing capacity in the arithmetic and logic (ALU) unit in comparison with a single-non-redundant processor (in the terminology used, the processor thus also comprises the foreground memory; the back-ground memory and Eurther peripheral apparatus are not considered herein). Similarly, another multiple ~01~
data processing system (for example, a communication system, a word processing system and the like) can also comprise such a multiple redundant clock system.
Preferred embodiments of the invention Figure 2 shows a self-synchronizing clock system for four single clocks in accordance with the invention. The number of clocks connected may be arbitrarily large and the degree of redundancy may also be increased. The first single clock is shown in detail in block 122. This clock is driven by an inter-nal oscillator haviny a frequency which is, for example, from20 to 100 times higher than the required operating frequency:
the latter frequency is formed by the counter 108 which acts as a frequency divider in conjunction with element 116. The oscil-lator frequency is not subject to very severe constraints.
The oscillator may be, for example, an oscillator which is adjus-ted by means of an external RC-network. This oscillator alter-nately supplies an odd clock pulse 01 and an even clock pulse 02, thus synchronizing the operation of the logic circuits 106 and 114 and the latch circuits 100, 104, 118 and 120. The rele-vant clock signals can also be formed by positive and negativeedges, respectively, of a single clock signal.
Each clock unit 122, 124, 130, 136 produces an external clock signal by way of the relevant toggle flip-flop 116, 128, 134, 140, respectively. The clock unit 122 receives the exter-nal clock signals of the clock units 124, 130, 136 in the mul-tiple latch circuit 100. The further clock units comprise cor-responding multiple latch circuits 126, 132, 138. Counter 108, ~0~59 -6a-which is in this case formed as a five-bit counter, counts the clock pulses ~1 subject to the condition that the latch cir-cuits 104 and 120 both contain a "1", because the AND-gate 106 is then conductive. In this respect reference is already made to figures 3 and 4 which show the logic relations OII which the operation of the counter 108, the majority circuit 102 and the toggle flip-flop 116 is based. The statements are expressed as so-called "guarded commands'l as based on a paper by E.W.
Dijkstra, in D. Gries, ed., Programming methodology, Springer 1978, pp 166-175 and also E~W. Dijkstra, A discipline of program-ming, Prentice Hall, 1976, p 24 ff. The guard preceeds the arrow and consists of a ~oolean expression. The command proper follows the arrow. The little blocks chain the commands within the do/od subroutine. The do/od indicates a loop. The commands are executable in parallel for then attaining a new system state.
For figure 3 an arbitrary number of clock units is assumed to be present. When the counter 108 has not tyet) reached its maximum count, p~ N, the latch circuit 120 receives a logic "1"
which is stored under the control of an even clock pulse. When the counter 108 has reached its maximum count, the latch cir-cuit 120 receives a logic "0" for storage. In that case, how-ever, the logic circuit 112 applies a "1" to the latch circuit 118, which "1" is stored under the control of an even clock pulse.
Under the ., ~
~ 121~:~59 P~ 10.470 7 19.9.1983 control of the next odd elock pulse, the AND-gate 11a then outputs a "1". As a resul-t, the countex 108 is reset to its startiny state and the state of the toggle flip-flop 116 changes. The value of the "own" clock signal on line 117 then ehanges.
s If the numbex of othex eloek units supplying an external signal different from that from the cloek unit 122 is not excessively laxge, the latch cixcuit 1oa~ reeeives a "1". For a redundaney degxee or error tole-ranee degree F, this means at the most F of the other elock circuits are allowed to supply a signal whieh deviates from the "o~n" eloek. F'or an extx~mely high reliability, notably when exclusively digital elements axe used (as in figures 2 and 6), the number n oE cloek units must be larger than or equal to 3F + 1. Usually a smaller num~er of cloek cix-cuits, such as is given by n~ 2F + 1, suffices notably for the solution shown in figure 5 which involves a phase-locked loop. The detection of the number of signals deviating from the "own" cloek ls performed in the logic eixeuit 102. When both lateh eireuits 1oa and 120 have stored a "one" (under the contxol of an even cloek pulse), the AND-gate 106 con-duets the odd cloek pulses until this situation is terminated; the counter 108 thus each time reaches its maximum eount and is subsequently reset to zero. In the ease of a ring eountex, xesetting would even be superfluous. The seeond line of figure 3 is thus implemented.
The output of the logie eixeuit 102 is also applied to the lo-gie eircuit 112. When the circuit 102 outputs a "0" (too many other clocks deviate), gate 106 is subsequently bloelced. The logic eireuit 112 now, however, implements the first line and the first part (up to or) of the third line of figure 3. When the signal on line 113 indieates that the counter 108 is in a low coun-t state (p~ m, for example, p< N/2), nothing happens so that the incrementation of eounter 108 is thereupon bloeked (first line of fi.gure 3). When the sicJnal on line 113 indieates that-the eolmter 108 is in a high coun-t state (for example, p~ N/2), -the maximum count state of this counter 108 is direetly emulated (third line, first part of figure 3). The indications do and od in ~igure 3 in-dieate that this proeedure is cyclically reprea-ted; the bloeks indicate chaining of the expressions; the logic ~ND-f~mc-tion has priority over the logie "O~"-funetion. In -the four-fold sys-tem deseribed, one of the eloclc units m-~y have an arbitrary synehronization condi-tion: in that case self-synehronizing always occurs. Thisholdsgood regardless of the ou-tput signal of this one deviating cloek unit. Notably the following s99 situations are accommodated:
a) the deviating clock unit outputs a static signal which, how-ever, is stored in a different manner by the various latch cir-cuits 100, 126, 132, 138 (in some as 10-l and in some as a "1").
b) an arbitrary noise signal is superposed on the signal of the deviating clock unit so that the counter of this clock unit may be in an arbitrary state at any instant. In the figure equal intervals are chosen for a "high" and a "low" count state.
The intervals need not be equal. It is alternatively possible to separate these intervals by a third interval, for example in that the condition in the first line is: p <N/4, in the third line is p~ 3N/4, and in that an additional line is inserted:
~-`D (s)> F and N/4~ p ~ 3N/4 ~ ERR.
Thus, in that case a fault indication occurs. An additional restriction can, for example, be imparted to this fault indica-tion, i.e. the start has to have taken place a given period of time previously: until that instant the operation "skip" i5 implemented. The latter period of time is determined simply by means of a monostable element which blocks the AND-gate which serves to supply the signal ERR. The condition of the count state is decoded by means of a decoder. The signal ERR can control a "clear mode" during which the output signals "clock"
and "data" of the relevant computer module (figure 1) are ignored by the other computer modules. Each module which detects a deviating signal from another module treats said other module as being faulty. This can be achieved by means of a switch (not shown for the sake of simplicity) which isolates the clock signal of the faulty module from the detecting module and replaces it ~2~0~S~
-8a-by the clock signal of the own clock. Any changes in the symbol correction code can be performed as described in Canadian Patent No. 1,163,373. Input signals having the value "terminated by a high impedance" are then treated as "O" in the data word recon-struction module in order that they will be ignored. Alter-natively, such a switch-off mechanism may be omitted, but in that case the decoding in the data word reconstruction modules is controlled selectivelyu The expressions of figure 4 correspond to those oE
figure 3 but serve notably for a situation involving four co-operating clocks. "S" represents the "own" clock signalO "V"
represents the majority of the other clock signals. The figures
3 and 4 otherwise correspond.
P~ 10.470 9 19.9.1983 Figure 5 shows an embodiment of a clock utilizing an oscilla-tor included in a so-called phase-locked loop (PLL). Such modules are commercially available and comprise the components indicated within the rectangle 300 which is drawn in broken lines: an EXCLUSIVE-OR-gate 302, a low-pass filter 304 and an oscillator (VCO) 306 whose frequency is controlled by the output signal of the low pass filter. The time con-stant of the low-pass filter (inverse limit frequency) is large with respect to the period of the voltage-controlled oscillator 306, for example 10 times larger. The output signal of the oscillator 306 is fed back to the input of the EXCLUSIVE-OR-gate 302 and, moreover, to the in-pu-t of the T-flip-flop 308. The latter acts as a two-divider because it changes its state each time a positive-going signal edge is received on its input. The clock shown in suitable for use in a four-fold clock sys-tem which is insusceptible to the failure of one of the four clocks. To this end, the inputs 312 are connected (via an interconnection not shown) to the clock outputs of the other clocks. Thus, when these other clocks have a construction as shown in figure 5, each of these outputs the output of the flip-flop of the relevant other clock which corres-ponds to the T-flip-flop 308. The output of the flip flop 308, or al-ternatively directly the output of the oscillator 306, can be used as aclock signal for a local station which is thus synchronized, provided that at least t~o relevant clock signals are received from other clocks on the inputs 312. The element 310 is a deviation-determining device which is constructed, for example, as a programmable logic array (PhA) or as a random access programmable read-only memory ~PROM). The operation thereof wi]l be described later; modules of this kind are commercially available. Instead of the element 308, use can be made of a four-di~ider, the outputs of both stategs together giving an indication that the third period is being completed; these two are then applied together to element 30 310. The elernent 308 may, for exarnple, also divide by a different fac--tor, for example by three. If it i5 necessary to form a symmetrical clock pulse, it is often also necessary to insert a low-pass filter or band-pass filter in the output line of -the divider 308 for -the removal of higher harmonics.
Figure 6 shows an em~odiment of a clock utilizing a counter;
thls circuit represents mainly an improvement of a circuit of the kind shown in figure 2. The oscillator 314 serves to render the operation of the circuit time-discrete. In contrast therewith the circuit shown in `` ~2~
P~lN 10.470 10 19.9.1983 figure 5 operates continuously, because the signals therein can in principle change at arbitrary instands. The oscillator 314 applies clock signals to the counter 316 which may be, for example, a conventio-nal four-bit counter. This counter has a maximum count output 320, for example an output for a ripple carry signal. Gutput 320 is connected, via an OR-gate 322, to an input INC for an inverted enable signal; when the counter has reached its maximum count, therefore, further clock sig-nals are ineffective. The counter also has an output 318 which outputs a high signal ~Jhen the count state exceeds a given value m. In the four-bit counter described, N has the value 15 and m, for example, has thevalue 8, so that the output signal of a bit state can be used. The out-put of the OR-gate-322 is combined with the output 318 of the counter 316 in AND-gate 324. The output signal of the AND-gate 324 is returned to the reset in~ut of the counter 316 so that the latter directly assumes its zero state again when its maximum count is reached. The out-put of the gate 324 is also connected to a t~-divider 326 whose opera-tion corresponds to the t~ divider 308 of figure 5. A data Elip-flop 328 which temporarily stores the output signal of the deviation-deter-mining device 310 under the control of a signal from the oscillator 314 is connected to the output of the deviation-determining device 310. Fi-nally, the output of the data flip-flop 323 is applied to the OR-gate 322.
Figure 7 shows the data content of the deviation~determining device 310 constructed as a PROM memory and adapted for a six-fold clock system. The translation to a progammable logic array has thus become elementary. The signal S represents the "own" clock signal (on the out-put of the elements 308 and 326 in figures 5 and 6 respectively). The signals X1, X2, X3, X4, X5 are the corresponding signa]s of the other five clocks. The signal D is the cutput signal of the deviation-deter-mining device. The columns D, S at the left-hand side represents the situation for S=0 if no more than two clock circuits may deviate; this number two is, therefore, the redundancy degree. The output signal D is formed as the majority signal between the signals X1, X2, X3, X4, X5.
The colu~ns D, S at the righ-t-hand side represent the situation for S-1;
the signal D is then form~d as the inverse value of the majori-ty signal between the signals X1, X2, X3, X4, X5. The column D1 at -the leEt-hand side represents the sit.uation where the system is designed for a fault tolerance degree F=1. D1=0 only if a qualified majority (at least four) 2~ S9 P~ 10.470 11 19.9.1983 of the signals X1 ... X5 has the value 0. The limits for this qualified majority as a function oE the number of clock circui-ts and the value of the redundancy degree have already ~een described. In case of a four-fold clock system, only the row numbers 4p-1, 4p-2 are taken with p=1, ... 2 .... 8. Each time X4~X5, and X4, X5 are ignored. Corresponding con-siderations are applicable to eight-fold and even larger clock systems.
A prcgrammable read-only memory of the kind described can be used as follows in a system comprising a num~er of clocks which is smaller than the numker of inputs of the PROM memory; the own clock signal is then applie~ to the free inputs. In the circuit shown in figure 6 it is also possible to include the EXCL~SIVE-OR-gate 302 in the function of the read-only memory; the delay introduced by the PROM memory as an active phenomenon in the circuit is then avoided. Sometimes the operation is thus improved. The output of the voltage-controlled oscillator is then added as an additional address line.
The differences with respect to the described state of the art notably concern the following:
a) the bistable element wherefrom the local clock signal is derived is situated at the output side of the phase-coupled loop or counter, b) the confrontation between the local clock signal and the clock signals of the other modules takes place at the input side of the circuit in the deviation-determinin~ device.
Consequently, /t~e case of n stuck-~ ircuits (constant output signal), the present circuit could usually cope with (2F + 1) mo~ules;
this is because the counter/phase-locked loops of the remaining opera-tive stations would continue counting in an unimpeded mannerO Further-more, notahle in the case of an arbitrary noise signal on an output of one of the clocks in the present circuit, such a noise signal would be removed by filtering by the low-pass filter of the phase-locked loop;
consequenlty, this signal will never reach the relevant bistable cir-cuit.
The akove difference b) simplifies the deviation-determining device, because the use of a singular m~jority-decision clevice suffices.
Moreover, no or or only hardly any compensation will be required for signal delays in -the deviation-determining device, because the confron-tation takes pL~ce at the input side -thereof.
P~ 10.470 9 19.9.1983 Figure 5 shows an embodiment of a clock utilizing an oscilla-tor included in a so-called phase-locked loop (PLL). Such modules are commercially available and comprise the components indicated within the rectangle 300 which is drawn in broken lines: an EXCLUSIVE-OR-gate 302, a low-pass filter 304 and an oscillator (VCO) 306 whose frequency is controlled by the output signal of the low pass filter. The time con-stant of the low-pass filter (inverse limit frequency) is large with respect to the period of the voltage-controlled oscillator 306, for example 10 times larger. The output signal of the oscillator 306 is fed back to the input of the EXCLUSIVE-OR-gate 302 and, moreover, to the in-pu-t of the T-flip-flop 308. The latter acts as a two-divider because it changes its state each time a positive-going signal edge is received on its input. The clock shown in suitable for use in a four-fold clock sys-tem which is insusceptible to the failure of one of the four clocks. To this end, the inputs 312 are connected (via an interconnection not shown) to the clock outputs of the other clocks. Thus, when these other clocks have a construction as shown in figure 5, each of these outputs the output of the flip-flop of the relevant other clock which corres-ponds to the T-flip-flop 308. The output of the flip flop 308, or al-ternatively directly the output of the oscillator 306, can be used as aclock signal for a local station which is thus synchronized, provided that at least t~o relevant clock signals are received from other clocks on the inputs 312. The element 310 is a deviation-determining device which is constructed, for example, as a programmable logic array (PhA) or as a random access programmable read-only memory ~PROM). The operation thereof wi]l be described later; modules of this kind are commercially available. Instead of the element 308, use can be made of a four-di~ider, the outputs of both stategs together giving an indication that the third period is being completed; these two are then applied together to element 30 310. The elernent 308 may, for exarnple, also divide by a different fac--tor, for example by three. If it i5 necessary to form a symmetrical clock pulse, it is often also necessary to insert a low-pass filter or band-pass filter in the output line of -the divider 308 for -the removal of higher harmonics.
Figure 6 shows an em~odiment of a clock utilizing a counter;
thls circuit represents mainly an improvement of a circuit of the kind shown in figure 2. The oscillator 314 serves to render the operation of the circuit time-discrete. In contrast therewith the circuit shown in `` ~2~
P~lN 10.470 10 19.9.1983 figure 5 operates continuously, because the signals therein can in principle change at arbitrary instands. The oscillator 314 applies clock signals to the counter 316 which may be, for example, a conventio-nal four-bit counter. This counter has a maximum count output 320, for example an output for a ripple carry signal. Gutput 320 is connected, via an OR-gate 322, to an input INC for an inverted enable signal; when the counter has reached its maximum count, therefore, further clock sig-nals are ineffective. The counter also has an output 318 which outputs a high signal ~Jhen the count state exceeds a given value m. In the four-bit counter described, N has the value 15 and m, for example, has thevalue 8, so that the output signal of a bit state can be used. The out-put of the OR-gate-322 is combined with the output 318 of the counter 316 in AND-gate 324. The output signal of the AND-gate 324 is returned to the reset in~ut of the counter 316 so that the latter directly assumes its zero state again when its maximum count is reached. The out-put of the gate 324 is also connected to a t~-divider 326 whose opera-tion corresponds to the t~ divider 308 of figure 5. A data Elip-flop 328 which temporarily stores the output signal of the deviation-deter-mining device 310 under the control of a signal from the oscillator 314 is connected to the output of the deviation-determining device 310. Fi-nally, the output of the data flip-flop 323 is applied to the OR-gate 322.
Figure 7 shows the data content of the deviation~determining device 310 constructed as a PROM memory and adapted for a six-fold clock system. The translation to a progammable logic array has thus become elementary. The signal S represents the "own" clock signal (on the out-put of the elements 308 and 326 in figures 5 and 6 respectively). The signals X1, X2, X3, X4, X5 are the corresponding signa]s of the other five clocks. The signal D is the cutput signal of the deviation-deter-mining device. The columns D, S at the left-hand side represents the situation for S=0 if no more than two clock circuits may deviate; this number two is, therefore, the redundancy degree. The output signal D is formed as the majority signal between the signals X1, X2, X3, X4, X5.
The colu~ns D, S at the righ-t-hand side represent the situation for S-1;
the signal D is then form~d as the inverse value of the majori-ty signal between the signals X1, X2, X3, X4, X5. The column D1 at -the leEt-hand side represents the sit.uation where the system is designed for a fault tolerance degree F=1. D1=0 only if a qualified majority (at least four) 2~ S9 P~ 10.470 11 19.9.1983 of the signals X1 ... X5 has the value 0. The limits for this qualified majority as a function oE the number of clock circui-ts and the value of the redundancy degree have already ~een described. In case of a four-fold clock system, only the row numbers 4p-1, 4p-2 are taken with p=1, ... 2 .... 8. Each time X4~X5, and X4, X5 are ignored. Corresponding con-siderations are applicable to eight-fold and even larger clock systems.
A prcgrammable read-only memory of the kind described can be used as follows in a system comprising a num~er of clocks which is smaller than the numker of inputs of the PROM memory; the own clock signal is then applie~ to the free inputs. In the circuit shown in figure 6 it is also possible to include the EXCL~SIVE-OR-gate 302 in the function of the read-only memory; the delay introduced by the PROM memory as an active phenomenon in the circuit is then avoided. Sometimes the operation is thus improved. The output of the voltage-controlled oscillator is then added as an additional address line.
The differences with respect to the described state of the art notably concern the following:
a) the bistable element wherefrom the local clock signal is derived is situated at the output side of the phase-coupled loop or counter, b) the confrontation between the local clock signal and the clock signals of the other modules takes place at the input side of the circuit in the deviation-determinin~ device.
Consequently, /t~e case of n stuck-~ ircuits (constant output signal), the present circuit could usually cope with (2F + 1) mo~ules;
this is because the counter/phase-locked loops of the remaining opera-tive stations would continue counting in an unimpeded mannerO Further-more, notahle in the case of an arbitrary noise signal on an output of one of the clocks in the present circuit, such a noise signal would be removed by filtering by the low-pass filter of the phase-locked loop;
consequenlty, this signal will never reach the relevant bistable cir-cuit.
The akove difference b) simplifies the deviation-determining device, because the use of a singular m~jority-decision clevice suffices.
Moreover, no or or only hardly any compensation will be required for signal delays in -the deviation-determining device, because the confron-tation takes pL~ce at the input side -thereof.
Claims (12)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A multiple redundant clock system, comprising a number of n?4 mutually synchronizing clocks, each of which comprises a respective clock output for a bivalent clock signal, said system comprising an interconnection network for applying the clock signal of each clock to each of the other clocks, each clock comprising an oscillator circuit and a deviation-determining device to an input of which the oscillator circuit is connected via an interconnection and which comprises further inputs for receiving the clock signals of the other clocks, characterized in that each clock comprises, as a part of said interconnection, a two-state dividing circuit which is switched over, each time under the control of a period signal of the local oscillator circuit, at a recurrent series of switch-over points and which outputs the associated signal value of its "own" clock signal continuously on its output in each state, the deviation-deter-mining device comprising a comparator for comparing the number of clock signals received from other clocks and deviating from its own clock signal with a permissible upper limit which at the most equals the largest integer that is not greater than ?(n-1) and to generate, in the case of a larger number, a deceler-ation signal in a first period which directly succeeds a switch-over point but an acceleration signal in a second period which directly preceeds a switch-over point in order to readjust the frequency of the oscillator circuit.
2. A multiple redundant clock system as claimed in Claim 1, characterized in that said upper limit at the most equals the largest integer that is not greater than 1/3(n-1).
3. A multiple redundant clock system as claimed in Claim 1, characterized in that the end of a said first period coincides with the beginning of a said second period.
4. A multiple redundant clock system as claimed in Claim 1, characterized in that between a said first period and a directly subsequent second period there is situated a third period, there being provided an error detection circuit in a clock for supply-ing an error signal in said third period when said upper limit is exceeded due to another clock.
5. A multiple redundant clock system as claimed in Claim 4, characterized in that there is provided a deactivation control element for deactivating, under the control of said error signal, the clock thus deemed faulty.
6. A multiple redundant clock system as claimed in Claim 3, characterized in that said dividing circuit is a two-divider which is controlled in synchronism with the period of the oscillator circuit.
7. A multiple redundant clock system as claimed in Claim 1, 2 or 3, characterized in that the oscillator circuit comprises a circuit loop which includes an EXCLUSIVE-OR-gate, a low-pass fil-ter, and an oscillator, the dividing circuit being connected to an output of the oscillator while the output of the deviation-determining device is connected to an input of the EXCLUSIVE-OR-gate in order to apply thereto, when said upper limit is exceeded, a first logic value during said first period and a second logic value during said second period, but otherwise the second logic value and the first logic value, respectively.
8. A multiple redundant clock system as claimed in Claim 1, 2 or 3, characterized in that the oscillator circuit comprises an oscillator and a counter which is connected to the oscillator and which counts from a start count state to a maximum count state, there also being provided a logic circuit which forms, under the control of an output signal of the deviation-determining device, a hold signal in the ease of a low count but an acceleration signal in the ease of a high count.
9. A multiple redundant clock system as claimed in Claim 1, 2 or 3, characterized in that the oscillator circuit comprises an oscillator and a counter which is connected to the oscillator and which counts from a start count state to a maximum count state, there also being provided a logic circuit which forms, under the control of an output signal of the deviation-determining device, a hold signal in the ease of a low count but an acceleration signal in the ease of a high count in that said acceleration signal emu-lates a maximum count signal.
10. A multiple redundant clock system as claimed in Claim 1, 2 or 3, characterized in that for n=4 the deviation-determining device comprises a majority decision device for the clock signals of the other clocks and a comparison circuit which receives an out-put signal of the majority decision device and the "own" clock signal.
11. A clock circuit which is intended for use in a multiple redundant clock system as claimed in Claim 1, 2 or 3, and which comprises (n-1) external connections for receiving externally formed clock signals, and which also comprises an oscillator cir-cuit, a dividing circuit and a deviation-determining device of the kind described.
12. A multiprocessor computer system comprising n computer modules, each computer module comprising a clock circuit so that the n clock circuits together constitute a multiple redundant clock system as claimed in Claim 1, 2 or 3, wherein each clock circuit comprises (n-1) external connections for receiving clock signals by other clock circuits in the system, and wherein each clock cir-cuit comprises an oscillator circuit, a dividing circuit and a deviation determining device of the kind described, and wherein each computer module also comprising a processor module for the processing of a data word, a reducing encoder which is connected to the processor module in order to form a code symbol from the data word so that the n code symbols formed from a data word form a code word of a single-symbol error-correction code, a memory module which is connected to the reducing encoder in order to store a code symbol per data word, and a data word reconstruction module, the data word reconstruction modules of all computer modules being connected to the relevant computer modules by way of a second interconnection network in order to receive the rele-vant code symbols of a code word and to reconstruct therefrom a data word for presentation to the processor module of the rele-vant computer module, the various data processing operations being synchronized by the clock system.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| NL8203921 | 1982-10-11 | ||
| NL8203921A NL8203921A (en) | 1982-10-11 | 1982-10-11 | MULTIPLE REDUNDANT CLOCK SYSTEM, CONTAINING A NUMBER OF SYNCHRONIZING CLOCKS, AND CLOCK CIRCUIT FOR USE IN SUCH A CLOCK SYSTEM. |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1210159A true CA1210159A (en) | 1986-08-19 |
Family
ID=19840391
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000438592A Expired CA1210159A (en) | 1982-10-11 | 1983-10-07 | Multiple redundant clock system comprising a number of mutually synchronizing clocks, and clock circuit for use in such a clock system |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US4779008A (en) |
| EP (1) | EP0107236B1 (en) |
| JP (1) | JPS5990125A (en) |
| CA (1) | CA1210159A (en) |
| DE (1) | DE3373568D1 (en) |
| NL (1) | NL8203921A (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61154221A (en) * | 1984-12-26 | 1986-07-12 | Toshiba Corp | Majority decision circuit |
| JPS6268314A (en) * | 1985-09-20 | 1987-03-28 | Nec Corp | Timing signal synchronizing system |
| NL8502768A (en) * | 1985-10-10 | 1987-05-04 | Philips Nv | DATA PROCESSING DEVICE, COMPRISING MULTIPLE, PARALLEL-OPERATING DATA PROCESSING MODULES, MULTIPLE REDUNDANT CLOCK, CONTAINING A NUMBER OF MACHINERY-SYNCHRONIZING CLOCK CIRCUITS FOR USE IN ANY IN-PROPERTY AND PROCESSING EQUIPMENT. |
| DE3638947C2 (en) * | 1986-11-14 | 1995-08-31 | Bosch Gmbh Robert | Process for the synchronization of computers of a multi-computer system and multi-computer system |
| DE3643002A1 (en) * | 1986-12-17 | 1988-06-30 | Philips Patentverwaltung | CIRCUIT ARRANGEMENT FOR SYNCHRONIZING DEVICES IN THE SWITCHING AND AMPLIFIER POINTS OF A TIME MULTIPLEX TRANSMISSION SYSTEM |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3859466A (en) * | 1972-05-23 | 1975-01-07 | Siemens Ag | Reciprocal synchronization of oscillators of a time multiplex telephone communication network |
| CH556576A (en) * | 1973-03-28 | 1974-11-29 | Hasler Ag | DEVICE FOR SYNCHRONIZATION OF THREE COMPUTERS. |
| CH623669A5 (en) * | 1973-11-14 | 1981-06-15 | Agie Ag Ind Elektronik | |
| JPS5620746Y2 (en) * | 1974-07-04 | 1981-05-16 | ||
| FR2379857A1 (en) * | 1977-02-07 | 1978-09-01 | Cii Honeywell Bull | GENERATOR OF CLOCK SIGNALS IN AN INFORMATION PROCESSING SYSTEM |
| FR2390856A1 (en) * | 1977-05-10 | 1978-12-08 | Lannionnais Electronique | TIME BASE |
| US4239982A (en) * | 1978-06-14 | 1980-12-16 | The Charles Stark Draper Laboratory, Inc. | Fault-tolerant clock system |
| FR2484104A1 (en) * | 1980-06-06 | 1981-12-11 | Chomette Andre | Microprocessor controlled synchronisation loop for VCO - uses HF signal cycle count to measure phase errors between VCO and references passing error changes |
| US4419629A (en) * | 1980-06-25 | 1983-12-06 | Sperry Corporation | Automatic synchronous switch for a plurality of asynchronous oscillators |
| NL8202685A (en) * | 1982-07-05 | 1984-02-01 | Philips Nv | CLOCK SIGNAL REGENATOR WITH HIGH STABILITY. |
-
1982
- 1982-10-11 NL NL8203921A patent/NL8203921A/en not_active Application Discontinuation
-
1983
- 1983-10-07 DE DE8383201439T patent/DE3373568D1/en not_active Expired
- 1983-10-07 EP EP83201439A patent/EP0107236B1/en not_active Expired
- 1983-10-07 CA CA000438592A patent/CA1210159A/en not_active Expired
- 1983-10-11 JP JP58189809A patent/JPS5990125A/en active Granted
-
1987
- 1987-06-17 US US07/063,542 patent/US4779008A/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| DE3373568D1 (en) | 1987-10-15 |
| EP0107236A1 (en) | 1984-05-02 |
| EP0107236B1 (en) | 1987-09-09 |
| JPS5990125A (en) | 1984-05-24 |
| JPH0420484B2 (en) | 1992-04-03 |
| NL8203921A (en) | 1984-05-01 |
| US4779008A (en) | 1988-10-18 |
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