CA1217826A - Frequency doubler with 50 percent duty cycle output - Google Patents
Frequency doubler with 50 percent duty cycle outputInfo
- Publication number
- CA1217826A CA1217826A CA000475273A CA475273A CA1217826A CA 1217826 A CA1217826 A CA 1217826A CA 000475273 A CA000475273 A CA 000475273A CA 475273 A CA475273 A CA 475273A CA 1217826 A CA1217826 A CA 1217826A
- Authority
- CA
- Canada
- Prior art keywords
- voltage
- output
- frequency
- input
- duty cycle
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/00006—Changing the frequency
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
- H03K5/1565—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern the output pulses having a constant duty cycle
Abstract
FREQUENCY DOUBLER WITH FIFTY PERCENT
DUTY CYCLE OUTPUT SIGNAL
Yusuf A. Haque ABSTRACT
A unique frequency doubler circuit is utilized which requires only a handful of standard components such as operational amplifier, logic gates, resistors, capacitors and switches. In contrast to certain prior art frequency doublers, frequency doublers constructed in accordance with the teachings of this invention do not require the use of a phase lock loop, thereby resulting in a substan-tial simplification of circuit construction. Furthermore, frequency doublers constructed in accordance with this invention utilize a feedback technique which assures that the duty cycle of the output signal will be 50%, or any other predefined value.
DUTY CYCLE OUTPUT SIGNAL
Yusuf A. Haque ABSTRACT
A unique frequency doubler circuit is utilized which requires only a handful of standard components such as operational amplifier, logic gates, resistors, capacitors and switches. In contrast to certain prior art frequency doublers, frequency doublers constructed in accordance with the teachings of this invention do not require the use of a phase lock loop, thereby resulting in a substan-tial simplification of circuit construction. Furthermore, frequency doublers constructed in accordance with this invention utilize a feedback technique which assures that the duty cycle of the output signal will be 50%, or any other predefined value.
Description
BACKGROUND OF THE INvENTIoN
.
This invention relates -to electronic circuits for pro-viding an output signal having a frequency twice that o:E the in~
put signal.
Fxequency doublers areknown in the prior art and are used to provide an ou-tput signal which has a frequency haviny twice the frequency of an input signal. E'requency doublers have long been used in radio frequency work; for example, to provide a high-frequency signal which is generated from a crystal or other oscillator having a lower frequency. These xequire components whose values and tolerances are not readily reproducible in sillcon MOS technology.
Frequency doublers can also be constructed utilizing phase lock loops. Use of phase lock loops requires comple~ cir-cuitry which requires large areas on silicon and results ln jitter (i.e., slight, but undesirable, shifts in frequency) in the final output signal. Frequency doublers using phase lock loop are des-cribed, for example, in "Phase Lock Techniques" p. 78, F.M. Gardner, John Wiley & Son, Inc. 1966.
SUMMARY
In accordance with the teachings of this invention, a unique frequency doubler circuit is utilized which requires only a handful of standard components such as operational amplifiers, logic gates, resistors, capacitors and switches. In contrast to certain prior art frequency doublers, frequency doublers con-, ~ .
~, .
~2~
structed in accordance with the teachings of this invention donot require the use of a phase lock loop, thereby resulting in a substantial simplification of circuit construc-tion. Further~
more, frequency doublers constructed in accordance with this invention utilize a feedback technicflle which assures that the duty cycle of -the output signal will be 50%, or any other pre-defined value.
Thus, in accordance with a broad aspect of the invention, there is provided a frequency doubler ci.rcuit comprising:
an input terminal for receiving an input signal;
an output terminal for providing an output signal hav-ing a frequency twice the frequency of said input signal;
adelay means having an input lead connected to said in-put terminal and having an output terminal;
an exclusive OR gate having a first input lead connected to said input terminal, a second input lead connected to said output lead of said delay means, and an output lead which pro-vides an intermediate signal having twice the frequency of said input signal; and means for adjusting the duty cycle of said intermediate signal to equal a desired duty cycle; and wherein said means for adjusting comprises:
means responsive to said intermediate signal which pro-vides a ramp voltage to increase in magnitude;
means for integrating said ramp voltage, providing an i ~~
~2~
- 2a -integrated voltage;
means for compariny said ramp voltage and said inte-grated voltage, thereby providing a locJical one output voltacJe when said ramp voltage is greater than said inte~rated voltage, and a l.ogical zero output voltaye when said ramp voltage is less than said lntegrated voltage.
BRIEE' DESCRIPTION OF THE DRAWINGS
Figure 1 is a schematic diagram of one embodiment of a frequency doubler constructed in accordance with the teachings of this invention;
Figure 2 is a graphical representation of the input signal Vin applied to the frequency doubler shown in Figure l;
Figure 3 is a graphical representation of the voltage V49 provided at node 49 of the frequency doubler shown in Figure l;
Figure ~ is a graphical representation of the voltage V50 provided at node 50 of the circuit of Figure l;
Figure 5 is a graphical representation of the voltage V51 provided at node 51 of the circuit in Figure l;
Figure 6 is a graphical representation of the output voltage VOUt provided by the circuit of Figure l;
Figure 7 is one embodiment of a delay means 12 shown in Figure l; and Figure 8 is one embodiment of an integrator which allows the frequency doubler of -this invention to provide an out-put signal oE other than 50% duty cycle.
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DETAILED DESCRIPTION
.
This invention relates -to electronic circuits for pro-viding an output signal having a frequency twice that o:E the in~
put signal.
Fxequency doublers areknown in the prior art and are used to provide an ou-tput signal which has a frequency haviny twice the frequency of an input signal. E'requency doublers have long been used in radio frequency work; for example, to provide a high-frequency signal which is generated from a crystal or other oscillator having a lower frequency. These xequire components whose values and tolerances are not readily reproducible in sillcon MOS technology.
Frequency doublers can also be constructed utilizing phase lock loops. Use of phase lock loops requires comple~ cir-cuitry which requires large areas on silicon and results ln jitter (i.e., slight, but undesirable, shifts in frequency) in the final output signal. Frequency doublers using phase lock loop are des-cribed, for example, in "Phase Lock Techniques" p. 78, F.M. Gardner, John Wiley & Son, Inc. 1966.
SUMMARY
In accordance with the teachings of this invention, a unique frequency doubler circuit is utilized which requires only a handful of standard components such as operational amplifiers, logic gates, resistors, capacitors and switches. In contrast to certain prior art frequency doublers, frequency doublers con-, ~ .
~, .
~2~
structed in accordance with the teachings of this invention donot require the use of a phase lock loop, thereby resulting in a substantial simplification of circuit construc-tion. Further~
more, frequency doublers constructed in accordance with this invention utilize a feedback technicflle which assures that the duty cycle of -the output signal will be 50%, or any other pre-defined value.
Thus, in accordance with a broad aspect of the invention, there is provided a frequency doubler ci.rcuit comprising:
an input terminal for receiving an input signal;
an output terminal for providing an output signal hav-ing a frequency twice the frequency of said input signal;
adelay means having an input lead connected to said in-put terminal and having an output terminal;
an exclusive OR gate having a first input lead connected to said input terminal, a second input lead connected to said output lead of said delay means, and an output lead which pro-vides an intermediate signal having twice the frequency of said input signal; and means for adjusting the duty cycle of said intermediate signal to equal a desired duty cycle; and wherein said means for adjusting comprises:
means responsive to said intermediate signal which pro-vides a ramp voltage to increase in magnitude;
means for integrating said ramp voltage, providing an i ~~
~2~
- 2a -integrated voltage;
means for compariny said ramp voltage and said inte-grated voltage, thereby providing a locJical one output voltacJe when said ramp voltage is greater than said inte~rated voltage, and a l.ogical zero output voltaye when said ramp voltage is less than said lntegrated voltage.
BRIEE' DESCRIPTION OF THE DRAWINGS
Figure 1 is a schematic diagram of one embodiment of a frequency doubler constructed in accordance with the teachings of this invention;
Figure 2 is a graphical representation of the input signal Vin applied to the frequency doubler shown in Figure l;
Figure 3 is a graphical representation of the voltage V49 provided at node 49 of the frequency doubler shown in Figure l;
Figure ~ is a graphical representation of the voltage V50 provided at node 50 of the circuit of Figure l;
Figure 5 is a graphical representation of the voltage V51 provided at node 51 of the circuit in Figure l;
Figure 6 is a graphical representation of the output voltage VOUt provided by the circuit of Figure l;
Figure 7 is one embodiment of a delay means 12 shown in Figure l; and Figure 8 is one embodiment of an integrator which allows the frequency doubler of -this invention to provide an out-put signal oE other than 50% duty cycle.
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DETAILED DESCRIPTION
2 One embodiment of a frequency doubler constructed in
3 accordance with the teachings of this invention is ~ho~m
4 in the schematic diagram of Figure 1. Frequency dowb-ler 10 includes input terminal 11 for receiving an inpwt 6 signal Vin having a frequency . Frequency doubler 10 7 also includes outpuk -te.rminal 24 for providing an output 8 voltage VOUt having a frequency 2f, double the frequency 9 of the input voltage Vin. The input signal Vin is shown in graphical form in Figure 2, and is typically within 11 the range of approximately 500Hz to 3KHz and has a duty 12 cycle within the range of approximately 30% to 70%.
13 Input signals having higher frequencies can be used, and 14 thus higher frequency output signals provided, if desired.
The input signal Vin is directly applied to one input 16 lead of exclusive OR gate 13. Input voltage Vin is also 17 applied to the input lead 12a of delay means 12, whose 18 output lead 12b is connected to the other input lead of n e~clt~
OR gate 13. Delay means 12 may comprise any suitable 2~ delay means, including a chain of inverters with capacitive ~1 loading on their output, as is shown in E'ig. 7. In one 22 embodiment of this invention, delay means 12 delays the 23 input signal Vin by a few microseconds prior to applying the delayed input signal to the second input lead of exclusive OR gate 13. It is generally desired that the 26 delay provided by delay means 12 be sufficient to allow 27 NOR gate 14 -to charge its output lead to the negative 28 supply voltage in order to provide a logical zero output 29 signal.
31 Exclusive OR gate 13 thus provides an output voltage 32 V49 (as shown in Figure 3) on output node 49. As can be 33 seen from Figure 3, V49 goes high for a short period of 34 time (approximately equal to the time delay provided by delay means 12) in response to each rising and falling 36 edge of input signal Vin. Thus, signal V49 has a fre-37 quency 2f, twice the frequency of input voltage Vin.
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a,, --However, signal V49 generally does no-t have a 50% duty cycle, as is often desired, but has a duty cycle of 2Tl/T2 where Tl = the delay provided by delay means 12; and T2 = l/f = the period of Vi .
The remainder of the circuit shown in Figure 1 serves to provide an output signal VOUt having a frequency of 2f, and which has a 50~ duty cycle.
Terminal 15 is connected to a positive supply voltage Vdd (typically 5 volts). Switches 16 and 18, together with cap-acitor 20, serve as a switched capacitor resistor equivalent. In the embodiment of this invention shown in Figure 1, switches 16 and 18 are N channel MOS -transistors being controlled by clock signals ~ and ~ , respectively. Switched capacitor resistor equivalents are well known in the prior art and thus will not be described in detail in this application. A more complete descrip-tion of the operation of a switched capacitor resistor equivalent is given by B. J. Hostica, R. W. Brodersen, P. R. Gray, in "MOS
Sampled Data Recursive Filters Using Switched Capacitor Integrat-ors", IEEE Journal of Solid State ~ircuits, Dec. 1977, pps. 600-609. Clock signals ~ and ~ preferably have a frequency f~ within the range of approximately 10KHz to ~00 K~z where the input signal has a frequency within the range of approximately lI~z to 50KEz The switched capacitor resistor equivalent formed by switches 16 and 18 and capacitor 20 serves to charge capacitor 21 to supply - 4a -voltage Vdd with -time constant (C21~C20) f~.
where C21 is the capacitance of capacitor 21 (typically approximately 20 picofarads);
C20 is the capacitance of capaeitor 20 (typically approximately l picofarad); and f~ is the frequency of clocks ~ and ~ .
7~
In one embodiment of this invention, a resistor is used 2 in place of switches 17, l9 and capacitor 20. This embodiment re~uires more area and provides less ~ield due 4 -to ~reater variations in resistance (where -the circuit is implemented usiny MOS technology) an~ -thus greater varia-6 tions in the result.ing time constant.
7 The voltage V50 thus generated on terminal 50 is 8 shown in Figure 4. Capacitor 21 is discharged when NOR
9 gate 14 provides a logical zero output signal which ~ occurs in one instance in response to a logical one 11 output signal from exclusive OR gate 13. Thus, when V49 12 goes high, the output signal of NOR gate 14 goes low and 13 voltage V50 follows this and is discharged as shown in 14 Figure 4-~6 Voltage comparator 22 has its inverting input lead 17 connected to node 50 and its noninverting input lead 18 connected to the output lead of operational amplifier 27.
19 The output signal V51 from comparator 22, which appears on node 51, is positive (lo~ical 1) when V50 is discharged 21 to a value less than the voltage which is provided on the 22 output lead of operational amplifier 27. The output lead 23 of operational amplifier 22 is connected to the input 24 lead of inverter 23, whose output lead is connected to output terminal 24 to provide the output signal VOUt and, 26 through resistor 25, to the noninverting input lead of 27 operational amplifier 27. Capacitor 26 is connected 2~ between the noninverting input lead of operational ampli-29 fier 27 and ground. Resistor 28 is~connec-te~ between ground and the inverting input lead of operational ampli-31 fier 27, and resistor 29 is connected between the invert-32 ing input lead of operational amplifier 27 and the output 33 lead o~ operational amplifier 27, thereby causing opera-34 tional amplifier 27 to have a closed loop gain of ~7 7~
1 G = 1 -~ (R29/R28 where G = the close~ loop gain of operational ~ amplifier 27 (typically 1 to 10~;
R2~ = the resistance of resistor 28; ~nd 6 R29 = the resistance of resi.stor 2g.
8 Capacitor 26 integrates the output voltage VOUt, and 9 operational amplifier 27 provides an amplified signal equal to G~VoUt dt to the noninverting input lead of operational ampli~ier 22.
~2 13 For stability, the voltage on the output lead of 14 operational amplifier 27 should be relatively constant.
This requixes that the result of the integration VOUt dt 16 when VOUt is high e~ual the result of the integration of 17 VOUt dt when VOUt is low. If this were not so, net 18 current would flow into the integrator and change the 19 output voltage. By providing the negative feedback through operational amplifier 27, the output signal VOUt 21 maintains a 50% duty cycle. For example, if the output ~2 signal VOUt has a duty cycle less than 50% such that 23 during each cycle VOUt remains a logical 0 longer than it ~4 remains a logical 1, the voltage stored on capacitor 26 will ~e less than when the duty cycle of VOUt is 50%.
26 With this decreased voltage applied to the noninverting 27 input lead of operational amplifier 27, operational 28 amplifier 27 provides a decreased output voltage to the 29 noninverting inpu-t lead of operational amplifi,er 22. The ~ output signal VS1 from operational amplifier 22 is a 31 logical 0 when the voltage V50 is greater than the output 32 voltage of operational amplifier 27, thereby causing ~51 33 to have a logical 0 value for a greater period of time, 34 which in turn causes the output signal VOUt to have a logical 1 output signal for an increased period o~ time.
36 Conversely, if the output signal VOUt has a duty cycle 37 greater than 50% such that during each cycle VOUt remains ~2~
a logical 1 longer than it remains a logical 0, the voltage stored on capacitor 26 will be greater than when the dut~
cycle of VOUt is 50%. With this increased voltage applie~
4 to the noninverting inpu-t lead of operational ampliier 27, operational amplifier 27 provides an increased outpu~
6 voltage to the noninverting input lead of operational 7 amplifier 22. The output signal V51 from operational 8 amplifier 22 is a logical 0 when the voltage V50 is ' greater than the ou-tput voltage of operati.onal ampli-fier 27, thereby causing V51 to have a logical 0 value 11 for a greater period of time, which in turn causes the 12 output signal VOUt to have a logical 1 output signal for 13 a increased period of time.
In this manner, the feedback provided by operational ~6 amplifier 27 provides output signal VOUt with a 50% duty 17 cycle.
1~
19 In an alternative embodiment of my invention, it is desired to provide an output signal VOUt having other than a 50% duky cycle. In this embodiment of my invention 22 integrator 127 (Figure 1) is replaced with integrator 227 23 of Figure 8. Integrator 227 of E'igure 8 is the same as, 24 with the addition of inverter 29 and buffer 30. Inverter 29 is an inverter r~ceiving as its input lead the output 2~ signal from operational amplifier 27. Buffer 30 is an 27 inverter receiving on its input lead the output signal 28 from inverter 29, and which provides an output signal on 29 output lead 27-1 to the noninverting input lead of opera-tional amplifier 22 (Figur~ 1). Buffer 30 is powered by 31 a positive reference voltage ~Vref and a negative reference 32 voltage -Vref which are generated in any one of a number 33 of ways well known in the prior art. The magnitudes of 34 +Vref and -Vref are selected to provide the desired duty cycle of the output signal VOUt provided on output lead 24 36 (Figure 1). Thus, the duty cycle is defined as:
38 D = (+Vref)/(¦+Vref~ Vref¦) 1 Thus, if a 60% duty cycle is desired, the magnitude of 2 Vref must be 1.5 times the magnitude of -Vref. Conversely, 3 iE a 25% duty cycle is desired, the magni-tude of -~Vref 4 must be one-third the magnitude of -Vref.
6 The specific embodiments of -this invention described 7 in this speciEication are intended to serve by way o,E
8 example and are not a limitation on the scope of my 9 invention. Mumerous other embodiments oE this invention will become apparent to those of ordinary skill in the 11 art in light of the teachings of this specification.
1~
~8 3~
13 Input signals having higher frequencies can be used, and 14 thus higher frequency output signals provided, if desired.
The input signal Vin is directly applied to one input 16 lead of exclusive OR gate 13. Input voltage Vin is also 17 applied to the input lead 12a of delay means 12, whose 18 output lead 12b is connected to the other input lead of n e~clt~
OR gate 13. Delay means 12 may comprise any suitable 2~ delay means, including a chain of inverters with capacitive ~1 loading on their output, as is shown in E'ig. 7. In one 22 embodiment of this invention, delay means 12 delays the 23 input signal Vin by a few microseconds prior to applying the delayed input signal to the second input lead of exclusive OR gate 13. It is generally desired that the 26 delay provided by delay means 12 be sufficient to allow 27 NOR gate 14 -to charge its output lead to the negative 28 supply voltage in order to provide a logical zero output 29 signal.
31 Exclusive OR gate 13 thus provides an output voltage 32 V49 (as shown in Figure 3) on output node 49. As can be 33 seen from Figure 3, V49 goes high for a short period of 34 time (approximately equal to the time delay provided by delay means 12) in response to each rising and falling 36 edge of input signal Vin. Thus, signal V49 has a fre-37 quency 2f, twice the frequency of input voltage Vin.
3~
~7 ~
a,, --However, signal V49 generally does no-t have a 50% duty cycle, as is often desired, but has a duty cycle of 2Tl/T2 where Tl = the delay provided by delay means 12; and T2 = l/f = the period of Vi .
The remainder of the circuit shown in Figure 1 serves to provide an output signal VOUt having a frequency of 2f, and which has a 50~ duty cycle.
Terminal 15 is connected to a positive supply voltage Vdd (typically 5 volts). Switches 16 and 18, together with cap-acitor 20, serve as a switched capacitor resistor equivalent. In the embodiment of this invention shown in Figure 1, switches 16 and 18 are N channel MOS -transistors being controlled by clock signals ~ and ~ , respectively. Switched capacitor resistor equivalents are well known in the prior art and thus will not be described in detail in this application. A more complete descrip-tion of the operation of a switched capacitor resistor equivalent is given by B. J. Hostica, R. W. Brodersen, P. R. Gray, in "MOS
Sampled Data Recursive Filters Using Switched Capacitor Integrat-ors", IEEE Journal of Solid State ~ircuits, Dec. 1977, pps. 600-609. Clock signals ~ and ~ preferably have a frequency f~ within the range of approximately 10KHz to ~00 K~z where the input signal has a frequency within the range of approximately lI~z to 50KEz The switched capacitor resistor equivalent formed by switches 16 and 18 and capacitor 20 serves to charge capacitor 21 to supply - 4a -voltage Vdd with -time constant (C21~C20) f~.
where C21 is the capacitance of capacitor 21 (typically approximately 20 picofarads);
C20 is the capacitance of capaeitor 20 (typically approximately l picofarad); and f~ is the frequency of clocks ~ and ~ .
7~
In one embodiment of this invention, a resistor is used 2 in place of switches 17, l9 and capacitor 20. This embodiment re~uires more area and provides less ~ield due 4 -to ~reater variations in resistance (where -the circuit is implemented usiny MOS technology) an~ -thus greater varia-6 tions in the result.ing time constant.
7 The voltage V50 thus generated on terminal 50 is 8 shown in Figure 4. Capacitor 21 is discharged when NOR
9 gate 14 provides a logical zero output signal which ~ occurs in one instance in response to a logical one 11 output signal from exclusive OR gate 13. Thus, when V49 12 goes high, the output signal of NOR gate 14 goes low and 13 voltage V50 follows this and is discharged as shown in 14 Figure 4-~6 Voltage comparator 22 has its inverting input lead 17 connected to node 50 and its noninverting input lead 18 connected to the output lead of operational amplifier 27.
19 The output signal V51 from comparator 22, which appears on node 51, is positive (lo~ical 1) when V50 is discharged 21 to a value less than the voltage which is provided on the 22 output lead of operational amplifier 27. The output lead 23 of operational amplifier 22 is connected to the input 24 lead of inverter 23, whose output lead is connected to output terminal 24 to provide the output signal VOUt and, 26 through resistor 25, to the noninverting input lead of 27 operational amplifier 27. Capacitor 26 is connected 2~ between the noninverting input lead of operational ampli-29 fier 27 and ground. Resistor 28 is~connec-te~ between ground and the inverting input lead of operational ampli-31 fier 27, and resistor 29 is connected between the invert-32 ing input lead of operational amplifier 27 and the output 33 lead o~ operational amplifier 27, thereby causing opera-34 tional amplifier 27 to have a closed loop gain of ~7 7~
1 G = 1 -~ (R29/R28 where G = the close~ loop gain of operational ~ amplifier 27 (typically 1 to 10~;
R2~ = the resistance of resistor 28; ~nd 6 R29 = the resistance of resi.stor 2g.
8 Capacitor 26 integrates the output voltage VOUt, and 9 operational amplifier 27 provides an amplified signal equal to G~VoUt dt to the noninverting input lead of operational ampli~ier 22.
~2 13 For stability, the voltage on the output lead of 14 operational amplifier 27 should be relatively constant.
This requixes that the result of the integration VOUt dt 16 when VOUt is high e~ual the result of the integration of 17 VOUt dt when VOUt is low. If this were not so, net 18 current would flow into the integrator and change the 19 output voltage. By providing the negative feedback through operational amplifier 27, the output signal VOUt 21 maintains a 50% duty cycle. For example, if the output ~2 signal VOUt has a duty cycle less than 50% such that 23 during each cycle VOUt remains a logical 0 longer than it ~4 remains a logical 1, the voltage stored on capacitor 26 will ~e less than when the duty cycle of VOUt is 50%.
26 With this decreased voltage applied to the noninverting 27 input lead of operational amplifier 27, operational 28 amplifier 27 provides a decreased output voltage to the 29 noninverting inpu-t lead of operational amplifi,er 22. The ~ output signal VS1 from operational amplifier 22 is a 31 logical 0 when the voltage V50 is greater than the output 32 voltage of operational amplifier 27, thereby causing ~51 33 to have a logical 0 value for a greater period of time, 34 which in turn causes the output signal VOUt to have a logical 1 output signal for an increased period o~ time.
36 Conversely, if the output signal VOUt has a duty cycle 37 greater than 50% such that during each cycle VOUt remains ~2~
a logical 1 longer than it remains a logical 0, the voltage stored on capacitor 26 will be greater than when the dut~
cycle of VOUt is 50%. With this increased voltage applie~
4 to the noninverting inpu-t lead of operational ampliier 27, operational amplifier 27 provides an increased outpu~
6 voltage to the noninverting input lead of operational 7 amplifier 22. The output signal V51 from operational 8 amplifier 22 is a logical 0 when the voltage V50 is ' greater than the ou-tput voltage of operati.onal ampli-fier 27, thereby causing V51 to have a logical 0 value 11 for a greater period of time, which in turn causes the 12 output signal VOUt to have a logical 1 output signal for 13 a increased period of time.
In this manner, the feedback provided by operational ~6 amplifier 27 provides output signal VOUt with a 50% duty 17 cycle.
1~
19 In an alternative embodiment of my invention, it is desired to provide an output signal VOUt having other than a 50% duky cycle. In this embodiment of my invention 22 integrator 127 (Figure 1) is replaced with integrator 227 23 of Figure 8. Integrator 227 of E'igure 8 is the same as, 24 with the addition of inverter 29 and buffer 30. Inverter 29 is an inverter r~ceiving as its input lead the output 2~ signal from operational amplifier 27. Buffer 30 is an 27 inverter receiving on its input lead the output signal 28 from inverter 29, and which provides an output signal on 29 output lead 27-1 to the noninverting input lead of opera-tional amplifier 22 (Figur~ 1). Buffer 30 is powered by 31 a positive reference voltage ~Vref and a negative reference 32 voltage -Vref which are generated in any one of a number 33 of ways well known in the prior art. The magnitudes of 34 +Vref and -Vref are selected to provide the desired duty cycle of the output signal VOUt provided on output lead 24 36 (Figure 1). Thus, the duty cycle is defined as:
38 D = (+Vref)/(¦+Vref~ Vref¦) 1 Thus, if a 60% duty cycle is desired, the magnitude of 2 Vref must be 1.5 times the magnitude of -Vref. Conversely, 3 iE a 25% duty cycle is desired, the magni-tude of -~Vref 4 must be one-third the magnitude of -Vref.
6 The specific embodiments of -this invention described 7 in this speciEication are intended to serve by way o,E
8 example and are not a limitation on the scope of my 9 invention. Mumerous other embodiments oE this invention will become apparent to those of ordinary skill in the 11 art in light of the teachings of this specification.
1~
~8 3~
Claims (2)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A frequency doubler circuit comprising:
an input terminal for receiving an input signal;
an output terminal for providing an output signal hav-ing a frequency twice the frequency of said input signal;
a delay means having an input lead connected to said input terminal and having an output terminal;
an exclusive OR gate having a first input lead con-nected to said input terminal, a second input lead connected to said output lead of said delay means, and an output lead which provides an intermediate signal having twice the frequency of said input signal; and means for adjusting the duty cycle of said intermediate signal to equal a desired duty cycle; and wherein said means for adjusting comprises:
means responsive to said intermediate signal which provides a ramp voltage to increase in magnitude;
means for integrating said ramp voltage, providing an integrated voltage;
means for comparing said ramp voltage and said integra-ted voltage, thereby providing a logical one output voltage when said ramp voltage is greater than said integrated voltage, and a logical zero output voltage when said ramp voltage is less than said integrated voltage.
an input terminal for receiving an input signal;
an output terminal for providing an output signal hav-ing a frequency twice the frequency of said input signal;
a delay means having an input lead connected to said input terminal and having an output terminal;
an exclusive OR gate having a first input lead con-nected to said input terminal, a second input lead connected to said output lead of said delay means, and an output lead which provides an intermediate signal having twice the frequency of said input signal; and means for adjusting the duty cycle of said intermediate signal to equal a desired duty cycle; and wherein said means for adjusting comprises:
means responsive to said intermediate signal which provides a ramp voltage to increase in magnitude;
means for integrating said ramp voltage, providing an integrated voltage;
means for comparing said ramp voltage and said integra-ted voltage, thereby providing a logical one output voltage when said ramp voltage is greater than said integrated voltage, and a logical zero output voltage when said ramp voltage is less than said integrated voltage.
2. The structure as in Claim 1 wherein:
said means for integrating is powered by a positive voltage source +Vref and a negative voltage source -Vref such that the duty cycle D of said output signal is defined as:
D = (+Vref)/(¦+Vref¦+¦-Vref¦)
said means for integrating is powered by a positive voltage source +Vref and a negative voltage source -Vref such that the duty cycle D of said output signal is defined as:
D = (+Vref)/(¦+Vref¦+¦-Vref¦)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/584,656 US4596954A (en) | 1984-02-29 | 1984-02-29 | Frequency doubler with fifty percent duty cycle output signal |
| US06/584,656 | 1984-02-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1217826A true CA1217826A (en) | 1987-02-10 |
Family
ID=24338276
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000475273A Expired CA1217826A (en) | 1984-02-29 | 1985-02-27 | Frequency doubler with 50 percent duty cycle output |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US4596954A (en) |
| EP (1) | EP0155041A3 (en) |
| JP (1) | JP2843320B2 (en) |
| CA (1) | CA1217826A (en) |
Families Citing this family (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4691170A (en) * | 1986-03-10 | 1987-09-01 | International Business Machines Corporation | Frequency multiplier circuit |
| CA1254957A (en) * | 1986-11-07 | 1989-05-30 | Mitel Corporation | Frequency doubler |
| JPH01320814A (en) * | 1988-05-23 | 1989-12-26 | Advanced Micro Devicds Inc | Circuit for multiplying frequency of a series of inputted pulses |
| US4885475A (en) * | 1988-09-09 | 1989-12-05 | United Technologies Corporation | Precision 50 percent duty cycle controller |
| DE4020977A1 (en) * | 1990-07-02 | 1992-01-16 | Broadcast Television Syst | CIRCUIT ARRANGEMENT FOR GENERATING A SYMMETRICAL PULSE SIGNAL |
| JP2861465B2 (en) * | 1991-05-16 | 1999-02-24 | 日本電気株式会社 | Frequency multiplier |
| US5227671A (en) * | 1992-04-14 | 1993-07-13 | Quantum Corporation | Circuit providing equalized duty cycle output |
| US5502419A (en) * | 1992-06-05 | 1996-03-26 | Canon Kabushiki Kaisha | Pulse width modulation signal generation and triangular wave signal generator for the same |
| US5812832A (en) * | 1993-01-29 | 1998-09-22 | Advanced Micro Devices, Inc. | Digital clock waveform generator and method for generating a clock signal |
| JPH07202649A (en) * | 1993-12-27 | 1995-08-04 | Toshiba Corp | Multiplier circuit |
| DE4407054C2 (en) * | 1994-03-03 | 1999-11-18 | Philips Patentverwaltung | Circuit arrangement for converting sinusoidal signals into rectangular signals |
| KR960009965B1 (en) * | 1994-04-14 | 1996-07-25 | 금성일렉트론 주식회사 | Circuit for multiplying a frequency |
| US5907254A (en) * | 1996-02-05 | 1999-05-25 | Chang; Theodore H. | Reshaping periodic waveforms to a selected duty cycle |
| US5757218A (en) * | 1996-03-12 | 1998-05-26 | International Business Machines Corporation | Clock signal duty cycle correction circuit and method |
| US5945857A (en) * | 1998-02-13 | 1999-08-31 | Lucent Technologies, Inc. | Method and apparatus for duty-cycle correction |
| US6066972A (en) * | 1998-10-13 | 2000-05-23 | International Business Machines Corporation | Differential receiver with duty cycle asymmetry correction |
| KR100533626B1 (en) * | 2003-04-01 | 2005-12-06 | 삼성전기주식회사 | Quadrature signal generator with feedback type frequency doubler |
| FR2879374B1 (en) * | 2004-12-15 | 2007-03-02 | Commissariat Energie Atomique | DOUBLE FREQUENCY DEVICE |
| JP4623286B2 (en) * | 2005-03-25 | 2011-02-02 | 日本電気株式会社 | Duty adjustment circuit |
| US7132863B2 (en) * | 2005-04-04 | 2006-11-07 | Freescale Semiconductor, Inc. | Digital clock frequency doubler |
| DE102006011448B4 (en) | 2006-03-13 | 2013-08-01 | Austriamicrosystems Ag | Circuit arrangement and method for providing a clock signal with an adjustable duty cycle |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3593156A (en) * | 1968-12-31 | 1971-07-13 | Gen Electric | Frequency doubler |
| US3601705A (en) * | 1969-04-02 | 1971-08-24 | Mobil Oil Corp | Frequency multiplication and displacement |
| JPS518551B1 (en) * | 1970-07-09 | 1976-03-17 | ||
| US3622210A (en) * | 1970-11-16 | 1971-11-23 | Bell Telephone Labor Inc | Transformerless frequency doubler |
| US3721766A (en) * | 1970-11-16 | 1973-03-20 | Motorola Inc | Frequency multiplying circuit utilizing time gates and switching signals of differing phases |
| US3648062A (en) * | 1970-11-16 | 1972-03-07 | Ford Motor Co | Wide-band noninductive frequency doubler |
| US3668489A (en) * | 1971-04-16 | 1972-06-06 | Gen Electric | Frequency doubler motor drive and motor |
| US3742353A (en) * | 1971-09-27 | 1973-06-26 | Parisi Ass Inc | Frequency measuring apparatus including phase locked loop |
| US3786357A (en) * | 1971-11-30 | 1974-01-15 | Gen Electric | Digital pulse train frequency multiplier |
| US3764927A (en) * | 1971-12-07 | 1973-10-09 | Gen Datacomm Ind Inc | Wide band frequency discriminator |
| US3721896A (en) * | 1971-12-23 | 1973-03-20 | Nippon Kokan Kk | Improved phase sensitive eddy current defect detector utilizing frequency doubling of detected signal prior to phase detection |
| US3771044A (en) * | 1973-02-21 | 1973-11-06 | Gte Laboratories Inc | Broad band frequency doubler and limiter utilizing magneto-resistive effect in a rotating magnetic field |
| US4048571A (en) * | 1973-03-12 | 1977-09-13 | Xerox Corporation | Frequency doubler |
| US3947780A (en) * | 1974-10-21 | 1976-03-30 | Mcdonnell Douglas Corporation | Acoustooptic mode-locker frequency doubler |
| US4042834A (en) * | 1975-06-12 | 1977-08-16 | Motorola, Inc. | Frequency doubler circuit |
| DE2549953C3 (en) * | 1975-11-07 | 1978-05-11 | Wabco Westinghouse Gmbh, 3000 Hannover | Circuit arrangement for obtaining output signals as a function of the output voltage of a sensor of an anti-lock device for motor vehicles |
| GB1550213A (en) * | 1975-12-08 | 1979-08-08 | Rca Corp | Frequency doubler |
| US4051386A (en) * | 1976-07-22 | 1977-09-27 | National Semiconductor Corporation | Frequency doubling circuit |
| US4077010A (en) * | 1976-12-08 | 1978-02-28 | Motorola, Inc. | Digital pulse doubler with 50 percent duty cycle |
| JPS53122351A (en) * | 1977-04-01 | 1978-10-25 | Hitachi Ltd | Generating circuit for double frequency signal |
| JPS5632825A (en) * | 1979-08-27 | 1981-04-02 | Shimadzu Corp | Frequency multiplying circuit |
| JPS5639624A (en) * | 1979-09-10 | 1981-04-15 | Hitachi Ltd | Pulse frequency multiplying circuit |
| JPS5778611A (en) * | 1980-10-31 | 1982-05-17 | Matsushita Electric Ind Co Ltd | Digital signal reproducing method |
| FR2497427A1 (en) * | 1980-12-29 | 1982-07-02 | Chazenfus Henri | CIRCUIT FOR ADJUSTING THE CYCLIC RATIO OF AN IMPULSE PERIODIC SIGNAL AND FREQUENCY MULTIPLIER DEVICE BY 2, INCLUDING THE ADJUSTING CIRCUIT |
| JPS57208723A (en) * | 1981-06-18 | 1982-12-21 | Seiko Epson Corp | Double-multiplication circuit |
| US4446389A (en) * | 1982-03-15 | 1984-05-01 | Ampex Corporation | Quadrature tach decoder circuit |
| JPS58191522A (en) * | 1982-05-04 | 1983-11-08 | Toshiba Corp | Frequency multiplier circuit for smiconductor integrated circuit |
-
1984
- 1984-02-29 US US06/584,656 patent/US4596954A/en not_active Expired - Lifetime
-
1985
- 1985-02-27 CA CA000475273A patent/CA1217826A/en not_active Expired
- 1985-02-27 EP EP85200265A patent/EP0155041A3/en not_active Withdrawn
- 1985-02-27 JP JP60036708A patent/JP2843320B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| EP0155041A2 (en) | 1985-09-18 |
| JPS60223319A (en) | 1985-11-07 |
| EP0155041A3 (en) | 1988-01-07 |
| US4596954A (en) | 1986-06-24 |
| JP2843320B2 (en) | 1999-01-06 |
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| Date | Code | Title | Description |
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| MKEX | Expiry |