CA1224556A

CA1224556A - System for switching trains of constant length data packets

Info

Publication number: CA1224556A
Application number: CA000443673A
Authority: CA
Inventors: Michel Servel; Alain Thomas
Original assignee: Individual
Current assignee: Individual
Priority date: 1982-12-29
Filing date: 1983-12-19
Publication date: 1987-07-21
Also published as: FR2538976A1; EP0113307B1; EP0113307A1; EP0113639B1; JPH0439820B2; FR2538976B1; DE3366490D1; EP0113639A1; DE3371450D1; US4603416A; JPS59135994A

Abstract

ABSTRACT

The system switches data packets, with headers, from input junctions to output junctions.
The series incoming packets are converted into parallel packets. The headers of cash incoming packet and the identity of the involved input junction are transferred to the address inputs of a control memory. The control memory supplies a new header which is assigned to the incoming packet, in replacement of the original header, in order to form the parallel outgoing packet with the remaining part of the incoming packet. A buffer memory is cyclically enabled for writing, in order to store the outgoing packets. Each parallel packet read out of the buffer memory is converted into a series packet which is assigned to the address multiplex. Queues store the addresses of a packet in the buffer memory, and are selectively enabled for writing, depending on information from the control memory. Each queue is assigned to an output junction. Responsive to a signal for indicating that one of the output junctions is enabled, the address contained in the corresponding queue is read, in order to find the output packet which is to be transferred to the outgoing junction in the buffer memory.

Description

01 The present invention relates to a TAM
02 (Time Division Multiplex) switching system for routing 03 pulse trains of constant length data packets. More 04 particularly, the invention relates to a TAM packet 05 switching system for use in processing various 06 services with various bit rates from a bit or a few 07 bits up to several Bits.
08 As an example, a multiple system carrying 09 synchronous packets each having a fixed length, is described in the cop ending Canadian patent application 11 serial No. 439,388, filed on October 20, 1983 by the 12 applicants and entitled "Synchronization for a digital 13 train intended for a correct framing of received 14 information". In that system, packets are data blocks with a fixed length of N bytes, for instance with 16 N=16. The first byte of the packet is the header for 17 identifying the packet being transmitted through the 18 multiplex system. The following fifteen bytes carry 19 the proper information. The multiplex medium is itself divided into time intervals having a fixed 21 length which is equal to the one of a packet. A time 22 interval may be either idle when it does not contain 23 any packet, or busy when it contains a packet. In the 24 first case, the byte value in the time slot corresponding to the label is zero, while, for any 26 busy time interval, it may usually be one of the 27 remaining 255 combinations.
28 In a PAM circuit multiplex, the time slots 29 are implicitly identified by their positions in each multiplex frame. In a packet multiplex of the above 31 mentioned type, each packet also occupies a constant 32 time interval, but is also identified by an explicit 33 address on the eight bits. A purpose of the invention 34 is to take advantage of that analogy for providing a synchronous packet multiplex switching system.
36 For guidance, the TAM switches used for so 01 switching n-channel multiplex digital telephone lines 02 are described in the technical book "La commutation 03 electronic" (Electron witching) by GRI~SEC, pages 04 247-252. In such TAM switches, the switching function 05 makes it possible to route the contents of any time 06 slot of any input multiplex Mecca to any time slot of 07 any output multiplex M~XSj. In particular, in the 08 through-output controlled TAM switches designed to 09 ensure a broadcasting function, the incoming time slots are stored at a well defined place in a buffer 11 memory. A control memory, which is programmed when 12 the communications are being established, assigns to 13 each outgoing channel the address of the place in the 14 buffer memory wherein the contents of the time slot will have to be transferred to the associated outgoing 16 channel. Outgoing channels are cyclically scanned and 17 control memory is also read cyclically.
18 A purpose of this invention is to provide 19 a synchronous packet switching system wherein the packets are considered as time intervals each with an 21 explicit address, so that those functions may be used 22 which exist in the through-output controlled TAM
23 switches. Essentially, the packet switching function 24 gives a new identification to each incoming packet which has been identified by the rank number of the 26 incoming multiplex carrying it and its header. The 27 new identification comprises two attributes of the 28 same type, i.e. a new header and the rank number of 29 the outgoing multiplex which the packet will be applied to. That is to say, the packet (Eli), e being 31 the number of the incoming multiplex and i the header, 32 is changed into a packet so with s being the number 33 of the outgoing multiplex and ] the new header.
34 In such a switching operation, the packet (Eli) must be processed before being stored in the 36 buffer memory. Indeed, it is submitted to a "header so 01 change or header switching" which corresponds to a 02 time slot change in a conventional TAM circuit 03 switching. The processing is controlled by a control 04 memory which has been programmed by the time the 05 packet communication is established. Thus, the header 06 1 is replaced by the header I. Then, the packet (e, 07 j) is stored at a known address in the buffer memory, 08 depending on the write time defined by e. That 09 address is stored in a queue associated with the outgoing multiplex s. Since the system is a 11 through-output control system, during the outgoing 12 multiplex scanning cycle, the queue associated with 13 the outgoing multiplex s is scanned in order to get 14 the address of the next packet to be carried by the outgoing multiplex s. As in TAM switches, the packet 16 data are stored in the buffer memory.
17 More particularly, in the above described 18 system, the whole packet has implicitly been submitted 19 to a series-to-parallel conversion before being written into the buffer memory, as in TAM switches.
21 In TAM switches, each channel is a 8-bit word. The 22 presently available 8-bit series-to-parallel 23 converters are fast enough to be used in those TAM
24 switches. With respect to packet switching, each packet is obviously made of several bytes, for 26 instance sixteen bytes as described in the above 27 mentioned Canadian patent application. Therefore, the 28 time required for parallel converting a whole packet 29 is substantially longer.
Furthermore, in a packet switch, once the 31 bytes have been parallel converted, the incoming 32 packets carried by each multiplex are always 33 transferred into a memory assigned to that multiplex 34 and used as an input queue or Fife (first in, first out) memory.
36 In a packet switch, the series-to-parallel 55~i 01 converter of the sequence of parallel bytes operates 02 at a time with a single input queue, i.e. a single 03 input multiplex, the set of input queues having to be 04 processed in a complete cycle, the duration of which 05 it the series transmission duration ox a packet. But 06 Fife memories implementing the queues are relatively 07 slow operating components. For the series-to-parallel 08 conversion of a packet, it is necessary to get access 09 sixteen times to the concerned queue, which requires an excessively long time and which limits the 11 processing capacity of the system. It is the same at 12 the output for the parallel-to-series conversion.
13 Another purpose of the invention is to 14 overcome that slowness in order to have a packet switching matrix with a performance which is 16 compatible with the flow rates of the video 17 communication services.
18 According to this invention, for avoiding 19 the mentioned waste of time, the series-to-parallel conversion of the input byte queues is replaced by 21 successive simultaneous permutations of bytes for the 22 set of the incoming multiplex, and for other 23 successive permutations for the set of outgoing 24 multiplex. Because the control logic circuitry, which comprises the control memory alone, can scan only one 26 label per byte slot, the labels of the packets from 27 different ingoing multiplex are chained one after the 28 other before being processed. To this end, a time 29 shift of one byte slot is provided in the input queues, from one queue to the following one. The 31 series-to-parallel converter is replaced by a rotation 32 matrix capable of performing a controllable rotation 33 on groups of N bytes (16 bytes). The rotation order 34 is incremented step-by-step, for each byte slot. At the output of the rotation matrix, data are in a 36 "parallel-diagonal" form which will be fully explained 12~S'~6 01 in the following specification. The data are stored 02 in the parallel-diagonal form in the buffer memory.
03 The parallel-to-series converter is also made of a 04 cyclically controlled rotation matrix which performs 05 the reverse shifts with respect to the input rotation 06 matrix shifts, in the reverse duration.
07 Thus, according to the present invention 08 in its most general form, there is provided a 09 switching system for switching a plurality of multiplexed groups of signals each of which comprise 11 time intervals containing fixed length data packets, 12 the multiplexed group of signals being incoming from a 13 plurality of input junctions which are being switched 14 toward a plurality of output junctions, each incoming or outgoing packet having a header and a series packet 16 having a train of bits, the switching system 17 comprising, a first conversion circuit coupled to an 18 input junction for receiving and converting the train 19 of bits of the packets from a plurality of incoming multiplexed groups of signals into parallel packets, 21 a programmable control memory circuit for transmitting 22 the header and the identity of the input junction 23 carrying an incoming packet, circuitry responsive to 24 the data output of the control memory circuit for delivering a translated header assigned to the 26 parallel incoming packet in replacement of its 27 original header, the translated header forming an 28 outgoing parallel packet with the remaining part of 29 the incoming packet, buffer memory circuitry which is cyclically enabled for a write operation for storing 31 the outgoing parallel packets, second conversion 32 circuitry responsive to a read out of the buffer 33 memory circuitry for converting each outgoing parallel 34 packet into a series packet which is assigned to an address multiplexed group of signals, a plurality of 36 queue circuits for storing the addresses of the so 01 outgoing parallel packets which are stored in the 02 buffer memory, the queue circuits being selectively 03 enabled for write operations in response to 04 information which is delivered from other data outputs 05 of the control memory, each of the storing queue 06 circuits being assigned to one of the output 07 junctions, and circuitry responsive to a signal 08 indicating that an output junction is enabled for 09 reading the address stored in the corresponding queue circuit, in order to find the outgoing packet for the 11 junction in the buffer memory.
12 The above mentioned features of the 13 present invention, as well as others, will appear more 14 clearly from the following description of a number of embodiments, the description being made in conjunction 16 with the accompanying drawings, wherein:
17 Figure 1 is the schematic diagram of a 18 packet switching matrix according to this invention, 19 Figure 2 is the schematic diagram of an input circuit, with an input queue, used in the matrix 21 shown in Figure 1, 22 Figures 3a-3f show waveforms illustrating 23 the operation of the circuit shown in Figure 2, 24 Figure 4 is a schematic diagram illustrating the operation of another embodiment of 26 the switching matrix according to this invention, 27 Figure 5 is a diagram illustrating the 28 relative positions of the input multiplex systems 29 before they enter the input rotation matrix, Figure 6 is a diagram illustrating the 31 positions of the multiplex systems after they have 32 entered the input rotation matrix, 33 Figure 7 is a diagram illustrating the 34 positions of the multiplex systems after they have entered the output rotation matrix, 36 - pa --~Z2 So 01 Figure 8 is a schematic diagram of a 02 switching matrix according to this invention, 03 Figures 9 and 10 are schematic diagrams of 04 transfer circuits used in the matrix shown in Figure 05 8, 06 Figure 11 is the schematic diagram of a 08 - 5b -I I

01 concentrator according to this invention, 02 Figure 12 is a schematic diagram of a 03 management circuit for processing the calls of the 04 concentrator shown in Figure 11, 05 Figure 13 is a block diagram of a 06 switching stage based on -the principle of the 07 switching matrix according to this invention, 08 Figure 14 is a schema-tic diagram of a 09 circuit of the switching stage shown in Figure 13, Figure 15 is a detailed diagram of a part 11 of the circuit shown in Figure 14, and 12 Figure 16 is a time diagram relative to 13 the operation of the part of circuit shown in Figure 14 15.
The block diagram shown in Figure 1 shows 16 a first embodiment of a switching matrix that is a 17 major component of the TAM packet switch according to 18 this invention. The data packets appearing on the 19 incoming junctions or multiplex El-E16 are to be switched in order to be transmitted over junctions or 21 multiplex Sluice. Each multiplex El to Eye, which 22 transmits a binary train, is connected to the input of 23 an input circuit Cell to SUE.
24 In each input circuit, shown in Figure 2, the input multiplex E is connected to the input of a 26 series-to-parallel converter s/p which supplies 27 parallel bytes. The output of converter s/p is 28 connected to the input of an input Fife queue FE, via 29 an 8-wire link D10-D17. The multiplex E is also connected to the input of a synchronization detection 31 circuit STY which analyses the incoming train and first 32 supplies the synchronization byte HE through a wire 33 Hoot, second supplies a "1" signal DO for each first 34 byte of a packet applied to the queue FE, through a wire if, and third supplies a "1" signal PUP each time 36 the processed packed is not idle, through a US
01 wire Pi.
02 The wire if is connected to a data input 03 of the queue FE. The queue memory FE is capable of 04 storing 9-bit words. Indeed the queues in circuits 05 Cell to SUE (Figure 1) are used for "aligning" the set 06 of incoming multiplex. The size of each queue must be 07 greater than 16 9-bit words. In practice, the 08 circuits Cell to SUE are the above mentioned time 09 shifting means for the incoming multiplex El-E16, the shifting being so that the headers of the outgoing 11 multiplex from circuits Silas are supplied 12 simultaneously, or, on the contrary, are sequentially 13 supplied as it will be explained later on.
14 As shown in Figure 2, the data inputs to the queue FE are applied over wires D10-D17 to the 16 converter s/p, and over the output wire if from the 17 synchronization detection circuit STY. The write clock 18 input of queue FE is connected from the output of an 19 AND gate PIE having a first input connected from the wire Hoot.
21 The signals transmitted on the wires 22 D10-D17, Hoot, if and Pi are depicted in Figures pa to 23 Ed, respectively.
24 Furthermore, the data outputs of the queue FE are connected to eight wires D00-D07 which transmit 26 the useful data, and a wire f2 which transmits the 27 packet beginning signal STY which, at the output, 28 corresponds to DO, at the input. The read clock input 29 is connected from the output of an AND gate PAL having its first input connected from one output HO of a 31 local time base BTL, which is pleziochronous with the 32 clock HE. (Pleziochronous means almost, but not 33 necessarily exactly, synchronized). The second input 34 of the AND gate PIE is a write enabling input VEX and the second input of the AND gate PAL is a read 36 enabling input AL In addition, the queue FE has an I

01 output PI whose output signal, when at "1", indicates 02 that the queue is empty and, when at "0", indicates it 03 is not empty.
04 The write enabling input VIE is connected 05 from the output of an AND gate Pal which has a first 06 input connected from the wire Pi, and a second input 07 connected from the output Q of a flip-flop BYE of the 08 type D. The set input of flip-flop BYE is connected 09 from the output of an AND gate PF2 which has a first input connected from the wire if, and a second input 11 connected from the output TV which is at "1" when the 12 queue is empty. The input D of flip-flop BYE is 13 connected from an AND gate PF4 having one input 14 connected from the output of an three-input RAND gate PF3. The other input of gate PF4 is connected from 16 the output of the flip-flop BYE. Therefore, the 17 flip-flop BYE can be set to "1" only by the output 18 signal of the gate PF2. The first input of the gate 19 PF3 is connected from the output of an inventor Ill whose input it connected from the output TV of queue 21 FE. The second input of gate PF3 is connected from 22 the output of an inventor IF whose input is connected 23 from the wire f2. The third input of gate PF3 is 24 connected from an output STY of the time base BTL, via a wire f3. The clock input of the flip-flop BYE is 26 connected from the clock output HO of BTL.
27 The signals HO and STY are provided by the 28 time base BTL on wires HO and f3 respectively as shown 29 in Figures ye and of, respectively. It appears that the signal STY on the wire f3 is a local frame 31 synchronizing signal, i.e. a signal delivered each 32 time sixteen pulses Hi have been emitted. In 33 practice, the width of the pulse STY is equal to one 34 cycle of signal HO and is forward shifted by a half-cycle with respect to an effective read-out 36 controlled by signal HO. That guard time of a half ~Z2 ~5S6 01 byte slot allows some negative drift during the 02 reading of the packet. Indeed, the signal STY may be 03 produced in the time base BTL by a simple divider by 04 16 circuit responding to signal AL, the initial time 05 of the divider operation being controlled as will be 06 described in the following specification.
07 The read enable input AL is connected from 08 the output Q of a flip-flop BVL having its input D
09 connected from the output of the invert Ill and its clock input is connected from the wire f3.
11 In normal operation, the flip-flop BYE is 12 at "1", the signals f2 and f3 are synchronous and the 13 queue is not empty. The output of the gate PF3 is at 14 "1", and the output Q of flip-flop BYE is at "1".
Since the output of the gate Pal is at "1". the 16 writing of the packets is enabled in the queue at the 17 rhythm or clock rate of the write clock HE. If the 18 queue FE is not empty, the input D of the flip flop 19 BVL is at "1". Therefore, the clock input f3 of BVL
enables the read out of the queue for the duration of 21 the next frame. In practice, the signal on the wire 22 if advances in the queue FE in parallel with the first 23 data octet which has been entered.
24 In the absence of the signal STY on wire f2 at the time the signal STY appears on wire f3, and 26 with the queue FE not empty, the output of the gate 27 PF3 turns to "0". The corresponding level is 28 transmitted to the write enable input through the 29 flip-flop BYE. The writing is therefore inhibited.
In such a condition, the flip-flop BYE will keep the 31 condition "0" as long as its set input is not 32 activated by the condition "queue empty" Aided with a 33 packet beginning signal DO on wire if.
34 Indeed, while the write operation is inhibited, the read-out operation goes on as long as 36 the queue is not completely empty, i.e. as long as 37 _ 9 _ so;

01 output signal from inventor Ill is "1". When the 02 queue has been emptied, the read-out operation is 03 interrupted by the next occurrence of the signal STY.
04 The queue FE being empty, flip-flop BYE in 05 condition "0" can only be set to "1" when wire if is 06 turned to the "1" level at the beginning of the next 07 incoming packet. As soon as flip-flop BYE has turned 08 its condition, write operation may resume unless the 09 next incoming packet is idle, which will be considered in the following specification. In the queue FE, the 11 first written byte of this packet is practically 12 immediately available at the queue output, with a bit 13 "1" applied to wire f2. Since the queue is no longer 14 empty, at the occurrence of a signal STY, the read-out operation is resumed through flip-flops BVL and PAL, 16 and gate in addition the gate PF3 confirms the normal 17 operation.
18 When an idle packet is detected in the 19 synchronization detection circuit STY, signal PUP is at "0", which inhibits the write operation.
21 In practice, the synchronization detection 22 circuit STY may be constituted by the circuit shown in 23 Figure 2 of the above mentioned cop ending Canadian 24 patent application serial No. 439,388, supplemented by a divider-by-eight for providing the signal HE.
26 Indeed, in that circuit, counter CT2 delivers the 27 signal DO and output of comparator COUP may be used 28 for delivering the signal PP. The output Hoot of 29 circuit STY is further connected to the serial-to-parallel converter s/p to ensure a correct 31 conversion of the train of bits into a train of 32 bytes. Alternatively, the circuit shown in Figure 2 33 of the present invention may comprise logic means for 34 canceling the contents of the Fife memory or queue FE
as soon as the output of RAND gate PF3 turns to "0".
36 In this case, the link Lo does not carry useless 01 bytes.
02 In the present embodiment, the multiplex 03 El-E16 (Figure I are connected from various sources 04 which are not normally synchronized. Therefore, the 05 packet labels or headers that they are carrying enter 06 the queues of the input circuits Silas at various 07 times. As a result therefrom, there is initially no 08 reason for having the headers simultaneously read at 09 the outputs of the queues. The logic circuitry, shown in Figure 2, enables the alignment of the read out on 11 the external reference STY supplied through wire f3.
12 Indeed, as here above mentioned, the output on wire f3 13 of the time base BTL determines the read out time of 14 each first packet byte in each queue.
The eight outputs D00-D7 of the circuits 16 Cell to SUE (Figure 1) are respectively connected to 17 the corresponding inputs of a multiplexer MY via 18 8-wire links Lo. The output of multiplexer MY is 19 connected to the input of a series-to-parallel converter s/p, shown in Figure 1. The converter s/p 21 delivers each complete incoming packet on an output 22 link Lo having 128 wires. The four output wires Lo of 23 a counter-by-sixteen C0, are connected to the control 24 input of the multiplexer MY. By means of counter C0, the multiplexer MY sequentially scans the outputs of 26 the queues of the input circuits, so that the packets 27 are ordered as shown in Figure 1, a packet El from the 28 junction El proceeding a packet En from the junction 29 En, and cyclically so on. In the link Lo, the first eight wires carry the header byte and are connected to 31 the address input of a control RAM memory MY, through 32 a link Lo. The data output of the control memory MY
33 comprises 24 wires, the first eight wires constituting 34 a 8-wire link Lo. The last 120 wires of the link Lo constitute the link Lo which is associated with the 36 link Lo for constituting a 128-wire link Lo, which I ~LSS6 01 carries the new header ] of the packet. The link Lo 02 is connected to the data input of a packet buffer 03 memory MT.
04 The last sixteen output wires of the 05 control memory MY constitute a link Lo which carries 06 the identity of the output junction or multiplex S
07 through which the concerned packet is to be 08 transmitted. The link Lo is connected to the write 09 control inputs of queues Fluff, the data inputs of which are connected from the 8-bit output of the time 11 base BTL. The 8-bit output of the time base BTL is 12 also connected to the write input E of a multiplexer 13 Mel whose output is connected to the address input of 14 the buffer memory MT. The read input L of the multiplexer Mel is connected to the outputs of the 16 queues Fluff. At last, the write/read control input 17 E/L of the multiplexer Mel is connected to an output H
18 of the time base BTL.
19 The output of the buffer memory MT is connected to the input of a parallel-to-series 21 converter P/S, through a 128-wire link Lo. The 22 converter P/S has sixteen groups of outputs 23 respectively connected to the inputs of sixteen 24 parallel-to-series converts p/s, through 8-wire links L10. The outputs of the converters p/s are 26 respectively connected to the output junctions or 27 multiplexes Sluice. In the converter P/S, the 28 process is reversed with respect to the one performed 29 in the converter S/P, i.e. the 128 parallel input bits are converted into a series of sixteen bytes, the 31 bytes being in parallel and sequentially transmitted 32 through the links L10. In the converters p/s, the 33 bytes are converted into a train of bits.
34 The switch shown in Figure 1 operates as follows. In the queues, the read speed is higher than 36 the write speed. Therefore, the read-out is triggered So 01 only when the queue contains a sufficient amount of 02 information, i.e. a complete packet. In the converter 03 S/P, the packet from El, if any, then the packet from 04 En, if any, and so on, are converted into parallel 05 form. During the time while one packet is being 06 transmitted over the input multiplex, sixteen packets 07 are supplied in succession through link Lo. In each 08 transmission cycle on link Lo, the packets are 09 identified by their rank e. Through the link Lo, the memory MY is addressed by the header i of the packet 11 having the rank e. In response, memory MY delivers 12 the new header through link Lo and the new rank s 13 through link Lo, so that the addressee multiplex is 14 determined in the case there is only one addressee.
Meanwhile the rest of the packet is stored 16 in the buffer memory MT via link Lo, the storing 17 address of the concerned packet is stored in the queue 18 having the rank s among the queues Fluff. It will be 19 noticed that the packets transmitted through link Lo have a new header which has been substituted for 21 original header 1. For reading the packets from the 22 buffer memory MT, the outputs of the queues Fluff are 23 scanned cyclically, so that those queues transmit in 24 sequence the addresses which are then transmitted through the multiplexer Mel. Therefore, at a given 26 time is of a cycle, the queue Us supplies the address 27 of the packet to be read from the buffer memory MT via 28 the link Lo. Since the packet has the rank s in the 29 cycle, the converter P/S transmits it to the output multiplex So, through the associated converter p/s.
31 Accordingly, it appears that a packet 32 having a header 1, which has been applied through the 33 multiplex He, is outgoing through the multiplex So 34 with the header I. Thus, the switching is really performed, and it should be clearly understood that, 36 when the packet communication is established, the I I

01 central control unit UCC has chosen the substitution 02 pair (s, j) for the pair (e, i) and has stored it in 03 the control memory MY at the address (e, i).
04 In the schematic diagram of the Figure 4, 05 the operation of a second embodiment of a switching 06 matrix according to the invention is illustrated in a 07 simple manner.
08 The switching matrix shown in Figure 4 09 comprises an input rotation matrix MORE and an output rotation matrix MARS, instead of the converters S/P and 11 P/S. The input matrix MORE has sixteen 8-wire inputs 12 which are respectively connected from links Cluck, 13 each of them carrying a packet multiplex wherein the 14 bytes are transmitted in parallel. It will be assumed that the relative time positions of the multiplex 16 carried by links Cluck are shown in Figure 5.
17 In Figure 5, each packet is shown as being 18 included in a long rectangle in full lines, and the 19 sixteen bytes of every packet are identified by their ranks 1 to 16. The multiplex which are respectively 21 carried by the junctions Cluck are designated by the 22 references Cluck in the left-hand column. It appears 23 that the multiplex from C2 is ahead by one byte slot 24 in advance of the multiplex from Of. Likewise, the multiplex from C3 is ahead by one byte slot in advance 26 of the multiplex from C2, and so on. Therefore, the 27 bytes "1" of the packets are shifted ahead by one byte 28 slot, from one row to the next one, i.e., the bytes 29 "1" form an apparent downward and forward oblique or diagonal line with respect to the time axis. In other 31 words, at a given time interval, a byte "1" is present 32 on the line Of, a byte "2" on the line C2, a byte "3"
33 on the line C3, .. a byte "16" on the line C16. At 34 the next time interval, a byte "2" is present on the line Of, a byte "3" on the line C2, .. and a byte "1"
36 on the line C16. Assuming that, at this time 01 interval, the byte "1" of the line C16 is physically 02 shifted to the line Of, the byte "2" of the line Of to 03 the line C2, the byte "3" of the line C2 to the line 04 C3, ... the byte "16" of the line C15 to the line C16;
05 then, at the next time interval, the byte "1" of the 06 line C15 is physically shifted to the line Of, the 07 byte "2" of the line C16 to the line C2, the byte "3"
08 of the line Of to the line C3, and so on, with an 09 additional shift for each next time interval. The configuration of Figure 6 will be obtained. It is 11 this physical shift which is performed by the input 12 rotation matrix MORE of Figure 4.
13 Therefore, the bytes are really arranged 14 as shown in Figure 6 when they are delivered on the sixteen 8-wire outputs Dl-D16 of the matrix MORE.
16 Thus, if, at the time To, the byte "1" of a packet is 17 delivered on output Do, the byte "2" of the same 18 packet will be delivered on output Do at the time To, 19 the byte "3" on output Do at the time To, and so on until the byte "16" is delivered on output D16 at the 21 time T16. Each packet looks like it is diagonally 22 arranged on the outputs Do to D16.
23 It should be noted that the eight wires of 24 the output Do sequentially deliver all the bytes "1", i.e. the headers of the incoming packets from links 26 D16-Cl. As a result, the physical situation is quite 27 similar to the one of the switching matrix shown in 28 Figure 1 as far as the headers are concerned. Thus, 29 the headers are sequentially delivered from the output Do and may be processed in a control memory such as MY
31 for replacing them by new headers.

32 In Figure 4, the output Do of the rotation 33 matrix MORE is connected to the input of a switching 34 and header converting circuit ACE, the output of which is connected to the input of a buffer memory Ml 36 through an 8-wire link. Furthermore, the outputs sluice 01 D2-D16 of the matrix MORE are respectively connected to 02 the inputs of the buffer memories M2-M16, through 03 8-wire links. The memories Ml-M16 form a data buffer 04 memory which has the same function as the memory MT in 05 the circuit shown in Figure 1 However, the time 06 positions of the multiplex delivered from outputs 07 Dl-D16, as shown in Figure 6, are such that, in the 08 data buffer memory formed by buffer memories Ml-M16, 09 the packets are arranged according to the configuration shown in Figure 6.
11 Obviously, the circuit ACE is provided 12 with a control memory which is able to perform the 13 conversion of the headers.
14 The outputs of the memories Ml-M16 are respectively connected to the corresponding inputs 16 Fluff of the output rotation matrix MARS, via 8-wire 17 links. The matrix MARS has sixteen 8-wire outputs 18 Gl-G16 which are connected to the output junctions or 19 multiplex of the switching matrix through parallel/series byte converters.
21 The outputs Gl-G16 are cyclically 22 processed for reading out the packets stored in the 23 memory M. Therefore, at the inputs Fluff, the 24 relative positions of the packets have a configuration similar to the one shown in Figure 6. Thus, the 26 packet which is to be delivered from output Go is 27 diagonally arranged with respect to time on the inputs 28 Fluff. That packet is followed by the packet which 29 is to be delivered from output Go, and so on.
As to the packet to be delivered from 31 output Go, at the time To, the output rotation matrix 32 MARS transmits directly to output Go the byte from 33 input Fly at the time To, the matrix MARS shifts the 34 byte applied to input F2 for transmitting it to output Go; at the time input To, the byte applied to F3 is 36 shifted and transmitted to output Go, and so on. In lZ2, I

01 the rotation matrix MARS, the bytes are shifted in the 02 opposite direction with respect to the shifting 03 operations in the matrix MORE.
04 Obviously, at the time To, the byte 05 applied to the input Fly is shifted and transmitted 06 from the output D16, and so on. Thus, the respective 07 positions at the outputs Gl-G16 are similar to the 08 respective positions on the inputs Cluck, as shown in 09 Figure 7.
Figure 8 gives a detailed diagram of one 11 embodiment of the circuit broadly shown in Figure 4.
12 The input junctions or multiplex El-E16 are connected 13 to the inputs Cluck of an input rotation matrix MORE, 14 through input circuits Silas. The data output Do of the matrix MORE is connected to the first eight 16 address inputs of a RAM memory MY in the circuit ACE, 17 through an 8-wire link. The outputs D2-D16 are 18 connected to the inputs of memories M2-M16, as shown 19 in Figure 4.
An 8-stage counter CUTS connected from a 21 time base BTL has a 4-wire output e for transmitting 22 the four low weight bits, the output e being connected 23 to the control input of a demultiplexer circuit AIR
24 which has sixteen outputs f3.1-f3.16 respectively connected to the inputs f3 of the input circuits 26 Silas. The cyclic operation of counter CUTS results 27 in having a level "1" circulating on the output 28 f3.1-f3.16. The signals sequentially applied to the 29 wires f3.1-f3.16 under control of the counter CUTS are thus time shifted so that the first bytes in the input 31 circuits Silas are read one after the other. As a 32 result, the outgoing packets have the time positions 33 illustrated in Figure 5.
34 Four second address inputs of the memory MY are connected to the link e. The link e is also 36 connected to the control input ODE insuring the US

01 shifting operations in the input rotation matrix MORE.
02 The counter CUTS is connected, through a 03 8-wire link K, first, to the input E of a multiplexer 04 Mel, second, to the data inputs of output address 05 queues FSl-FS16, and, third, to the input of an adder 06 +1 which adds 1 to the address it receives from 07 counter CUTS. The output of the adder Al is connected 08 in parallel to the respective inputs E of multiplexes 09 MX2-MX16, through 8-wire links. It is not necessary to provide the adder, but it keeps the oblique 11 configuration of the packets in the memories Ml-M16, 12 taking into account the byte period which is used for 13 analyzing a header in the circuit ACE.
14 The output of memory MY is connected to its output register R through 24 wires. The first 16 eight outputs of register R are connected to the input 17 of the buffer memory Ml through a link I, and the last 18 sixteen outputs are separately connected to the write 19 control inputs of the output address queues FSl-FS16.
The clock input of register R is connected to the 21 output of clock H in the time base BTL, the output H
22 being synchronized with the read clock HO mentioned in 23 Figure 2.
24 The outputs of memories Ml-M16 are connected to transfer circuits CTRl-CTR16 whose 26 outputs are respectively connected to the inputs 27 Fluff of the output rotation matrix MRS.
28 In the transfer circuit Curl, shown in 29 Figure 9, the output of the memory Ml is connected to the first group of the 8-wire inputs of a multiplexer 31 Mel having two input groups, the second input group 32 being connected to a potential corresponding to the 33 bit "0". The output of multiplexer Mel is connected 34 to the input Fly of matrix MRS.
In the transfer circuit CTR2, shown in 36 Figure 10, the four odd output wires, the wires being 122 ~5S6 01 numbered 0,1,...,7, from memory My are respectively 02 connected to the first inputs owe a multiplexer MV2A, 03 while the four even outputs wires are respectively 04 connected to the first inputs of a multiplexer MV2b.
05 The second inputs of the multiplexer MV2a are 06 connected to a potential corresponding to the bit "0", 07 while the second inputs of the multiplexer MV2b are 08 connected to a potential corresponding to the bit 09 "1". The four output wires of the multiplexes MV2a and MV2b respectively form the odd and even output 11 wires of the transfer circuit CTR2, which are 12 connected to the input F2 of the output rotation 13 matrix MRS.
14 The structure of every transfer circuit CTR3-CTR16 is the same as circuit CTR2 shown in Figure 16 10.
17 The control inputs of the circuits Curl to 18 CTR16 are respectively connected from the 19 corresponding outputs of a 16-bit register REV (Figure 8). The data input of the register REV is connected 21 from the output of a multiplexer MUGS, and its clock 22 input is connected to the output of clock H of BTL.
23 The sixteen inputs of the multiplexer MUGS are 24 connected from the output wire "queue empty" of the queues FSl to FS16. The control input of multiplexer 26 MUGS is connected to the link e.
27 The outputs G1-G16 of the matrix MARS are 28 respectively connected to the output junctions or 29 multiplex S1-S16.
The shift control input CUDS of the matrix 31 MARS receives the data from the link e, after each bit 32 has been reversed in an inventor. The link e is also 33 connected, on one hand, towards a demultiplexer TRY
34 and, on the other hand, towards the control input of a multiplexer IFS. The sixteen separate outputs of the 36 demultiplexer TRY are separately connected to the read Lo sty 01 inputs of the queues FSl-FS16. In the demultiplexer 02 TRY the binary number transmitted through link e is 03 decoded into a read order, formed on the appropriate 04 wire, in order to control the reading of an address in 05 one of the queues FSl-FS16.
06 The data outputs of queues FSl-FS16 are 07 connected to the corresponding inputs of the 08 multiplexer IFS, through sixteen 8-wire links 09 LSl-LS16. The 8-wire OlltpUt of the multiplexer IFS is connected to the input of a counter-register All.
11 The 8-wire output of the counter register All is 12 connected, on one hand, to the input L of the 13 multiplexer Mel, and, on the other hand, to the input 14 of a counter register ADELE. The 8-wire output of the counter register ADELE is connected on one hand, to the 16 input L of a multiplexer MCCOY, and, on the other hand, 17 to the input of the next counter register ADELE, and so 18 until the counter register ADELE.
19 Each counter register ADLl-ADL16 is connected, on one hand, to the output H of the base 21 time clock BTL through its loading input or count 22 function selection input, and, on the other hand, to 23 another output OH of BTL through it selected function 24 enabling input. The frequency of signals from output OH is twice the frequency of signals from output H.
26 The 8-wire outputs of multiplexes 27 MXl-MX16 are respectively connected to the address 28 inputs of memories Ml-M16. The write/read control 29 inputs E/L of multiplexes MXl-MX16 are connected from OUtpllt H, for selecting either the group associated 31 with the input E, carrying the write addresses, or the 32 group associated with the input L carrying the read 33 addresses.
34 The operation of the switching circuit shown in Figure 8 will now be described. The 36 operation of the input circuits Silas has been 1~455~

01 already described with reference to Figures 1-3. The 02 input rotation matrix MORE may be one of the circuits 03 called "Rotate Matrix" or 'shift Matrix" available on 04 the market in technology EEL look under the 05 No. 100158. When shifted, the output Do transmits the 06 header 1 to the memory MY which also receives via link 07 e the rank number of the input junction from counter 08 CUTS. From the addresses e and i, the memory MY
09 supplies the new header and the identity s of the appropriate output junction or multiplex So.
11 Meanwhile, the counter CUTS delivers a number out of 12 28, which represents the address Aid at which the 13 header is to be written into memory Ml. Also at the 14 same time, the address Aid is stored in the queue FSl-FS16 which is designated by the value s from 16 output of register R of control memory MY. Still, at 17 the same time, the header is written. The function 18 of the adder +1 has been already described. As a 19 result, the bytes 2-15 of the packet having the new header will be successively written into the 21 corresponding memories M2-M6, with the oblique 22 configuration of Figure 6.
23 It should be noted that memories Ml-M16 24 are provided for 16x16 packets and are therefore addressed through eight wires.
26 The sixteen queues FSl-FS16 are cyclically 27 scanned, from the time base BTL, through the link e 28 and the demultiplexer TRY The information carried by 29 the link e is also used for selecting the input of the multiplexer IFS which is connected to the queue 31 selected by the demultiplexer TRY The inventors IN, 32 which are mounted between the link e and the input ODE
33 of the output rotation matrix MARS, are provided for 34 ensuring that matrix MARS will operate in the reverse direction with respect to the input matrix MORE.
36 During the first half of a byte slot, the 01 address Aid of the packet header is transmitted to the 02 counter register All, from the output of which, and 03 through multiplexer Mel, the memory Ml is addressed 04 for read-out operation. During the second half of a 05 byte slot, the counter of the register All is 06 incremented by 1 and the memory Ml is addressed for 07 writing through multiplexer Mel. At the next byte 08 slot, the counter register All transmits its contents 09 to the counter register ADELE, and, from multiplexer lo IFS, it receives a new address found in the next if queue. Thus, at this time, and during the first half 12 byte slot, the memory My may be addressed for read-out 13 operations. From the contents of the register ADELE
14 and through multiplexer MCCOY, i.e. the second byte of the packet may be read. During the second half byte 16 slot, the counter register ADELE is incremented by l.
17 At the next byte slot, the byte 3 may be read from the 18 contents of ADELE, and so on.
19 Thus, it appears that the bytes of a packet are read in sequence from the memories Ml-Ml6, 21 at addresses varying from Aid to Audi).
22 Furthermore, the control information of the output 23 rotation matrix MARS varies at each byte slot. The 24 bytes of a packet are sequentially delivered from the same output Go. In the associated parallel-to-serial 26 converter p/s, the bytes are converted into a train of 27 bits. The incoming packet with its modified header is 28 available on the desired output junction.
29 It is noted that the frequency of signals from output OH performs two operations in one byte 31 slot.

32 The control memory MY is a 4Kx24 RAM
33 memory programmed from outside, by the control unit 34 UCC. As here above stated, it assigns to each packet from an incoming multiplex a new header corresponding I to the outgoing multiplex So, corresponding to the or 01 queue(s) FSi that will be enabled in parallel for 02 writing, depending on the status of the sixteen output 03 wires S from the register R associated with the 04 control memory MY. The address of the first byte of 05 the concerned packet, marked by CUTS, is stored in the 06 enabled queue(s) FSi. Thus, it appears that the 07 switching matrix according to the invention, not only 08 can transmit the packets point by point, but also 09 allows them -to be broadcasted when several queues FSi are marked.
11 When the queues FSl-FS16 are empty, their 12 outputs deliver the value 0. It means that no packet 13 is to be sent on the corresponding multiplex, or else, 14 that the transmitted packet must have a null header if, as here above mentioned, it is desired to use the 16 synchronization mode described in the above mentioned 17 Canadian patent application. When the output "queue 18 empty" wire of a queue FSi, enabled by the 19 demultiplexer TRY is at "1", indicating that the scanned queue is empty, the signal "1" appears at the 21 output of the multiplexer MUGS, so that the first 22 output wire of the register REV is at "1", connecting 23 the multiplexer Mel (Figure 9) of Curl to the bit 24 potential "0". Thus, a null byte is supplied by Mel on the input Fly At the next time of the clock H, the 26 bit "1" of register REV is on the next wire, and, in 27 transfer CTR2, multiplexes MV2a and MV2b are 28 respectively connected to the bit potentials "1" and 29 "0". Therefore, multiplexes MV2a and MV2b (Figure 10) deliver to the input F2 a byte made of "1" and "0"
31 in alternance~ The process is the same for -the next 32 byte slots and the transfer circuits CTR3 (Mesa, MV3b) 33 to CTR16 (MV16a, MV16b). A packet is thus constituted 34 with a null header and a succession of "1" and "0" in alternance.
36 In Figure 11, there is shown a packet Shea 01 concentrator which practically operates as the 02 switching circuit shown in Figure I.
03 Before describing in detail the 04 concentrator shown in Figure 11, it will be noticed 05 that a concentrator may be directly realized from the 06 matrix of Figure 8, by reducing the number of 07 junctions at the output, i.e. the number of 08 multiplexes. However, it seems better to have a 09 greater number of input junctions while keeping the same number of output junctions. This solution is 11 carried into effect in the concentrator shown in 12 Figure 11.
13 The concentrator shown in Figure 11 has 32 14 input junctions El-E32 which are connected to the input circuits Silas, the Fife output TV, 16 indicating that the queue is not empty, is connected 17 to a service call wire de which is at "1" when the 18 queue contains information. Further, the wire f3 is 19 connected to a read control wire Ye which is enabled for controlling the reading of the queue. The 21 32-wires de and the 32-wires Ye are connected to a 22 call processing circuit GO, of which an embodiment is 23 shown in detail in Figure 12.
24 In Figure 12, the 32-wires de are respectively connected to the corresponding inputs of 26 a rotation matrix Marl whose control input is 27 connected, through a 5-wire link, from a counter CUP
28 which is controlled by the clock output H of the time 29 base BTL, the 32-wire output of the matrix Marl being connected to the input of a priority encoder COP. The 31 5-wire output of the encoder COP is connected to the 32 input of a decoder TRY which has 32 output wires 33 connected to the inputs of a rotation matrix MR2, the 34 control input of the latter being connected from the counter CUP, and its 32 output wires constituting the 36 wires Ye. An encoder TRY is also connected to the ,556 01 wires Ye for converting the information present on one 02 of said wire into a 5-bit word supplied to the output 03 MAD.
04 In Figure 11, the output MAD is connected, 05 on one hand, to the corresponding input of a control 06 memory MOO. The output of the register Rev is 07 connected, on one hand, to the control input of a 08 multiplexer Melt and, on the other hand, to the input 09 of a register REV. The output of the register REV is connected, on one hand, to the control input of a 11 multiplexer ME (not shown), and, on the other hand, 12 to the input of a register REV (not shown), and so on, 13 until a register ROY associated with a multiplexer 14 MOE.
Each multiplexer MEl-ME16 has 32 8-wire 16 inputs which are respectively connected from the 17 outputs of the 32 input queues FEl-FE32. The outputs 18 of the multiplexes MEl-ME16 are equivalent to the 19 outputs Dl-D16 shown in Figure 8, and are connected to the control memory MOO and the buffer memory MT
21 respectively. The sixteen 8-wire outputs of the 22 buffer memory MT are connected to the corresponding 23 inputs of an output rotation matrix MRS.
24 The concentrator shown in Figures 11 and 12 operates as follows. The wires de of the input 26 circuits Cell to SUE are enabled when the associated 27 queues contain information. In the rotation matrix 28 Marl (Figure 12), the calls applied to the inputs are 29 shifted under control of the cyclic counter CUP. In the priority encoder COP, which may be realized with 31 the commercially available circuits BCLlOOK 100165, 32 the marked input which has the highest priority is 33 selected, and the code of that input is delivered from 34 the output of the encoder. Thus, the output wire of the decoder TRY which corresponds to the code 36 delivered from COP is enabled. In the rotation matrix ~z,~S5~i 01 MR2 which is controlled in synchronism with the matrix 02 Marl, the order of the enabled input is shifted in the 03 opposite direction, so that, through the wire Ye, the 04 queue which is controlled is the one which has been 05 chosen by the priority encoder circuit COP. In short, 06 one of 32-wires is chosen with a rotating priority.
07 Furthermore, the encoder TRY delivers a 08 5-bit code word corresponding to the enabled output 09 wire of MR2. The output word of encoder TRY is transmitted to the register Rely and, in the 11 multiplexer Melt the input corresponding to the queue 12 Fez (the letter "i" means any of the queues FEl-FE32) 13 of the circuit Cell chosen by COP is selected by the 14 output of register Rely Thus, the header of the first packet contained in the concerned queue Fez is 16 transmitted to the control memory MOO through 17 multiplexer Melt In the memory MOO, the header is 18 modified, as here above described with reference to 19 Figure 8.
At the next byte slot, the content of 21 register Rev is loaded into the register REV. The 22 register Rev being also loaded again. Thus, at this 23 byte slot, the input of the multiplexer ME which 24 corresponds to the queue Fez is selected by the contents of register REV. The concerned queue 26 transmits its second byte which is transmitted to the 27 memory My of buffer memory MT. This process is 28 repeated until the multiplexer MOE is reached.
29 At this time, at shifted addresses, the buffer memory MT contains the packet of which the 31 configuration is memory MT which is the one shown in 32 Figure 6. At the output, the rotation matrix MARS
33 restores the normal structure, i.e. the packet is 34 transmitted to a single output junction, as it has been described with reference to the circuit shown in 36 Figure 8.

lo is 01 From the above, and except for the time 02 shifts and the permutations, it appears that the 03 concentrator of Figure 11 is very similar to a 04 switching matrix. The control memory MOO it addressed 05 from the packet header and the 5-bit word supplied by 06 the encoder To this word defining the geographical 07 address of the incoming multiplex. At the output, the 08 addressing is made as in the matrix of Figure 8.
09 Switching matrices with unblocked capacity 16x16 may be grouped for obtaining unblocked 11 structures of greater size. It is also possible to 12 realize switching system structures of the "extended 13 T" type, as in TAM circuit switching.
14 The block diagram shown in Figure 13 shows how a matrix 32x32 may be realized, according to this 16 invention, from two parallel identical modules having 17 a capacity 32x16. The structure of the modules 32x16 18 is shown in Figure 14.
19 The switching stage of the module comprises two input groups El to Eye and Eye to Eye.
21 The inputs El-E16 are connected to the inputs of an 22 input rotation matrix Morel, through byte converters 23 s/p and input circuits (not shown). The inputs 24 EYE are likewise connected to the inputs of an input rotation matrix MRE2. The matrices Morel to MRE2 26 operate as the matrix MORE shown in Figure 8.
27 The outputs Do and Do of the matrices 28 Morel and MRE2 are respectively connected to the 29 corresponding inputs of two memories MY and MY', through 8-wire links. The other four addressing 31 inputs of those memories MY and MY' are connected in 32 parallel to the output of a time base clock BTL. The 33 first eight data outputs of the memories MY and MY' 34 are respectively connected to the inputs of the buffer memories Ml and Mel, each of them being a part of one 36 of two groups of buffer memories EMT and EMT'. As the I

01 memory MT shown in Figure 8, the memory EMT comprises 02 sixteen buffer memories Ml-M16, and the memory Em' 03 comprise sixteen buffer memories M'l-M'16.
04 The outputs D2-D16 of rotation matrix Morel 05 are respectively connected to the data inputs of the 06 memory M2-M16, and the outputs D'2-D'16 of MREZ are 07 respectively connected to the data inputs of the 08 buffer memories M'2-M'16. The outputs of the buffer 09 memories Ml and Mel are connected to the input Fly of an output rotation matrix MARS, through a wired OR
11 gate; the outputs of the buffer memories My and Moe 12 are likewise connected to the input Fly of the matrix 13 MRS. The outputs Gl-G16 of matrix MARS are connected 14 to the outputs of the stage, through converters (not shown).
16 The memories EMT and EMT' are read from 17 the queues Hi to H16 which are similar to the queues 18 FSl to FS16 of the circuit shown in Figure 8. The 19 write control inputs of the queues Hl-H16 are respectively connected to the outputs of the circuits 21 Pulp. Each circuit Pal to POW has two inputs 22 which one respectively connected from the output wires 23 having the same rank in the last sixteen outputs of 24 each memory MY and MY'.
Figure 15 is the detailed scheme of a 26 circuit Pi associated with a queue Hi. The write 27 input HO of each queue Hi is connected to the output 28 of an AND gate Pal, having a first input connected 29 from the clock output OH of the time base BTL and a second input connected from the output of an OR gate 31 PRY. The two inputs of the OR gate PRY are respectively 32 connected from the outputs of two AND gates PX2 and 33 PX3. One input of the AND gate PX2 is connected from 34 the sty output wire of the memory MY, the other input being connected from the clock output H of the time 36 base BTL. One input of the AND gate PX3 is connected I So 01 from the sty output wire of the memory MY', the other 02 input being connected from the clock output H of the 03 time base, through an inventor IV.
04 The system shown in Figures 14 and 15 05 operates as follows. Either the group comprising 06 rotation memory Morel, memory MY, buffer memories EMT, 07 or the group comprising rotation memory MRE2, memory 08 MY', buffer memories EMT', operates as the group MORE, 09 MY, MT as Figure 8 operates. However, the read system of the buffer memories is different. A packet 11 addressed to a given output may simultaneously come 12 from two incoming multiplexes respectively coming from 13 two input blocks. Therefore, it is necessary to have 14 the possibility of making two address writings in the involved queue(s) Hi. Such a result is obtained with 16 the circuit shown in Figure 15.
17 In a clock cycle H (Figure 16), one half 18 of the time is assigned to the scanning of the write 19 calls issuing from the memory MY, the other half being assigned to the write calls of the memory MY'. The 21 two significations signals are successively conveyed 22 to the corresponding input of the gate Pal which 23 samples them at the double rate of the clock OH.
24 Then, the writing operation may take place with the sampled signals. In the case illustrated by the 26 signal Ha of Figure 16, there are (1) no writing 27 operation for a first cycle of the clock H, (2) one 28 writing operation for the next cycle, (3) two writing 29 operations for the last cycle.
Furthermore, the signal delivered from the 31 gate PX2 is loaded into the queue Hi as a Thea bit 32 indicating either the buffer memory EMT or EMT' in 33 which will be the packet of which the address is 34 loaded in Hi. The gth bit will be used for enabling the output of one of the two buffer memories.
36 In the above description, the packets have ~z~ss~

01 n=16 bytes corresponding to the number of incoming or 02 outgoing multiplexes, but it will be understood that 03 the system according -to the invention generally allows 04 the processing of a multiple integer of k of n bytes.
05 In this case, in the circuits of Figures 1 and I, the 06 header substitution and the switching control are 07 cyclically performed only once in k times.

Claims

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A switching system for switching a plurality of multiplexed groups of signals each of which comprise time intervals containing fixed length data packets, the multiplexed group of signals being incoming from a plurality of input junctions which are being switched toward a plurality of output junctions, each incoming or outgoing packet having a header and a series packet having a train of bits, the switching system comprising:
first conversion means coupled to an input junction for receiving and converting the train of bits of the packets from a plurality of incoming multiplexed groups of signals into parallel packets;
programmable control memory means for transmitting the header and the identity of the input junction carrying an incoming packet, means responsive to the data output of said control memory means for delivering a translated header assigned to the parallel incoming packet in replacement of its original header, said translated header forming an outgoing parallel packet with the remaining part of the incoming packet;
buffer memory means which is cyclically enabled for a write operation for storing the outgoing parallel packets;
second conversion means responsive to a read out of the buffer memory means for converting each outgoing parallel packet into a series packet which is assigned to an address multiplexed group of signals;

a plurality of queue means for storing the addresses of the outgoing parallel packets which are stored in the buffer memory, said queue means being selectively enabled for write operations in response to information which is delivered from other data outputs of the control memory, each of said storing queue means being assigned to one of the output junctions; and means responsive to a signal indicating that an output junction is enabled for reading the address stored in the corresponding queue means, in order to find the outgoing packet for said junction in the buffer memory.

2. A system according to claim 1, wherein the first conversion means comprise processing means for converting each series packet into an incoming diagonal packet of which the bytes are respectively delivered from n outputs, while keeping their original time order, so that any header of any packet is delivered from the first output.

3. System according to claim 2, wherein the buffer memory comprises n individual memories, a chain of n serial mounted counter-registers, the queue means having data outputs which are selectively coupled to give access to the inputs of said chain of n serially mounted counter-registers, the n counter-registers being individually associated with the n memories which supply read addresses for said memories, the counter-registers moving and incrementing address information with the chain to read the information which is converted into diagonal packets.

4. The system according to claim 2 wherein the conversion means comprise shifting means for timely shifting of an incoming multiplexed group of signals so that the headers of the various multiplexed groups of signals do not occur simultaneously, said headers being delivered in sequence to the first input.

5. The system according to claim 3 wherein the conversion means comprise shifting means for timely shifting of an incoming multiplexed group of signals so that the headers of the various multiplexed groups of signals do not occur simultaneously said headers being delivered in sequence to the first input.

6. The system according to claim 2, wherein the processing means comprise an n-step rotation matrix, with n outputs and n inputs.

7. The system according to claim 3, wherein the processing means comprise a n-step rotation matrix, with n output and n inputs.

8. The system according to claim 4, wherein the processing means comprise a n-step rotation matrix, with n output and n inputs.

9. The system according to claim 5, wherein the processing means comprise a n-step rotation matrix, with n output and n inputs.

10. The system according to claim 1, wherein there are n additional input junctions, the first conversion means comprising a circuit for detecting the presence of information at the input junctions to select one of said junctions, and means for converting the packet received from the selected junction into n bytes which are delivered in parallel.

11. The system according to claim 4, wherein the shifting means comprise a buffer FiFo queue which receives data from a multiplexed group of signals associated with an incoming junction, and logic circuit means for controlling a write-read operation in the queue, so that when the queue is not empty a packet is supplied in synchronism with an external reference clock.

12. The system according to claim 5, wherein the shifting means comprise a buffer FiFo queue which receives data from a multiplexed group of signals associated with an incoming junction, and logic circuit means for controlling a write-read operation in the queue, so that when the queue is not empty a packet is supplied in synchronism with an external reference clock.

13. The system according to claim 6, wherein the shifting means comprise a buffer FiFo queue which receives data from a multiplexed group of signals associated with an incoming junction, and logic circuit means for controlling a write-read operation in the queue, so that when the queue is not empty a packet is supplied in synchronism with an external reference clock.

14. The system according to claim 7, wherein the shifting means comprise a buffer FiFo queue which receives data from a multiplexed group of signals associated with an incoming junction, and logic circuit means for controlling a write-read operation in the queue, so that when the queue is not empty a packet is supplied in synchronism with an external reference clock.

15. The system according to claim 8, wherein the shifting means comprise a buffer FiFo queue which receives data from a multiplexed group of signals associated with an incoming junction, and logic circuit means for controlling a write-read operation in the queue, so that when the queue is not empty a packet is supplied in synchronism with an external reference clock

16. The system according to claim 9, wherein the shifting means comprise a buffer FiFo queue which receives data from a multiplexed group of signals associated with an incoming junction, and logic circuit means for controlling a write-read operation in the queue, so that when the queue is not empty a packet is supplied in synchronism with an external reference clock.

17. The system according to claim 2, wherein the second converting means comprise a n-step rotation matrix with n inputs and n outputs, said inputs being coupled to receive data from the buffer memory.

18. The system according to claim 3, wherein the second converting means comprise a n-step rotation matrix with n inputs and n outputs, said inputs being coupled to receive the data from the buffer memory.

19. The system according to claim 4, wherein the second converting means comprise a n-step rotation matrix with n inputs and n outputs, said inputs being coupled to receive the data from the buffer memory.

20. The system according to claim 5, wherein the second converting means comprise a n-step rotation matrix with n inputs and n outputs, said inputs being coupled to receive the data from the buffer memory.

21. The system according to claim 6, wherein the second converting means comprise a n-step rotation matrix with n inputs and n outputs, said inputs being coupled to receive the data from the buffer memory.

22. The system according to claim 7, wherein the second converting means comprise a n-step rotation matrix with n inputs and n outputs, said inputs being coupled to receive the data from the buffer memory.

23. The system according to claim 2, wherein the bits of the packets are arranged in bytes.

24. The system according to claim 17, 18 or 19, wherein each packet comprises n integer of n bytes, wherein the integer is at least one.

25. The system according to claim 20, 21 or 22, wherein each packet comprises n integer of n bytes, wherein the integer is at least one.