CA1229880A - Local modulated carrier data network with a collision avoidance protocol - Google Patents

Abstract

LOCAL MODULATED CARRIER DATA NETWORK
WITH A COLLISION AVOIDANCE PROTOCOL
Abstract of the Disclosure There is disclosed an improved modem for a single frequency, modulated RF carrier local data network for a distributed data processing system and a method for line acquisition and contention resolution. The protocol established for line acquisition and contention resolution is implemented by a modem controller. The controller causes the receiver section to listen for foreign carriers to determine when the line is busy. When the client device of the modem desires to send a data packet to another unit, the modem controller causes the receiver to listen for a certain pre-burst period and then causes the transmitter to send a non data bearing burst of RF carrier out on the line and simultaneously causes the receiver to listen to the line for interference beating, i.e. changes in amplitude on the line which indicates another unit is requesting the line. To insure beat patterns, the frequency of the burst carrier is swept over a range during the burst. If a contention is found, a resolution thereof is made utilizing a random delay and retry protocol. After the burst, the controller causes the receiver to listen to the line for other carriers. If none are found, the controller causes the transmitter to transmit a data packet preceded by a preamble of 100%
modulation level RF carrier. During the preamble period, all receivers in the system set their respective automatic gain control levels to a level for comfortable reception. The gain level so established depends upon the strength of the received signal. This amplification level is maintained throughout the entire data packet. In this manner, the transmission line is acquired prior to the transmission of data packets, thus preventing the

Description

sack round Of The Invention g The invention relates to the field of local data networks, and~ more particularly, to the field of contention resolution protocols for local data networks using modulated RF carriers.
As the computer using segment of the population has yrown, it has become more important to share expensive assets among multiple users. For example in large companies with large mainframe CPU's, their associated peripherals, and large central data bases, as well as numerous local devices/ task processors and terminals used by indivdual employees and subdivisions of the company, it is advantageous to have the remote users be able to share the assets o~ the mainframe CPU. Thus it is advantageous to have the remote task processors be able to send and receive data from the main CPU, tap the main data bases and be able to print data and ~tore and retrieve data using the printers and magnetic storage media of the main CP~ .
Many companies already have existing coaxial cable networks in place to transmit video ~or security or cable television channels. To avoid having to install a new set of cables for the computer system it is advantageous to be able to use existing video coaxial cable for the distribu~ed data processing system"
Some systems using modulated RF carriers to transmit data exist in the prior art. However, such systems typically utilize repeaters and head end retransmission apparatus and are more expensive. For example, the head end retransmission appara~us of cable tele~ision systems is designed to receive data at one frequency and convert it to data of another fre~uency for retransmission on the cable. The repeaters in the cable have t~o separate amplifiers, each connected to the same ca~le, and wi~h one for each direction~ ~ecause the output of one amplifier must be connected to the input of the other t unless each 1s works at a different frequency, the repeaters will oscillate. Where different frequencies are used, a head end retransmission unit is necessary. Different cables for transmission and reception could be ~lsed but this too requires head end apparatus and the use of two cables is more expensive. It is advantageous to eliminate the need for repeaters and head end apparatus and to use a system and protocol which makes it possible to transmit and receive on the same frequency because a simpler~ less expensive system results.
Broadband systems have a major problem with detection of colliding transmissions. In the prior art, there have been schemes proposed to solve this problem. One such scheme adopted by the I.E.E.E. is the so-called token passing scheme. In these systems a token signal is passed around the system and only the unit which has the token can transmit. However, these schemes can be inefficient where the unit which has the token has nothing to transmit at the time and passes the token along but needs to transmit a data packet soon after the token is passed. In such a case, the unit m~st wait until the token comes around again before it can transmit.
It is important that contention resolution protocols be adopted to avoid colliding transmissions.
Summary O The Disclosure There is disclosed herein apparatus and a method for transmitting and receiving serial data on a transrnission medium utilizing modems which transmit and receive sinyle frequency modulated RF carriers and which incorporate a contention resolution scheme to a~oid colliding transmissions. There is no need for repeaters or head end retransmission apparatus in the disclosed system.
The apparatus of the local data network disclosed herein as the preferred embodiment consists of coaxial cable with a plurality of taps on the line, two taps for each modem. Howe~er, the concept could easily be used in ~z~

other embodiments utilizing fiber optic cable or other transmission mediums. To each pair of taps there is connected a transceiver modem with transmit and receive sections which work at the same frequency RF signal. In a fiber optic system, a single color would be used. Each modem can be coupled to additional devices through an optional multiplexer. ~he transceiver is controlled by a modem controller which causes the receiver to listen for other carriers on the line during the non-transmitting state. When a client device connected to the modem desires to send data, after deciding the line is quiet~
the modem controller causes the transmitter to send an access burst of 100~ modulated radio frequency carrier and cause~ the recei~er to listen or amplitude chanyes on the line caused by interference beating between the access burst and any other carrier on the line. To insure beating, the modem controller causes the frequency of the access burst to be swept over a range of frequencies during the burst.
If inter erence is found, a random d~lay co~.t~olled by a random number generator occurs prior to retry If no intererence is found during the burst, the modem controller causes the receiver to listen for a certain post burst period. If no foreign carrier is detected on the line, the modern controller causes a data packet preceded by a preamble of 100~ rnodulated RF carrier to be sent.
During the preamble of the data packet1 the automatic gain control circuits of all modems on the line cause their receiver gain leve1s to ~e adjusted depending upon the signal strength at their locations on the lin~. The automatic gain control level established in each receiver during the preamble is held constant throughout the data packet.

Brief Description Of The Drawin~s Figure 1 is a drawing of a typical prior art computer installation using parallel connections.
Figure 2 is a prior art local data network using coaxial cable and baseband data transmission.
Figure 3 is a sample pulse train of data pulses as transmitted on the coaxial cable of Figure 2.
Figure 4 is a system diagram of the units in a local distributed processing system such as might use the invention described herein.
Figure 5 is a waveform diagram of a modulated RF
carrier used to transmit data between the units of the system of Figure 4.
Figure 6 is a block diagram of the modem of ~he invention.
Figures 7A and B are a general flow chart of steps in the protocol follo~ed by the modem of Figure 6.
Figures aA and 8B are a detailed logic diagram of the modem control engine.
Figure 9 is a state flo~ diagram showing the states the modem control engine can assume and the paths between states.
Fig~res 1~A - C are a detailed flow chart of the separate steps in the line acquisition and collision avoidance protocol e~tablished by the modem control englne.
Figure 11 is a detailed schematic of the modulator, RF
amplifier and diode switch oF the transmitter.
Eigure 12 is a detailed logic diagram of the data encoder of the transmitter.
Pigure l3 is a detailed logic diagr~m of the active tap, RF amplifier, demodulator, AGC ramp generatort manual gain control, sample and hold circuit, burst switch and the burst gain control of the receiver~
Figure 14 is a detailed schematic diagram of the A/D
converter, carrier detect, threshold d~tect and sample and hold control circuits of the r~ceiver.

Figure 15 is a detailed logic diagram of the data decoder in the receiver.
Detailed Descri tion Of The Preferred E~bodiment p Referring to Figure 1 there is shown a typical S parallel cable computer installation. The computer or CPU
30 is coupled to its various peripherals 32, 34 and 36 by parallel conductor cables 38, 40 and 42. These cables carry data, address and control signals to and from the units of the system.
The system shown in Figure 1 is inade~uate for distributed processing systems requiring remote installations for terminals, task processors and other peripherals, because multiconductor cable is very expensive and would cause signal attenuation large enough to render the system inoperative since the signals on the cables 38, 40 and 42 are transmitted at TTL levels. The signal transmission characteristics of multiconductor cable are simply not good enough to locate a peripheral two kilometers away rom the CPU 30 because the signals sent rom one unit to the other would never reach the addressed unit or be unreadable when they arrived.
Further, it would be necessary to lay new cable for the system of Figure l, where existing coaxial cable may already be in place.
ReEerring to Figure 2 there is shown one proposed solution for distributed local data networks which utili~e coaxial cable which may or may not already be in place in the user facility. This system sometimes referred to as Ethernet~ The Ethernet~ system transmits data between the units 44, 46, 48, 50 and 52 of the system on the coaxial cable 54. The units of the sytem place square w~ve pulses in serial format on the coax 54 in the manner sho~n in Figure 3.
Referring to Figure 4 there is shown a drawinq o a typical local data network utilizing coaxial line which could ~Itilize the invention de5cri~ed herein. A coaxial 1~2~88~1 cable 64 is coupled throughout a user facility to various units of the distributed data processing system. For example a main CPU 66 and its associated line printer, disk drive or magnetic tape reader 68 can be connected to the coax 64 in the main data processing room. Remo~e terminals 70 and 72 may be located elsewhere in the building. A local task processor 74 mi~ht be loca~ed in the test lab or ~esign area to perform local application programs. Each unit on the system can have the benefit of use of the main CPU 66 and its high speed peripherals to process or put data into or take data out of the main data bases.
The system of ~`igure 4 typically operates with a carrier frequency oi about 50 mhz with a data rate of about 3 mHz.
Data is transmitted between the units of the system of Fi~ure 4 via an amplitude modulated carrier such as that illustrated in Figure 5. Frequency modulation or pulse width modulation could also be used. A lop~ic 1 is represented in the preferred embodiment by a section of the carrier modulated at 10~% of its amplicude such as at 31~ /

~ S _ ~ r ~ b p A ' ~ ' ~9~

77 while a logic zero would be represented by a section of carrier modulated at some arbitrary smaller perc~ntage of the 100% value, for example 1~7~ in the preferred embodiment, as illustrated at 79. The data encodin~
scheme of the preferred embodiment is non-re~urn-to-zero encodin~ but other coding schemes could be used in other embodiments. This modulated KF carrier scheme is commonly called broadband.
Each unit in the system of Figure 4 utilizes a modem of the type described herein. In Figure 6 there is shown a block diagram of the modem for the local data network invention described herein. Figures 7A and 7B are a flow chart of the line acquisition collision avoidance protocol implemented by the modem of Fi~ure 6. Referring simultaneously to Figure 6, 7A and 7B, the opera~ion and construction of the modem is as follows.
The modem is comprised of a transceiver 78 including a transmit section 80 and a receive sec~ion ~2. Bo~h the transmit section and the receive section are coupled to a strip line ~4~ The strip line ~4 is coupled to the coax 64 in Figure 4 usin~ standard coaxial type connectors and is designed using standard transmission line techniques such that the strip line R4 is e~fectively an extension of the coax 64 and has a characteristic impe~ance to substan~ially match that of the coax to which it is attached.
The transmitter section 80 is comprised of a daca encoder 86 which converts a transmit clock Tx CLK si~nal on a line 88 and a transmit data Tx DATA si~nal on a line 90 to the non-return-to-~ero-space modulation si~nal NR2-S
on the line 92. The signals on the lines 88 and gO are transmitted throu~h an optional multiplexer ~MUX) 94 of conventional desL~n and a buffer 96 to the data encoder 86 from one of the four clien~ devices ~not shown) coupled ~o the MUX g4. If the multiplexer 94 is not used then block 94 should be interpreted as the client device. Further ~2988~

the si~nals for requesting to send data, RTS Sum ~nd RTA
Sum become RTS and RTA when ~he multiplexer 94 is not used. The multiple~er 94 serves to su~ the individual requests to send or acknowled~e from the individual client devices into the composite signals RTA Sum and RTS Sum so that the modem will know when any of its client devices is requesting to send or acknowled~e.
The NRZ-S modulation signal on the line 92 is coupled to a modulator 98 and is used to amplitude modulate an RF
carrier generated in the modulator 98. The modulated carrier is coupled from the modulator 98 to an RF
amplifier 100 via a line 1~2 where it is amplified. The gain of the R~ amplifier 100 is controlled by the Carrier Enable signal on a line 181 from a modem control en~ine 104- The modem control engine 104 shuts off the RF
amplifier 100 when no transmission is desired.
The modulated carrier si~nal at the output of the RF
ampliier 100 is coupled to a diods switch 101 via a line 106. The diode swicch 101 is coupled to ~he strip line ~4 via a tap 1 ns and is also coupled to the Carrier Enable signal on the line 181. The tap 10~ is a capacitor soldered to the conductor of the strip Line 10~. The diode switch 101 is forward-biased by the Carrier Enable si~nal when the transmitter is transmittin~ so as to present a low output impedance to the strip line 84 whLch closely matches the impedance of the transmission medium. When the transmi~ter is not ~ransmi~ing, ~he diode switch lOl is rever~e-biased by the absence of the Carrier Enable signal so as to present a high impedance to the strip line ~4.
In the receiver 82, the strip line 84 is coupled co an active hi~h impedance ~ap circui~ 11n via an strip line 112. The func~ion of the active high impedance ~ap llO
and the strip line 112 is to present a hi~h impedance to the s~rip line 84 at all timss with little or no ima~inary componeTIt so as to ~inimiæe insertion loss and no~ load ..~

~Z2~8~
g down the coax 64 when a large number of modems are coupled to the coax line~ The modem of Figure 6 would iunction without the high impedance tap llO but not as many mode~s could be coupled to the coax ~4 because of excessive loading. The minimization of the reactive component of the impedance presented to the strip line 84 by the active tap 110 serves to minimize the amount of reflected power from the tap so as to minimize the standing wave pattern caused by disturbances of the line ~4.
The output of the high impedance tap 110 is fed on the line 113 to the inpu~ of an RF amplifer 114. The RF
amplifier has its ~ain input coupled to a Gain Control j signal on a line 117 from a burst switch 118. The Gain Control signal on the line 117 is controlled so that the RF amplifier 114 assumes a cer~ain gain level during some . portions of the acquisition protocol and a different ~ain level during other periods in ~he acquisition protocol as will be explained in more detail below.
The output of the RF amplifer 114 is applied to a demodulator 116 via a line 11~ The demodulator 116 converts the P~ si~nal on the line 11~ to an analog si~nal called RF Envelope on a line 120 which has an amplitude which varies with the amplitude of the envelope of the RF
signal on the line 119.
The line 12~ is coupled to che input of an analo~ to di~ital converter 122. The A/D conver~er 122 compares the signal on ~he line 12n to an adjustable reference voltage and ~enerates an ~lRZ-SR si~nal on a line 124 which is . true or lo~,ic 1 when the amplicude o~` the si~nal on the ! ~ 30 line 120 exceeds the reference level.
The signal on ~he line 120 is also coupled to che input of a carrier decec~ circuit 12~ and to the inpu~ of an A~:C threshold detec~ circuit 12~. The carrier detect circuit 126 senses the level of the signal on ~he line 120 3~ and compares it with ~ ~ixed reerence level to determine if a carrier is present on ~he strip line 84. The carrier A~

38~
-- 1 o--detect circuit generates a Carrier signal on a line 130 which is true when the signal on the line 120 exceeds the predetermined reference level.
The AGC threshold detect circuit 128 compares the R~
envelope signal to an adjustable reference voltage and generates a Fast Carrier signal on a line 132. This Fast Carrier si~nal is coupled to an input of a sample and hold control circuit l 34 .
The sample and hold control circuit 134 functions with the AGC threshold detector 128, the AGC ramp generator 138, the sample and hold circuit 136, the burst switch 11 and the modem control engine 104 to establish the automatic gain control level for the RF amplifier 114 during receive periods. That is during receive periods t the receiver automa~ic gain control circuitry must sample a constant amplitude preamble signal, portion l l 5 in Figure 5, at the start of each data packet in order to establish an appropriate amplification level, and hold this amplification level constant for receipt of the data packet following the preamble 115.
The manual gain control 140 is coupled to inputs of both the AGC ramp generator and the sample and hold control 134 by a line 144. The output of the AGC ramp ~enerator 138 is coupled to the input of the sample and hold control circuit l 36 by a line 146. The sample and hold control circuit 134 has its OULpUt coupled to a control input of the sample and hold circuit l 36 by a line 14~. The sample and hold circuit l 36 has its output coupled through the burst switch 118 to the automatic gain control input 117 of the RF amplifier 114. The burst switch 11~ is also coupled to a bursc gain control 142 by a line 150 and is coupled to the Burst Enable si~nal from the modem control en~ine 104 by a line 152.
Generally, the receiver's gain control circuitry has two phases of opera~ion. The first phase is during bursting by the transmitter when access to the line is .~

~LZ29~38~) desired. During this phase~ the receiver must listen for interference beating on the line which will resul~ in amplitude changes of the received signal. To detect these changes, the gain of the RF amplifier 114 must be re~uced so that the RF amplifier 114 i5 not swamped by the outpu~
j from the transmitter 80 and so that the output of the demodulator 116 can be compared to a fixed reference level.
During interference beatin~, the D.C. si~nal on the line 1 2n will be rising above and falling below a fixed reference level. The A/D converter circuit 122 looks for this phenomena during burstin~ to determine when anoth~r carrier is on the line. The A/D converter 12~ ~enerates the siRnal NRZ-S on the line 124 which will contain a pulse each time the changing level on the line 120 exceeds the reference level.
This first phase of gain control operation is accomplished by the modem control engine 1Q4 si~nallin~
~he burst switch 118 by making a Burst Enable signal on a line 152 true indicating that burstin~ is occurrin~ This causes ~he sample and hold signal on ~he llne 137 from ~he sample and hold circui~ 136 co be disconnected from the gain control input 117 o~ the RF amplifier 114~
Simulcaneously, the manually ad3us~able bursc ~ain control 142 is connected to the line 117 and controls the gain of the RF amplifier 114. The burst gain control 142 can be manually set to establish the ~ain at any de~ired level depending upon the predet~rmined reference level.
The second phase oE operation of che recei~er ~ain control circuitry is during ~he daca transmission preamble. The gain ~f ~he RF afnplifier 114 is initially set at a maximum until a preamble is detecced when ~he transmiteer i5 not bur~in~ as determined by the carrier decect circuit 126 and the burs~ swi~ch 118~ When a preamble occurs, ~he signal on ~he line 130 causes the sample and hold control circuit 134 to si~nal the AGC ramp ~%~81~3 , ~
generator 138 via the line 135 to start ~enerating a ra~p signal voltage on the line 146 which is passed through the sample and hold circuit 136 and the burst switch 11~ to the RF amplifier 114 and causes the ~ain to be decreased. As the gain of the RF amplifier 114 is ramped down, the D.C. level of the signal on the line 120 starts to change un~il it reaches a certain threshold level.
When the threshold level is reached~ the AGC threshold detector 128 signals the sample and hold control circuit 134 via the line 132 that the proper ~ain level has been ,established. The sa~ple and hold concrol circuit 134 then signals the sample and hold circuit 136 via the line 148 to hold the D.C. level on the line 137 steady at the level then existing. That D.C. level is directly coupled to the RF amplifier 114 gain control inpuc on the line 117 through the burst switch 11~ to hold the gain steady throughout the entire data packet.
The incoming data packe~ is decoded in a data decoder 156 which is coupled to the NRZ-SR signal on the line

2~ 124. The daca decoder 156 recovers the clock signal from the NRZ data coming in and synchroni2es the incoming data with the local modem clock which is par~ of the data decoder 156. The received data and the recovered clock signals are transmitted through a huffer 158 and to the clLent device as the Rx DATA and Rx CLK signals on lines 160 and 1~ xespectively.
The opera~ion of the modem controL engine 104 in relation to the client task processors, the receiver and the transmitter in carryin~ out the transmit protocol will be best unders~oo~ by referring to Figures 7A and 7B in con,junction with Figure 5.
Figures 7A and 7B are a flow chart of the steps carried out by che modem control en~ine ~MCE~ 104 in carrying out the trans~it line acquisition and contention

3~ resolution protocol. Iniciallyt the mode~ control en~ine starts at power up stat~ in block 164 of Figure 7A wherein the system is initialized and then moves to a llsten state 166. In that state the MCE 104 listens for foreign carriers on the line 64 by checki~g the state of the Carrier signal on the line 130. If the line is not quiet, Carrier will be true and the MCE 104 will make a transition on the path 167 to a sta~e 168 wherein the MC~
104 will time the foreign carrier by enabling an internal timer and watching the Carrier signal on the line 130.
The purpose of this series of steps is to determine the duration of the foreign carrier to determine if it is a burst, data packet or an acknowledgment packet. This determination is made by determining whether the Carrier signal is on longer than a predetermined time. If it is on longer than a predetermined time, then an attempt counter internal to the ~CE 104 is reset to zero attempts after the carrier signal disappears. In Figure 7~ this step is represented hy a transition to a state 170 along a path 172.
After resetting the attempt counter~ the MCE 104 returns to the listen ~tate 166 along a path 174.
Referring to Figures 8A and B, 9, and 10A, B and C the actual implementation of this portion of the transmit protocol can be understood more fully. Figures 8A and 8B
are a detailed logic diagram o~ the modem control engine. Figure ~ ;s a machine state diagram of the separate states the modem control en~ine l04 can assume and of the paths between the states. Figures 1OA - C are a detailed flow diagram o the steps in the transmit protocol implemented by the modem control engine 104.
Referring first to Fi~ures 8A and B, the heart of the MCE 104 is shown on Figure 8B as a fuse programmable logic sequencer (FPLS) 176. This sequencer is, in the preferred embodiment, an 82S105 manufac~ured by Signetics~ The FPLS
is coupled to the attempt counter 107 by the signal lines INCR and RESET on lines 177 and 179 respectively which increment the counter and pre~load it to a predetermined ~22988~

constant of 011 0 binary respectively.
The FPLS 176 is coupled to the transmitter 80 in Figure 6 by the Hold Encoder si~nal on a line 178, a Carrier Enable signal on a line 180 and the Burst Enable signal on a line 152.
The FPI,S 176 is coupled to the recei~er 82 by the si~nal Carrier on the line 130 in Figure 8A, the signal Fast Carrier on the line 132, the Burst Enable si~nal on the line 152 in Figure 8B and the signal NRZ-SR on the line 124 in Figure 8B, Finally the FPLS is coupled to ~he client clevice by si~nals RTS or, optionally, RTS Sum if a ~ultiplexer is presen~ on a line 154, RTA or, optionally, RTA Sum on a line 1~2 and CTS or, optionally, CTS Sum on a line 1~5.
That is, if ~he optional multiplexer is pres~nt, the ~TS, RTA and CTS ~i~nals are RTS ~um, RTA Sum and CTS Sum, respectively.
The FPLS 176 is moclified structurally by descrvying selected fuses in the internal structure of the ch~p to 2~ implement the Boolean funo~ions illustrated in the ~able accompanyin~ Figures 9. The ~able is included below and should be referred to in conjunction wich ~he dlscusslon of Figure g. The transmission and contention resolution protocol repre~en~ed by Fi~ures 7A and B, lOA - C, 9, and 8A and B will be explained s~ructurally and functionally by referring ~o the above-lisced drawlngs in coniunction with the following explanation.
The steps of ~he protoco~ represen~ed by states t66, 1k~ and 1 7n in Figure 7A-~ are detailed in Flgure 1OA (, ancl Figur~s 9. The liscen s~a~e 166 i5 represen~ed by che decision block 1fi6A in Fi~ures 1OA and s~ate 166 in ~igure 9. ~he signal C.~D is equivalent to either Carrier or Fast Carrier because these ~wo ~ignal~ are co~bined by the OR gate 131 in Figure ~A. In state 166 a5 soon ag the 3~ si~naL C.CD on ~he line 2~3 coupled to ~he I~ input o~
FPL5 176 in Figure ~B beco~ crue, che FPL~ cha~e& to a 2~3~

state 168A along a path 167. There is listed below a table for the inputs and outputs from the FPLS 176 for each of the paths in Figure 9~

5 Path Inputs Outputs 167 C.CD Nil 168B Nil Timer Enahle 168D 5td & C.CD Nil 168F C.CD not Nil 168G C.CD not Reset 174 Nil Reset & Incr 182A RTA ~ C.CD not Carrier Enable s Hold Encoder S Timer Enable 182B RTA not Nil 180C RTA & 3td CTS & Carrier Enable Ack Window 180D ~TA not Nil 180F C.CD not Nil 190 C.CD not & RTS ~ Timer Enable RTA not 191 C.CD not & RTS not Nil & Attempt not 192D Attempt CTS & Reset 192E. Attempt not & C.CD Burst Enable S Carrier not & RTS & 3td Enable ~ Hold Encoder & Timer Enable S Incr 195 Nil CTS & Reset ~ Incr &
Timer Enable 194C 3td Nil 196C RTS not Nil i ~g~8~

P Inputs O1lt~UtS
196D RTS & Contention Ti~er En & Burst En &
Burst En & Carrier En Hold Encoder 196E 5td h Contention not Timer En & RTS
IC38D 5td & RBN Nil 198E RBN not & Std Nil 19~G C.CD not Timer Enable 1981 6td & C.CD not Nil 198K C.CD Nil 198~1 Nil Timer Enable 198M Attempt noc & Nil C.CD not 199 Attempt & C.CD not Reset 198P C.CD & Std Nll 200F 6td Timer En 200C RTS no~ Nil 200D RTS & C.CD Nil 201 Nil Timer Enable 202B C.CD not & RBM Nil 202C Std & C~CD Nil 202E C.CV not & ~BN not Timer En 2nOE C.CD not & ~td & RTS Carrier Enahle ~ Hold Encoder ~ Timer Enable ~0 204C RTS no~ Nil 2n4D 3~d & RTS CTS ~ Carrler En & Reset 204F RTS not Reset ~ Incr 3~ 204G C.CD not ~ RTA not Timer En & Ack Windo~

,~

Path Inputs Outputs 204H RTA ~ C.CD not Timer En & Hold En & Ack Window & Carrier En 205 C.CD Nil 204J 2.5 td not & C.CD Carrier En & Hold En &
not & RTA Ack Window 204M Nil Ack Window & Carrier Enable & Timer En &
Hold Encoder 2~4K 2.5 td & C.CD not Nil The nomenclature C.CD/Nil for the path 167 transition shown in Figure 9 means that when the I2 inpu~ C.CD in Figure 8B becomes true, the path 1~7 is taken and there is no output at any of the outputs FO-F7 in Figure ~B. It is suggested that the reader use 8B, Figure 9 and the table herein to understand physically which inputs and outputs are in various conditions durin~ various mschine scates.
Fi~ures 7A and 7B and Fi~ures 1OA - C should be used by the reader to understand conceptually che prv~ocol steps which are imple~ented by the FPLS 176.
As previously noted, th~ purpose of the state 168 in Fi~ure 7A is to determine whether the detected carrier which caused the transition on the path 167 was a burst carrier or a data packe~. Referrin~ to Figure 1~A, when the FPLS reaches the state 1fi8A, the outpu~ signal F3, Times Enable, on line 187 in Figure 3A i~ made true. This initiates a timer 186 in FiRure ~A which is comprised of two 74LS161 standar~ TTL synchronous eounters wl~h direct clear such as are manufactured by Texas Instrumen~s, Inc.
and numerous other sources. Boeh count2rs are ~our-bic binary synchronous counters which starc co eount when the Timer Enable slgnal on the line 187 is crue. The variou~
outpuCs of the coun~ers are coupled cogether in known 3~ fashion to generate five ouput aignals, i.e~, 2.5td on line 241, 3td on line 233, 5td on line 235, 6cd on line 237 and 8td on line ~39. Each of these outpu~ lines ~2~

carries a signal which makes a transition ~~rom one logic state to another at a predetermined multiple of a fixed time period td. This unit of time measure td is equal to the transmission delay on the line.
The object of the state 168 in Figure 7A is to determine whether the detected carrier lasts for a period greater than 5td. The FPLS makes its transition from state 166 to 168A along the path 167 in Figure g as soon as the input signal I2, C.CD, becomes true indicating that a carrier has been detected. The Timer Enable signal, F3, is then immediately made true in making the transition on the path 168B to the state 168C.
Referring to Figure 9 the FPLS stays in state 168C
until Std has expired and the C.CD signal is still true, at which time it makes a transition on the path 168D to a state 168E. No output is generated on ~his transition.
When C.CD becomes false, the FPLS makes a transition from the state 168E to a state 170 alon~ a path 168G. In making this transition, the Reset signal on the line 179 in Figure 8B is made true causing the attempt counter 107 to be enabled for a parallel load. When the state 170 is reached, the signal Reset remains true and the signal Incr on the line 177 in Figure 8B is made true which parallel loads the binary constant 0110 at the A-D inputs into the attempt counter. If C.CD becomes false befvre 5td has expired, however, the FPLS moves back to the state 166 along the path 168F which indicates that the foreign carrier lasted less than 5tdl is no longer present, and that the line is clear.
To account for the possibility that. the packet was addressed to one of its client devices, the FPLS 176 checks for the presence of a request to acknowledge signal RTA or, optionally, RTA Sum at its I1 input. In Figures 9 and 10A, this decision is represented by the transition rom decision block 166D in state 166 to the block 180A in state 180 along the path 182A. This transition occurs ~98~

, g when the FPLS 176 ~inds its I1, input true and its I2 input false indicating that the line is now quie~ and one of its client devices has been requested to acknowledge a data packet.
When the input variables are I1 and I2, not, one of the client devices has been requested to acknowledge a data packet. In that event the transition along the path 1~2A is made and the output signals Carrier Enable (F1) on the line 181, Hold Encoder (F2) on the line 178 and Timer Enahle (F3) on the line 187 in Figure ~B are made true, These signals enable the transmitter 8~ to produce an AGC
burst as a preamble for an acknowledgment packet.
Referring to Figure 6, the Carrier Enable si~nal on ~he line 1R1 drives the RF amplifier lO0 in the cransmitter to maximum ~ain and causes a iorward bias on the diode switch 101 to puc the RF carrier on the strip line 84 and coax 64 via the line 1~8. The ~old Encoder signal on the line 178 causes the dat.a encoder 86 to pu~
out a string of logic 1's on the line 92 coupled to th~
modulator 98~ This causes the modula~or to modulace the RF carrier at the 100~ amplitude level. In Fi~ure ~B, Ti~er Enable signa:l starts the timer 1~6 which time~ the AGC preamble period.
Reierring to Figur~s 9 ~nd 6, if the RTA signal on ~he 2~ line 182 from the cLient device ~oes ~alse before the expiration of 3td, the FPLS 176 will return to the state 166 along the path l82B. No output is P~eneraced durin~, this transition.
If RTA is still true after 3~ has expired, the FPLS
will move co a state 180B alon~ a pat~ 1flOC. In the sta~e 1 ~na che FPLS will be holdin~ true the CTS si~nal on ~he line 1R5 in Figure 6 and will also be holdin~, ~rue the si~nals Carrier En~ble on line 1R1 in ~i~ure ~ and the si~,nal Ack Window on the line 1~1 in Fi~u~e ~B. These signals tell the client device co send the acknowled~ment packet which ic does along the Tx DATA and Tx CLK paths 9 8~

and 88 in Figure 6. The acknowledgment data goes out on ~ , the line in whatever NRZ code has been established for the acknowledgment protocol.
While the acknowledgment packet is going out, the receiver 82 in Figure 6 is receiving the carrier and the carrier detector 126 in Figure 6 is holding the carrier signal on the line 130 true while the Fast Carrier signal on the line 132 is also true. These Carrier and Fast Carrier signals cause the C.CD signal to be true by the action of the gate 131 and the flip flop 133 in Figure 8A. The flip flop 133 serves to synchronize the output of the gate 131 with the modem clock such that the signal C.CD on the line 223 will be set to the true condition on a low to high transition of the modem clock cycle. When the acknowledgment packet is sent, the client device removes the RTA or, optionally, the RTA Sum signal on the line 182 which causes the FPLS to move Erom the state lSOB
to the state 180E along the path 180~. The state 180E i5 a waiting state which waits for the signal C.CD to ~o false indicating that the line is quiet. When that occurs, the FPLS 176 makes the transition back to the state 166 along the path 180F to continue to listen to the line.
Referring to Fiyure 1OA, if the original data packet which came in was not addressed to any of the client devices, then the FPL5 rnust determine if any of the client devices are requesting to send data to any other unit in the system. This determination is represented by the block 166E in the state 166. The FPLS looks for the presence of the RTS signal on the line 154 in ~igure 8B
from its client device or devices. If none is found, then the FPLS remains in the state 166 as indicated by the path 166F in Figure 1OA.
However, i RTS is true then the FP~S makes a transition from the state 166 to a state 192 via a path 190 as shown in Figure 7A. The purpose of making this transition is to establish that the line i5 quiet prior to transmitting an access burst signalling an intention to acquire the line.
As will be apparent to those skilled in the art from the notations for path 190 in the table for Figure 9, the input cor.ditions required to make the transition from the state 166 to the state 192 are that RTS be true while the C.CD and RTA signals are false indicating that the line is quiet and no request to acknowledgment is present while one of the client devices is requesting to send a data packet. In making this transition, the FPLS 176 raises Timer Enable to true which starts the timer 186 to time the listening period for 3td.
Referring to Figures 7A, 9 and 10A & B, in the state 192, the FPLS checks the previous number of attempts. If 10 previous attempts have been made to transmit~ the FPLS
will transfer to the state 194A along the path 192D in order to send a false transmission messaye. During this transition, the Reset signal on the line 179 in Figure 8B
is made true resetting the attempt counter and the signal ~TS on the line 185 in Fig~re 8B is made true indic~ting the FPLS is signalling a false transmission.
If the previous number of attempts is less than 10~
Attempt on line 193 in Figure 8B is false. In that event, the FPLS checks the C.CD signal at its I2 input to see if any foreign carriers are on the line. If C.CD is false, the FPLS checks to see if RTS on line 154 in Figure 8B i5 false. If all three signals are false, the FPLS makes a I transition from the state 192 back to the state 166 via the path 191.
If a foreign carrier comes on the line during this pre-burst listening period with the number of attempts less than 10, the FPL senses that the coax line 64 is not ~ quiet from the C.CD signal and makes the transition to the ¦ previously described state 16eA along the path 204I. The foreign carrier is timed in the state 168 as previously described and processing proceeds as previously described.

IN
38~

When the transition to the state 194A in Figures 7A, 9 and 10B is made, the CTS signal~ or optionally, the CTS
Sum on the line 185 in Figure 6 is made true and then false 3td later by the FPLS indicating to the client device trying to send data that there is so~e sort of trouble or heavy traffic and the transmission is aborted. This operation is represented by the transi~ion on the path 195 to the state 194B in Figures 1OB and 9.
On this path the attempt counter 107 is pre-loaded with a constant and the timer is enabled. When 3td expires the FPI,S moves to the state 198J on the path 194C.
Referring to Figure 7A, 9 and 10~ if 10 previous attempts have not been made to transmit and the line has been quiet for 3td and the client device is still requesting to send, the FPLS makes a transition to the burst for 2td state 196 along the path 192E. This marks the start of the 2td burst of non data bearing carrier for contention resolution. This transition on the path 192P
will not occur unless the RT5 signal is still true indicaring that the client device still desires to send 2 data packet, attempt is false and the coax line has been quiet for 3td as indicated by C.CD false and 3td true.
The YPLS then makes the Burst Enable, Carrier En~ble, Hold Encoder, Timer Enable and Incr. siqnals true on the lines 152, 181, 178, 187 and 177 respectively in Figure 8B. The Timer Enable signal starts the Timer 186 to time the burst, and the Incr. signal increments the attempt counter 107 to keep account of the number of attempts to acquire the coax line 64 which have been made to transmit the data packet for which the transmission request has been made.
If RTS becomes false while in the state 1~6, the FPLS will make a transition back to the listen state 166 along a path 196C.
Referring to Figure 6, the ~lold Encoder signal causes the data encoder 86 to put a string of NRZ logic 1's on the line 32 to cause the modulator to modulate the XP

~%9~

Carrier at 100% amplitude such that the burst carries no data. The Carrier Enable signal on line 181 enables the RF amplifier 100 in the transmicter 82 and causes the R.F.
amplifier 100 to pass the modulated carrier on line 102 through to the diode switch 101 and causes the diode switch lOl to change impedance states from a high impedance to a low impedance which approximately matches the impedance of the strip line 84.
The Burst Enable signal on the line 152 is coupled to an RF tank circuit 99 in the transmitter sn as well as the burst switch 118 in the receiver. The RF tank 99 is coupled to the modulator 98 so as to control the frequency of the RF carrier generated by the modulator 98 by virtue of the electrical characteristics of the RF tank 94. When the Burst Enable signal is false during non-burst transmissions/ the electrical characteristics of the RF
tank 99 are stable and the frequency of the RF carrier does not vary. However, during burst, the Burst Enable signal causes the electrical characteristics of the RF
tank to be varied. The varving elecrical characteristics of the RF tank cause the frequency of the RF carrier to be swept automatically over a range of frequencies durin~ the burst transmission.
The purpose of alcering the frequency of the RF
carrier is to insure that ~hat the contention will be decected if another modem is simultaneously burstin~.
That is, ~wo burst carriers will interfere with each other and cause interference beating as i5 known in the art.
The interference beatin~ will cause the ampli~ude on the carrier on the strip line 84 to change in a random wave motion. The reason this interference beating is desirable is to enable the receiver ~2 and modem control engine 104 to more easily determine whether another modem is simulcaneously con~endin~ for the coax line 64.
The Burst Enable signa~ aLso causes the burst switch `ll8 in the receiver 82 to disconnec~ the AGC signal on the ~z~

line 137 from che AGC input line 117 to the RF ampli~ier 114. Simultaneously, the burst gain control signal on the line 150 is applied to the gain control input 117 of the RF amplifier 114 to se~ che ~ain at a iixed, predetermined, manually adju~table level. This level is established such that the demodulator 116 and AID
converter 122 will detect amplitude changes caused by the beating in ~he demodulated carrler analog signal on the line 120. If beating is occurring, the A/D converter 122 will generate an NRZ-SR pulse on the line 124 each time the signal on the line 120 rises above a prede~ermined level.
The next machine sta~e in ~he transmission prococol is to test ~he NRZ~SR signal to determine if any ocher modem lS is contending for the line. Referring to Figures lOB, 7A, and ~B, the FPLS moves to state 1~6B, wherein the FPLS
examines the Contention signal on a line t97 to determine if a con~ention exist, In Fi~ure BB, the Contention signal is generated by a contention si~n~l ~enerator 220.
The contention signal on the line 197 i5 generated ~
two conventional TTL 74LS279 latches 188 and 183 and a 74LS175 sync latch ~27. The latch 1~8 ~erve~ Co delay the opening of the con~entlon window by a predecermined time by not raisn~ the Q output on the line 2n3 until 2.3 microseconds after ~urst ~nable on rhe line 152 becomes true. This is necessar~ because for a shorc period after Burst F.nable becomes crue, ~he receiver 82 is not able to decect any con~ention~s. The delay is implemented by applying the Burst ~nable s1gnal to che set not input of the lacch 188 chrou~h a NAN~ gate ~45 which has an input coupled via a line which carries a signal from the timer 186 which does noc become true un~il the 2.3 microseconds after the burst start~ as will be apparent upon lnspection of Figures 8A.
The concencion signa1 on the line 197 becomes true when the content1On window siQnal on the line 203 is true ~.~

~913~

and the NRZ-SR signal on the line 124 from the receiver 82 is true and the Modem Clock signal on the line 111 makes a low to high r.ransition. Contention Window and NRZ-SR are applied to the set not input of the latch 183 through a conventional 74LSOO NAND gate 209.
When Contention is true on the line 197) the FP~S 176 knows that the receiver 82 is seeing amplitude changes in the strip line 84 indicatin~ that another modem is contending for the transmission medium.
Referrin~ to Fi~ures 9, 7A and 1OB, there are three paths out o~ the state 196 for the FPLS 176~ The path 1~C is taken if the RTS signal becomes false. When this happens, the FPLS knows the client device no longer desires to send or that RTS was falsely asserted for some reason and returns to the listen s~ate 166.
If a con~ention is four1d, the FPL~ moves to a contention resolution state 198 via a pa~h 196D. If no contention i5 found, the FPLS moves to a post burst listen state 200 via a path 1 96E ~
2~ The contention resolution protocol of the state 198 consists of a series of s~eps ~o deter~lne the amount of delay before re~rying ~e transmission. The amounc of delay is determined by ~enerarin~ a random binary number using the randomness of the beat pattern itself and using the random binary number to control the amount of delay before a re~ry attempt.
Referring to Figure 1nB, the first steps in the contention resolutlon protocol are steps 19~A, B and C.
Sceps 198A and B wait or che burst to finish after 2td.
In step 198C, the FP~S checks the state of the random binary number ~RBN~ ~er-erator 211 in Figure ~B to see if che ~BM on the line 221 is true or ~a1se. If the RBN is true, the FPLS ~akes a path 198~ back to the Listen s~ate 1~6 to retry the transrnission ater whatever transitiQns are made fro~ the stace 166 as prev-ously described.

~h`

8~

If the RBN is false~ the FPLS 176 moves over the path 198E to a state 198F where it waits for the foreign carrier to drop off the line by waiting for the signal C.CD to become false. When C.CD does become false, the 5FPLS moves over a path 198G to a listening state 198H
which lasts for 6td.
The details of the RBN generator will be apparent to those skilled in the art upon inspection of Figure 8B.
The RBN generator is comprised of a TTL 74LS74 flip flop 10217 with its D input 213 coupled to the Q not ou~put 215 and its clock input coupled to the NRZ-SR signal on the line 124. The Q output 225 of ~he flip flop 217 is coupled to the D input of a sync flip flop 219 which has its clock input coupled to the Modem Clock si~nal from ~he 15timer 186 in Figure ~A. I~atever is the state on the Q
output 225 of the fLip flop 217 at the time of a low to high transition of the Modem Clock signal will be transferred to the Q output 221 as the si~nal RBN. As a result of this structure, Lhe flip flop 2t7 will toggle 20each time the NRZ-S si~nal makes an upward transition~
Because the beat pattern on che strip line 84 is random, the toggling action is random and the binary number resulting therefrom will be random.
Returning to Figure 10B, the FPLS, after determining 2Sthat che foreign carrier is off the line, starts a 6td listening period on the path 19~G such that it stays in the state 198H for 6td. If, during the listening period, no forei~n carrier is detected throu~h the C.CD si,~nal OTl the line 223 in Figures 8A and B, the FPLS returns to the 30listenin~ state 1fi6 via a path 19~I after 6td expires.
However, if a forei~n carrier is detected durlng the 6~d listening period, then the FPLS makes a transition to a detected carrier state 198J via a path 19~K. The FPLS
then moves to a state 198L by a path 199 wherein i~
enahles the t:imer and checks the condition of the C.CD
si~nal durin~ a 5td time period. The FPLS also checks the ,~,~ }, ~,, .

8~

condition of the attempt counter. If the C.CD signal goes false before the expiration of 5td and the number- o previous at~empts is less than 10, the FPLS moves to the previously described state 198F via the path 198M.
Processing then proceeds as previously described.
If the number of attempts has reached 10, the FPLS
enables the attempt counter for parallel load and moves over a path 198N to the previously described state 194A to send a false transmission signal. Processing then proceeds as previously described.
If the C.CD signal remains on during the entire 5td time period, upon the signal 5td becoming true, the FPLS
moves from the state 198L via a path 1~8P to the previously described state 168E. When the carrier drops the FPLS moves on the path 168G to the previously described state 170 to load reset the attempt counter and then returns to the listen state 166 via the path 174.
Thereafter~ proces~ing proceeds as previously described.
Thus a random distribution of delay periods is incorporated prior to tra~nsmission retry.
Returning to the state 196 in Figures 10B and 7A, if no contention was detected during the 2td burst period, the ~PLS 176 moves to a post burst listening period state 200 vi~ the path 136E. The first step in this post-burst 2S listening period protocol is 20nA where the FPLS wai~s for a period of 1td, i.e., 5 microseconds. Upon the expiration of this period, the FPLS moves to a state 200B
along the path 200F and the timer 186 is started. While in the state 200B, if the signal ~TS becomes alse, the FPLS trans~ers back to the previously descri~ed state 166 via a path 200C.
Whi1e in the state 2QOB, if a carrier is detected by , the signal C.CD becoming true and RTS i~ still true~ then ¦ the FPLS moves to a timer state 202 via a path 2QOD to determine if the detected carrier is a burst, data pacXet or ack~1owledge packet. I~nmediately upon reaching the ~9~8~

state 202, the FPLS makes a transition on the path 201 to a state 202A. The transition on the path 201 causes the Timer Enable signal to be made true.
Referring to Figure 7A, the purpose of the state 202 is to time the foreign carrier to determine whether it is a burst carrier or a data or acknowledge packet. The protocol of the steps of the state 202 are shown in more detail in Figure 10C. The first step is to begin timing the foreign carrier. If the signal C.CD becomes false before the expiration of 5td and RsN is true, the FPLS
transfers to the previously described listen state 166 in Figure 1OB via the path 202B. If RBN is false however~
the FPLS transfers via the path 202E to the previously described state 198H to listen for 6tdo If C.CD is still on at the expiration of 5td, the FPLS transfers on the path 202C to the previously described state 168E.
Processing from those points then proceeds as previously described.
Returning to the state 2QOs in Figures 9 and 1OB, if no foreign carrier is discovered on the line during the post burst listening period of the state 200 in Figure 7A, then the FPLS will transfer to a state 204 via a path 200E. The purpose of the state 204 is to transmit the preamble to a data packet for the purpose of allowing the receivers in the system to adjust their gain levels. This transEer occurs when C.CD becomes false, RTS is true and 8td is true.
There are two steps in the transmission sequence. The first step is 209A in Figures 7B and 10C and Figure 9.
The purpose of this step is to transmit a preamble to the data consisting of a 100% modulated non data bearing RF
carrier which lasts for 3td. If the client device trying ~, to send a data pacXet renders the signal RTS false, then ; the FPLS will return to the state 166 via the path 204C.
If the client device is still requesting to send data~
the FPLS will move to the state 204B via the path 204D

after the preamble. The purpose of the state 204B is to send the data packet. The FPLS, in moving to the state 204B along the path 204D, sends the signal CTS or, optionally, CTS Sum when using an optional MUX.
Thereafter, the client device sends the data to be modulated onto the RF carrier to the transmitter 80 in Figure 6 through the buffer 96 along the Tx DATA line 9C
and the Tx CLK line 88. The FPLS in moving to the state 204B makes the signal Carrier Enable true which causes the transmitter 80 to set the gain of the RF amplifier 100 at transmit levels and to cause the diodes switch 104 to switch to its low impedance state. Thereafter, the data goes onto the strip line via the line 108 and the attempt counter is enabled for a pre-load.
Upon completion of transmission of the data packet, the FPLS moves to the listen state 204E along the path 204F to wait for the carrier to drop. The transition to the state 204E does not occur until the signal RTS becomes false indicating that the client device has ccmpleted ~ sending its data pac~et. Upon making the tra~sition, the attempt counter is pre-loaded to 0110 binary.
In the state 204E, the FPLS waits for the carrier signal on the strip line 84 to drop as indicated by the signal C.CD becoming false. The signal C.CD is true during the transmission of the data packet because the receiver section 82 has its gain automatically set by its own automatic gain control circuitry during the preamble section of the data packet to the proper level to receive the signal from the transmitter 80. ~
There are two possibilities for the address of the previously transmitted data~ First, the data may have been sent to a client device connected ~o a forei~n modem, or second, the data may have been sent to one o the other client devices coupled to an optional multiplexer connected to the same modem. To determine which is the case, the FPLS examines a siqnal RTA on a line 182 from ~ 2 9 the client device to determine if the data was sent to one of its own client devices. If the block 94 is a multiplexer in Figure 6, the signal on the line 1~2 is RTA
Sum which is a combination of the request to acknowled~e si~nals ~TA from each of the client devices attached to the multiplexer. Otherwise the signal on the line 182 is simply the request to acknowledge si~nal from the client device.
If RTA is true, the FPLS transfers from the state 204E
1~ to the previously descri~ed state 1~OA along the path 204H. Processin~ ~hen continues as previously described in order to send out an acknowled~ement packe~.
If RTA has not beco~e true by the time the state 2~4F.
is reached, the F~LS 17~ makes a transition to the state 204L along the path 204G. The pa~h 204G will be taken only if the FPI,S inputs C.C~ not and RTA not are true when the state 204E is reached. The Timer Enable and ~ck Window outputs will be made true when this transirion is made to create the acknowledge window.
If the signal C.CD becomes true while the FPLS is in the state 204L, the FPLS cransfers from the state 204L to the previou~ly described state 168A via the pa~h 205 ~o time the foreign carrier to determine what kind of trans~ission it is.
If, however, the si~nal C.CD is false with RTA
becomin~ true while in the state 204L, the FPLS determines whether 2.5td have expired since the acknowledgment window was opened. If 2.5td has no~ elapsed, and there is stilL
no forei~n carrier on the strip line and RTA is true~ the modem's own client device has received the data, and the FP~S transfers control on the pach 204J to the state 204~J
and then, immediately~ to the previousl~ describecJ stiate 180A via the path 2n4M to send an acknowled~ment packet.
If RTA remains false, the FPLS continues to wait un~il either the ~ie,nal C.CD has become crue or the siRnal C.C~
has remained false and 2.5td has expired.
lf both C.CD is false and 2.5td has expired~ ~he FPLS
~nows no acknowled~ment has been received and cransfers .

~L2~9 back to the previously described state 166 via the path 204K and processing continues as previously described.
This completes the description of the line acquisition protocol of the modem depicted in Figure 6.
The individual details of the functional blocks of the transmitter ~n and the receiver R2 are seen in Figures 11t 12, 13, 14 and 15.
Figure 11 shows the details of the modulator 98, the amplifier 10(), the diode switch 101 and the RF eank circui~ 99. These elements will be described in terms of their function only since the details of the functions of the individual components and the interconnections thereof with the integrated circuits will be apparent to those skilled in the art.
The heart of the modùlator 98 is a Motorola MC1373 TV
video modulator. The chip has an internal RF oscillator and RF modulator and depends upon the circuitry connected to lines 208 and 20f7 to determine che frequency of the carrier ~,enerated by the RF oscillator. The modulating signal is the si~nal NRZ S on che line ~2. Thls signal or a test modulation signal is supplied through a standard TTL 741-1 open collector buffer with its output coupled to the baseband input 229 of the modulator. The RF tank inputs 206 and 208 are coupled LO a parallel-tuned circuit comprised of an inductor 210 with a lS0 pico~arad capacitor 212 coupled to one end and a 150 plcofarad capacitor 214 coupled ~o the inductor 210 at the o~her end. Between the two capacieors 212 and 214 there is coupled a Motorola MV 1405 varactor diode 216 which completes the parallel-tuned circuit. The anode of ~he varactor diode is coupled ~o the capacitor 212 while the cathode of the varactor is coupled to the capacitor 214.
The cathode of the varactor diode 216 is also coupled to the Burst Enable signal ~hrough a 7417 open collector buffer amplifier 218~ The output of the buffer 218 is coupled to a 15 volt supply through a resistor 226 and to lZ~9~

the cathode of a 5.1 volt zenor diode 222 which has its anode ~rounded. When the Burst Enable si~nal on the line 152 is false, a 15 volt si~nal will be applied co the cathode of the varactor diode 21h, and ~he diode will be in a revers~ biased state because of the 15 volt supply volta~e coupled through the resistors 224 and 226 to the node 228. Thus~ a certain fi~ed junction capacitance will exist in the varactor diode 216 when the Burst Enable signal on the line 152 is false. Therefore, when Burst Enable is false, the carrier frequency generated by the RF
oscillator and the MC 1373 will be fixed at a reference frequency of around 50 megahertz.
When, however, the Burst Enable signal is trueJ the buffer 218 ~Jill ground the line 230 which will result in the varactor 216 becoming less reverse biased. The biased condition on the varactor 216 chan~es the junction capacitance thereo which causes the ~o~al capacitance in the tuned RF tank circuit 99 to be altered. This insures that the frequency of the carrier durin~ the burst se~ment of the acquisition protocol will be al~ered over a ran~e of frequencies co insure that interference beat patterns will oceur with any burst signals put out by other sim~lar modems.
The modula~ed RF output on che line 1n2 is coupled to che input of the RF amplifler 100 the hearc of which is a Motorola MC 1350 inte~,raced IF amplifier 232. The amplifier 232 has its ~ain con~rol input coupled to the Carrier Enable si&nal on line 181 throu~h a 74LS02 NOR
gate 234 and a 7417 open colleccor buffer 236. A vol~age divider comprised o~ the resis~ors 238 and 240 establish a steady state gain control level on the line 242 when che Carrier Enable signal on ~he line 181 is false~ When the Carrier Enable si~nal is true, che voltage on line 24~ is altered by the buffer 236 so as to allow the amplifier 232 to pass the RF carrier signal on line 1n2 throu~h co ~he diode switch 1~1 on the line l0~ a~ will be apparent to those s~iL}ed in the art.

~9~

A Motorola MWA 130 broadband amplifier is interposed between the output of the RF amplifier 232 and the input on line 106 of the diode switch 101. The purpose of this ampli~ier is to supply additional fixed gain for the fundamental and all harmonics of the modulated RF si~nal at the output of the amplifier 232.
The diode switch 101 is comprised of a 1~4003 diode 24fi interposed between the line 106 and a reed relay 248 coupled to the strip line fl4 throu~h a 1~0~0 picofarad capacitor 250. The cathode of the diode 246 is connected through a load resis~or 252 to the collector of a 2N3~04 transistor 254 which has its emitter grounded. The base of the transistor 254 is connected to ground through a resistor 256 and is connected to the anode o~ the diode 246 ~hr~ugh a resistor 258. The anode of ~he diode 246 is also connected throu~h line 106 and a resistor 26~ to the collector of a 2N3906 transistor ~2. The emitter of this PNP transistor 2~2 is coupled to a 15 volc D~Co supply via a line to 2h4. The base of the transistor 262 i5 coupled through a resistor 266 to the output of a ~tandard 7417 open collector buffer 268. The inpu~ of this buffer 26R
is coupled to the output of the NOR ~ate 234. As will be apparent to those skilled in the art, the foregoin~
structure of the diode switch 101 will cause the diode 246 to be ~orward-biased when the Carrier Enable si~nal on 1~1 is true. The reed swicch 248 will be closed when the modem is powered on. Therefore, when che Carrier Enable si~nal on the lLne 181 is true, the low impedance of ~h~
forward-biased diode 246 is presenced to the strip line and cends to pro~ide a closer match between the outpuc impedance of the cransmitter 80 and the characteristic impedance o the strip line fl4.
However, when the Car~ier Enable si~n~l on ~he line 181 is false~ the diode 246 is reverse-biased and a hi~h impedance is presented to ~he strip line 84 by the transmitter 8~). Thus, the strip line 84 i~ no~ loaded :~22~8~
~ -34-down by a low impedance at the transmitter output when the modem is in the receive or listening states.
Referring to Figure 12 there is shown a detailed logic diagram of the data encoder of ~he transmitter. The heart of the data encoder 86 is a standard 74LS109 JK positive edge tri~gered flip flop. The NRZ-S si~nal on the line ~2 is coupled through the output of a 74LS0~ and gate 273 with one of its inputs coupled to the Q output of the flip flop 270 by the line 272~ The clear input on line 274 is coupled to a constan~ positive DC voltage equivalent to a logic 1. The preset input 276 is coupled to the output of a 74LS02 NOR gate 277 which has one of its inputs coupled to the ~old Encoder si~nal on the line 178 and the other to the output of an inverter 284 which has its input coupled to a conscant DC voltage source equivalent tO a logic 1. A switch 285 is coupled to the input line 282 and to ground to cause a logic 0 condi~ion on the line 282 when the switch is in a test position. The input 282 is in a logic l condicion when the switch 2R5 is in the normal operation position.
When ~he Hold Encoder signal on the line 178 is true, the 74LS02 forces the preset input coupled to the line 27h to a logic 0 state which forces the Q output 272 of the flip flop 270 co a logic 1 condition re~,ardless of the condition at the J and K inputs 278 and 2~0 respectively and re~ardless of the condition at the clock input 2~8.
~ecause the AND gate 273 has ics other input coupled to a line 275 which is ~lways in a lo~ic 1 condition during nor~al operation, the NRZ-S signal on the line 92 is a constant lo~ic l when the signal Hold Encoder is true.
When the Mold ~ncoder signal on ~he line 178 is false, the N~R gate 277 will hold the preset input 276 of the flip flop 270 in a logic 1 condition because of the logic 1 level signal during no~mal operatiun at the node 2B2 which is converted by the invercer 284 to ~ lo~ic 0 signal on the line 286 coupled to the other inpu~ of ~he NOR ~ate 277. Thus, during normal operation, when the hold Encoder signal on the line 178 is false, both the preset and the clear inputs are in a logic 1 condition and the flip flop 270 is free to change state in response to the conditions at the J and K inputs, 278 and 280 respectively, and the clock input 288. The clock input 288 is couplea through a 74LS14 inverter 290 to the signal Tx CLK on the line 88 from the buffer 96 in Figure 6. The K input 280 is coupled to the signal Tx DATA on the line 90 while the J
input 278 is coupled through a 74LS14 inverter 292 to the line 90.
The foregoing input structure of the Elip rlop 270 implements a non-return-to-zero-space encoding scheme where a transition during a bit cel 1 indicates a logic zero and no transition indicates a logic 1. That is, when the data bit on the line 90 is a logic 1 at the time of the negative transition of the signal Tx CL~ on the line 88, the J input ~78 will be in a logic 0 condition and the R input ~BO will be i~ a logic 1 condltion. The resultant positi~e goin~ transition at the clock input 288 ~ill cause the flip flop 270 to remain in whatever state it wa~
in during the last bit cell which indicates that the data bit was a logic 1. However, when the data ~it on the line 90 is a logic 0 at the time o the negative transition of ~5 the clock si~nal on the line 88, the flip flop 270 will toggle from its previQus state, which indicates a logic zero in the bit s t ream.
Referring to Figure 13 there is shown in detail a schematic diagram of portions of the receiver~ Figure 13 includes the detailed circuitry of the active tap 110, the RF amplifier 11~, the demodulator t16, the A~C ramp generator 138, the burst switch 118$ the manual gain control 140, the sample and hold circuit 136 and the ~urst ¦ gain control 142.
The active tap 110 is comprised of a strip line 112 which contacts the strip line ~4 coupling the strip line ~2~

to a high input impedance active gain stage. The purpose of the active tap 110 is to minimize the insertion loss while presenting a high, substantially non-reactive iTnpedance to the strip line 84. The strip line 84 is an extension of the coaxial line 64 and is designed in accordance with microwave RF design principles. The strip line 112 physically touches the strip line 84 and is designed to have a capacitive reactance component of impedance which cancels out the inductive reactance component of the impedance presented by the input network of inductors and capacitors.
The active tap 110 presents an input impedance for the receiver 82 of approximately 4,000 ohms with little or no reactive component such that very little disturbance is created by the active tap 110 on the 75 ohm strip line.
It is the reactive component of the input impedance which .~ill cause reflected energy so the active tap has been designed to both present a hi~h impedence and to cancel out the reactive component of that input impedance. Thus, a large number of modems are connected to the coaxial line 64 without loading down the line.
The dimensions of the strip line 112 are critical to establishing the proper reactance cancelling component of the input impedance for the receiver. The strip line 112 has been computer optimized in the preferred embodiment, and it has been found that a strip line 112 which is approximately 0.009 inches wide by 0.584 inches long will have the proper reactive component. The strip line 112 is connected to the base lead of a Motorola MRF 904 high frequency transistor 306 through an impedance rnatching network comprised of and inductor 294 and a capacitor 298. An inductor 296 couples the node between the inductor 294 and the capacitor 298 to ground. ~n inductor 300 couples the node between the capacitor 2g8 and the base of the transistor 306 to ground throuqh a capacitor 302. The anode of a 1N4448 diode 308 is coupled to the node between the capacitor 302 and the inductor 300. The ca~hode of the diode 308 is connected to ground through a resistor 310. The anode of the diode 308 is also coupled through a resistor 312 to a 15 volt DC supply. A bypass capacitor 313 couples the ~15 volt DC supply to ~round.
The base of the transistor 306 is also coupled to ground through a capacitor 304. The purpose of the inductors 294/ 296 and 30n and the capacitors 29~, 302 and 3n4 is to match the output impedance of the strip line 112 to che input impedance of the transistor 306. The input impedance of the transistor 3n6 is defined by its S
parameters in the Motorola R.Fc Data Rook. Those skilled in the art will appreciate that the impedance looking into the necwork in~erposed between the base of the transistor 306 and the output of the strip line 112 toward the base will approximately match the input impedance of the transis~or 3n6 at the frequency of interest and have a certain reacti~e component. However the i~pedance looking ~rom the strip line 84 into ~he s~rip line 112 toward the base of the transistor 306 should ~e approximately 4,00n ohms with li~le or no reactive component.
The emitter of the ~ransistor 3~6 i5 coupled to ground throu~h the resistors 314 and 316. These resistors supply negative voltage feedback to the transistor 306 to 2S stablize it. The purpose of the diode 3n8 is to supply temperature trackin~ for Ch~ transistor 30fi to make its operations scable over a range of te~peratures.
The collector of the transistor 3Qfi is coupled to the 15 volt supply through a~ inductor 31~ and a resisLor 320. A resistor 322 is coupled across the inductor 318, and capacitors 324 and 326 are coupled between the node between the inductor 318 and ~he resistor 32~ and ~round. The collector of the transistor 306 is aL~o coupled through a capacitor 330 to the output line 113 of the acCLve ~ap which is coupled to ~he input of the RF
amplifier 114. The purpose of ~he output network ~2:29~
-3~-comprised of the inductor 318, the resisto} 322 and the capacitors 324, 32~ and 330 is to present an output impedance looking into the active ~ap from the line 113 of approximately 50 ohms.
The heart of the RF amplifier 114 is a Motorola MC
1350 integrated IF amplifier 332. The output of the amplifier 332 is applied through a transformer 334 and a capacitor 337 to the RF 338 input of the demodulator 116 by the line 119. The function of the various components in the RF amplifier 114 will be apparent to those skilled in the art.
The heart of the demodulator 116 is a Motorola MC 133n low-le~rel video detector 336. I`he detector 336 converts the modulated RF carrier at its input 338 to a varying DC
volta,~e signal at its output 120- The si~nal on the line 120 varies in DC level with t~e amplitude of the RF
carrier at the input 33~. The RF Envelope si~nal on ~he line 120 is approxlmately 2 volts for a tO0% modulated carrier at 338 and rises to ~6 volts for no carrier at the input 338. The function of the other comporlents in the demodulator 116 will be apparent to those skilled in the art.
The operation of the burst switch 118 in Fi~ure 13 is controlled by the Burst Enable signal on the line 152.
;25 The burst switch 11~S is comprised of a normally closed relay contact 339 which is coupled to the output of che sample and hold circuit 136 by the line t37 and is coupled to the gain concrol input line 117 of the RF amplifier 114 through a resisto~ 340. A separate normally open relay contact 342 is connected between ~he output 1 5n of ~he burst ~ain control 142 anà the Rain control input 1t7 of the RF amplifier 1t4 through the resistor 340. The burst F,aLn control t42 is a manually adjustable potentiometer 344 coupled between a 7.5 volt DC volta~e source and l~rOUlld, ;~

~2~

The burst enable signal on the line 152 is coupled to Che input of the relay driver invertin~ amplifier 346 which controls the relay contacts 339. When Burst Enable is true, the contac~s 339 are opened by the relay driver 346, In the preferred embodimentt the relay driver is an HI200-5 manufactured by Harris Semiconductor. The Burst Enable signal is also coupled through an inverter 348 ~o the input of an inverting relay driver amplifier 350 which controls the contacts 342 and is the same model as the driver 346. When the Burst Enable signal on t~e line 152 is true, Lhe relay driver amplifier 350 causes the contacts 342 to be closed. Thus when the Burst Enable signal is trueJ Lhe gain control input 117 of the ~F
amplifier 114 is coupled through the relay contacts 342 to a manually adjusta~le DC voltage level established by the setting of the potentiometer 344. The potentiometer 344 is set at a level to prevent the RF amplifier 114 from ~eing swamped by the burst transmission of the transmi~ter 80 in Figure 6. The demodulator 116 then converts the received signal by the RF amplifier 114 into the analog de~odulated carrier signal on the line 1~0 which is coupled to the A/D converter 122~ the carrier detector 126, and the ACG threshold detector 128 in Figure 6.
Reerring to Figure 14 there is shown ~he detailed circuitry of the A/D converter 122, the carrier detector 126 and the AGC threshold detector 128 and the sample and hold concrol circuit 134.
The A/D converter 122 is used to convert the analog signal on the line 120 to the di~ital pulses of the signal NRZ-SR on the line 124. As previously noted, the signal NRZ-SR is used by ~he modem control engine 104 in Figure 6 to detect when there is a contention on the coax cable during the burst. Further t the signal NRZ-S is used by the daca decoder 156, shown in more de~ail in Figure 15, to recover the received data and the clock encoded in the data to synchronize the local receiver clock wi~h the transmitter clock~

r.~

98~3~

--~o--The A/D con~erter 122 generates the NRZ-SR signal by using a National Semiconductor LM 360 volta~e comparator or e~uivalent to compare the si~nal on the line 120 to a reference voltage on a line 354 connected to the non-inverting input. The reference voltage on the line 354 isgenerated by a manually adjustable potentiometer 356 coupled between a 15 volt DC voltage source and ground..
In the preferred embodiment, the reference voltage on the line 354 is set at approximately 3.8 volts. The signal vn the line 120 is coupled through a resistor ~5~ to the inverting input of the comparator 352. Durin~ ~urstS the burst circuitry sets the demodulated carrier si~nal on the line 12() to a level oi 3.6 volts if only the carrier from the transmi~ter ~0 is on the line. When the si~nal on the 1~ line 120 exceeds the threshold reference vol~age on the line ~54, a positive goin~ transition occurs on the line 124. The signal on ~he line 120 will vary in amplitude because of beatin~ which is occurrin~ on the strip line ~4 because of a concention for the line with another modem which al~o bursts simultaneously. The NRZ-SR si~nal will constituce a train oi pulses randomly spaced from each ocher.
The carrier detec~ circuit 126 also has as its heart a Wational Semiconductor IM 311 volta~e comparator 360~ The inver~ing inpu~ 362 of the comparator 360 is coupled to the si~nal on che line 120 throu~h a diode 364 Rnd a resiscor 366 which funccion in conjunc~lon with a resiscor 365 and a capaci.tor 367 coupled from the Line 362 to ground to filter ~he signal and smooth it out to prevent the output signal from the comparator 360 ~n the line 374 from pulsing. It i5 desirable that once a carrier is detected, che carrier signal on the line 13~ stay on untll the signal on che line 120 ri~es to 6 volts ~or predetermlned cime, The non-inverting input 3~8 Ls co~pled to a carrier threshold manually ad~us~able potentiome~er 370 through a 98~3~

~,, resistor 372. The carrier threshold potentiometer 370 is coupled between a +5 volts DC supply and ~round and can be adjusted to establish a reference level at the input 3fi~
over a sufficient range to detect any level of carrier out to the maximum range of the system. The output of the voltage comparator 36~ on the line 374 is coupled to the D
input of a 74LS74 flip flop 37R by a line 374 and is coupled through a positive feedback resistor 371 to the non-inverting input of the comparator 3~0. The positive 1~ feedback provides a hysteresis in the switching point such ~hat the comparator will switch states when the ~oltage on the line 120 drops below approximately n.4 volts but will not switch again until the voltage on the line 120 rises above approximately 1.5 volts.
Th~ flip flop 378 serves as a di~ltal filter with a sampling rate of 3 ~egahertz because of the connection o-f the clock input 379 ~o a 3 me~ahert~ clock input. That is unless the signal at the D input on che line 374 drops to a Logic 0 for more than the period of ~he clock or during a rising clock edge, the carrier signal on the line 13~
will remain a lo~ic 1. The flip flop 378 has its preset and clear inputs both held high when the switch 376 is in the automatic gain control position. The swicch 376 has a manual gain control position which grounds the clear input of the flip flop 378 such thac the si~nal Carrier on the line 130 is always false.
The Carrier signal on t~e line 130 is coupled ~o a NAND gate 380 in the sample and hold control circ~it 134 which generates an output signal AGC KAMP not, on the line 135 which ls coupled to the AGC ra~p generator 138 in Figure 13. When the switch 37S is in che manual gain control position, the Carrier signal on ~he line 130 is always false regardless of the amplitude of the signal on the line 120 which causes the AGC RAMP not signal on the line 135 to ~?e false or a logic 1. The effect of this will be d~scussed in connection wLth the operation of the AGC RAMP genera~or 13R in Fl~ure 13.

9~18~

The ACG threshold detector 128 in ~igure 14 serves to determine when the signal on the line 120 exceeds a certain AGC threshold level established by a potentiometer 382 at the non-inverting input 384 of a National Semiconductor LM 311 voltage comparator 386 or equivalent. The signal on the line 120 is applied to the inverting input of the comparator 386. The comparator 386 is connected to have positive feedback around the comparator to cause hysteresis and to prevent oscillation. This positive feedback also avoids excessive noise in the output. The positive feedback is provided hy a resistor 388 feeding part of the output signal on the line 132 back to the non-inverting input 384. The amount of feedback is selected such that when the signal 120 falls below the 0.6 volt reference level set by the AGC
threshold potentiometer 382, the output on the line 132 goes immediately to a logic 1 condition. However, when the signal on the line 120r starting from below the 0.6 reference level begins to rise, it must reach a level of ~ approximately two volts b2fore the output on the line 13 drops to a logic 0.
During non-burst times it is the responsibility of the AGC Ramp generator 138 and the sample and hold circuit 136 in Figure 13 to work in con~unction with the AGC threshold 25 detector 128 and the sample and hold control circuit 134 in Figure 14 to adjust the gain of the ~F amplifier during the preamble of the incoming data packet to a level ~or comfortable reception of the entire data packet and then to hold the gain at that established level or the entire data packet~ This is accomplished as follows:
When the preamble of the incoming data packe~ is received t the 100~ modulated RF carrier causes the siynal on the line 120 to move from the 6 volt condition indicating no carrier to the zero volt condition, indicating full carrier at the RF input 338 of the demodulator 116. As the voltage on the line 120 coupled to the inverting input of th~ AGC threshold detector comparacor 386 passes through the 0.6 volt reference voltage established by the potentiometer 382, the output on the line 132 switches from a logic 0 to a lo~ic 1.
Because a carrier is bein~ received, the carrier detector 126 causes the Carrier si~nal on the line 130 to be true. The NAND gate 380 in the sample and hold control circuit 134 has its inputs coupled to the lines 13~ and 132 and therefore sees true sign31s at its inputs during ~he preamble period. This causes its output si~nal AGC
RAMP not to be true or a logic 0.
This AGC Ramp not signal on the line 135 is coupled to the inputs of two open collector 7417 buffers 390 and 39~
in the AGC ramp genera~or 13~ in Figure 13. The OUtpllt of the bufier 390 is coupled through a resistor 394 to the base of a PNP 2N3906 ~ransistor 396. The coLlector of thi~ transiscor is coupled throu~h a resistor 3~ and a capacitor 400 to ground. The output of ch~ buffer 3~2 is coupled to the base of a 2N3904 NPN ~ransiscor 402. The collector of the tran~istor 402 is coupled throu~h a resistor 404 to the un~rounded node of che capacitor 400. Becau~e the sl~nal on ~he line 135 i~ a lo~ic ~
durinR the preamble, the transis~or 3~6 will be turned on and the transistor 402 will be turne~ cff. Since the emitcer of the tran~ixtor 396 i~ coupled co a 7.5 voLt DC
voltage source, a current flow will be e~tabli~hed throu~h the tr~nsistor 396, ~he resistor 39R, the line 4n6, the line 408 and the capacieor 40n to zround. Thus the voltage on the line 408 will be~in to ramp up~ard during the preamble. Just before the preamble started, the voltage on the line 408 would be approximately ground by vir~ue of tran~istor 402 being turned on by a f~l~e AGC
Ramp not si~nal, i.e., a lo~ic 1. Thi~ e~tablishe~ a low re~istance path ro~ the :line 4Q~ chrough the resistor 4~4 ancl the transistor 4Q~ to the grounct conneccion at the emict~r lead of che transLstor 4~2. The lLne 408 is ~ ~ L,.

%9~

connec~ed to the input line 144 of the sample and hold circuit 136 through a capacitor 409. The heart of the sample and hold circuit 136 is a National Semiconductor LF
398 sample and hold circuit 410~
The Sample/Hold noc terminal of the sample and hold circuit 410 is connected to a line 11tR carrying the Sample/Hold not signal from the output of a NAND gate 412 in the sample and hold control circuit 134 on Figure 14.
The NAND gate 412 has one of its inputs coupled to che output of an inverted input OR gate 414 which in turn has one of its inverted inputs coupled to the line 132 from the AGC threshold de~ector 128. The other input of the NAND gate 412 is coupled to the output of an AND gate 416. This AND gate has one of its inputs coupled to the Carrier signal on the line 130 and the other input coupled to the signal Burst GC not on the line 418 from the output of the inverter 348 in the burst switch 11~ on Figure 13. When the preamble is being receivedt the transmitter 80 is not bursting and therefore the inputs to the ANP
gat~ 41~ are both in a logic 1 condition. Therefore the output on the line 419 coupled to an input of the NAND
~ate 412 is in a logic 1 condition. The o~her input to the NAND gate 412, i.e., the line 423 is also in a logic () condition at this point in time because a ull carrier is being received during the preamble which causes the output of the AGC threshold detector comparator 3~6 to assume a logic 1 condition. Therefore the inverted input OR ~ate 414 causes the signal on the line 423 to be in a logic n condition which causes the NA~D gate 412 to cause the signal Sample~Hold not on the line 148 to be in a loglc 1 condition. This causes the sample and hold chip 410 in Figure 13 to act as if a conducting wire were coupled between ~he input line 144 and the output line 137 coupled through the closed relay contacts 339 ~0 the gain control 3~ input l l 7 Of the RF a~pli~ier 332.
Thus as the preamble is just startin~ to come in r the RF amplifier 114 has its gain sec at a maximum value by - ~%2~
-virtue of the discharged condition of the capacitor 400 which was dischar~ed through the transistor 402 by the action of the signal AGC Ramp not on the line 135. The sample and hold circuit 410 continues to act as a straight-through conductor as the volca~e on the capacitor 400 begins to rise. As the voltage on the capacitor 4Q0 rises, the gain of the RF amplifier 332 is decreased whic~
is reflected in a rising DC level of the signal on the line 120. As the si~nal on the line 120 rises, it eventually reaches a cross-over point of about 2 volts at the inverting input of the AGC threshold detector comparator 386 in FL~ure 14~ However~ when this 2 volt point is reached, the output of the comparator 386 chan~es to a logic 0 which causes the output of the inverted input 1S OR gate 414 to change to a logie 1. At that time J both inputs to the NAWD gate 412 will be in a lo~ic 1 condition which causes the signal Sample/Hold not on the line 14~ co become a logic 0. When ~he line 148 drops to a logic 0 condition, the sample and hold circui~ 41 n in Fi~ure 13 ~0 holds the volca~e level on the line 137 at its then existing level thereby establishing the level of gain of che RF amplifier 114 a~ a fixed level which las~s for approximately 4 or 5 milliseconds. This period is lon~
enough to receive the entire incoming data packet.
At the same time that the signal Sample/Mold no~
changed to a logic 0, the si~nal AGC RAMP not on the line 135 also changed condition causing the translstor 4n2 to once a~ain turn on and dischar~e che capacitor 4~0 makinp, it ready for the next carrier search.
A latch 14g has its ~ Lnput coupled to the output of an inverted input Or ~ate 15t. One input ~o the ~ate 15l is coupLed to che output of the NANn ~ate 4l2 and the other input is coupled to the Q not output of the 74L574 latch 149. This Q no~ outpuc is also coupled to che other inpu~ of the inverted input Or ~ate 414~

~ , The purpose of the latch 149 is to latch the line 148 for noise immunity to noise on the line 132 during a packet. As long as a carrier is present, the Sample/Hold not signal on the line 14~ will remain in hold mode after hold has been established.
Referring to Figure 15 there is shown a detailed logic diagram of the data decoder 156 in Figure 6. The decoder is comprised of a local receiver clock 42Q which puts out a pulse train at 24 me~ahertz on the output line 422.
This local clock signal on line 422 is applied to the clock input of a divide by ei~ht counter 425 which divides the 24 megahertz clock si~nal down to the 3 meRahertz data rate of the system. The output of the counter 425 is the si~nal RECOVCLK on ~he line 424. A reframe buffer 426 has a data input coupled to the signal NRZ SR from the A/D
converter 122 in Fi~ure 14.
The local clock signal on the line 422 is coupled chrou~h an inverter 430 to the clock input 432 of the reframe buffer 426. The NRZ-SR si~nal on the line 124 represents the incomlng data from the coax ~4. The clock transitions on ~he clock inpu~ 432 to che first flip flop 434 of the reframe buf~er 426 serve co reframe che incoming data with the local clock as will be apparen~ to those skilled in the art.
Th~ reframed data appears on the Q output of the fllp flop 434, line 428, which is couplecl co the D input of a second flip flop ~36 in the reframe buffer 426~ The purpose of the second flip flop 436 is to reset all the flip flops in the divide ~y eight counter 425 whenever there is a low to high cransltio~ of the reframed incomin~
data si~nal on ~he line 428.
~ecause the phase of the signal RECOVCl,K on 424 compar~d co the phase of the clvck which W2S used ~o encode the si~nal ~RZ-SR on the line 124 is not known, there must be some struct~lre which yank~ the divide by ei~ht counter outpuc si~nal RECOV~LK signal back to ~he 38~

middle of the bit cells every ti~e the phase starts to drifc off from the transmit clock phase. The structure which acco~plishes this function is the flip flop 436 and the NAND gate 439. The flip flop 436 has its clock input cvupled to the local clock output 422. The Q not output of the flip flop 436 is coupled to one input of the NAND
gate 439 which has its other input coupled ~o the reframed data signal on the line 428. The output of the NAND gate 439 is coupled to the reset inputs of all ~hree flip flops of the divide by eight counter 425. As will be appreciated by those skilled in the ar~r the output 441 of the NAND gate 439 makes a high to low transition every time the reframed data on the line 428 ~akes a low to high transition. This causes the RECOVCLK si~nal on the line 424 to ~ake its transitions approximately ln the middle of each data bit cell of the incoming data si~nal on the line 124 to synchronize the RECOVCLK signal on the line 424 with the transmitter clock of the sending modem~ To avoid loss of synchronization during a lon~ string of one's, the transmitting client's data link controller causes æero bit insertion. That is, a zero is inserted by the transmitter after any succession of five contlguous logic I's within a frame.
The RECOVCLK signal on the line 424 is applied to the clock input of a decoder 431. The decoder 431 ls comprised of a 74LS164 shift register chip 433 having its data input coupled co ~he Reframed Data signal on the line 428. The Qa and Qb outputs of the shift register 433 of the decoder 431 are applied through a 74S86 exclusive OR
gate 435 and an inverter 437 to the D input of a 74S74 flip flop 438. The flip flop 43R has its clock input coupled ~v ~he si~nal RECOVCLK not on the line 440. The Q
OlltpUt of the flip flop 438 is the signal Rx DATA on the line 162 coupled ~o the MIJX 94. The Rx CLK signal on the line 16P in Fi~ure ~ is the same as ~he si~nal RECOVCLK
not on che line 440. The detailed desicription of the , i!~

~ 2 ~ 9 -~8-operation of the decoder 431 will be appreciated by those skilled in the art.
It will be apparent to those skilled in the art that numerous modifications can be made to the invention described without departing from the true spirit and scope of the invention as defined by the claims appended hereto. All such modifications are intended to be included within the scope of the followin~ claims.

2~

Claims (19)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. An apparatus for detecting contentions for the transmission medium in a modulated carrier local data network having a plurality of transmitter and receiver modems, each modem comprising:
means for transmitting a non data bearing burst of energy on said transmission medium;
means for receiving signals on said transmission medium, said receiving means receiving said burst while said burst is being transmitted;
means for preventing data transmission in response to detection by said receiving means of energy from any other modem; and means for transmitting data over the transmission medium if no energy from any other modem is detected.

2. An apparatus for detecting contentions for the transmission medium in a modulated carrier local data network having a plurality of transmitter and receiver modems, each modem comprising:
means for transmitting a non data bearing burst of energy;
means for varying the frequency of said burst;
means for receiving signals on said transmission medium; and means for preventing data transmission in response to detection by said receiving means of energy from any other modem.

3. An apparatus for detecting contentions for the transmission medium in a modulated carrier local data network having a plurality of transmitter and receiver modems comprising:
means for transmitting a non data bearing burst of waveform with a frequency that varies during the burst;
means for receiving signals on said transmission medium and detecting amplitude changes on said transmission media caused by interference beating between the signals from two or more transmitters contending for the transmission media; and means for detecting the presence of any signal on said transmission medium during a predetermined post burst listening period.

4. An apparatus as defined in Claim 2 wherein said non data bearing burst is a sinusoidal radio frequency carrier having a fixed amplitude.

5. An apparatus as defined in Claim 4 wherein said receiving means includes:
a variable gain receiver coupled to said transmission medium to receive carrier energy and amplify it in accordance with said variable gain;
a demodulator for converting the received signal into a D.C. signal which has an amplitude which varies with the amplitude of the output from said variable gain receiver;
a comparator means for comparing the output signal of said demodulator to a reference signal during said burst and for generating a contention signal when said D.C. signal achieves a predetermined relationship to said reference signal; and a means for setting the gain of said variable gain receiver to a predetermined level during bursting such that said comparator means will not generate said contention signal unless interference beating with another carrier is causing the amplitude of the received signal to vary.

6. An apparatus as defined in Claim 5 further including a controller means coupled to said transmitting means and said detecting means to cause said transmitting means to transmit said burst while simultaneously causing said gain setting means to set the gain of said variable gain receiver at the predetermined level to detect interference beating on said transmission medium.

7. An apparatus as defined in Claim 6 wherein said controller means also is coupled to said comparator means and causes said gain setting means to set the gain of said receiver to a second predetermined level during said post burst listening period and monitors the output of said comparator means to determine if a signal is present on said transmission media.

8. An apparatus as defined in Claim 2 or 3 further comprising means for controlling a delay imposed before a retry to transmit is initiated by generation of a random number which determines the delay.

9. An apparatus as defined in Claim 2 wherein each transmitter and receiver modem in the data network both transmits data to the other modems and receives data from the other modems on a single frequency.

10. An apparatus as defined in Claim 9 wherein each section of each modem receives data from the transmitter section in its own modem.

11. An apparatus as defined in Claim 10 further comprising means for automatically adjusting the gain of the receiver section of each modem in the data network to a predetermined level during an unmodulated preamble signal preceding each transmitted data packet and holding that level constant during receipt of the entire data packet.

12. An apparatus for detecting contentions for the transmission medium in a broadband local data network comprising:
first means for generating a burst of energy containing no data;
second means for causing the frequency of said burst to be varied during the burst;
third means for receiving energy from said transmission medium and for generating a signal when the amplitude of said received energy is above a threshold level, said third means having variable gain;
fourth means for setting the gain of said third means during said burst such that said third means will generate no signal unless interference beating is causing the amplitude of the received energy to vary;
and fifth means for determining whether interference beating has occurred and for causing a retry to transmit a predetermined period later as determined by a random number generated by the randomness of the interference beat pattern itself.

13. An apparatus as defined in Claim 3 further comprising means for imposing a delay before a retry to transmit is initiated by generation of a random number which determines the delay, said random number being generated by the randomness of the interference beat pattern.

14. An apparatus as defined in Claim 1 wherein said non data bearing burst is a sinusoidal radio frequency carrier having a fixed amplitude.

15. An apparatus for detecting contentions for the transmission medium in a modulated carrier local data network having a plurality of transmitter and receiver modems, each modem comprising:
means for transmitting a non data bearing burst of energy, said burst being a sinusoidal radio frequency carrier having a fixed amplitude;
means for receiving signals on said transmission medium, said receiving means comprising:
a variable gain receiver coupled to said transmission medium to receive carrier energy and amplify it in accordance with said variable gain;
a demodulator for converting the received signal into a D.C. signal which has an amplitude which varies with the amplitude of the output from said variable gain receiver;
a comparator means for comparing the output signal of said demodulator to a reference signal during said burst and for generating a contention signal when said D.C. signal achieves a predetermined relationship to said reference signal; and a means for setting the gain of said variable gain receiver to a predetermined level during bursting such that the comparator means will not generate said contention signal unless interference beating with another carrier is causing the amplitude of the received signal to vary; and means for preventing data transmission in response to detection by said receiving means of energy from any other modem while said burst is being transmitted.

16. An apparatus as defined in Claim 1 further comprising means for controlling a delay imposed before a retry to transmit is initiated by generation of a random number which determines the delay.

17. An apparatus as defined in Claim 1 wherein each transmitter and receiver modem in the data network both transmits data to the other modems and receives data from the other modems on a single frequency.

18. An apparatus as defined in Claim 17 wherein each section of each modem receives data from the transmitter section in its own modem.

19. An apparatus for detecting contentions for the transmission medium in a modulated carrier local data network having a plurality of transmitter and receiver modems, each modem comprising:
means for transmitting a non data being burst of energy on said transmission medium;

means for receiving signals on said transmission medium, said receiving means receiving said burst while said burst is being transmitted;
means for preventing data transmission in response to detection by said receiving means of energy from any other modem; and means for automatically adjusting the gain of the receiver section of each modem in the data network to a predetermined level during an unmodulated preamble signal preceding each transmitted data packet and holding that level constant during receipt of the entire data packet, wherein each section of each modem receives data from the transmitter section in its own modem and each transmitter and receiver modem in the data network both transmits data to the other modems and receives data from the other modems on a single frequency.