CA1230164A - Pager decoding system - Google Patents

Abstract

ABSTRACT:
"Pager decoding system."

A pager decoding system which is suitable for use with signal formats, such as POCSAG, in which code words are sent in batches, each batch containing a syn-chronisation code word and (n-1) address/message code words, n being the number of code words in a batch, each code word comprising m bits.
The pager is able to detect or regain synchro-nisation code word when the carrier signal is lost due to fading.
When synchronisation is lost input data received by the pager is combed through by switching-on the pager for a duration of m bits at intervals correspond to (n+1) code words. The data received is stored in a shift register having m stages and in which a synchronisation code word can be assembled within two batch periods. Once the synchronisation code word has been detected the pager can be switched to a normal data receiver mode.
In another fade recovery mode the (m-1)th, mth, and (m+1)th bit positions every nth code word are searched to see if a preamble or synchronisation code word is present.
If none is detected after a predetermined number of bat-ches has been searched then the pager assumes the loss of synchronisation mode described above.

Description

~;~3V~69~

The present invention relates to a pager decod-ing system for use in a paging system employing a s-tandard code such as the CCIR radiopaging Code No. 1, otherwise known as POCSAG (Bri-tish Post ~ffice Code Standardisation Advisory Group.).
The present invention will now be described, by way of example, with reference to the accompanyiny draw-ings, in which:
Figure 1 is a diagram showing POCSAG transmis-sion format, Figure 2 is a diagram showing the POCSAG addresscode word and message code word formats, Fiyure 3 is a block schematic circuit diagram of a paying receiver and shows those parts which are necessary for the understanding of the pager decoding system in accordance with the invention, Figure 4 comprises waveform diagrams 4A to 4D
which illustrate the change from the data receive mode to the face recovery mode, and Figure 5 comprises waveform diagrams 5~ to 5E
which illustrate the opera-tion of the decoding system in its carrier-off mode.
Although the POCSAG code is becoming widely known, in order to understand the present invention it is worth mentioning the signal and code word formats of POCSAG and in this respect reference is made to Figures 1 and 2 of the accompanying drawings. Figure 1 shows the signal format which comprises a preamble 10 of at least 57~ bits, which comprises alternate ones and zeroes, and a series of batch.es 12, 14 each of 544 bits. The preamble 10 at its shortest has a duration of a number of bits cor-respondinq to one of the batches plus a thirty-two bit code word. A batch 12 or 14 comprises a thirty-twc bit synchronisation code word 16 and eight frames 18, each of which frames comprises two code words ~0 each of thirty-two bits length. Thus each batch 12, 14 is formed by seventeen code words 2Q each of 32 bits.

P~B 32 958 la There are two types of code words 20, there are address code words 22 and message code words 24. The first bit of a code word determines whether it is an address code word because its value is zero or whether it is a message code word because its value is one. In the case of an address code word, bits 2 -to 19 are address bits corresponding to the eighteen most significant bits of a twenty-one bit identity assigned to the paging receiver.
The three least significant bits are not transmitted but serve to define the frame within a batch in which the address code word must be transmitted. Four discrete addresses are assigned to each paging receiver having a given twenty-one bit identity, selection of a particular ` 1230164 P~IB 32 95~ 2 16-1-1984 one of the four addreases is accorcling to the values assig-ned to tlle bit3 20 and 21. Bits twenty-two to thirt~-one are cyclic redundancy checl~ bits and the final bit, bit 32 is chosen to give even -parity on the complete code word.
~[n the case of a message code word 24 the bits

2 to 21 are assigned as message bits whicll do not follow the allocations of the address code word 22, however bits 22 to 32 do.
A batch is formed by a synchronisation code word which precedes in time sixteen other code words. Since the identity of a paging recei~-er is defined by an address code word 22 transmitted in a given time frame 18 within a batcll 12, 14, then it is unnecessary for the paging recei~-er to receive any address code words other than those in its allocated frame. Thus the paging receiver may switch off when other frames are being transmitted thus providing a battery saving capability. In any transmission of a ba-tch, an idle (unallocated) address code word is transmitted in the event that a particular code ~ord location within that batch is not required for the trans-mission of a paging call.
~ paging call requiring transmission of message code words 24 is formatted such that an appropriate number of message code words 24 related to the length of the 25 message are concatenated onto one of the address code words 22 assigned to the particular paging recei~er. Although message code words 24 (~igure 2) may continue into a sub-sequent batch due to the length of the messages, the normal batch structure, that is si~teen code words 20 30 preceded by a synchronisation code word 16 is maintained.
With the POCSAG signalling structure, a paging decoder has to synchronize itself first with the preamble 10 and second with the synchronisation code word 16. Unless the paging decoder is synchronised to the synchronisation 35 code word, it will be unable to decode successfully address code words in their assi~ned frame.
In operation, a paging receiver in its carrier-ofr rnode w}len there are no transmissions from its base lZ301 64 PIIB 3~ ~5X 3 16-1-19~4 station is usually switched on once every seventeen code ~ord5 for a ~luration of a thirty-two bi-t code word ln order to -letect the prearnble bit pattern which may be transmitted. As the preamble for POCSAG is a-t least eigllteen code words in dura-tion it ~ill quickly be detected.
Thereaf-ter the paging receiver is continuously energised for a cluration of eighteen code words in order to detect the si~chronisation code word 16 which is concatenated onto the preamble 10. Thereafter the paging receiver assumes its data receive rnode and switches its receiver section off until its assigned time frame and then switches it on for that tirne frame in order to deeode address code words.
Then the decoder will be switched off until the time slot allocated to the synchronisation code word in a subsequen-t concatenated batch, the decoder is then switched on in order to decode that synchronisation eode word and subse-quently the address code word in the following allocated frame. If the synehronisation eode word is not deteeted then the paging deeoder may not deeode address code words in the alloeated subsequent time frame. Thus it is essential to aehieve and maintain word s~lehronisation. It is im-portant that synehronisation and address eode words are deeoded aceeptably in order to Iceep a suffieiently low falsing rate.
British Patent Specification 2,~6,106A discloses a pager decoding circuit with an intelligent synchronisa-tion eireuit. This known eireuit employs a s~lehronisation strategy whieh tolerates at least some degree of error in an attempt to aehieve bateh synehronisation. The deeocling eireuit inelu~es means for e,~amining the reeei~-ed bit pattern in order to seareh initially for the presenee of preamble. ~en a mateh or near mateh to the preamble bit pattern is deteeted~ the deeoding eireuit examines the reeeived bit pattern for the synehronisa-tion eocle word.
35 l~en a mateh o-r a near matell to the s,vnehronisation eode word is achieved the deeoding eireuit is deelTled to be in bateh synehroIlisatioIl in whieh ease it is tllen abLe to examine the aclclress eocle ~ords in its assi~led ~'rarne in .~ ~.Z30~64 PIIB 3~ ')5g 4 16-1-1984 order to detect the receipt of a paging call.
The decoding circuit then examines each syn-chronisation time slot in subsequent batches in order to detec-t the s~chronisation code word in those batches and S thereafter detect address code ~rords in the allocated time frame ~rith:in those batches. If a match bet~reen the received bit pattern and the stored reference s~nchronisation code word is not achieved nor a near match to a certain number of bits in error is obtained then the address frarne is not e-camined for address code words. If the synchroni-sation code word is again not detected in the tirne slot allocated for the synchronisation code word in the next following batch, assuming that a bateh has been trans-mitted, then the decoding circuit deems tha-t batch synchro-lS nisa-tion has been lost and thence reverts -to its carrier-off mode in ~ihich it examines the received bit pattern for the preamble bit pattern or a near mateh to it.
1rhen examining the received bit pat-tern for preamble the known eircuit switches on for one eode word slot in eaeh bateh, as before, thus guaranteeing deteetion of preamble if it is being transmitted. Onee preamble has been deteeted the reeeiver then ecamines the bit pattern for the synehronisation eode word. ~len this has been deteeted the known eireuit assumes a data reeeive mode as deseribed previously.
This known deeoding eireuit has two drawbaelcs.
Firstly it eannot resume eorreet bateh synehronisation should a long fate, greater than eighteen eode words (worst ease) oeeur, eausing irreeoverable errors in the reeeived b:it pattern beeause the cireuit ~ill have re-verted to preamble deteetion operation in a earrier-off mode whilst eoded data is still being transmitted. Conse-quently the probability of detecting preamble in eoded data is very low causing batehes of data (e.g. addresses) to be overloolced. The seeond drawbaelc in the operation of this known deeoding eireuit nay oeeur if the paging reeeiver is used in a heavily loaded, zoned, transmission system. ,~ ~oned ~ransmission system as speeified ~rithin ~Z3~164 PIIB 3' ~5l~ 5 1~ 19g4 the POCSl~Cr descrip-tion wollld allow for the transmission of a preamble immediately concatenated to the end of a batclI ot` code words should the pa.ging receiver be in an overlal~ region of two transmission zones and the data transmission period in the former zone was continuous for the complete zone time period. Under such circumstances the known ^ircuit would no-t detect the transmitted pre-amble (assuning that the received bit pattern is de-cod~ble as preamble) since immediately following failure to detect a synchronisation code word, as would occur at the cnd of transmission on one zone or in an ~mzoned system, the known decoder will be only e~amining the re-ceived bit pattern for the following synchroIlisation code word wilich will not be present because preamble is being lS transmitted.
It is -the object of this present invention to recover and maintain batch synchronisation more effectively than is possible in the prior art system.
According to the present invention there is provided a pager decoding system suitable for use with a signal format in which code words of m bits are sent in batched of n code words~ each batch containing a synchro-nisation code word and (n-1) address/message code ~iords, the system comprising timing means for switching-on a re-ceiver section of the pager for a duration correspondingto m bits at inter~-als corresponding to (n+1) code words, shift register means for storing data received during the rn bit periods, the shift register naving m stages and the data being concatenated onto the data received in the 30 previous interYal, and preamble and synchro~isation code word detecting rneans coupled to the shift register means, the detecting means producing output signals in response to a prearnble bi-t pattern being cle-tected or a synchroni-sation code word being detected, one of said output sig-35 nals~ prodlIced :in response to tlle detection of the pre-amble, be-i.ng used to set the timing ;mealls to wait for synchronisation cocle worcl letectioIl and another of said output si~lals, procIuced in response to the detection of --` 1230164 P~IB 3~ ~5~ 6 16-1-19~L~

the s~Ichronisation code word being used to reset the timing means so that the pager operates in a data receive mode.
The pager decoding s,~stem in accordance ~;ith the present invention enables a transmitted signal to be de-tected and properly s,vnchronised if there has been a loss of signal due to a deep fade as well as due to the termina-tion of a previous transmission and -the commencement of a new one. ~dditionally the system is inherentl~- capable of greater battery economy in the carrier-off mode because it is turned-on every (n+1) code ~ords rather than every n code ~ords as is done in kno~-n POCSAG pagers.
The pager decoding system in accordance ~Yith the present invention may further comprise means for detecting the absence of a synchronisation code word when the pager is o~erating in its data receive mode, said neans producing an OUtp~lt signal in response to detecting the absence of the s,~Ichronisation code word such that the pager operates in a fade recovery mode, which output signal is applied to the timing means, said timing means enables data input to the shift register for at least ~ bit periods and activates the preamble and synchronisation code word de-tecting means for the (m-1)the, mth ancl (m+l )th bit periods in every nth code word, whereby in response to detecting 25 preamble or a synchronisation code ~iord the timing means is reset so that the pager operates in a data receive mode but if no synchronising sig~al is detected after a pre-determined number of batches then the pager adopts a carrier-off mode in which data is s~itched into the shift 30 register means every ~n+1) code words.
By being able to e~amiIle the input signal in the fade recovery mode for a predeterrnine-l nllmber of batches, the pager decodin~ system is capable of recoveri.n~ synchro-nisation in the event of a fade lasting several batches 35 whereas the cited kno~in s~-s tcal reverts tO a carrier-off nnode very qllickl.y w~lich means that batch s~-nchrollisation is not ach:ie~ed w~til a ne~ translllis~ioll is made, :i.e~
preambl.e translrl:ittcd.

~2~

PEIB 32 9~8 7 Referring to Figure 3, the paging receiver 100 comprises a receiver section 102 which is turned-on and -off by a receiver power control circuit 104 which is con-trolled by a timer con-trol circuit 106. A thirty-two stage shift register 108 is coupled to the receiver section 102. Outputs of each of the stages of the shift register 108 are coupled to an address detector 110 and to a pre-amble and synchronisation detector 112. In the interests of clarity not all 32 outputs have been shown. The detector 112 has two outputs 114, 116 on which appear respectively output signals indicating that the preamble bit pattern and synchronisation bit pattern have been detected. These outputs 114, 116 are connected to a pxe-amble and synchronisation pulse generator 118. In response to an output signal on the output 114, the generator 118 produces a pulse on a line 120 and in a similar manner an output signal on the output 116 causes a pulse to be pro-duced on the line 122. The lines 120 and 122 are coupled to the timer control circuit 106. A ~rame number store 124 which holds the number of the frame in which the add.ress code word is transmitted is also coupled to the timer control circuit 106.
An address store 128 which stores the addresses allocated to the paging receiver 100 is coupled to the address detector 110. An output of the detector 110 is connected to an alert control circuit 130 which controls lZ3~)164 PT~B 3~ 95~ 8 16-1-1904 the energisation of an acoustic transducer 132. The timing control circuit has an output coI~ected to the address detector 110.
Assu~ing that the paging receiver 100 is already in bit and batch synchronisation then the timing control circuit 106 causes the power control circuit 104 to ener-gise the receiver section 102 at the synchronisation code word interval and the allocated frame inter~al in each batch. If an address allocated to the paging receiver 100 is detected then the alert control circuit 130 causes the transducer 132 to be energised.
The operation of the decoding system in the fade recovery and carrier-off modes will now be described with reference to Figures 4 and 5 of the accompanying drawings.
lS In Figure ~ the left-hand part refers to the data receive mode and the right-hand par~ refers to the fade recovery mode wherein the data is lost to the receiver, this is sho~-n in broken lines in waveform diagram 4A.
In the data receive mode the preamble 10 (not shown in ~igure 4) and the synchronisation code word 16 have been detected, the receiver is both bit synchronised and batch synchronised. This is shown in wav0form diagrarn 4B wherein the receiver section 10~ (Figure 3) is switched-on or powered-up at the intervals 40 to receive the syn-chronising code word 16.
The pulse generator l1~ produces synchro~isingpulses 42, waveform diagram 4C, at times corresponding to the end of the parity bit, bit 3~, of the synchroni-sation code words 16. These pulses~ ~len generatedl are used by the timing control circuit 1 o6 to control the switching of the receiver 10~ by means of signals to the receiver power control circuit 104 for the detection of address code words and to predict the time occllrrence of the synchronisation code word at the start of the subse-quent batch by means of a counter within the tin~ing con-trol circu.t 106 which produces an output ever~ seven-teenth code ~ord in anticipat:ion of the receipt of the subsequent s~lchronisation code word.

:1230~64 PI.B 3'' 95~ 9 16-l-l9~4 Once the synchronisation code word has been de-tected, the timing control circu:it 106 switches off or powers clo~ the receiver section 102 by means of the re-ceiver power control circuit 104 until the frarne 18 (~igure 1) in wllich its address code words are assigned, at which time the timing control circuit 106 switches on the re-ceiver section 102 for the dura-tion o~ that particuiar frame, this is denoted by the pulses L~4 i,n diagram 4B. At the encl of the address frame, the timing control circuit 106 s~;itches off the receiver section 102 again until the start of the subsequent synchronisation code word time slot, at which time the receiver section 102 is again switched on in order to repeat the process.
I~en data is lost or eorrupted beyond detection, lS sa,v due to a fade iIl the received signal, as sho~n in brolcen lines in waveforln 4~, the s~chronisation code word cannot 'be detected ~hen the recei~er section 102 is s-~-it-ched on for the duration of the synchronisation code word time slot and no synchronising pulse is produced b~,- the pulse generator 118. On failing to cletect the first of these synchronisation pulses, denoted by an arro~ 46 in timin~ diagram 4D, the timing eontrol eircuit 10~ switches the pager from the data receive mode 4~ to the fade re-eovery mode 50. As no synehronising pulse 42 is gerlerated, the timi,ng control circuit lO~ inhibits the recei~er power control circuit 104 so that the reeeiver section 102 is not s~itehed on at the assigned address frame time slot.
The timing eontrol cireuit 106 continues running and causes the reeeiver seetion 102 to be switehed on every seven-teenth eode ~ord time slot in order to attempt to retainsynellronisation should the pager be in a deep fade such that data reeeption would be mairltaiIled when the fade ends.
In the fade reeovery mode it is not possible to determine whetller true data is being reeeived and henee whether bit 35 synehronisati,on is being ma-intained. Thus in order to aeeo~-nt for any timing errors introcluced, the deeoding systeln insl~ects the incoming data for pre.~ ble as ;e]l as for s,~chronisation eode wo~cd ~just in case tlle loss of data lZ30164 PIIB 32 ~15~ 10 1~ 198'i is due to a cessation of transmission of data, al the 31st, 32nd and 33rd bit positions every seventeenth code word. The face recovery mode is maintained for a predeter-minecl number of batches~ ~or e~arnple 30 batches, whereupon -the timer control circuit 106 switches the decoding system to the carrier~off mode. The e~act number of batches during .~hich the -~ace recovery mode is maintained is a function ofthe stabilities of the transmitter and receiver data frequency crystal oscillatiors and of the characteristics of the bit synchrorlisation technique employed. In order to detect the synchronisation code word at the 31st bit position, the receiver section 102 is turned-on one bit earlier than is customary. In addition, to detect the synchronisation code ~ord at the 33rd bit position the receiver section 102 is turned-off one bit later than is custosnary.
In the carrier-off mode the paging receiver section 102 is switched-on and the input signal is clocked into tlle 32-stage shift register 108 for 32 bit periods 20 and thell the receiver section 102 is switched-off. Outputs of the shift register stages are coupled in parallel to the preamble and synchronisation signal detector 112.
Assuming that the preamble bit pattern or the synchroni-sation code ~ord is not stored in the shift register 108 25 then precisely eighteen code words later the receiver section 102 is switched-on and another thirty-two bits are stored by being concatenated onto the already stored data. As each bit is clocked in a check is made by the synchronisation and preamble detector 112 to determine 30 whether 32 bits of preamble or the synchronisation code wird is present in the shift register 108. If preamble is detected which is indicative that a new transmission is being made then the synchronisation pulse gellerator 118 produces an output on the line 122 coupled to the timing 35 control circuit 106 which maintains the receiver section 10~ on ~mtil synchronisation code word is detected up to a maximllm of eigllteen cocle words duration should a syn-chronisation code word not be detected. If the synchroJli-PIIB 32 ~5~ 11 16-1-19~4 sation code w~rd is detected, the pulse generator 118 pro-duces a synchronising pulse which causes the timer control circuit 1oGto switch the decoding circuit into the data receive mode.
If the loss of signal is due to a long fade then the first thing detected will be the synchronisation word.
Thus lJy switching-on the receiver section 102 every eighteen code words, the decoder is able to comb through all the relative bit positions in a batch iIl seventeen batch durations. By using the shift register 10~ in the manner described it is possible to pick-up the synchroni-sation code word in spite of the fact that the sl~itching-on and s~itching-o~f of the ~eceiver section 10~ is not synchronised to the incoming data. How this is done will be described with reference to Figure 5.
Waveform diagram 5~ illustrates the incoming data with a synchronisation code ~iord 16 every seventeen co~e words as is usual with the POCSAG code structure.
Diagram 5B illustrates the switching-on of the receiver 102 every eighteen code words. Diagram 5C illustrates the blocks of 32 bits of data being read into the shift regis-ter 114. The left-hand block received first comprises 32 bits of which some are the first part ~ of a s~lchronisation code word~ The next time the receiver section 102 is turned 25 on the first data to be read-in is the second part Y of the subse~uent syllchronisation code word.~At the instant that the concatenated parts ~Y and Y are configured in the shift register to ~orm a complete synchronisation code word, see diagram 5D~ the synchronisation si~llal detector 30 112 recognises that the shift register 1~ contains the synchronisation code word and causes the svnchronising pulse generator 11~ to produce a syrlchronisatiorl pulse, diagram 5~, which is used by the timing control circuit 106 to reset tho receiver power control circuit 10!~ so 35 that the pager operates in a data receive mode as before.
~ lthough the decodin~ system in accordance with the present invention has been described with particular reference to the POC~ ~ormat~ it is cal~able with suitable ~Z30~6~
PI-IB 32 95~ 12 16-1-19~4 ada~tions to other format5 having a fi.xed length regular batch structure, each batch comprising a synchronisation code ~rord ~Those position in a batch is fi~ed relative to address and/or message code ~ords, and multiples of such batches being concatenated ~ith the preceding preamble to form a transmitted sigrnal.

Claims (3)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A pager decoding system suitable for use with a signal format in which code words of m bits are sent in a sequence of batches of n code words, each batch containing a synchronization code word followed by (n-1) address/
message code words, and each sequence of batches being preceded by a predetermined preamble pattern of at least m(n+1) bits, the system comprising a receiver section for receiving data, timing means for switching-on the receiver sec-tion of the pager for a duration corresponding to m bits at intervals corresponding to (n+1) code words, shift register means, coupled to the receiver section, for storing data received during the m bit periods, said shift register having m stages and the data being con-catenated onto the data received in a previous interval, and preamble and synchronization code word detecting means coupled to said shift register means and to a pre-amble and synchronization pulse generator, the preamble and synchronization pulse generator being further coupled to the timing means, said detecting means producing output signals in response to a preamble bit pattern being detected or a synchronization code word being detected, one of said output signals, produced in response to the detec-tion of the preamble bit pattern, being used to set said timing means for maintaining said receiving station in an ON state until said synchronization code word is detected, another of said output signals, produced in response to the detection of the synchronization code word, being used to reset said timing means so that the pager operates in a data receive mode wherein said receiving station is main-tained in an OFF state for a predetermined time period after detection of said synchronization code word and then is switched ON for a predetermined time frame.

2. A pager decoding system as claimed in Claim 1, further comprising means for producing an output signal in response to the absence of a synchronization code word when the pager is operating in its data receive mode, which output signal is applied to the timing means so that the pager operates in a fade recovery mode, said timing means then enabling data input to the shift register for at least (m+2) bit periods and activating said preamble and synchronization code word detecting means for the (m-1), m-th and (m+1)-th bit periods in every n-th code word, whereby in response to the subsequent detection of a syn-chronization code word, said timing means is reset so that the pager operates in said data receive mode, and in response to a synchronization code word not being detected within a predetermined number of batches, said timing means is reset so that the pager operates in a carrier-off mode in which data is switched from said receiving station into said shift register after reception of each sequence of (n+1) code words.

3. A pager receiver including a decoding system as claimed in Claim 1 or 2.