CA1232037A - Filter arrangement - Google Patents
Filter arrangementInfo
- Publication number
- CA1232037A CA1232037A CA000480109A CA480109A CA1232037A CA 1232037 A CA1232037 A CA 1232037A CA 000480109 A CA000480109 A CA 000480109A CA 480109 A CA480109 A CA 480109A CA 1232037 A CA1232037 A CA 1232037A
- Authority
- CA
- Canada
- Prior art keywords
- capacitor
- resistor
- voltage
- filter arrangement
- resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G5/00—Tone control or bandwidth control in amplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H11/00—Networks using active elements
- H03H11/02—Multiple-port networks
- H03H11/24—Frequency-independent attenuators
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H19/00—Networks using time-varying elements, e.g. N-path filters
Abstract
Abstract "Filter arrangement."
A first resistor (R1) and a first capacitor (C1) constitute a filter arrangement having a time constant which is not very accurate due to the inaccuracy of the resistor and the capacitor values in intergrated circuits. The time constant is adjusted using a circuit comprising a reference resistor (R2) and a switched capacitor (C3).
The value of the reference resistor (R2) and the equivalent resistance of the switched capacitor (C3) are compared by means of an integrator (C2, 2) from whose output (9) a control voltage is taken via a hold circuit (C4, C5), which control voltage is equal to the voltage at that point on the reference resistor where the resistance value is equal to that of the switched capacitor (C3). By means of comparator (21 to 30) and switches (S11 to S20) a percentage of the total resistance of the first resistor (R1) is short-circuited, which percentage is equal to the difference between the resistance of the reference resistor (R2) and the equivalent resistance of the switched capacitor (C3), expressed as a percentage of this equivalent resistance.
(Fig. 1).
A first resistor (R1) and a first capacitor (C1) constitute a filter arrangement having a time constant which is not very accurate due to the inaccuracy of the resistor and the capacitor values in intergrated circuits. The time constant is adjusted using a circuit comprising a reference resistor (R2) and a switched capacitor (C3).
The value of the reference resistor (R2) and the equivalent resistance of the switched capacitor (C3) are compared by means of an integrator (C2, 2) from whose output (9) a control voltage is taken via a hold circuit (C4, C5), which control voltage is equal to the voltage at that point on the reference resistor where the resistance value is equal to that of the switched capacitor (C3). By means of comparator (21 to 30) and switches (S11 to S20) a percentage of the total resistance of the first resistor (R1) is short-circuited, which percentage is equal to the difference between the resistance of the reference resistor (R2) and the equivalent resistance of the switched capacitor (C3), expressed as a percentage of this equivalent resistance.
(Fig. 1).
Description
PUN 11020 1 Lo 08-02-t985 Filter arrangement."
The invention relates to a filter arrangement comprising at least a first resistor and a first capacitor, which provide a time constant determined by the product of the resistance of the resistor and the capacitance of the capacitor, and a trimming circuit comprising a switched second capacitor for adjusting the time constant of the filler arrangement.
a means of such an arrangement any known active or passive filter can be formed. In particular, such an arrangement may constitute an input or an output filter in a discrete-time switched-capacitor filter.
In integrated circuits resistors and capacitors can be fabricated only with a limited accuracy, so that the time constants in the filter arrangements are very inaccurate. The article "Switched Resistor Filters - A continuous Time Approach to Monolithic MOS-Filter Design", EYE Transactions on Circuits and Systems, Vol. Casey, No. 5, May 1982, pages 30~-315, describes a filter arrangement which enables more accurate time constants to be obtained. In this arrangement each resistor is constituted by a field-effect transistor (FETE whose resistance is determined by a voltage established between the gate and 2û the source by means of a capacitor. For each resistor there are provided two Frets which are alternately switched into the actual filter and into a trimming circuit. In this trimming circuit the resistance of the FRET
is made equal to the equivalent resistance of a switched capacitor. This result in a time constant which only depends on the ratio between the capacitance of the capacitor in the actual filter and the capacitance Or the switched capacitor and on the clock frequency with which the capacitor is switched. During integration a very accurate capacitance ratio between the capacitors can be obtained. The clock frequency. which is determined by an external circuit, can also be defined accurately.
However, a drawback of this known circuit arrangement is that the non-linear relationship between the resistance of the Frets and the control voltages gives rise to inaccuracies in the time constants.
Moreover, the resistances of the Frets at equal gate voltages are found PUN 11020 2 1Z3~3~ 08-02-19~5 to differ substantially due to differences in the voltages on the drain electrodes and on the backdates. Further, the use of two Frets for each resistor is likely to give rise to crosstalk between the clock signals employed for switching.
Therefore, it is an object of the invention to provide a filter arrangement comprising a trimming circuit by means of which the time constants can be adjusted more accurately. According to the invention a filter arrangement of the type specified in the opening paragraph is characterized in that the trimming circuit further lo comprises - a reference resistor across which a first reference voltage is established, a second reference voltage which is proportional to the first reference voltage is established across the second capacitor, - first means or generating a control voltage which is a measure of the difference between the resistance of the reference resistor and the equivalent resistance of the second capacitor, which equivalent resistance is substantially equal to the ratio between the second reference voltage and the charge transfer per unit of time averaged over a specific time interval owing to the complete discharging of said second capacitor in said time interval, and - second means for short-circuiting a part of the first resistor by means of said control voltage, which part expressed as a percentage of the total resistance of said first resistor, is substantially equal to the difference between the resistance of the reference resistor and the equivalent resistance of the second capacitor, expressed as a percentage of the resistance of the reference resistor.
Like the known arrangement, an arrangement in accordance with the invention utilizes the fact that the time constant constituted by the equivalent resistance of the second switched capacitor and the first 30 capacitor depends only on the ratio between the capacitances of these capacitors and on the clock period with which the second Capacitor is switched. The invention is based on the recognition of the fact that this dependence can also be obtained for the actual time constant of the filter by comparing the value of a reference resistor with the 35 equivalent resistance of the switched second capacitor in a trimming circuit in order to determine the position on the reference resistor where its resistance value is equal to that of the switched suctioned capacitor. The desired time constant of the filter is then obtained by 1232~33~7 PUN 1102û 3 Deb short-circuiting the first resistor from the same relative position as the position found on the reference resistor.
in a filter arrangement in accordance with the invention real resistors are trimmed, thereby precluding in the occurrence of non-linearities. Since the filter comprises only one resistor for each time constant, there is no cross-talk between the switching clocks. Another major advantage of an arrangement in accordance with the invention is that all the time constants of a filter arrangement can be adjusted by means of one trimming circuit.
In an embodiment of the invention the first means for generating the control voltage may comprise an integrator which comprises an amplifier having an inverting input, a non-inverting input at a fixed potential. and an output which is fed back to the inverting input by means of a third capacitor, which inverting input is further connected to a first terminal of a reference resistor whose second terminal is at a first reference potential, which integrator integrates the current through the reference resistor during a first time interval, the second capacitor supplying an amount of charge corresponding to a voltage across the switched capacitor equal to the second reference voltage to the inverting input at a first instant in the first time interval and the control voltage being taken from the output of the amplifier at a second instant in the first time interval. In the case of a positive first reference voltage the voltage on the integrator decreases linearly when the integration interval begins. At the instant that the charge on the second capacitor is applied to the input of the amplifier a voltage transient occurs on the output, after which the voltage again decreases linearly. If at the second instant the total voltage variation at the output of the integrator has become equal to zero, the equivalent resistance of the second capacitor will be equal to 30 the resistance of the reference resistor. If at the second instant the voltage at the output of the integrator is positive the equivalent resistance of the second capacitor will be smaller than the value of the reference resistor. The voltage on the output of the integrator is then equal to the voltage across the difference between the resistance no the 35 reference resistor and the equivalent resistance of the second capacitor.
The first means may be characterized further in that they comprise:
- a first switch arranged between the output and the inverting input of 1232~37 the amplifier.
- a second switch for connecting a first terminal of the second capacitor to a third terminal which is at a second reference potential and to a first point which is at the same potential as the non-inverting input of the amplifier,- a third switch for connecting the second terminal of the second capacitor to a second point which is at the same potential as the non-inverting input of the amplifier and to the inverting input of the amplifier, and - first and second clock means for controlling the first switch, the second switch and the third switch, the first clock means switching the second capacitor between the third terminal and the second point and short circuiting the third capacitor by means of the first switch during a second time interval, and the second clock means switching the second capacitor between the first point and the inverting input of the amplifier during a third time interval starting at the first instant and continuing until at least the second instant.
The first means may further comprise a hold circuit for holding the output voltage of the integrator from the second instant until the corresponding instant in the next integration interval.
Suitably, the hold circuit may constitute a filter circuit for filtering undesired signal components out of the output voltage of the integrator. Such a hold circuit may comprise a fourth capacitor which can be connected to the output of the amplifier and in parallel with a fifth capacitor by a fourth switch.
The second means for short-circuiting parts of the first resistor may be characterized in that they comprise a plurality of comparators having first inputs and second inputs, of which the first inputs carry the control voltage of which the second inputs are coupled 30 to equidistantly spaced lappings on the reference resistor, which comparators further comprise first outputs and second outputs for controlling switches which can short-circuit parts of the first resistor, which parts, expressed as percentages of the total resistance of said first resistor, are substantially equal to the parts situated 35 between the lappings on the reference resistor, expressed as percentages of the total resistance of said reference resistor. Preferably, the comparators exhibit hysteresis in order to ensure that they are not responsive to, for example, noise. If the filter arrangement comprises PUN 11020 5 1~32Q37 OB-02-19B5 further resistors which define further "time constants" in conjunction with associated capacitors. these further resistors may be provided with switches which can short-circuit parts of the resistors, which parts, expressed as percentages of the total resistance of said further resistors, are substantially equal to the parts situated between the lappings on the reference resistor, expressed as percentages of the total resistance of said reference resistor, and the first outputs and Tao second outputs of the comparators control the switches associated with these resistors.
The invention, will now be described in more detail, by way ox example, with reference to the accompanying drawings, in which Fig. 1 shows a first embodiment of the invention, Fig. 2 shows the clock signals for controlling the switches and some voltage waveforms appearing in the arrangements shown in Fig. 1 and Fig. 3 shows a second embodiment of the invention.
Fig. t shows a first filter arrangement in accordance with the invention. The actual filter is constituted by a passive first-order low-pass filter comprising a resistor R1 - R and a capacitor C1 - C
providing a time constant ARC, in which the input signal V1 to be filtered is applied to the resistor R1 and the filtered signal is taken from the capacitor C1. However, the resistor R1 and the capacitor C1 cannot be integrated very accurately, so that the ARC time constant is very inaccurate, In order to obtain an accurate time constant the filter arrangement is provided with a trimming circuit.
This circuit comprises an integrator constituted by an operational amplifier 2 having an inverting input 3, a non-inverting input I, and an output 5. The non-inverting input is at a reference voltage, in the present case 0 V. Capacitor C2 which can be short-circuited by means 30 Of a switch 51~ provides feedback from the output 5 to the inverting input 3. A reference resistor R2 R is arranged between the inverting input 3 and the input 6 of the integrator. A reference voltage OR is applied to the input 6. The integrator further comprises a capacitor C3 which can be switched between the input 6 and the earthing point B
35 and between the inverting input 3 and the earthing point 7 by means of switches So and So. The output 5 of the integrator is also connected to a hold and filter circuit comprising a capacitor I and a hold capacitor C5. By means of a switch So the capacitor C4 can be 123;2~37 PUN 11020 6 aye connected to the output 5 of the integrator and to the terminal 9 of the capacitor C5. It is to be noted that the switches So to So may be of any known type and may comprise, for example, p-channel field-effect transistors. The switches So to So are controlled by clock means 1û, shown schematically, which supply clock pulses 01 and 02' Towards its end which is connected to the amplifier 2 the reference resistor R2 comprises a plurality of regularly spaced lappings 11 to 20, which are each connected to one of the inputs of Out of the comparators 21 to 30, whose other inputs are connected to the output 9 of the hold circuit. The resistor R1 of the filter also comprises a plurality of lappings 31 to 40 which are spaced in the same way as the lappings on the reference resistor R2 because in the present example the reference resistor is identical to the resistor R1. The outputs of the comparators 21 to 30 control switches S11 to 15 S20, which can connect the lappings 31 to 40 to the junction point So of the resistor R1 and the capacitor C1 and which can thus short-circuit parts of the resistor R1. The switches S11 to S20 may comprise, for example, an N-channel and a P-channel field effect transistor whose source and drain electrodes have been interconnected.
The operation of the arrangement will be described with reference to Fig. 2, in which Figs. pa and 2b show the clock signals 01 and 02 for controlling the switches 51 to So and Figs. 2c and Ed show the voltage VOW on the output 5 of the integrator and the voltage Vow on the output 9 of the hold circuit, respectively.
If the clock signal 01 is low the switches So to So are in position 1 and if the clock signal 01 is high the switches 51 to So are open, unless the clock signal 02 is low, in which case the switches So to So are in position 2. If the clock signal 02 is high the switches So to So are open, unless the clock 30 signal 01 is low.
In the interval t1-t2 of the clock signal 01 the capacitor C2 is short-circuited by the switch So, so that this capacitor is fully discharged. The current through the reference resistor R2 is then drained to the output of the operational amplifier 35 2. At the same time capacitor C3 is charged to the reference voltage OR. At the instant to at which the clock signal 01 goes hit"
the switch So opens so that the input voltage OR is integrated by the integrator. The voltage on the output 5 of the integrator thin lZ3Z~3~
decreases in conformity with the equation:
Vow OR R2C2 11) At the instant t = to the clock signal 02 goes low. The capacitor C3 is then connected to the inverting input 3 of the amplifier 2 so that the voltage on this input becomes equal to -OR. Since the non-inverting input 4 at a voltage of O V the inverting input 3 is a virtual earthing point. The operational amplifier 2 immediately causes the inverting input 3 to return to zero volts via capacitor C2. As a result of this, a voltage transient will appear on the output S of the integrator at the instant t - to, which transient is given by:
Vow - OR C9 12) After this voltage transient the integration of the reference voltage OR proceeds in the same way, so that the voltage Vow on the output then varies as shown in Fig. 2c.
At the instar1t t to tot- clock signal 02 goes high again, so that the switch So is oper1ed. The capacitor C4 therm carries the output voltage Vow at the instant t to, i.e. the voltage at an instant to - to - to after the beginning of the integration. At the instant t - to the clock signal 01 goes low again, so that the switch 54 is set to position 1. The voltage on the hold capacitor C5 then becomes equal to the voltage on capacitor C4. it has been assumed that a number of clock cycles has ela~secd prior to the instant t - t11 because in reality the voltage on the capacitor C5 will not be equal to the voltage on the capacitor C4 until a number of clock cycles has elapsed due to the voltage division 30 effected by these capacitors. As a result of this, the hold circuit also constitutes a filter circuit. Spurious voltages in the output voltage of the integrator as a result of, for example, switching transients or noise will influence the voltage on the hold capacitor only to a small extent owing to the voltage division. In this respect it is an advantage 35 that the hold capacitor C5 has a substantially higher capacitance the the capacitor I
For this voltage Vow on the output 9 of the hold circuit it follows from equations (1) and (2) that:
232~3~
PUN 11020 Oboes V 2 VOW (t = to) - OR (C2 R2C2) (3) If capacitors C2 and C3 are identical, i.e. C2 = C3 = OR, it follows that t m I ) This voltage is equal to the voltage at that point on the reference lo resistor R2 where the resistance between this point and the input 6 lo equal to the equivalent resistance of the capacitor C3, which resistance is equal to tm/CR over the interval to Indeed the voltage between this point and input 6 is equal to:
OR R C
The invention relates to a filter arrangement comprising at least a first resistor and a first capacitor, which provide a time constant determined by the product of the resistance of the resistor and the capacitance of the capacitor, and a trimming circuit comprising a switched second capacitor for adjusting the time constant of the filler arrangement.
a means of such an arrangement any known active or passive filter can be formed. In particular, such an arrangement may constitute an input or an output filter in a discrete-time switched-capacitor filter.
In integrated circuits resistors and capacitors can be fabricated only with a limited accuracy, so that the time constants in the filter arrangements are very inaccurate. The article "Switched Resistor Filters - A continuous Time Approach to Monolithic MOS-Filter Design", EYE Transactions on Circuits and Systems, Vol. Casey, No. 5, May 1982, pages 30~-315, describes a filter arrangement which enables more accurate time constants to be obtained. In this arrangement each resistor is constituted by a field-effect transistor (FETE whose resistance is determined by a voltage established between the gate and 2û the source by means of a capacitor. For each resistor there are provided two Frets which are alternately switched into the actual filter and into a trimming circuit. In this trimming circuit the resistance of the FRET
is made equal to the equivalent resistance of a switched capacitor. This result in a time constant which only depends on the ratio between the capacitance of the capacitor in the actual filter and the capacitance Or the switched capacitor and on the clock frequency with which the capacitor is switched. During integration a very accurate capacitance ratio between the capacitors can be obtained. The clock frequency. which is determined by an external circuit, can also be defined accurately.
However, a drawback of this known circuit arrangement is that the non-linear relationship between the resistance of the Frets and the control voltages gives rise to inaccuracies in the time constants.
Moreover, the resistances of the Frets at equal gate voltages are found PUN 11020 2 1Z3~3~ 08-02-19~5 to differ substantially due to differences in the voltages on the drain electrodes and on the backdates. Further, the use of two Frets for each resistor is likely to give rise to crosstalk between the clock signals employed for switching.
Therefore, it is an object of the invention to provide a filter arrangement comprising a trimming circuit by means of which the time constants can be adjusted more accurately. According to the invention a filter arrangement of the type specified in the opening paragraph is characterized in that the trimming circuit further lo comprises - a reference resistor across which a first reference voltage is established, a second reference voltage which is proportional to the first reference voltage is established across the second capacitor, - first means or generating a control voltage which is a measure of the difference between the resistance of the reference resistor and the equivalent resistance of the second capacitor, which equivalent resistance is substantially equal to the ratio between the second reference voltage and the charge transfer per unit of time averaged over a specific time interval owing to the complete discharging of said second capacitor in said time interval, and - second means for short-circuiting a part of the first resistor by means of said control voltage, which part expressed as a percentage of the total resistance of said first resistor, is substantially equal to the difference between the resistance of the reference resistor and the equivalent resistance of the second capacitor, expressed as a percentage of the resistance of the reference resistor.
Like the known arrangement, an arrangement in accordance with the invention utilizes the fact that the time constant constituted by the equivalent resistance of the second switched capacitor and the first 30 capacitor depends only on the ratio between the capacitances of these capacitors and on the clock period with which the second Capacitor is switched. The invention is based on the recognition of the fact that this dependence can also be obtained for the actual time constant of the filter by comparing the value of a reference resistor with the 35 equivalent resistance of the switched second capacitor in a trimming circuit in order to determine the position on the reference resistor where its resistance value is equal to that of the switched suctioned capacitor. The desired time constant of the filter is then obtained by 1232~33~7 PUN 1102û 3 Deb short-circuiting the first resistor from the same relative position as the position found on the reference resistor.
in a filter arrangement in accordance with the invention real resistors are trimmed, thereby precluding in the occurrence of non-linearities. Since the filter comprises only one resistor for each time constant, there is no cross-talk between the switching clocks. Another major advantage of an arrangement in accordance with the invention is that all the time constants of a filter arrangement can be adjusted by means of one trimming circuit.
In an embodiment of the invention the first means for generating the control voltage may comprise an integrator which comprises an amplifier having an inverting input, a non-inverting input at a fixed potential. and an output which is fed back to the inverting input by means of a third capacitor, which inverting input is further connected to a first terminal of a reference resistor whose second terminal is at a first reference potential, which integrator integrates the current through the reference resistor during a first time interval, the second capacitor supplying an amount of charge corresponding to a voltage across the switched capacitor equal to the second reference voltage to the inverting input at a first instant in the first time interval and the control voltage being taken from the output of the amplifier at a second instant in the first time interval. In the case of a positive first reference voltage the voltage on the integrator decreases linearly when the integration interval begins. At the instant that the charge on the second capacitor is applied to the input of the amplifier a voltage transient occurs on the output, after which the voltage again decreases linearly. If at the second instant the total voltage variation at the output of the integrator has become equal to zero, the equivalent resistance of the second capacitor will be equal to 30 the resistance of the reference resistor. If at the second instant the voltage at the output of the integrator is positive the equivalent resistance of the second capacitor will be smaller than the value of the reference resistor. The voltage on the output of the integrator is then equal to the voltage across the difference between the resistance no the 35 reference resistor and the equivalent resistance of the second capacitor.
The first means may be characterized further in that they comprise:
- a first switch arranged between the output and the inverting input of 1232~37 the amplifier.
- a second switch for connecting a first terminal of the second capacitor to a third terminal which is at a second reference potential and to a first point which is at the same potential as the non-inverting input of the amplifier,- a third switch for connecting the second terminal of the second capacitor to a second point which is at the same potential as the non-inverting input of the amplifier and to the inverting input of the amplifier, and - first and second clock means for controlling the first switch, the second switch and the third switch, the first clock means switching the second capacitor between the third terminal and the second point and short circuiting the third capacitor by means of the first switch during a second time interval, and the second clock means switching the second capacitor between the first point and the inverting input of the amplifier during a third time interval starting at the first instant and continuing until at least the second instant.
The first means may further comprise a hold circuit for holding the output voltage of the integrator from the second instant until the corresponding instant in the next integration interval.
Suitably, the hold circuit may constitute a filter circuit for filtering undesired signal components out of the output voltage of the integrator. Such a hold circuit may comprise a fourth capacitor which can be connected to the output of the amplifier and in parallel with a fifth capacitor by a fourth switch.
The second means for short-circuiting parts of the first resistor may be characterized in that they comprise a plurality of comparators having first inputs and second inputs, of which the first inputs carry the control voltage of which the second inputs are coupled 30 to equidistantly spaced lappings on the reference resistor, which comparators further comprise first outputs and second outputs for controlling switches which can short-circuit parts of the first resistor, which parts, expressed as percentages of the total resistance of said first resistor, are substantially equal to the parts situated 35 between the lappings on the reference resistor, expressed as percentages of the total resistance of said reference resistor. Preferably, the comparators exhibit hysteresis in order to ensure that they are not responsive to, for example, noise. If the filter arrangement comprises PUN 11020 5 1~32Q37 OB-02-19B5 further resistors which define further "time constants" in conjunction with associated capacitors. these further resistors may be provided with switches which can short-circuit parts of the resistors, which parts, expressed as percentages of the total resistance of said further resistors, are substantially equal to the parts situated between the lappings on the reference resistor, expressed as percentages of the total resistance of said reference resistor, and the first outputs and Tao second outputs of the comparators control the switches associated with these resistors.
The invention, will now be described in more detail, by way ox example, with reference to the accompanying drawings, in which Fig. 1 shows a first embodiment of the invention, Fig. 2 shows the clock signals for controlling the switches and some voltage waveforms appearing in the arrangements shown in Fig. 1 and Fig. 3 shows a second embodiment of the invention.
Fig. t shows a first filter arrangement in accordance with the invention. The actual filter is constituted by a passive first-order low-pass filter comprising a resistor R1 - R and a capacitor C1 - C
providing a time constant ARC, in which the input signal V1 to be filtered is applied to the resistor R1 and the filtered signal is taken from the capacitor C1. However, the resistor R1 and the capacitor C1 cannot be integrated very accurately, so that the ARC time constant is very inaccurate, In order to obtain an accurate time constant the filter arrangement is provided with a trimming circuit.
This circuit comprises an integrator constituted by an operational amplifier 2 having an inverting input 3, a non-inverting input I, and an output 5. The non-inverting input is at a reference voltage, in the present case 0 V. Capacitor C2 which can be short-circuited by means 30 Of a switch 51~ provides feedback from the output 5 to the inverting input 3. A reference resistor R2 R is arranged between the inverting input 3 and the input 6 of the integrator. A reference voltage OR is applied to the input 6. The integrator further comprises a capacitor C3 which can be switched between the input 6 and the earthing point B
35 and between the inverting input 3 and the earthing point 7 by means of switches So and So. The output 5 of the integrator is also connected to a hold and filter circuit comprising a capacitor I and a hold capacitor C5. By means of a switch So the capacitor C4 can be 123;2~37 PUN 11020 6 aye connected to the output 5 of the integrator and to the terminal 9 of the capacitor C5. It is to be noted that the switches So to So may be of any known type and may comprise, for example, p-channel field-effect transistors. The switches So to So are controlled by clock means 1û, shown schematically, which supply clock pulses 01 and 02' Towards its end which is connected to the amplifier 2 the reference resistor R2 comprises a plurality of regularly spaced lappings 11 to 20, which are each connected to one of the inputs of Out of the comparators 21 to 30, whose other inputs are connected to the output 9 of the hold circuit. The resistor R1 of the filter also comprises a plurality of lappings 31 to 40 which are spaced in the same way as the lappings on the reference resistor R2 because in the present example the reference resistor is identical to the resistor R1. The outputs of the comparators 21 to 30 control switches S11 to 15 S20, which can connect the lappings 31 to 40 to the junction point So of the resistor R1 and the capacitor C1 and which can thus short-circuit parts of the resistor R1. The switches S11 to S20 may comprise, for example, an N-channel and a P-channel field effect transistor whose source and drain electrodes have been interconnected.
The operation of the arrangement will be described with reference to Fig. 2, in which Figs. pa and 2b show the clock signals 01 and 02 for controlling the switches 51 to So and Figs. 2c and Ed show the voltage VOW on the output 5 of the integrator and the voltage Vow on the output 9 of the hold circuit, respectively.
If the clock signal 01 is low the switches So to So are in position 1 and if the clock signal 01 is high the switches 51 to So are open, unless the clock signal 02 is low, in which case the switches So to So are in position 2. If the clock signal 02 is high the switches So to So are open, unless the clock 30 signal 01 is low.
In the interval t1-t2 of the clock signal 01 the capacitor C2 is short-circuited by the switch So, so that this capacitor is fully discharged. The current through the reference resistor R2 is then drained to the output of the operational amplifier 35 2. At the same time capacitor C3 is charged to the reference voltage OR. At the instant to at which the clock signal 01 goes hit"
the switch So opens so that the input voltage OR is integrated by the integrator. The voltage on the output 5 of the integrator thin lZ3Z~3~
decreases in conformity with the equation:
Vow OR R2C2 11) At the instant t = to the clock signal 02 goes low. The capacitor C3 is then connected to the inverting input 3 of the amplifier 2 so that the voltage on this input becomes equal to -OR. Since the non-inverting input 4 at a voltage of O V the inverting input 3 is a virtual earthing point. The operational amplifier 2 immediately causes the inverting input 3 to return to zero volts via capacitor C2. As a result of this, a voltage transient will appear on the output S of the integrator at the instant t - to, which transient is given by:
Vow - OR C9 12) After this voltage transient the integration of the reference voltage OR proceeds in the same way, so that the voltage Vow on the output then varies as shown in Fig. 2c.
At the instar1t t to tot- clock signal 02 goes high again, so that the switch So is oper1ed. The capacitor C4 therm carries the output voltage Vow at the instant t to, i.e. the voltage at an instant to - to - to after the beginning of the integration. At the instant t - to the clock signal 01 goes low again, so that the switch 54 is set to position 1. The voltage on the hold capacitor C5 then becomes equal to the voltage on capacitor C4. it has been assumed that a number of clock cycles has ela~secd prior to the instant t - t11 because in reality the voltage on the capacitor C5 will not be equal to the voltage on the capacitor C4 until a number of clock cycles has elapsed due to the voltage division 30 effected by these capacitors. As a result of this, the hold circuit also constitutes a filter circuit. Spurious voltages in the output voltage of the integrator as a result of, for example, switching transients or noise will influence the voltage on the hold capacitor only to a small extent owing to the voltage division. In this respect it is an advantage 35 that the hold capacitor C5 has a substantially higher capacitance the the capacitor I
For this voltage Vow on the output 9 of the hold circuit it follows from equations (1) and (2) that:
232~3~
PUN 11020 Oboes V 2 VOW (t = to) - OR (C2 R2C2) (3) If capacitors C2 and C3 are identical, i.e. C2 = C3 = OR, it follows that t m I ) This voltage is equal to the voltage at that point on the reference lo resistor R2 where the resistance between this point and the input 6 lo equal to the equivalent resistance of the capacitor C3, which resistance is equal to tm/CR over the interval to Indeed the voltage between this point and input 6 is equal to:
OR R C
2 R
(5) This voltage corresponds to a resistance value equal to:
t t I - R m (it) The control voltage as given by equation (4) appears on a input of each comparator 21 to 30. The inputs of the comparators 21 to 30 which are connected to the lappings 11 to 20 on the reference resistor R2 carry a voltage which increases stops from zero volts. The outputs of the 25 comparators 21 to 30 for which the control voltage Vow on one input is higher than the tapped voltage on the other input set the corresponding switches S11 to S20 connected to the lappings 11 to 40 from position 1 to position 2. As a result of this, a part of resistor R1 is short-circuited, which part is substantially equal to the part of the 30 reference resistor R2 across which the voltage Vow appears.
The effective time constant of the filter arrangement then becomes equal to:
off RX . C C to (7) Thus, the time constant is determined by the ratio between two capacitances, which can be established accurately by means of integrated-circuit technology, and by a time interval, which can be defined very 1~232~
accurately by the clock means.
The accuracy with which the time constant is realized also depends on the number of comparators used. Only in the case of an unlimited number of comparators a part of the resistor R1 is short-circuited which corresponds to the control voltage Vow. In the case ova limited number of comparators the accuracy depends on the fraction of the resistor which can be short-circuited and the number of comparators used for this purpose. The magnitude of the fraction is determined by the inaccuracy in the value of the uncorrected time constant R7C1 of the filter. If this is for example 25Z, it is adequate when I of the resistor can be short-circuited. The reference resistor and the resistor to be trimmed can only be made equal to each other with a limited accuracy by means of integrated circuit technology. The maximum number of comparators for short circuiting a specific fraction then depends on the inaccuracy in the equality of the resistors.
The comparators may be of any customary type. In order to ensure that if the control voltage on one input is substantially equal to the taped voltage on the other input, the outputs of the comparators cannot alternately short-circuit and not short-circuit a portion of the resistor, for example in response to noise, the comparators preferably exhibit hysteresis in their control characteristics. As a result of this, the part which is short-circuited, for example if the control voltage exceeds the tapped voltage, is not switched in again until the control voltage has become a specific amour smaller than the tapped voltage In the present embodiment the value of the resistor R1 to be trimmed is equal to the value of the reference resistor R2, so that the desired time constant is obtained by short-circuiting a part of the resistor R1 equal to that part of the reference resistor R2 across 30 which the control voltage appears. However, the resistor to be trimmed may alternatively have a resistance value which differs from that of the reference resistor. The tapping on the resistor R1 to be trimmed should then be arranged in such a way that the part which can be short-circuited, expressed as a percentage, is equal to the part with the 35 lappings of the reference resistor R2. The effective time constant Isle equation 7) is then equal to:
Jeff R2 ' off R2CR to (8) In the present embodiment prior to the integration period the capacitor C3 is connected to terminal 6 which is at the reference voltage OR.
In an alternative embodiment capacitor C3 may be connected to a separate terminal, which is at a reference voltage OR' - OR, where is a proportionately constant. In order to obtain the same equivalent resistance of capacitor C3 as in the embodiment described, the total amount of charge of capacitor C3 should be the same.
Capacitor C3 should then have a capacitance C3' = I
In the present embodiment the capacitor I is disconnected from the output of the integrator at the instant t - to, at which the capacitor C3 is disconnected from the inverting input 3 of the integrator. It is noted that the capacitor C3 may be disconnected from this input at an instant later than t - to. An advantage of the filter arrangement in accordance with the invention is that all the time constants in the filter can be adjusted simultaneously by means of one trimming circuit.
An embodiment in which two time constants are adjusted will be described with reference to Fig. 3, which shows a second-order Sullen and Key filter. This filter is employed as an anti-aliasing input filter for a discrete-time switched-capacitor filter. Identical parts bear the same reference numerals as in Fig. 1. The actual filter comprises a resistor R1 and a resistor R3 which should bear a specific relation to the capacitor C1 and the capacitor C6 for a specific filter action. The resistor R3 and capacitor C6 are connected to the non-inverting input of an operational amplifier 60 with full negative feedback, whose inverting input is connected to that terminal of the capacitor C1 which is remote from the junction point 50. The resistor R3 comprises 30 lappings 71 to 80 which, like the lappings on the resistor R1, are spaced from each other at distances whose ratio to the distances between the lappings 11 to 20 on the reference resistor is equal to the ratio between the resistance values of these resistors. The lappings are connected to switches S21 to S30 which, like the switches S11 to 35 S20, are controlled by the outputs of the comparators 21 to 30. Thus, a part of the resistor R3 is short-circuited which is proportional to the part of the resistor R1 which is short-circuited. The two resistors are then trimmed in such a way that in conjunction with the ~L232~37 PUN 11020 11 Owe capacitors they give the desired filter characteristic.
The invention is not limited to the embodiments described in the foregoing but may also be used for the adjustment of time constants in any passive or active filter arrangement. Further, a large number of modifications of the embodiments described are possible. For example, instead of the integrator, any other circuit for generating a control voltage which is a measure of the difference between the resistance of the reference resistor and the equivalent resistance of the switched capacitor may be used, For the hold circuit many other circuit arrangements are conceivable to those skilled in the art, If clocked comparators are employed in which the voltages on the outputs do not change between two clock periods, the hold circuit may be dispendr,d with,
(5) This voltage corresponds to a resistance value equal to:
t t I - R m (it) The control voltage as given by equation (4) appears on a input of each comparator 21 to 30. The inputs of the comparators 21 to 30 which are connected to the lappings 11 to 20 on the reference resistor R2 carry a voltage which increases stops from zero volts. The outputs of the 25 comparators 21 to 30 for which the control voltage Vow on one input is higher than the tapped voltage on the other input set the corresponding switches S11 to S20 connected to the lappings 11 to 40 from position 1 to position 2. As a result of this, a part of resistor R1 is short-circuited, which part is substantially equal to the part of the 30 reference resistor R2 across which the voltage Vow appears.
The effective time constant of the filter arrangement then becomes equal to:
off RX . C C to (7) Thus, the time constant is determined by the ratio between two capacitances, which can be established accurately by means of integrated-circuit technology, and by a time interval, which can be defined very 1~232~
accurately by the clock means.
The accuracy with which the time constant is realized also depends on the number of comparators used. Only in the case of an unlimited number of comparators a part of the resistor R1 is short-circuited which corresponds to the control voltage Vow. In the case ova limited number of comparators the accuracy depends on the fraction of the resistor which can be short-circuited and the number of comparators used for this purpose. The magnitude of the fraction is determined by the inaccuracy in the value of the uncorrected time constant R7C1 of the filter. If this is for example 25Z, it is adequate when I of the resistor can be short-circuited. The reference resistor and the resistor to be trimmed can only be made equal to each other with a limited accuracy by means of integrated circuit technology. The maximum number of comparators for short circuiting a specific fraction then depends on the inaccuracy in the equality of the resistors.
The comparators may be of any customary type. In order to ensure that if the control voltage on one input is substantially equal to the taped voltage on the other input, the outputs of the comparators cannot alternately short-circuit and not short-circuit a portion of the resistor, for example in response to noise, the comparators preferably exhibit hysteresis in their control characteristics. As a result of this, the part which is short-circuited, for example if the control voltage exceeds the tapped voltage, is not switched in again until the control voltage has become a specific amour smaller than the tapped voltage In the present embodiment the value of the resistor R1 to be trimmed is equal to the value of the reference resistor R2, so that the desired time constant is obtained by short-circuiting a part of the resistor R1 equal to that part of the reference resistor R2 across 30 which the control voltage appears. However, the resistor to be trimmed may alternatively have a resistance value which differs from that of the reference resistor. The tapping on the resistor R1 to be trimmed should then be arranged in such a way that the part which can be short-circuited, expressed as a percentage, is equal to the part with the 35 lappings of the reference resistor R2. The effective time constant Isle equation 7) is then equal to:
Jeff R2 ' off R2CR to (8) In the present embodiment prior to the integration period the capacitor C3 is connected to terminal 6 which is at the reference voltage OR.
In an alternative embodiment capacitor C3 may be connected to a separate terminal, which is at a reference voltage OR' - OR, where is a proportionately constant. In order to obtain the same equivalent resistance of capacitor C3 as in the embodiment described, the total amount of charge of capacitor C3 should be the same.
Capacitor C3 should then have a capacitance C3' = I
In the present embodiment the capacitor I is disconnected from the output of the integrator at the instant t - to, at which the capacitor C3 is disconnected from the inverting input 3 of the integrator. It is noted that the capacitor C3 may be disconnected from this input at an instant later than t - to. An advantage of the filter arrangement in accordance with the invention is that all the time constants in the filter can be adjusted simultaneously by means of one trimming circuit.
An embodiment in which two time constants are adjusted will be described with reference to Fig. 3, which shows a second-order Sullen and Key filter. This filter is employed as an anti-aliasing input filter for a discrete-time switched-capacitor filter. Identical parts bear the same reference numerals as in Fig. 1. The actual filter comprises a resistor R1 and a resistor R3 which should bear a specific relation to the capacitor C1 and the capacitor C6 for a specific filter action. The resistor R3 and capacitor C6 are connected to the non-inverting input of an operational amplifier 60 with full negative feedback, whose inverting input is connected to that terminal of the capacitor C1 which is remote from the junction point 50. The resistor R3 comprises 30 lappings 71 to 80 which, like the lappings on the resistor R1, are spaced from each other at distances whose ratio to the distances between the lappings 11 to 20 on the reference resistor is equal to the ratio between the resistance values of these resistors. The lappings are connected to switches S21 to S30 which, like the switches S11 to 35 S20, are controlled by the outputs of the comparators 21 to 30. Thus, a part of the resistor R3 is short-circuited which is proportional to the part of the resistor R1 which is short-circuited. The two resistors are then trimmed in such a way that in conjunction with the ~L232~37 PUN 11020 11 Owe capacitors they give the desired filter characteristic.
The invention is not limited to the embodiments described in the foregoing but may also be used for the adjustment of time constants in any passive or active filter arrangement. Further, a large number of modifications of the embodiments described are possible. For example, instead of the integrator, any other circuit for generating a control voltage which is a measure of the difference between the resistance of the reference resistor and the equivalent resistance of the switched capacitor may be used, For the hold circuit many other circuit arrangements are conceivable to those skilled in the art, If clocked comparators are employed in which the voltages on the outputs do not change between two clock periods, the hold circuit may be dispendr,d with,
Claims (10)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A filter arrangement comprising at least a first resistor and a first capacitor. which arrangement has a time constant which is determined by the product of the resistance of the resistor and the capacitance of the capacitor, and a trimming circuit comprising a switched second capacitor for adjusting the time constant of the filter arrangement, characterized in that the trimming circuit further comprises:
- a reference resitor across which a first reference voltage is established, a second reference voltage which is proportional to the first reference voltage is established across the second capacitor, - first means for generating a control voltage which is a measure of the difference between the resistance of the reference resistor and the equivalent resistance of the second capacitor, which equivalent resistance is substantially equal to the ratio between the second reference voltage and the charge transfer per unit of time averaged over a specific time interval owing to the complete discharge of said second capacitor in said time interval, and - second means for short-circuiting a part of the firt resistor by means of said control voltage, which part, expressed as a percentage of the total resistance of said first resistor, is substantially equal to the difference between the resistance of the reference resistor and the equivalent resistance of the second capacitor, expressed as a percentage of the resistance of said reference resistor.
- a reference resitor across which a first reference voltage is established, a second reference voltage which is proportional to the first reference voltage is established across the second capacitor, - first means for generating a control voltage which is a measure of the difference between the resistance of the reference resistor and the equivalent resistance of the second capacitor, which equivalent resistance is substantially equal to the ratio between the second reference voltage and the charge transfer per unit of time averaged over a specific time interval owing to the complete discharge of said second capacitor in said time interval, and - second means for short-circuiting a part of the firt resistor by means of said control voltage, which part, expressed as a percentage of the total resistance of said first resistor, is substantially equal to the difference between the resistance of the reference resistor and the equivalent resistance of the second capacitor, expressed as a percentage of the resistance of said reference resistor.
2. A filter arrangement as claimed in Claim 1, characterized in that the first means comprise an integrator which comprises an amplifier having an inverting input, a non-inverting input at a fixed potential, and an output which is fed back to the inverting input by means of a third capacitor, which inverting input is further connected to a first terminal of a reference resistor whose second terminal is at a first reference potential, which integrator intergrates the current through the reference resistor during a first time interval, the second capacitor supplying an amount of charge corresponding to a voltage across the switched capacitor equal to the second reference voltage to the inverting input at a first instant in the first time interval and the control voltage being taken from the out-put of the amplifier at a second instant in the first time interval.
3. A filter arrangement as claimed in Claim 2, characterized in that the first means further comprise - a first switch arranged between the output and the inverting input of the amplifier, - a second switch for connecting a first terminal of the second capacitor to a third terminal which is at a second reference potential and to a first point which at same potential as the non-inverting input of the amplifier, - a third switch for connecting the second terminal of the second capacitor to a second point which is at the same potential as the non-inverting input of the amplifier and to the inverting input of the amplifier, and - first and second clock means for controlling the first switch, the second switch and the third switch, the first clock means switching the second capacitor between the third terminal and the second point and short-circuiting the third capacitor by means of the first switch during a second time interval, and the second clock means switching the second capacitor between the first point and the inverting input of the amplifier during a third time interval starting at the first instant and continu-ing until at least the second instant.
4. A filter arrangement as claimed in Claim 3, char-acterized in that the first means further comprise a hold circuit for holding the output voltage of the integrator from the second instant until the corresponding instant in the next integration interval.
5. A filter arrangement as claimed in Claim 4, char-acterized in that the hold circuit also constitutes a filter circuit for filtering undesired signal components out of the output voltage of the integrator.
6. A filter arrangement as claimed in Claim 5, char-acterized in that the hold circuit comprises a fourth cap-acitor which can be connected to the output of the ampli-fier and in parallel with a fifth capacitor by a fourth switch.
7. A filter arrangement as claimed in Claim 6, char-acterized in that the fourth switch is controlled by the first and second clock means, the first clock means con-necting the fourth capacitor in parallel with the fifth capacitor during the second time interval and the second clock means connecting the fourth capacitor to the output of the amplifier during the third time interval.
8. A filter arrangement as claimed in Claim 1, char-acterized in that the second means comprise a plurality of comparators having first inputs and second inputs, of which the first inputs carry the control voltage and of which the second inputs are coupled to equidistantly spaced tappings on the reference resistor, which comparators further com-prise first outputs and second outputs for controlling switches which can short-circuit parts of the first resis-tor, which parts, expressed as percentages of the total resistance of said first resistor, are substantially equal to the parts situated between the tappings on the reference resistor, expressed as percentages of the total resistance of said reference resistor.
9. A filter arrangement as claimed in Claim 8, char-acterized in that the comparators each have a first thres-hold for the voltage difference between the first input and the second input, above which first threshold the sign of the voltage difference between the first output and the second output changes and have a second threshold, which is lower than the first threshold, for the voltage differ-ence between the first input and the second input, below which second threshold the sign of the voltage difference between the first output and the second output again changes.
10. A filter arrangement as claimed in Claim 8 or 9, characterized in that for each resistor in the filter arrangement, which resistor should bear a specific rela-tionship to the associated capacitor in order to obtain a desired filter action, there are provided associated switches which can short-circuit parts of the resistor, which parts expressed as percentages of the total nests-lance of said resistor, are substantially equal to the parts situated between the tappings on the reference resistor, expressed as percentages of the total resistance of said reference resistor, and the first outputs and second outputs of the comparators control the switches associated with these resistors.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| NL8401370 | 1984-05-01 | ||
| NL8401370A NL8401370A (en) | 1984-05-01 | 1984-05-01 | FILTER SWITCHING. |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1232037A true CA1232037A (en) | 1988-01-26 |
Family
ID=19843872
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000480109A Expired CA1232037A (en) | 1984-05-01 | 1985-04-25 | Filter arrangement |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US4691171A (en) |
| EP (1) | EP0163333B1 (en) |
| JP (1) | JPS60254815A (en) |
| CA (1) | CA1232037A (en) |
| DE (1) | DE3578529D1 (en) |
| NL (1) | NL8401370A (en) |
Families Citing this family (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0191529B1 (en) * | 1985-02-13 | 1991-11-27 | Philips Electronics Uk Limited | Electrical filter |
| GB2189955B (en) * | 1986-04-30 | 1990-02-14 | Philips Electronic Associated | Electrical filter |
| GB2190255B (en) * | 1986-04-30 | 1989-11-29 | Philips Electronic Associated | Electrical filter |
| JPS6335006A (en) * | 1986-07-30 | 1988-02-15 | Toshiba Corp | Automatic adjusting filter |
| US5063309A (en) * | 1990-03-28 | 1991-11-05 | Silicon Systems, Inc. | High frequency continuous time filter |
| US5124593A (en) * | 1990-09-26 | 1992-06-23 | National Semiconductor Corporation | Continuous-time filter tuning circuit and method |
| US5243239A (en) * | 1991-01-22 | 1993-09-07 | Information Storage Devices, Inc. | Integrated MOSFET resistance and oscillator frequency control and trim methods and apparatus |
| CA2100568C (en) * | 1991-01-22 | 2000-11-07 | Sakhawat Khan | Integrated mosfet resistance and oscillator frequency control and trim methods and apparatus |
| ES2123538T3 (en) * | 1992-07-24 | 1999-01-16 | Alsthom Cge Alcatel | FREQUENCY TUNING SYSTEM FOR AN OTA-C PAIR. |
| JPH0760988B2 (en) * | 1993-02-15 | 1995-06-28 | 日本電気株式会社 | Filter circuit |
| EP0851378B1 (en) * | 1996-12-30 | 2004-03-10 | DATALOGIC S.p.A. | Method and device for measuring and regulating a time constant of an electronic circuit forming part of an optical code reader |
| FR2775141B1 (en) | 1998-02-19 | 2002-10-11 | Sgs Thomson Microelectronics | TIME CONSTANT CALIBRATION DEVICE |
| US6873205B1 (en) | 2000-10-27 | 2005-03-29 | The Trustees Of Columbia University In The City Of New York | Active continuous-time filter with increased dynamic range in the presence of blocker signals |
| US7646236B2 (en) * | 2006-04-07 | 2010-01-12 | Qualcomm Incorporated | Method and apparatus for tuning resistors and capacitors |
| TWI381173B (en) * | 2008-10-29 | 2013-01-01 | Raydium Semiconductor Corp | Capacitance measurement circuit and capacitance measurement method thereof |
| CN111342818A (en) * | 2018-12-19 | 2020-06-26 | 力智电子股份有限公司 | Filter and operation method thereof |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3070762A (en) * | 1960-05-02 | 1962-12-25 | Texas Instruments Inc | Voltage tuned resistance-capacitance filter, consisting of integrated semiconductor elements usable in phase shift oscillator |
| FR2109514A6 (en) * | 1969-06-20 | 1972-05-26 | Anvar | |
| US3715680A (en) * | 1971-07-29 | 1973-02-06 | Bell Telephone Labor Inc | Active rc loss equalizer |
| US3760289A (en) * | 1972-06-21 | 1973-09-18 | Kinetic Technology Inc | Active filter network having a variable center frequency |
| US3824501A (en) * | 1973-07-12 | 1974-07-16 | Bell Telephone Labor Inc | Automatic cable equalizer |
| GB1585081A (en) * | 1976-01-07 | 1981-02-25 | Perkin Elmer Ltd | Scanning spectrophotometers |
| US4132957A (en) * | 1977-10-26 | 1979-01-02 | Hekimian Laboratories, Inc. | Programmable amplifier |
| US4392068A (en) * | 1981-07-17 | 1983-07-05 | General Electric Company | Capacitive commutating filter |
| NL8203979A (en) * | 1982-10-15 | 1984-05-01 | Philips Nv | Analogue attenuator controlled by binary switches - is used for volume and tone controls in stereo HI=FI systems using resistive ladder and divider chain |
-
1984
- 1984-05-01 NL NL8401370A patent/NL8401370A/en not_active Application Discontinuation
-
1985
- 1985-04-24 DE DE8585200636T patent/DE3578529D1/en not_active Expired - Lifetime
- 1985-04-24 EP EP85200636A patent/EP0163333B1/en not_active Expired
- 1985-04-25 CA CA000480109A patent/CA1232037A/en not_active Expired
- 1985-04-29 US US06/728,126 patent/US4691171A/en not_active Expired - Fee Related
- 1985-04-30 JP JP60093509A patent/JPS60254815A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| DE3578529D1 (en) | 1990-08-09 |
| NL8401370A (en) | 1985-12-02 |
| JPS60254815A (en) | 1985-12-16 |
| US4691171A (en) | 1987-09-01 |
| EP0163333A1 (en) | 1985-12-04 |
| EP0163333B1 (en) | 1990-07-04 |
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