CA1234436A - Arrangement for providing data signals for a data display system - Google Patents
Arrangement for providing data signals for a data display systemInfo
- Publication number
- CA1234436A CA1234436A CA000465216A CA465216A CA1234436A CA 1234436 A CA1234436 A CA 1234436A CA 000465216 A CA000465216 A CA 000465216A CA 465216 A CA465216 A CA 465216A CA 1234436 A CA1234436 A CA 1234436A
- Authority
- CA
- Canada
- Prior art keywords
- signals
- bit
- map memory
- buffer
- microprocessor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
- G09G5/39—Control of the bit-mapped memory
- G09G5/393—Arrangements for updating the contents of the bit-mapped memory
Abstract
ABSTRACT OF THE DISCLOSURE
The present invention includes a microprocessor which acts to generate groups of its signals from its read only memory (ROM), thereby forming character representations of groups of coded signals, such as ASCII coded signals, coming from a main data processing device. The groups of bit signals are temporarily stored in a buffer which at a subsequent time transmits, in parallel, groups of said bit signals to a bit map memory through logic circuitry. The group, or block, transfer of these bit signals in parallel occurs during horizontal or vertical blank periods. The parallel transfer during the blank periods provides part of the basis for acceleration of the transfer of data to a display device as compared with the prior art. In addition, the microprocessor provides address information signals to a graphic display controller, which in turn provides starting addresses for the location of the bit signals in addition, a bit map memory device is employed to provide pixel information to a CRT display device to create the characters to be displayed.
The present invention includes a microprocessor which acts to generate groups of its signals from its read only memory (ROM), thereby forming character representations of groups of coded signals, such as ASCII coded signals, coming from a main data processing device. The groups of bit signals are temporarily stored in a buffer which at a subsequent time transmits, in parallel, groups of said bit signals to a bit map memory through logic circuitry. The group, or block, transfer of these bit signals in parallel occurs during horizontal or vertical blank periods. The parallel transfer during the blank periods provides part of the basis for acceleration of the transfer of data to a display device as compared with the prior art. In addition, the microprocessor provides address information signals to a graphic display controller, which in turn provides starting addresses for the location of the bit signals in addition, a bit map memory device is employed to provide pixel information to a CRT display device to create the characters to be displayed.
Description
~3~3~
AN IMPROVED ARRANGEMENT FOR PROVIDING
DATA SIGNALS FOR A DATA DISPLAY SYSTEM
In order to show on a cathode ray tube (CRT) screen some image, whether it be text or graphics, the CRT beam must be turned on (brightened in the case of -the image being bright and the background dull) at the correct -time to produce a dot, or a series of dots to make a bar, and the like. The foregoing necessitates -that the display system have a data storage means which transmits data signals, representing the image to be displayed, in synchronism with clock signals from a clock signal generator.
In the prior art, the clock generator is usually located in the CRT circuitry. In synchronism with the clock signals the CRT beam is turned on (or not turned on) as the beam gets to the correct data location. It should be understood that in the case of the intelligence being in a dark mode, against a bright background, then the beam would be turned off. All of the foregoing is well understood in the prior art.
Further in the major part of the prior art, if a system is going to display both graphics and text, two different memory and control systems have been employed. It has been only when the information is finally transmitted to the CRT device that the graphics and text signals have been meshed, or multiplexed.
The introduction of the bit map memory, to the display art, has made the task somewhat easier because in a bit map memory, there is a memory for each pixel location on the CRT screen. Hence, whatever image is to be seen (either text, or graphics, or a combination of both) can be written into the bit map memory and from that one memory was it is scanned) both graphics end text data signals can be -transmitted to the CRT screen to be shown.
The major problem that occurs in -the prior art is that the bit map memory was not used for text but the text I
was encoded Eros a c~ilaracter geIler~tor anal contirlually transmitted to -the CRT. While the prior art system aye fast, it required two separate memory systems. The present system permits both text and graphics to use the same memory while S operating with the speed of the separate memories of -the prior art. The prevent invention employs a five-fold improvement in transmitting data signals to the data display device as will be explained below.
The system in accordance with the invent ion employs a microprocessor as a dedicated slave device to a main data processing system The microprocessor responds -to groups of coded signals from the main data processing system. In response to each group of coded signals, the present system provides a group of bit signals from a ROM means, which kit signals graphically define the text character assigned to the coded set of signals being received. In other words, if eight bits of ASCII coded signals are transmitted from the main data processing device, that group of signals causes, in a preferred embodiment, the cJeneration of a group of by 10 bits from the ROM in the microprocessor. In the microprocessor, ten bytes of elate are stored in ROM memory means for each possible text character to be shown. The group of bit signals are block trrlnsferrec1 from -the ROM of the microprocessor to buffer.
Thereafter the bit signal group, which has been properly arranc~ec1, is transferred in parallel during sync signal blank periods. To effect this block transfer, a graphic display ~3~3~
controller device provides addresses to the bit map memory so that a bloc transfer is written into the bit map memory at a particular starting address.
The microprocessor is programmed to determine whether a bloc -transfer requires one or two cycles end accordingly characters are transferred from the buffer in either one step or two steps. The bit signals in the buffer are located -to match where, within a word location, in the bit map memory they are to be ultimately located. The dedication of the microprocessor to lo providing encoded signals, the speed of the parallel transfer, the fact that the transfer is made during the horizontal and vertical blank period, utilization of the graphic display controller to provide the addresses, and the prearrangement of the bits in the buffer enable the data transfer to be more rapidly accomplished than in the prior art.
In one broad aspect of the invention there is provided a system for displaying text which has a CRT display means and a bit map memory means connected thereto to store pull information for transfer to said CRT display means, characteri~ecl in -that said system has an arrangement for accelerating data signals representing text characters from a main computer means to said bit map memory means comprising in combination: microprocessor means connected to said main computer -to receive therefrom instruction signals, address signals and coded signals representing text characters, said microprocessor means providing groups of bit signals arranged in different positions, each defining a different Tut character -to ~L23~L~3~i 'ye disp'~ye~, ion resporlse to r*celving different groups of said coded signals; buffer means connected to said microprocessor means -to receive said groups of bit signals and store -the same for further transmission in parallel; first circuitry means connecting said buffer means to said bit map memory means for transmitting said groups of bit signals in parallel from said buff means to said bit map memory means; controller circuitry means connected to said microprocessor means to receive address signals and instruction signals therefrom; second circuitry means connecting said controller circulator means to said bit map memory means to provide address signals and instruction signals thereto to direct said different groups of bit signals to particular locations in said bit map memory and alternatively to cause said bit map memory means to read out pixel information from certain locations to said CRT display means.
In a second broad aspect of the invention there is provided a system which has a CRT display means for displaying text characters and a bit map memory means connected thereto to store pixel information for -transfer to said CRT display means, an arrangement for accelerating data signals representing text characters from a main computer to said bit map memory means comprising in combination: microprocessor means having at least ROM means connected to said main computer to receive therefrom instruction signals, address signals and coded signals representing text characters, said ROM means providing respectively different matrices of bit signals, each of which matrices defines a -text character in configuration, in response owe -to receiving different groups of said coded Saigon.; buffer means connected to said microprocessor means to receive spa d matrices of bit signal and store the same for further transmisc,iorl in parallel; first circuitry means disposed to connect said buffet Nancy to said bit map memory means for transmitting said matrices of bit signals in parallel thereto;
control circuitry means connected to said microprocessor means to receive address signals and instruction signals therefrom; second circuitry means connecting said controller circuitry means to said bit map memory to provide address signals thereto direct said matrices of bit signals to particular locations in said bit map memory mean and alternatively to cause said bit map memory means to read said pixel information from certain locations to said CRT display means; said control circuitry means including clock signal generator ineans which generate write signals, horizontal sync signals end vertical sync signals, said clock signal venerator means being connected at least to said buffer means to cause said buffer means to transmit segments of said mutters of bit signals during horizontal and vertical blank time; masking meals -to selectively mast signals being transmitted from said buffer means to said bit map memory means; and third circuitry mean coupling said masking means to said microprocessor means to receive control signals therefrom whereby in response to a group of coded signals being -transmitted by void main computer to said microprocessor means, said coaled signals are encoded into a matrix of bit signals, arranged into suitable position I
in said microprocessor means and transmitted to solid buffer means and whereby -thereafter in response -to cluck signals during horizontal and vertical blank times yips of bit signals from said Burr means are transmitted in parallel to said bit mop memory Nancy whereat -they are partially sassed ankle partially masked enroot to location designated by address psychoanalyze trarlsmit-ted to said bit map memory from said controller circuitry.
The objects and features of the present invention will be better understood after studying -the description below taken in conjunction with the drawings wherein:
Figure 1 is a block schematic diagram ox the present system;
Figure depicts the letter D as it appears in the ROM and as i-t later appears in the buffer;
Figure 3 depicts the letter E as it appears in the TOM and as it later appears in the buffer;
Fleecer 4 depicts the letter C as lo appears in the ROM end as it later appears in the buffer; and Figure 5 depicts the transfer of Betty sinkholes from -the buffer -to the hit map memory.
no Figure I -there it Sheehan main computer 11 which is connected by channel 13 -to a microprocessor 15. It should be understood that -the main computer 11 is the heart of a co~nputincg system and is connected to many terminals end peripherals which are not shown in Figure 1. It should also be understood that the channels shown thwart Figure 1 comprise a plurality of I
parallel wit en and the signals transmitted over -these channels include address signals, instruction signals, end data to be displayed signals. The microprocessor in a preferred embodiment is an 8085 manufactured by Intel Corporation. It should be understood -that the microprocessor 15 includes a-t least a central processing unit, ROM memory means, RAM memory means and logic circuitry to generate instruction information signals.
As can be gleaned from Figure 1 tiler is a buffer 23 connected by channel 21 to RAM 18 of the microprocessor 15. The present system operates with a 16-bit word that is broken up into two 8-bit bytes. in the ROM 16 there is 5 toned a plurality of 8 by 10 bit groups, each of which configures a character to be displayed. In other words, as will become clearer hereinafter, the letter "D" would be graphically represented by bit signals stoned in an appropriate location in -the ROM. Also as will become clearer hereinafter, when -the group of bit signals is -transmitted frown the ROM, it is transmitted through the central processing unit of the microprocessor back into the RAM 13, and in the course of that action the bit signals are revolved so that when they are transmitted from the RAM 18 along charlrlel 21 to buffer 23, they end up in the proper locations for transmission to the bit map memory 33. The arrancJincJ of the bits etc. will be more clearly understood from the discussion of Figures 2 through 5.
The buffer 23 is formed -to store 16 bits in a row and to store 10 rows. One character at a -time is -transferred from the RUM 18 to the buffer 23. The bit signals stoned in -the ~23~ 6 buffer 23 representing the character are trarl~ferrecl in parallel 16 bits at a time through the multiplier (hereinafter MU) 27 along channel 37 and into the bit map memory I As will become clearer in the discussion of Figures 2 through 5 when the bit signals are transmitted into the bit map memory six. of those bits are masked out on chamlel 40. The bit signals from the buffer 23 are located in the bit map memory in accordance with address signals present on channel 39.
As can also be leaned from an examination o. Figure 1 there is a graphic display controller 19 connected to the microprocessor 15 through the channel 17. In a preferred embodiment the graphic display controller (hereinafter referred to as the GDC) is a MICRO POD 7220 manll~actured by NEW
Corporation. The GDC 19 has memory means to store address and instruction infoxmatiorl from the microprocessor and also includes two registers which can be incremented or decrement Ed to accomplish the changing of an address. The GDC 19 also includes a write signal generator which provides clod signals as well as horizontal and vertical sync signals. The sync signals are transmitted on connection 57 to the CRT 51 to the srlift register 53 and to the microprocessor 15. Write clod slsnals are transmitted to the buffer 23 and to destination counter Lo over connection 31. In addition -the horizontal and vertical sync signals operate within the GDC I to accomplish certain operations thereirl. For every horizontal blank period there are seven write cycles generated and for every vertical blank period there are 594 write cycles generated. Other rates could be used.
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The desalination counter 41 is included in the layout in Figure 1 because it is part of an overall system. However, it is not employed with the invention described in this description. The operation of -the destination counter 41 is described in my cop ending Canadian Patent Application 465,215 filed October 11, 1984, Dante et at. and which is assigned to the assigrlee of this application. The GDC 19 accepts address information and instruction information from the microprocessor 15 and holds that information to effect address signals on channel 39 so that characters being transferred from the buffer 23 are properly located in the bit map memory 33.
As can be seen in Figure 1, the GDC 19 transmits its address information along channel 25, along chanrlel 35, through MU 29, through decoder 45, onto the channel US. The MU 29 has a second input on chamlel 43, from the destination counter 41, but as was mentioned above, -that circuitry plays no role in the operation of the present invention. Insofar as -the present invention is concerned, it can be assumed that the address information from -the GDC 19 always goes through the MU 29, i.e., that the MU 29 is not even present. The decoder 45 takes the address information and decodes it into the proper signals to operate with the bit map memory 33. In a preferred embodiment the decoder 45 is a 74LS253, manufactured by Teas Irlstrument6 Corporation. Those signals are held in the latch so that they are present when the bit signals on channel 37 arrive at the bit map memory 33. It should also be noted that channel 91 and latch 93 are also circuitry elements which are used in ~l~3~13~
connection with a split-screen smooth scrolling circuit described in the aforementioned co-pending application, i.e., channel 91, latch I end channel 97 play no role in the operation of the present invention.
When the characters have been stored in the bit map memory 33, they are read therefrom in response to address sunless on channel 39. the bit signals or pixel signals being transmitted from the bit map memory 33 are transmitted along channel 56 to shift requester 53. The signals are advanced from lo shift resister 53 in response to horizontal sync signals on connection 57. When the signals are advanced from shift register 53 they pass along channel 58 to the CRT 51. Since the signals on channel 58 are transmitted in synchronism with the horizontal sync signal, they are present in synchronism with the byway of the CRT, which is what is required to provide the display.
In Figure 1 there is shown a MU 31 which has two inputs, namely channels 49 and 47. When bit signals are briny transmitted from the buffer I through MU 27 and along channel 37, certain of those signals must be masked so that only the proper positions in the bit map memory are energized. The microprocessor 15 through its CPIJ keeps an account of what sunless, or what signals from the buffer device I require masking and hence a set of masked signals are transmitted on channel I to MU 31. The signals on channel 49 in turn energize or do not energize certain write enable signals on channel JO and the system in effect electronically masks certain I
signals off channel 37. The oilier input to the MIX 31 is channel 47 which comes from the GDC. The GDC it has the ability to transmit cjraphic display signals along charnel 25 and the channel 35, through the MU I and along channel 37. While -that capability is present in the system shown in Figure l, it aloes no-t become part of the present invention. The present in~entiorl is directed to accelerating the signals representincJ-text characters from the main computer 11 to the CRT 51. The fi~e-folc3. feature of the present invention which acts together to accelerate the signals representing the characters includes the concept of using the microprocessor 15 as a dedicated slave. In accordance with this dedication, a group of 8-bit ASCII coded signals sent on channel 13 is immediately transformed into an 8 by lo bit group which is -transferred out of the TOM lo. That 8 by lo bit group of bit signals is immediately transformed into a 16 by lo bit cJrc-up in the RAM 18 and then transferred to buffer 23. On the course of that transformation the second feature comes into play because -the bit signals are properly arranged during the foregoing transformation so that when they are located in buffer 23, they are in the proper locations upon transfer to the bit map memory 33. The third feature lies in -the capability of buffer 23 -to -transmit the bit signals in parallel and hence the proper locating of the bit signals in -the bit map memory is speeded up because of -the parallel transmission. The parallel transmissions are accomplished during blank periods end this Earth feature also adds to the overall speeding up of the I
operation since -the transmissions are taking place during time periods which otherwise might not be used. The fifth feature of the present invention is the use of the GDC 19 which prickles the address information and monitors the address information so that -the buffer sends its signals into the bit map mer.lory a-t the proper addresses. As was mentioned earlier, the GDC has two resisters. In the "present" address register there is initially located the starting address to which the information in the buffer 23 will be sent and located. II1 response -to each write signal from the write clock generator in the GDC 19 the starting address register is incremented. The region ending value register Lyle initially be loaded with the value of ten in the preferred embodiment because the buffer 23 will have ten words stored therein and the operation is such that the buffer will be completely emptied before it is reloaded. Accordingly, in response to the write signals, the region ending value register will he decrement Ed. When the region ending value resister has a value of zero, the microprocessor is informed by the GDC that buffer 23 can be reloaded. The feature of having such traffic control outside of the microprocessor adds to the overall speed of the operatiorl.
If we study Figures 2 through 5 the operation of -the present system will become clearer. In Figures 2, 3 and 4, there is depicted on the left-hand side the arrangement of the bit signals in the ROM. The letter "D" in Figure 2 is shown in the ROM in an 8 ho lo configuration and it will be noted that the top row of -the Z by lo matrix is left blank. The reason æ3~3~
that eke top row is loft blank is so -that when -the letters are joined together on the screen, there will be space between tune rows of letters. In Figure 3 the letter "E" is show in the ROM
on the left-hand side in an 8 by JO configuration, and in figure the letter "C" is shown in the ROM in an 8 by lo configuration.
When the letter "D" shown in the ROM configuration in Figure 2 is transferred from the ROM 16 to the buffer I in Figure 1, that set of bit signals is transmitted through the CPU
of the microprocessor 15 and the signals are revolved 50 that they are located in the 16 by 10 buffer configuration shown in Figure 2. It will be noted in the buffer configuration of figure 2 that there is a left-hand column 61 which is shown blank. Actually there are zeros stored in the blank locations.
It should also be noted that there is a right-hancl calmly 63 which has Eros located in i-t. From the column 61 through the column 63 there are ten bit positions and hence the letter lid"
in Figure 2 in -the buffer configuration is located in a JO by lo group. The remaining six columns 65 are blank and as will become clearer hereinafter, those columns are masked when -the inforJnation is transferred from the huller 23 into the bit map memory 33.
The microprocessor 15 is programmed to accommodate a number of formats. The microprocessor 15 knows that upon the firs-t transfer of a group of bit signals from the buffer 23, -the letter will be configured in the first ten hits, and hence the control signals on channel I to the MU 31 dictate that the I
mask effected on channel I will mask out: the last six Kit positions depicted as columns 65 in Figure 2.
The foregoing can be understood from a study of Figure 5. In Figure 5 -there is shown the organization of four alcoholizes in -the bit map memory 33. At each of the addresses 0, 1, 2, and 3 (designated as addresses in Figure 5) the bit map memory can store 16 kits or one word. The 16 bit locations are designated as O through 15. In Figure 5 the first row represents the memory elements for the pixel locations on the CRT. It can be seen in Figure 5 that all of these firs row locations are blank. It will be recalled that -the top row of the group in the ROW is blank to provide a space between rows of words on the display, hence this first row is blank. The second row in Figure 5 shows the bit signals which would be transferred to transfer the second row of each of -the letters "D", "E" and "C" as depicted in Figures 2, 3 and 4. Thus far we have discussed the transfer of one row of bitts in -the letter "D" from -the ROM to the buffer as depicted in Figure 2. Let us consider how the bit signals are transferred from the buffer into -the bit map memory as shown in Figure 5. At location 67 the buffer is shown storing the second row of bit information (depicted in Figure 2). When the second row of bit information is briny transferred from -the buffer 23, through the MU 27, along challnel 37, -the microprocessor 15 provides the ~23~ 6 masking inEorlnatioIl to tile MIX 31 so that tile last six pixel locatioIls are Unasked or blanked arid tilts is indicated in Figure 5 at locatioIl 67 by tile x's. ~ccording1y, loaded into tile second row of tile bit map Mueller at toe positiorls 0 through 9, we see that the bit sicJna1s are tile same as tile bit sickness ill tile first ten positions ox tile location Go. 'rho starting address in the present address register in tile GDC started out with tile address 0, and tile blaIlk oLI~latioll sly toe first row was traIlslnitted from tile I burner islet tile by t nap ~nelnory. At that time tile region lel~CJ~ value register ill tic JOKE I was clecrelllel~tc?d. In response to tile next write clock signal the proselyte aclcdress register in tile GDC is incremerlted lay 50, and laurels the second row in tile bit map Monroe and its positions 0 through 9 are loaded as shown in position Go. it that time tile 1engtl resister will be decrement Ed and the operation countless until each of tile rows 70 trough 79 shown in Figure 2 has Boyle transferred Rowley tile buffer 23, tl~rougl~ tile MU 27, along tile cleanly 37 to tile bit nap memory. Since each of these transfers requires that tile last six positions be masked, tile mask inEorIllatioll on 99 renewals constant until there has been a transfer of a complete character frown the buffer 23 to tile bit map Illelnory 33. Wllell tile (ICKY "present"
resister has Boyle increIllelltecl ten times end tile 1engtl~
endiIly register has been decremellted ten times, tile GDC
advises the microprocessor that a new character can be transferred from tile ROM 16 through the RUM 1f3 to buffer 23. In the present elnbodiment seven words frown tile buffer 23 can be traIlsferred to tile bit map memory during a l~orizonta1 bunk period. ~ccording1y at tile end of Such a horizontal berrylike period toe JOKE will have its present address register redneck 90~ or tile eighth lisle and toe 1encJtll eIlcdirlc3 address register will be set at 3. Durirlc3 tile second llorizoIlta1 blaIlk period, toe remailing three rows, namely rows 77 through 79 ill Figure 2, will be transferred from tile buffer 23 to tile bit Inapt nleIllory. ~urirlc3 tile third ~3~3~.
Ilorizolltal blank time, tile Inieroprocessor 15 will load toe letter "E" prom tile IAMB 16 throucJII the lo 3 into tile buffer 23 and the process will repeat itself.
When the letter "H:" is loaded from tile IAMB 16 to tile buffer 23 it takes the eonfiguratiorl shown in Figure 3. Tile microprocessor knows that the letter I
is tile second letter being loaded and the system knows that tile bit positiolls 10 through 15 (Figure 5) in the bit Illap Inlayer IIIUSt llaVC a partial of the letter "Lo" loaded If) tllereiJ~ ccorclillcJly~ tile letter I from tile IAMB, as show ill Lowry 3, is revolved so that it ends up in tile buffer as slyly in tile buffer collEiguration portion ox Figure 3.
Luring tile first cycle of tile second transfer the micro-processor sends masking instruction information 011 charnel ~19 so that tile first ten column pOSitiOIIS transferred from tile buffer 23 are masked. This is shown at location 80 of Figure 5. Ill location go of lucre 5 it can be noted that tile O through 9 bit ~Osit:iOIls would be Unasked (illclicatecl by x's) and only the inforlllatioll in bit positiorls 10 through 15 would }ye trànsferrecl to the bit map Mueller. Lyle system would repeat the operation, always maskirlc3 talc first ten positiolls until the bit map Mueller is loaded with the inform troll SIEGE ill Sioux 131 of Faker 3. It tilts, title tile registers of the GL)C would indicate to the Inicroprocessor that sexual 131 fled been loaded. Ilowever, tile microprocessor 15 is programmed to know tilt during the second operation there must be second unloadillg of the buffer 23 and at that time positions through 15 must be maslced as shown by section 83 irk Figure 5. In section 33 (in FicJure 5), it I can be seen that tile first three bits plus tile blanlc rigllt-lland colulnll (Shelley in section 85 of FicJure 3) are else trallsEerred to tile bit Illap Illelllory allot that the positiolls I through I are musical out. 'I've Gl)C in the nlealltillle has cllanc3ecl tile address frown O to 1 allot Halsey the tree bits plus tile l~lanlc calmly are located irk positions ,1 -- 16 I!
I
(1, 1, 2 aloud 3 of address 1 ill e big hap Inlayer.
toe recJister.s ill GL~C 19 il~clieate to toe ll1ieroproeessor that toe 1~7adillcJ of so- Eliot US has Lyle eoJ~i~>lel~ed, isle ll1ierouroeessor will eol1~ Ellen to load tile letter C Eroln 5 toe ION lug tllrouclll Lomb 1~3 islet tile Burr 23 as sly Lyle Lowry eollEi~Jul:at:ioll o E l; issuer . Wllell tile third letter, ill our ease tile littler "C", is trallsferred Rowley Lowe buffer
AN IMPROVED ARRANGEMENT FOR PROVIDING
DATA SIGNALS FOR A DATA DISPLAY SYSTEM
In order to show on a cathode ray tube (CRT) screen some image, whether it be text or graphics, the CRT beam must be turned on (brightened in the case of -the image being bright and the background dull) at the correct -time to produce a dot, or a series of dots to make a bar, and the like. The foregoing necessitates -that the display system have a data storage means which transmits data signals, representing the image to be displayed, in synchronism with clock signals from a clock signal generator.
In the prior art, the clock generator is usually located in the CRT circuitry. In synchronism with the clock signals the CRT beam is turned on (or not turned on) as the beam gets to the correct data location. It should be understood that in the case of the intelligence being in a dark mode, against a bright background, then the beam would be turned off. All of the foregoing is well understood in the prior art.
Further in the major part of the prior art, if a system is going to display both graphics and text, two different memory and control systems have been employed. It has been only when the information is finally transmitted to the CRT device that the graphics and text signals have been meshed, or multiplexed.
The introduction of the bit map memory, to the display art, has made the task somewhat easier because in a bit map memory, there is a memory for each pixel location on the CRT screen. Hence, whatever image is to be seen (either text, or graphics, or a combination of both) can be written into the bit map memory and from that one memory was it is scanned) both graphics end text data signals can be -transmitted to the CRT screen to be shown.
The major problem that occurs in -the prior art is that the bit map memory was not used for text but the text I
was encoded Eros a c~ilaracter geIler~tor anal contirlually transmitted to -the CRT. While the prior art system aye fast, it required two separate memory systems. The present system permits both text and graphics to use the same memory while S operating with the speed of the separate memories of -the prior art. The prevent invention employs a five-fold improvement in transmitting data signals to the data display device as will be explained below.
The system in accordance with the invent ion employs a microprocessor as a dedicated slave device to a main data processing system The microprocessor responds -to groups of coded signals from the main data processing system. In response to each group of coded signals, the present system provides a group of bit signals from a ROM means, which kit signals graphically define the text character assigned to the coded set of signals being received. In other words, if eight bits of ASCII coded signals are transmitted from the main data processing device, that group of signals causes, in a preferred embodiment, the cJeneration of a group of by 10 bits from the ROM in the microprocessor. In the microprocessor, ten bytes of elate are stored in ROM memory means for each possible text character to be shown. The group of bit signals are block trrlnsferrec1 from -the ROM of the microprocessor to buffer.
Thereafter the bit signal group, which has been properly arranc~ec1, is transferred in parallel during sync signal blank periods. To effect this block transfer, a graphic display ~3~3~
controller device provides addresses to the bit map memory so that a bloc transfer is written into the bit map memory at a particular starting address.
The microprocessor is programmed to determine whether a bloc -transfer requires one or two cycles end accordingly characters are transferred from the buffer in either one step or two steps. The bit signals in the buffer are located -to match where, within a word location, in the bit map memory they are to be ultimately located. The dedication of the microprocessor to lo providing encoded signals, the speed of the parallel transfer, the fact that the transfer is made during the horizontal and vertical blank period, utilization of the graphic display controller to provide the addresses, and the prearrangement of the bits in the buffer enable the data transfer to be more rapidly accomplished than in the prior art.
In one broad aspect of the invention there is provided a system for displaying text which has a CRT display means and a bit map memory means connected thereto to store pull information for transfer to said CRT display means, characteri~ecl in -that said system has an arrangement for accelerating data signals representing text characters from a main computer means to said bit map memory means comprising in combination: microprocessor means connected to said main computer -to receive therefrom instruction signals, address signals and coded signals representing text characters, said microprocessor means providing groups of bit signals arranged in different positions, each defining a different Tut character -to ~L23~L~3~i 'ye disp'~ye~, ion resporlse to r*celving different groups of said coded signals; buffer means connected to said microprocessor means -to receive said groups of bit signals and store -the same for further transmission in parallel; first circuitry means connecting said buffer means to said bit map memory means for transmitting said groups of bit signals in parallel from said buff means to said bit map memory means; controller circuitry means connected to said microprocessor means to receive address signals and instruction signals therefrom; second circuitry means connecting said controller circulator means to said bit map memory means to provide address signals and instruction signals thereto to direct said different groups of bit signals to particular locations in said bit map memory and alternatively to cause said bit map memory means to read out pixel information from certain locations to said CRT display means.
In a second broad aspect of the invention there is provided a system which has a CRT display means for displaying text characters and a bit map memory means connected thereto to store pixel information for -transfer to said CRT display means, an arrangement for accelerating data signals representing text characters from a main computer to said bit map memory means comprising in combination: microprocessor means having at least ROM means connected to said main computer to receive therefrom instruction signals, address signals and coded signals representing text characters, said ROM means providing respectively different matrices of bit signals, each of which matrices defines a -text character in configuration, in response owe -to receiving different groups of said coded Saigon.; buffer means connected to said microprocessor means to receive spa d matrices of bit signal and store the same for further transmisc,iorl in parallel; first circuitry means disposed to connect said buffet Nancy to said bit map memory means for transmitting said matrices of bit signals in parallel thereto;
control circuitry means connected to said microprocessor means to receive address signals and instruction signals therefrom; second circuitry means connecting said controller circuitry means to said bit map memory to provide address signals thereto direct said matrices of bit signals to particular locations in said bit map memory mean and alternatively to cause said bit map memory means to read said pixel information from certain locations to said CRT display means; said control circuitry means including clock signal generator ineans which generate write signals, horizontal sync signals end vertical sync signals, said clock signal venerator means being connected at least to said buffer means to cause said buffer means to transmit segments of said mutters of bit signals during horizontal and vertical blank time; masking meals -to selectively mast signals being transmitted from said buffer means to said bit map memory means; and third circuitry mean coupling said masking means to said microprocessor means to receive control signals therefrom whereby in response to a group of coded signals being -transmitted by void main computer to said microprocessor means, said coaled signals are encoded into a matrix of bit signals, arranged into suitable position I
in said microprocessor means and transmitted to solid buffer means and whereby -thereafter in response -to cluck signals during horizontal and vertical blank times yips of bit signals from said Burr means are transmitted in parallel to said bit mop memory Nancy whereat -they are partially sassed ankle partially masked enroot to location designated by address psychoanalyze trarlsmit-ted to said bit map memory from said controller circuitry.
The objects and features of the present invention will be better understood after studying -the description below taken in conjunction with the drawings wherein:
Figure 1 is a block schematic diagram ox the present system;
Figure depicts the letter D as it appears in the ROM and as i-t later appears in the buffer;
Figure 3 depicts the letter E as it appears in the TOM and as it later appears in the buffer;
Fleecer 4 depicts the letter C as lo appears in the ROM end as it later appears in the buffer; and Figure 5 depicts the transfer of Betty sinkholes from -the buffer -to the hit map memory.
no Figure I -there it Sheehan main computer 11 which is connected by channel 13 -to a microprocessor 15. It should be understood that -the main computer 11 is the heart of a co~nputincg system and is connected to many terminals end peripherals which are not shown in Figure 1. It should also be understood that the channels shown thwart Figure 1 comprise a plurality of I
parallel wit en and the signals transmitted over -these channels include address signals, instruction signals, end data to be displayed signals. The microprocessor in a preferred embodiment is an 8085 manufactured by Intel Corporation. It should be understood -that the microprocessor 15 includes a-t least a central processing unit, ROM memory means, RAM memory means and logic circuitry to generate instruction information signals.
As can be gleaned from Figure 1 tiler is a buffer 23 connected by channel 21 to RAM 18 of the microprocessor 15. The present system operates with a 16-bit word that is broken up into two 8-bit bytes. in the ROM 16 there is 5 toned a plurality of 8 by 10 bit groups, each of which configures a character to be displayed. In other words, as will become clearer hereinafter, the letter "D" would be graphically represented by bit signals stoned in an appropriate location in -the ROM. Also as will become clearer hereinafter, when -the group of bit signals is -transmitted frown the ROM, it is transmitted through the central processing unit of the microprocessor back into the RAM 13, and in the course of that action the bit signals are revolved so that when they are transmitted from the RAM 18 along charlrlel 21 to buffer 23, they end up in the proper locations for transmission to the bit map memory 33. The arrancJincJ of the bits etc. will be more clearly understood from the discussion of Figures 2 through 5.
The buffer 23 is formed -to store 16 bits in a row and to store 10 rows. One character at a -time is -transferred from the RUM 18 to the buffer 23. The bit signals stoned in -the ~23~ 6 buffer 23 representing the character are trarl~ferrecl in parallel 16 bits at a time through the multiplier (hereinafter MU) 27 along channel 37 and into the bit map memory I As will become clearer in the discussion of Figures 2 through 5 when the bit signals are transmitted into the bit map memory six. of those bits are masked out on chamlel 40. The bit signals from the buffer 23 are located in the bit map memory in accordance with address signals present on channel 39.
As can also be leaned from an examination o. Figure 1 there is a graphic display controller 19 connected to the microprocessor 15 through the channel 17. In a preferred embodiment the graphic display controller (hereinafter referred to as the GDC) is a MICRO POD 7220 manll~actured by NEW
Corporation. The GDC 19 has memory means to store address and instruction infoxmatiorl from the microprocessor and also includes two registers which can be incremented or decrement Ed to accomplish the changing of an address. The GDC 19 also includes a write signal generator which provides clod signals as well as horizontal and vertical sync signals. The sync signals are transmitted on connection 57 to the CRT 51 to the srlift register 53 and to the microprocessor 15. Write clod slsnals are transmitted to the buffer 23 and to destination counter Lo over connection 31. In addition -the horizontal and vertical sync signals operate within the GDC I to accomplish certain operations thereirl. For every horizontal blank period there are seven write cycles generated and for every vertical blank period there are 594 write cycles generated. Other rates could be used.
~3~3~;
The desalination counter 41 is included in the layout in Figure 1 because it is part of an overall system. However, it is not employed with the invention described in this description. The operation of -the destination counter 41 is described in my cop ending Canadian Patent Application 465,215 filed October 11, 1984, Dante et at. and which is assigned to the assigrlee of this application. The GDC 19 accepts address information and instruction information from the microprocessor 15 and holds that information to effect address signals on channel 39 so that characters being transferred from the buffer 23 are properly located in the bit map memory 33.
As can be seen in Figure 1, the GDC 19 transmits its address information along channel 25, along chanrlel 35, through MU 29, through decoder 45, onto the channel US. The MU 29 has a second input on chamlel 43, from the destination counter 41, but as was mentioned above, -that circuitry plays no role in the operation of the present invention. Insofar as -the present invention is concerned, it can be assumed that the address information from -the GDC 19 always goes through the MU 29, i.e., that the MU 29 is not even present. The decoder 45 takes the address information and decodes it into the proper signals to operate with the bit map memory 33. In a preferred embodiment the decoder 45 is a 74LS253, manufactured by Teas Irlstrument6 Corporation. Those signals are held in the latch so that they are present when the bit signals on channel 37 arrive at the bit map memory 33. It should also be noted that channel 91 and latch 93 are also circuitry elements which are used in ~l~3~13~
connection with a split-screen smooth scrolling circuit described in the aforementioned co-pending application, i.e., channel 91, latch I end channel 97 play no role in the operation of the present invention.
When the characters have been stored in the bit map memory 33, they are read therefrom in response to address sunless on channel 39. the bit signals or pixel signals being transmitted from the bit map memory 33 are transmitted along channel 56 to shift requester 53. The signals are advanced from lo shift resister 53 in response to horizontal sync signals on connection 57. When the signals are advanced from shift register 53 they pass along channel 58 to the CRT 51. Since the signals on channel 58 are transmitted in synchronism with the horizontal sync signal, they are present in synchronism with the byway of the CRT, which is what is required to provide the display.
In Figure 1 there is shown a MU 31 which has two inputs, namely channels 49 and 47. When bit signals are briny transmitted from the buffer I through MU 27 and along channel 37, certain of those signals must be masked so that only the proper positions in the bit map memory are energized. The microprocessor 15 through its CPIJ keeps an account of what sunless, or what signals from the buffer device I require masking and hence a set of masked signals are transmitted on channel I to MU 31. The signals on channel 49 in turn energize or do not energize certain write enable signals on channel JO and the system in effect electronically masks certain I
signals off channel 37. The oilier input to the MIX 31 is channel 47 which comes from the GDC. The GDC it has the ability to transmit cjraphic display signals along charnel 25 and the channel 35, through the MU I and along channel 37. While -that capability is present in the system shown in Figure l, it aloes no-t become part of the present invention. The present in~entiorl is directed to accelerating the signals representincJ-text characters from the main computer 11 to the CRT 51. The fi~e-folc3. feature of the present invention which acts together to accelerate the signals representing the characters includes the concept of using the microprocessor 15 as a dedicated slave. In accordance with this dedication, a group of 8-bit ASCII coded signals sent on channel 13 is immediately transformed into an 8 by lo bit group which is -transferred out of the TOM lo. That 8 by lo bit group of bit signals is immediately transformed into a 16 by lo bit cJrc-up in the RAM 18 and then transferred to buffer 23. On the course of that transformation the second feature comes into play because -the bit signals are properly arranged during the foregoing transformation so that when they are located in buffer 23, they are in the proper locations upon transfer to the bit map memory 33. The third feature lies in -the capability of buffer 23 -to -transmit the bit signals in parallel and hence the proper locating of the bit signals in -the bit map memory is speeded up because of -the parallel transmission. The parallel transmissions are accomplished during blank periods end this Earth feature also adds to the overall speeding up of the I
operation since -the transmissions are taking place during time periods which otherwise might not be used. The fifth feature of the present invention is the use of the GDC 19 which prickles the address information and monitors the address information so that -the buffer sends its signals into the bit map mer.lory a-t the proper addresses. As was mentioned earlier, the GDC has two resisters. In the "present" address register there is initially located the starting address to which the information in the buffer 23 will be sent and located. II1 response -to each write signal from the write clock generator in the GDC 19 the starting address register is incremented. The region ending value register Lyle initially be loaded with the value of ten in the preferred embodiment because the buffer 23 will have ten words stored therein and the operation is such that the buffer will be completely emptied before it is reloaded. Accordingly, in response to the write signals, the region ending value register will he decrement Ed. When the region ending value resister has a value of zero, the microprocessor is informed by the GDC that buffer 23 can be reloaded. The feature of having such traffic control outside of the microprocessor adds to the overall speed of the operatiorl.
If we study Figures 2 through 5 the operation of -the present system will become clearer. In Figures 2, 3 and 4, there is depicted on the left-hand side the arrangement of the bit signals in the ROM. The letter "D" in Figure 2 is shown in the ROM in an 8 ho lo configuration and it will be noted that the top row of -the Z by lo matrix is left blank. The reason æ3~3~
that eke top row is loft blank is so -that when -the letters are joined together on the screen, there will be space between tune rows of letters. In Figure 3 the letter "E" is show in the ROM
on the left-hand side in an 8 by JO configuration, and in figure the letter "C" is shown in the ROM in an 8 by lo configuration.
When the letter "D" shown in the ROM configuration in Figure 2 is transferred from the ROM 16 to the buffer I in Figure 1, that set of bit signals is transmitted through the CPU
of the microprocessor 15 and the signals are revolved 50 that they are located in the 16 by 10 buffer configuration shown in Figure 2. It will be noted in the buffer configuration of figure 2 that there is a left-hand column 61 which is shown blank. Actually there are zeros stored in the blank locations.
It should also be noted that there is a right-hancl calmly 63 which has Eros located in i-t. From the column 61 through the column 63 there are ten bit positions and hence the letter lid"
in Figure 2 in -the buffer configuration is located in a JO by lo group. The remaining six columns 65 are blank and as will become clearer hereinafter, those columns are masked when -the inforJnation is transferred from the huller 23 into the bit map memory 33.
The microprocessor 15 is programmed to accommodate a number of formats. The microprocessor 15 knows that upon the firs-t transfer of a group of bit signals from the buffer 23, -the letter will be configured in the first ten hits, and hence the control signals on channel I to the MU 31 dictate that the I
mask effected on channel I will mask out: the last six Kit positions depicted as columns 65 in Figure 2.
The foregoing can be understood from a study of Figure 5. In Figure 5 -there is shown the organization of four alcoholizes in -the bit map memory 33. At each of the addresses 0, 1, 2, and 3 (designated as addresses in Figure 5) the bit map memory can store 16 kits or one word. The 16 bit locations are designated as O through 15. In Figure 5 the first row represents the memory elements for the pixel locations on the CRT. It can be seen in Figure 5 that all of these firs row locations are blank. It will be recalled that -the top row of the group in the ROW is blank to provide a space between rows of words on the display, hence this first row is blank. The second row in Figure 5 shows the bit signals which would be transferred to transfer the second row of each of -the letters "D", "E" and "C" as depicted in Figures 2, 3 and 4. Thus far we have discussed the transfer of one row of bitts in -the letter "D" from -the ROM to the buffer as depicted in Figure 2. Let us consider how the bit signals are transferred from the buffer into -the bit map memory as shown in Figure 5. At location 67 the buffer is shown storing the second row of bit information (depicted in Figure 2). When the second row of bit information is briny transferred from -the buffer 23, through the MU 27, along challnel 37, -the microprocessor 15 provides the ~23~ 6 masking inEorlnatioIl to tile MIX 31 so that tile last six pixel locatioIls are Unasked or blanked arid tilts is indicated in Figure 5 at locatioIl 67 by tile x's. ~ccording1y, loaded into tile second row of tile bit map Mueller at toe positiorls 0 through 9, we see that the bit sicJna1s are tile same as tile bit sickness ill tile first ten positions ox tile location Go. 'rho starting address in the present address register in tile GDC started out with tile address 0, and tile blaIlk oLI~latioll sly toe first row was traIlslnitted from tile I burner islet tile by t nap ~nelnory. At that time tile region lel~CJ~ value register ill tic JOKE I was clecrelllel~tc?d. In response to tile next write clock signal the proselyte aclcdress register in tile GDC is incremerlted lay 50, and laurels the second row in tile bit map Monroe and its positions 0 through 9 are loaded as shown in position Go. it that time tile 1engtl resister will be decrement Ed and the operation countless until each of tile rows 70 trough 79 shown in Figure 2 has Boyle transferred Rowley tile buffer 23, tl~rougl~ tile MU 27, along tile cleanly 37 to tile bit nap memory. Since each of these transfers requires that tile last six positions be masked, tile mask inEorIllatioll on 99 renewals constant until there has been a transfer of a complete character frown the buffer 23 to tile bit map Illelnory 33. Wllell tile (ICKY "present"
resister has Boyle increIllelltecl ten times end tile 1engtl~
endiIly register has been decremellted ten times, tile GDC
advises the microprocessor that a new character can be transferred from tile ROM 16 through the RUM 1f3 to buffer 23. In the present elnbodiment seven words frown tile buffer 23 can be traIlsferred to tile bit map memory during a l~orizonta1 bunk period. ~ccording1y at tile end of Such a horizontal berrylike period toe JOKE will have its present address register redneck 90~ or tile eighth lisle and toe 1encJtll eIlcdirlc3 address register will be set at 3. Durirlc3 tile second llorizoIlta1 blaIlk period, toe remailing three rows, namely rows 77 through 79 ill Figure 2, will be transferred from tile buffer 23 to tile bit Inapt nleIllory. ~urirlc3 tile third ~3~3~.
Ilorizolltal blank time, tile Inieroprocessor 15 will load toe letter "E" prom tile IAMB 16 throucJII the lo 3 into tile buffer 23 and the process will repeat itself.
When the letter "H:" is loaded from tile IAMB 16 to tile buffer 23 it takes the eonfiguratiorl shown in Figure 3. Tile microprocessor knows that the letter I
is tile second letter being loaded and the system knows that tile bit positiolls 10 through 15 (Figure 5) in the bit Illap Inlayer IIIUSt llaVC a partial of the letter "Lo" loaded If) tllereiJ~ ccorclillcJly~ tile letter I from tile IAMB, as show ill Lowry 3, is revolved so that it ends up in tile buffer as slyly in tile buffer collEiguration portion ox Figure 3.
Luring tile first cycle of tile second transfer the micro-processor sends masking instruction information 011 charnel ~19 so that tile first ten column pOSitiOIIS transferred from tile buffer 23 are masked. This is shown at location 80 of Figure 5. Ill location go of lucre 5 it can be noted that tile O through 9 bit ~Osit:iOIls would be Unasked (illclicatecl by x's) and only the inforlllatioll in bit positiorls 10 through 15 would }ye trànsferrecl to the bit map Mueller. Lyle system would repeat the operation, always maskirlc3 talc first ten positiolls until the bit map Mueller is loaded with the inform troll SIEGE ill Sioux 131 of Faker 3. It tilts, title tile registers of the GL)C would indicate to the Inicroprocessor that sexual 131 fled been loaded. Ilowever, tile microprocessor 15 is programmed to know tilt during the second operation there must be second unloadillg of the buffer 23 and at that time positions through 15 must be maslced as shown by section 83 irk Figure 5. In section 33 (in FicJure 5), it I can be seen that tile first three bits plus tile blanlc rigllt-lland colulnll (Shelley in section 85 of FicJure 3) are else trallsEerred to tile bit Illap Illelllory allot that the positiolls I through I are musical out. 'I've Gl)C in the nlealltillle has cllanc3ecl tile address frown O to 1 allot Halsey the tree bits plus tile l~lanlc calmly are located irk positions ,1 -- 16 I!
I
(1, 1, 2 aloud 3 of address 1 ill e big hap Inlayer.
toe recJister.s ill GL~C 19 il~clieate to toe ll1ieroproeessor that toe 1~7adillcJ of so- Eliot US has Lyle eoJ~i~>lel~ed, isle ll1ierouroeessor will eol1~ Ellen to load tile letter C Eroln 5 toe ION lug tllrouclll Lomb 1~3 islet tile Burr 23 as sly Lyle Lowry eollEi~Jul:at:ioll o E l; issuer . Wllell tile third letter, ill our ease tile littler "C", is trallsferred Rowley Lowe buffer
2 3 to tile by t Illap Illelllory, tile eolul~ s 0, 1, 2 all 3 as well a; 1 lye oily Us 5 1~1 Allah lo wow L be Illas)cecl out allot Lyle Lo tile letter '(I will be tral~s.EerL-ecl allot loacle~l islet tile e~.l.ullllls 5 tllroucJll I with tile Clairol else tile Scholl as l s I V I .
Its was ll1elll:iolled earlier, tile Luke Silas are located ill tile buffer within a word eonEiguratio~ tile 15 sly way that they will be loaded islet tile bit 11l1p Il1elllory Whitehall a warily eollEic~uratioll, all tilts of course saves title Jill Lyle ul.tilllLlte trallsEel.LlllcJ of tile illEorlllat.i.oll islet tile lilt Ill Al) Lyle . lo also 1~c~c owls Laureate l:rolll ill- ~c>re~Jois cliseussioll Lyle toe use of tile l11ieroproeessor 15 as a 20 cleclieatecl slave lC).L- Isle PUrL)OSC! of Ellen a eye cellulose islet a lar-cJe lowlier owe sicJIla.Ls lllereases tile spool wictll wlliell tile illEorlllatioll is trallsEerred Eroln tile Inlay eoillputer to tile CRT. In audition, the ~eser1ption of figures 2-5 yin Colt CtiOII Tuttle tile ullclerstalldillsl of it inure 1 IIl~J eat it 25 clear Lyle tile tr.al~sEer of lo illor~llat1Oll Rowley tile Lowry 23 ill parallel, dur.illq blalllc tithes in rissoles lo Lyle writhe clock siclllclls, rapidly il1ereases tile trallsEer of tile illEor-lllal:10ll Eerily tile Lyle colllputer to toe CRT 51. file use of Isle LO (Jo provide Lyle stroll cJ addresses allot to keep track 30 of wlliell aclc1resses are ill eta as well as wllell Lyle cllar.1ctcr has bell trallsl erred colltributes lo tie speed of tile overall ol~cratioll.
-- I
Its was ll1elll:iolled earlier, tile Luke Silas are located ill tile buffer within a word eonEiguratio~ tile 15 sly way that they will be loaded islet tile bit 11l1p Il1elllory Whitehall a warily eollEic~uratioll, all tilts of course saves title Jill Lyle ul.tilllLlte trallsEel.LlllcJ of tile illEorlllat.i.oll islet tile lilt Ill Al) Lyle . lo also 1~c~c owls Laureate l:rolll ill- ~c>re~Jois cliseussioll Lyle toe use of tile l11ieroproeessor 15 as a 20 cleclieatecl slave lC).L- Isle PUrL)OSC! of Ellen a eye cellulose islet a lar-cJe lowlier owe sicJIla.Ls lllereases tile spool wictll wlliell tile illEorlllatioll is trallsEerred Eroln tile Inlay eoillputer to tile CRT. In audition, the ~eser1ption of figures 2-5 yin Colt CtiOII Tuttle tile ullclerstalldillsl of it inure 1 IIl~J eat it 25 clear Lyle tile tr.al~sEer of lo illor~llat1Oll Rowley tile Lowry 23 ill parallel, dur.illq blalllc tithes in rissoles lo Lyle writhe clock siclllclls, rapidly il1ereases tile trallsEer of tile illEor-lllal:10ll Eerily tile Lyle colllputer to toe CRT 51. file use of Isle LO (Jo provide Lyle stroll cJ addresses allot to keep track 30 of wlliell aclc1resses are ill eta as well as wllell Lyle cllar.1ctcr has bell trallsl erred colltributes lo tie speed of tile overall ol~cratioll.
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Claims (12)
OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:-
1. A system for displaying text which has a CRT display means and a bit map memory means connected thereto to store pixel information for transfer to said CRT display means, characterized in that said system has an arrangement for accelerating data signals representing text characters from a main computer means to said bit map memory means comprising in combination: microprocessor means connected to said main computer to receive therefrom instruction signals, address signals and coded signals representing text characters, said microprocessor means providing groups of bit signals arranged in different positions, each group defining a different text character to be displayed, in response to receiving different groups of said coded signals; buffer means connected to said microprocessor means to receive said groups of bit signals and store the same for further transmission in parallel; first circuitry means connecting said buffer means to said bit map memory means for transmitting said groups of bit signals in parallel from said buffer means to said bit map memory means;
controller circuitry means connected to said microprocessor means to receive address signals and instruction signals therefrom; second circuitry means connecting said controller circuitry means to said bit map memory means to provide address signals and instruction signals thereto to direct said different groups of bit signals to particular locations in said bit map memory and alternatively to cause said bit map memory means to read out pixel information from certain locations to said CRT
display means.
controller circuitry means connected to said microprocessor means to receive address signals and instruction signals therefrom; second circuitry means connecting said controller circuitry means to said bit map memory means to provide address signals and instruction signals thereto to direct said different groups of bit signals to particular locations in said bit map memory and alternatively to cause said bit map memory means to read out pixel information from certain locations to said CRT
display means.
2. A system for displaying text according to claim 1 characterized in that said microprocessor means is formed to arrange said group of bit signals when they are transmitted to said buffer means so that said bit signals are stored in said buffer means in a matrix with columns, the bit signals of each column being in the same positions relative to one another that they will be stored in said bit map memory means.
3. A system for displaying text according to claim 1 characterized in that said microprocessor means is formed to arrange said groups of bit signals so that the bit signals making up the characters are positioned in columns, the bit signals of each column being positioned relative to one another in the same fashion that they will be stored in said bit map memory means.
4. A system for displaying text according to claim 1 characterized in that each character to be displayed is formed in an 8 by 10 matrix of bit signals and is transformed into a 16 by 10 matrix of bit signals in said microprocessor means, in that said buffer means is formed to store at least a 16 by 10 matrix of bit signals, and in that said bit signals are transmitted from said buffer means in one cycle and alternatively in two cycles depending upon whether or not said bit signals stored therein represent a continuous character makeup.
5. A system for displaying text according to claim 1, characterized in that said controller circuitry means includes a clock signal generator which generates write signals, horizontal sync signals, and vertical sync signals and in that said clock signal generator is connected to said buffer means to cause said buffer means to transmit segments of said groups of bit signals during horizontal and vertical blank times.
6. A system for displaying text according to claim 5, characterized in that said microprocessor means is formed to monitor the operation of said buffer means so that said buffer means must transmit all of the bit signals held therein before said microprocessor means will transmit a new group of bit signals thereto.
7. A system for displaying text according to claim 1, characterized in that said arrangement for accelerating data signals further comprises a means to mask signals being transmitted from said buffer means to said bit map memory means and third circuitry means coupling said means to mask signals to said microprocessor means to receive control signals therefrom.
8. A system for displaying text according to claim 1, characterized in that each character to be displayed is formed in ROM means in said microprocessor means in an 8 by 10 matrix of bit signals and is transformed into a 16 by 10 matrix of bit signals in said microprocessor means, in that said buffer means is formed to receive and store at least a 16 by 10 matrix of bit signals, in that said arrangement for accelerating data signals further comprises a means to mask signals being transmitted from said buffer means to said bit map memory means and third circuitry means coupling said means to mask signals to said microprocessor means to receive control signals therefrom whereby said means to mask signals operates on said bit signals in conjunction with address signals from said controller circuitry means to reduce every eight 16 by 10 matrices of bit signals into eight 10 by 10 matrices of bit signals when located in said bit map memory means.
9. A system for displaying text according to claim 1, characterized in that said microprocessor means includes read only memory (ROM) means which is formed to receive said groups of coded signals and formed to provide a different group of bit signals respectively for each different group of coded signals received.
10. A system which has a CRT display means for displaying text characters and a bit map memory means connected thereto to store pixel information for transfer to said CRT display means, an arrangement for accelerating data signals representing text characters from a main computer to said bit map memory means comprising in combination: microprocessor means having at least ROM means connected to said main computer to receive therefrom instruction signals, address signals and coded signals representing text characters, said ROM means providing respectively different matrices of bit signals, each of which matrices defines a text character in configuration, in response to receiving different groups of said coded signals; buffer means connected to said microprocessor means to receive said matrices of bit signals and store the same for further transmission in parallel; first circuitry means disposed to connect said buffer means to said bit map memory means for transmitting said matrices of bit signals in parallel thereto;
controller circuitry means connected to said microprocessor means to receive address signals and instruction signals therefrom; second circuitry means connecting said controller circuitry means to said bit map memory means to provide address signals thereto to direct said matrices of bit signals to particular locations in said bit map memory means and alternatively to cause said bit map memory means to read said pixel information from certain locations to said CRT display means; said control circuitry means including clock signal generator means which generate write signals, horizontal sync signals and vertical sync signals, said clock signal generator means being connected at least to said buffer means to cause said buffer means to transmit segments of said matrices of bit signals during horizontal and vertical blank times; masking means to selectively mask signals being transmitted from said buffer means to said bit map memory means; and third circuitry means coupling said masking means to said microprocessor means to receive control signals therefrom whereby in response to a group of coded signals being transmitted by said main computer to said microprocessor means, said coded signals are encoded into a matrix of bit signals, arranged into suitable positions in said microprocessor means and transmitted to said buffer means and whereby thereafter in response to clock signals, during horizontal and vertical hank times, croups of bit signals from said buffer means are transmitted in parallel to said bit map memory means whereat they are partially passed and partially masked enroute to locations designated by address signals transmitted to said bit map memory means from said controller circuitry means.
controller circuitry means connected to said microprocessor means to receive address signals and instruction signals therefrom; second circuitry means connecting said controller circuitry means to said bit map memory means to provide address signals thereto to direct said matrices of bit signals to particular locations in said bit map memory means and alternatively to cause said bit map memory means to read said pixel information from certain locations to said CRT display means; said control circuitry means including clock signal generator means which generate write signals, horizontal sync signals and vertical sync signals, said clock signal generator means being connected at least to said buffer means to cause said buffer means to transmit segments of said matrices of bit signals during horizontal and vertical blank times; masking means to selectively mask signals being transmitted from said buffer means to said bit map memory means; and third circuitry means coupling said masking means to said microprocessor means to receive control signals therefrom whereby in response to a group of coded signals being transmitted by said main computer to said microprocessor means, said coded signals are encoded into a matrix of bit signals, arranged into suitable positions in said microprocessor means and transmitted to said buffer means and whereby thereafter in response to clock signals, during horizontal and vertical hank times, croups of bit signals from said buffer means are transmitted in parallel to said bit map memory means whereat they are partially passed and partially masked enroute to locations designated by address signals transmitted to said bit map memory means from said controller circuitry means.
11. A system for displaying text according to claim 2, characterized in that for first and second characters to be respectively stored in adjacent regions in said bit map memory means, the microprocessor means arranges the bit signals of said first character in one matrix and the bit signals of said second character in the next matrix transmitted to said buffer means so that the column having bit signals forming the start of said second character is located in a column of said next matrix corresponding to one of the columns of said one matrix having no bit signals forming part of said first character.
12. A system for displaying text according to claim 11, characterized in that a first group of adjacent columns of said one matrix are transferred from said buffer means to said bit map memory means and other columns of said one matrix not included in said first group are masked by masking means during transfer, and a second group of adjacent columns of said next matrix are transferred from said buffer means to said bit map memory means so that said first column of said second group is adjacent to said last column of said first group and other columns of said next matrix not included in said second group are masked by said masking means during transfer.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US543,107 | 1983-10-18 | ||
| US06/543,107 US4625203A (en) | 1983-10-18 | 1983-10-18 | Arrangement for providing data signals for a data display system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1234436A true CA1234436A (en) | 1988-03-22 |
Family
ID=24166603
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000465216A Expired CA1234436A (en) | 1983-10-18 | 1984-10-11 | Arrangement for providing data signals for a data display system |
Country Status (13)
| Country | Link |
|---|---|
| US (1) | US4625203A (en) |
| EP (1) | EP0145530A3 (en) |
| JP (1) | JPS60101637A (en) |
| KR (1) | KR900006942B1 (en) |
| AU (1) | AU568159B2 (en) |
| BR (1) | BR8405250A (en) |
| CA (1) | CA1234436A (en) |
| DK (1) | DK166300C (en) |
| FI (1) | FI844086L (en) |
| GR (1) | GR80595B (en) |
| IE (1) | IE842670L (en) |
| MX (1) | MX157393A (en) |
| ZA (1) | ZA848032B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4851834A (en) * | 1984-01-19 | 1989-07-25 | Digital Equipment Corp. | Multiport memory and source arrangement for pixel information |
| JPH0736105B2 (en) * | 1986-04-11 | 1995-04-19 | 三菱電機株式会社 | Display controller |
| DE3710696A1 (en) * | 1987-03-31 | 1988-11-10 | Nixdorf Computer Ag | METHOD FOR PROCESSING THE MEMORY CONTENT OF AN IMAGE REPEAT MEMORY AND CIRCUIT ARRANGEMENT FOR IMPLEMENTING THE METHOD |
| US5956524A (en) * | 1990-04-06 | 1999-09-21 | Micro Technology Inc. | System and method for dynamic alignment of associated portions of a code word from a plurality of asynchronous sources |
| US20030088611A1 (en) * | 1994-01-19 | 2003-05-08 | Mti Technology Corporation | Systems and methods for dynamic alignment of associated portions of a code word from a plurality of asynchronous sources |
| KR100918297B1 (en) * | 2003-02-15 | 2009-09-18 | 엘아이지넥스원 주식회사 | Raster circuit capable of controlling timing of video mixing system |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4078249A (en) * | 1976-06-01 | 1978-03-07 | Raytheon Company | Digital display composition system |
| US4240075A (en) * | 1979-06-08 | 1980-12-16 | International Business Machines Corporation | Text processing and display system with means for rearranging the spatial format of a selectable section of displayed data |
| JPS56111884A (en) * | 1980-02-08 | 1981-09-03 | Hitachi Ltd | Refreshing system for display picture |
| US4496944A (en) * | 1980-02-29 | 1985-01-29 | Calma Company | Graphics display system and method including associative addressing |
| DE3014437C2 (en) * | 1980-04-10 | 1982-05-27 | Siemens AG, 1000 Berlin und 8000 München | Arrangement for displaying alphanumeric characters on a screen of a display unit |
| US4366476A (en) * | 1980-07-03 | 1982-12-28 | General Electric Company | Raster display generating system |
| US4486746A (en) * | 1981-11-24 | 1984-12-04 | Hughes Aircraft Company | Digital system for raster scan display of video and alpha-numerics with single bit map memory |
| US4555775B1 (en) * | 1982-10-07 | 1995-12-05 | Bell Telephone Labor Inc | Dynamic generation and overlaying of graphic windows for multiple active program storage areas |
| US4474628A (en) * | 1983-07-11 | 1984-10-02 | Ireco Chemicals | Slurry explosive with high strength hollow spheres |
-
1983
- 1983-10-18 US US06/543,107 patent/US4625203A/en not_active Expired - Lifetime
-
1984
- 1984-10-11 GR GR80595A patent/GR80595B/en unknown
- 1984-10-11 CA CA000465216A patent/CA1234436A/en not_active Expired
- 1984-10-15 ZA ZA848032A patent/ZA848032B/en unknown
- 1984-10-15 MX MX203051A patent/MX157393A/en unknown
- 1984-10-16 JP JP59217216A patent/JPS60101637A/en active Granted
- 1984-10-17 BR BR8405250A patent/BR8405250A/en not_active IP Right Cessation
- 1984-10-17 AU AU34436/84A patent/AU568159B2/en not_active Ceased
- 1984-10-17 EP EP84402086A patent/EP0145530A3/en not_active Withdrawn
- 1984-10-17 FI FI844086A patent/FI844086L/en not_active Application Discontinuation
- 1984-10-17 IE IE842670A patent/IE842670L/en unknown
- 1984-10-17 KR KR1019840006422A patent/KR900006942B1/en not_active IP Right Cessation
- 1984-10-18 DK DK498884A patent/DK166300C/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR850002998A (en) | 1985-05-28 |
| JPS6329289B2 (en) | 1988-06-13 |
| AU3443684A (en) | 1985-04-26 |
| US4625203A (en) | 1986-11-25 |
| KR900006942B1 (en) | 1990-09-25 |
| ZA848032B (en) | 1985-06-26 |
| EP0145530A3 (en) | 1989-07-26 |
| FI844086L (en) | 1985-04-19 |
| AU568159B2 (en) | 1987-12-17 |
| FI844086A0 (en) | 1984-10-17 |
| EP0145530A2 (en) | 1985-06-19 |
| JPS60101637A (en) | 1985-06-05 |
| DK498884A (en) | 1985-04-19 |
| IE842670L (en) | 1985-04-18 |
| DK166300C (en) | 1993-08-30 |
| MX157393A (en) | 1988-11-21 |
| BR8405250A (en) | 1985-08-27 |
| DK498884D0 (en) | 1984-10-18 |
| GR80595B (en) | 1985-01-25 |
| DK166300B (en) | 1993-03-29 |
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| MKEX | Expiry |