CA1235754A - Digital demodulator arrangement for quadrature signals - Google Patents
Digital demodulator arrangement for quadrature signalsInfo
- Publication number
- CA1235754A CA1235754A CA000465960A CA465960A CA1235754A CA 1235754 A CA1235754 A CA 1235754A CA 000465960 A CA000465960 A CA 000465960A CA 465960 A CA465960 A CA 465960A CA 1235754 A CA1235754 A CA 1235754A
- Authority
- CA
- Canada
- Prior art keywords
- digital
- phase
- signal
- signals
- quadrature
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D3/00—Demodulation of angle-, frequency- or phase- modulated oscillations
- H03D3/007—Demodulation of angle-, frequency- or phase- modulated oscillations by converting the oscillations into two quadrature related signals
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/10—Frequency-modulated carrier systems, i.e. using frequency-shift keying
- H04L27/14—Demodulator circuits; Receiver circuits
- H04L27/144—Demodulator circuits; Receiver circuits with demodulation using spectral properties of the received signal, e.g. by using frequency selective- or frequency sensitive elements
- H04L27/152—Demodulator circuits; Receiver circuits with demodulation using spectral properties of the received signal, e.g. by using frequency selective- or frequency sensitive elements using controlled oscillators, e.g. PLL arrangements
- H04L27/1525—Demodulator circuits; Receiver circuits with demodulation using spectral properties of the received signal, e.g. by using frequency selective- or frequency sensitive elements using controlled oscillators, e.g. PLL arrangements using quadrature demodulation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
- H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
- H04L27/38—Demodulator circuits; Receiver circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D2200/00—Indexing scheme relating to details of demodulation or transference of modulation from one carrier to another covered by H03D
- H03D2200/0041—Functional aspects of demodulators
- H03D2200/005—Analog to digital conversion
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D2200/00—Indexing scheme relating to details of demodulation or transference of modulation from one carrier to another covered by H03D
- H03D2200/0041—Functional aspects of demodulators
- H03D2200/0052—Digital to analog conversion
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D3/00—Demodulation of angle-, frequency- or phase- modulated oscillations
- H03D3/006—Demodulation of angle-, frequency- or phase- modulated oscillations by sampling the oscillations and further processing the samples, e.g. by computing techniques
Abstract
DIGITAL DEMODULATOR ARRANGEMENT FOR
QUADRATURE SIGNALS
Abstract of the Disclosure A direct conversion receiver in which the quadrature I and Q signals are converted into pulse density modulated digital data streams by delta-sigma modulators 14, 15. The resultant digital data streams are then processed in a logic block 18 according to predetermined logic truth tables. The digital output of the processor 18 is then converted back to an analogue signal.
QUADRATURE SIGNALS
Abstract of the Disclosure A direct conversion receiver in which the quadrature I and Q signals are converted into pulse density modulated digital data streams by delta-sigma modulators 14, 15. The resultant digital data streams are then processed in a logic block 18 according to predetermined logic truth tables. The digital output of the processor 18 is then converted back to an analogue signal.
Description
~ ~3S75~
04 This invention relates to digital 05 demodulation arrangements Eor quadrature signals formed 06 in a zero I.F. or direct conversion radio receiver.
07 In the drawings, which illustrate the prior 08 art and embodiments of the present invention, 09 Figure 1 illustrates a demodulator according 10 to the prior art, 11 Figure 2 illustrates a demodulator 12 arrangement according to the invention, 13 Figure 3 illustrates the principle of a 14 delta-sigma modulator, Figure 4 is a phasor diagram relating to the 16 function of the circuitry of Figure 2, 17 Figures 5 and 6 are further phasor diagrams, 18 Figure 7 illustrates an implementation of 19 the demodulator logic of Figure 1, Figure 8 illustrates an alternative 21 implementation of the demodulator logic, and 22 Figure 9 illustrates an implementation for 23 55B demodulation.
24 In British patent application No. 8127797 25 (Serial No. 2106734A) there is described a direct 26 conversion receiver incorporating a multi-mode digital 27 demodulator, using the configuration shown in Figure 1.
28 In this receiver, the input signals from the antenna (or 29 from the cable system or whatever) are mixed in two 30 mixers 1, 2 with a local oscillator 3. In either the 31 oscillator or signal path a quadrature network is 32 interposed 4 or 4' such that the relative phases of 33 either the signal or the local oscillator have a phase 34 difference of 90 at the two mixers. (As an 35 alternative, two 45 phase shift networks of opposite 36 sign may be used, one in the signal and one in the local 37 oscillator). The outputs from the mixers are low-pass 5~754 ~ - 2 -02 filtered 5, 6 to select the difference frequency between 03 the input signal and the local oscillator. Af-ter 04 amplification via 7, 8 (if necessary) the signals in the 05 two channel.s (termed the 'I' or in-phase and the 'Q' or 06 quadrature channels) are converted from analogue to 07 digital form I', Q' by elemer.-ts 9, 10. The digital 08 signals are processed in a digital signal processing block 09 11, which may consist of hardwired logic or which may be a microprocessor(s) programmed with software. The processor 11 performs the demodulation of the signals and may also 12 provide filtering and other post-detection functions. It 13 further may provide specialized outputs such as feedback 14 to the other receiver parts to control gain or phase -such feedback being either digital or converted to 16 analogue via a digital to analogue converter.
17 The present invention provides for a simplified 18 realisation of the digital processor demodulator using an 19 approximation to the perfect system disclosed in the prior art and, interalia, makes use of a particular form of 21 analogue-to-digital converter. A demodulator for both 22 amplitude and phase modulations is described, together 23 with a number of variants to provide additional functions.
24 According to the present invention there is provided a radio receiver having a first signal path in 26 which a signal is mixed with a local oscillator frequency 27 running at the main transmission frequency and then 28 filtered to give a first mixed signal defined as an 29 in-phase signal (I), a second signal path in which the received signal is mixed with the local oscillator 31 frequency but with a relative phase shift and then 32 filtered to give a second mixed signal defined as a 33 quadrature signal (Q), each signal path including 34 analogue-to-digital conversion means whereby the I and Q
:~35754 01 ' -- ~ --02 signals are converted into pulse density modulated (PDM) 03 digital data streams respectively, the receiver a]so 04 including a logic means to which the outputs oE -the PDM
05 streams are applied, whereby the logic means output is a 06 demodulation of the digital signals.
07 In the arrangement shown in Figure 2 the I
08 and Q channels are separately digitised as single serial 09 data streams using analogue-to-digital converters 14, 15, which may be of the delta-sigma modulator type 11 described OR Pulse Density Modulators as described in 12 British patent 1450989. Figure 3 shows the basic 13 structure of such a modulator. The analogue input is 14 compared with a reference voltage in comparator 20. The difference between the input and reference voltages sets 16 the D input of a clocXed bistable 21. The Q output of 17 the bistable is applied in a negative feedback to the 18 input. The outputs of the pulse density modulators are 19 applied to a logic block 18. Logic block 18 produces a digital word output dependent on the states of the I & Q
21 pulse density inputs. There may also be a clock input 22 to the block 1~. The outputs are appLied to a 23 digital-to-analogue converter 19 when necessary, and 24 smoothed using a low-pass filter which may consist simply of an RC section, or which may be a more complex 26 filter.
27 The function of the circuitry may be seen 28 with reference to Figure 4 which shows a phasor 29 diagram. The reference phase for this diagram is the local oscillator phase and the amplitudes of two 31 channels are represented on the axes at right-angles.
32 An input signal at any instant in time may be 33 represented by a phasor as shown, having relative phase 34 ~, and amplitude rl. Thus, for example, a frequency modulated signal would have constant amplitude and the 36 phase would vary as the integral of the ~ ~35754 modulating information in the usual way. A continuous-wave carrier would be represented by a phasor which rotated at a constant speed either clock-wise or anti-clockwise depending on whether it were higher or lower in frequency than the local oscillator.
In the present case, the values of I or Q at the digital processor are constrained to be zero or one or a series of such digits since they are a digital data stream and we choose to represent all zeros at the left or ~ottom of the diagram and all ones at the right or top.
TABLE I
I Q Phase o 0 225 ` 20 The amplitude may be represented by any number of digits of the data streams and an approximation to the amplitude or phase decoded.
For example, for one data bit at a time, the phase may clearly be deduced to be in one quadrant and assigned that value by the logic block as given in Table I.
Since the phase values are binarily related to 90 increments, this phase can be represented by a two bit data output. A logic circuit to implement this is given in Figure 7.
By subtracting one phase value from the previous phase value, the differential of the phase (i.e. the frequency) is demodulated. Thus, just as the inputs are estimated by an incremental digital stream, the demodulated outputs are also estimated. When these outputs are smoothed, an adequate approximation to the required demodulated information is obtained.
1~35~5~ 1 While the approximations made above are accurate for phasors which truly lie in the 45 or 135 positions etc, intermediate values are not so accurately demodulated, since they are formed as a linear approximation between the available outputs. The peak error in this process is half-way between the set values:
for example, a phasor which actually would be represented by exact values of I equals unit~ and Q equals three quarters will be approximated as one half of 45, that is, 22.5, whereas the correct output is arc tangent 0.5 which is 26.6. This is in fact the peak error and is clearly repeated at eight points around the phasor diagram and has a maximum value of about +4 . In many circumstances, this approximation is adequate. However, if greater fidelity is needed, then this can be provided by taking more than one sample of data at a time.
Figs. 5 and 6 show the case where a pair of sequential samples of the I and Q data are used. Thus the left and bottom is '00' the right and top '11' and a ~ 20 value of 0.5 assigned to the combinations '01' or '10' at the centre - ('01' and '10' have the same significance since each data sample has equal weight). Correct output values may now be assigned for the intermediate samples.
Fig. 5 shows the phase outputs. In a similar - 25 fashion, Fig. 6 gives the amplitude values for the first quadrant, and Table II summarises the values for this case. Note that for the phase output the I=10, Q=10 case is undefined. In this case the output may be held at the previous value or an interpolation made between previous and subsequent values.
1~35~54 TABLE II
S ~ PHASE(~) ~ AMPLlT~
00 O0 225 ~ 2 ~0 00 11 135 ~ 2 11 00 310 ~ 2 11 10 oO 1 1 15 11 11 45 ~ 2 . .. _ , . _ NOTE 10=01 as well In both of these cases, the output samples are only available at half the clock rate of the analogue-to-digital converters. However, this is more than compensated by the improved accuracy.
Alternatively, the data from the 'one-bit' -analogue-to-digital converter may be slipped through such that each bit is used twice and the output remains at the original clock sampling rate.
Clearly, the principle may be extended to taking any number of bits of data at a time. It will also be clear that as the clock frequency is made higher, smaller analogue input signals can be demodulated wi~h adequate resolution. That is, the dynamic range of the processor can be increased directly with the clock rate.
The hardware needed for the block 18 in Fig. 2 consists in essence of logic to implement either Table I
or Table II as a truth table. Fig. 7 shows an exemplary ~ ;~35754 implementation for the simplest case of the one-bit-at-a-time phase and frequency demodulator. In this case, the phase values have binary weights (i.e. 0, 45, 90) and can thus be directly assigned. The combinational logic shown is merely one possible way of achieving the function required.
For frequency demodulation the differential of the phase is required and this may be ob~ained by subtracting each phase output word from its predecessor.
The subtractor block 22 uses the clocX input to time the storing of one word and its subtraction from the previous one. A 2-bit output (i.e. without the most-significant bit) is used.
To implement the amplitude values of Table I and the whole of Table II, outputs from the processor block 18 are needed which do not have simple binary relationships. Two possibilities exist here: firstly, the correct values may be assigned at the point OL
digital-to-analogue conversion. Thus, the digital-to-analogue converter is provided with weighted outputs (set, for example, by the ratios of resistors or capacitors or the width of pulses, etc.) which have the values of 1, ~, ~ etc., as necessary. This method is suitable where no further digital processing is employed.
The second method outputs a conventional binary weighted digital word of sufficient number of bits to describe the required values to any accuracy desired.
Thus, to give a better than 1% accuracy, a 7-bit word is employed~ However, only a small number of such words are needed (e.g. 3 for the two-bits-at-a-time amplitude demodulator, including all zeros and all ones as two of them). In this case, the simplest hardware form is a look-up table 23, Fig. 8, addressed with the I'and Q
values and outputting the appropriate word. This data word can now be further processed using conventional digital signal processing techniques.
i ;~3575~
A number of other functions may also be needed in practical equipments. These may be derived from the fundamental data of phase and amplitude or will sometimes be more conveniently obtained directly. For example, for automatic gain control feedback, an output is needed which is derived from the square of the amplitude. This can be provided directly by (I + Q ). The result of this is compared with a threshold and a single bit output provided whenever the value is exceeded. Smoothing this value gives the analogue a.g.c. voltage. Table II gives the conversion values applicable to this case.
Single-sideband demodulation requires a special configuration as given in patent application No. 8127797.
The local oscillator is nominally placed in the centre of the sideband and the phase of the output samples then needs to be shifted at a rate which is the equivalent of the offset frequency fr-om the originals (suppressed) carrier. Fig. 9 shows the required circuitry for the one-bit-at-a-time case. The phase is shifted by adding or subtracting a fixed number (depending on whether the signal is an upper or lower sideband) in the phase logic 24.
04 This invention relates to digital 05 demodulation arrangements Eor quadrature signals formed 06 in a zero I.F. or direct conversion radio receiver.
07 In the drawings, which illustrate the prior 08 art and embodiments of the present invention, 09 Figure 1 illustrates a demodulator according 10 to the prior art, 11 Figure 2 illustrates a demodulator 12 arrangement according to the invention, 13 Figure 3 illustrates the principle of a 14 delta-sigma modulator, Figure 4 is a phasor diagram relating to the 16 function of the circuitry of Figure 2, 17 Figures 5 and 6 are further phasor diagrams, 18 Figure 7 illustrates an implementation of 19 the demodulator logic of Figure 1, Figure 8 illustrates an alternative 21 implementation of the demodulator logic, and 22 Figure 9 illustrates an implementation for 23 55B demodulation.
24 In British patent application No. 8127797 25 (Serial No. 2106734A) there is described a direct 26 conversion receiver incorporating a multi-mode digital 27 demodulator, using the configuration shown in Figure 1.
28 In this receiver, the input signals from the antenna (or 29 from the cable system or whatever) are mixed in two 30 mixers 1, 2 with a local oscillator 3. In either the 31 oscillator or signal path a quadrature network is 32 interposed 4 or 4' such that the relative phases of 33 either the signal or the local oscillator have a phase 34 difference of 90 at the two mixers. (As an 35 alternative, two 45 phase shift networks of opposite 36 sign may be used, one in the signal and one in the local 37 oscillator). The outputs from the mixers are low-pass 5~754 ~ - 2 -02 filtered 5, 6 to select the difference frequency between 03 the input signal and the local oscillator. Af-ter 04 amplification via 7, 8 (if necessary) the signals in the 05 two channel.s (termed the 'I' or in-phase and the 'Q' or 06 quadrature channels) are converted from analogue to 07 digital form I', Q' by elemer.-ts 9, 10. The digital 08 signals are processed in a digital signal processing block 09 11, which may consist of hardwired logic or which may be a microprocessor(s) programmed with software. The processor 11 performs the demodulation of the signals and may also 12 provide filtering and other post-detection functions. It 13 further may provide specialized outputs such as feedback 14 to the other receiver parts to control gain or phase -such feedback being either digital or converted to 16 analogue via a digital to analogue converter.
17 The present invention provides for a simplified 18 realisation of the digital processor demodulator using an 19 approximation to the perfect system disclosed in the prior art and, interalia, makes use of a particular form of 21 analogue-to-digital converter. A demodulator for both 22 amplitude and phase modulations is described, together 23 with a number of variants to provide additional functions.
24 According to the present invention there is provided a radio receiver having a first signal path in 26 which a signal is mixed with a local oscillator frequency 27 running at the main transmission frequency and then 28 filtered to give a first mixed signal defined as an 29 in-phase signal (I), a second signal path in which the received signal is mixed with the local oscillator 31 frequency but with a relative phase shift and then 32 filtered to give a second mixed signal defined as a 33 quadrature signal (Q), each signal path including 34 analogue-to-digital conversion means whereby the I and Q
:~35754 01 ' -- ~ --02 signals are converted into pulse density modulated (PDM) 03 digital data streams respectively, the receiver a]so 04 including a logic means to which the outputs oE -the PDM
05 streams are applied, whereby the logic means output is a 06 demodulation of the digital signals.
07 In the arrangement shown in Figure 2 the I
08 and Q channels are separately digitised as single serial 09 data streams using analogue-to-digital converters 14, 15, which may be of the delta-sigma modulator type 11 described OR Pulse Density Modulators as described in 12 British patent 1450989. Figure 3 shows the basic 13 structure of such a modulator. The analogue input is 14 compared with a reference voltage in comparator 20. The difference between the input and reference voltages sets 16 the D input of a clocXed bistable 21. The Q output of 17 the bistable is applied in a negative feedback to the 18 input. The outputs of the pulse density modulators are 19 applied to a logic block 18. Logic block 18 produces a digital word output dependent on the states of the I & Q
21 pulse density inputs. There may also be a clock input 22 to the block 1~. The outputs are appLied to a 23 digital-to-analogue converter 19 when necessary, and 24 smoothed using a low-pass filter which may consist simply of an RC section, or which may be a more complex 26 filter.
27 The function of the circuitry may be seen 28 with reference to Figure 4 which shows a phasor 29 diagram. The reference phase for this diagram is the local oscillator phase and the amplitudes of two 31 channels are represented on the axes at right-angles.
32 An input signal at any instant in time may be 33 represented by a phasor as shown, having relative phase 34 ~, and amplitude rl. Thus, for example, a frequency modulated signal would have constant amplitude and the 36 phase would vary as the integral of the ~ ~35754 modulating information in the usual way. A continuous-wave carrier would be represented by a phasor which rotated at a constant speed either clock-wise or anti-clockwise depending on whether it were higher or lower in frequency than the local oscillator.
In the present case, the values of I or Q at the digital processor are constrained to be zero or one or a series of such digits since they are a digital data stream and we choose to represent all zeros at the left or ~ottom of the diagram and all ones at the right or top.
TABLE I
I Q Phase o 0 225 ` 20 The amplitude may be represented by any number of digits of the data streams and an approximation to the amplitude or phase decoded.
For example, for one data bit at a time, the phase may clearly be deduced to be in one quadrant and assigned that value by the logic block as given in Table I.
Since the phase values are binarily related to 90 increments, this phase can be represented by a two bit data output. A logic circuit to implement this is given in Figure 7.
By subtracting one phase value from the previous phase value, the differential of the phase (i.e. the frequency) is demodulated. Thus, just as the inputs are estimated by an incremental digital stream, the demodulated outputs are also estimated. When these outputs are smoothed, an adequate approximation to the required demodulated information is obtained.
1~35~5~ 1 While the approximations made above are accurate for phasors which truly lie in the 45 or 135 positions etc, intermediate values are not so accurately demodulated, since they are formed as a linear approximation between the available outputs. The peak error in this process is half-way between the set values:
for example, a phasor which actually would be represented by exact values of I equals unit~ and Q equals three quarters will be approximated as one half of 45, that is, 22.5, whereas the correct output is arc tangent 0.5 which is 26.6. This is in fact the peak error and is clearly repeated at eight points around the phasor diagram and has a maximum value of about +4 . In many circumstances, this approximation is adequate. However, if greater fidelity is needed, then this can be provided by taking more than one sample of data at a time.
Figs. 5 and 6 show the case where a pair of sequential samples of the I and Q data are used. Thus the left and bottom is '00' the right and top '11' and a ~ 20 value of 0.5 assigned to the combinations '01' or '10' at the centre - ('01' and '10' have the same significance since each data sample has equal weight). Correct output values may now be assigned for the intermediate samples.
Fig. 5 shows the phase outputs. In a similar - 25 fashion, Fig. 6 gives the amplitude values for the first quadrant, and Table II summarises the values for this case. Note that for the phase output the I=10, Q=10 case is undefined. In this case the output may be held at the previous value or an interpolation made between previous and subsequent values.
1~35~54 TABLE II
S ~ PHASE(~) ~ AMPLlT~
00 O0 225 ~ 2 ~0 00 11 135 ~ 2 11 00 310 ~ 2 11 10 oO 1 1 15 11 11 45 ~ 2 . .. _ , . _ NOTE 10=01 as well In both of these cases, the output samples are only available at half the clock rate of the analogue-to-digital converters. However, this is more than compensated by the improved accuracy.
Alternatively, the data from the 'one-bit' -analogue-to-digital converter may be slipped through such that each bit is used twice and the output remains at the original clock sampling rate.
Clearly, the principle may be extended to taking any number of bits of data at a time. It will also be clear that as the clock frequency is made higher, smaller analogue input signals can be demodulated wi~h adequate resolution. That is, the dynamic range of the processor can be increased directly with the clock rate.
The hardware needed for the block 18 in Fig. 2 consists in essence of logic to implement either Table I
or Table II as a truth table. Fig. 7 shows an exemplary ~ ;~35754 implementation for the simplest case of the one-bit-at-a-time phase and frequency demodulator. In this case, the phase values have binary weights (i.e. 0, 45, 90) and can thus be directly assigned. The combinational logic shown is merely one possible way of achieving the function required.
For frequency demodulation the differential of the phase is required and this may be ob~ained by subtracting each phase output word from its predecessor.
The subtractor block 22 uses the clocX input to time the storing of one word and its subtraction from the previous one. A 2-bit output (i.e. without the most-significant bit) is used.
To implement the amplitude values of Table I and the whole of Table II, outputs from the processor block 18 are needed which do not have simple binary relationships. Two possibilities exist here: firstly, the correct values may be assigned at the point OL
digital-to-analogue conversion. Thus, the digital-to-analogue converter is provided with weighted outputs (set, for example, by the ratios of resistors or capacitors or the width of pulses, etc.) which have the values of 1, ~, ~ etc., as necessary. This method is suitable where no further digital processing is employed.
The second method outputs a conventional binary weighted digital word of sufficient number of bits to describe the required values to any accuracy desired.
Thus, to give a better than 1% accuracy, a 7-bit word is employed~ However, only a small number of such words are needed (e.g. 3 for the two-bits-at-a-time amplitude demodulator, including all zeros and all ones as two of them). In this case, the simplest hardware form is a look-up table 23, Fig. 8, addressed with the I'and Q
values and outputting the appropriate word. This data word can now be further processed using conventional digital signal processing techniques.
i ;~3575~
A number of other functions may also be needed in practical equipments. These may be derived from the fundamental data of phase and amplitude or will sometimes be more conveniently obtained directly. For example, for automatic gain control feedback, an output is needed which is derived from the square of the amplitude. This can be provided directly by (I + Q ). The result of this is compared with a threshold and a single bit output provided whenever the value is exceeded. Smoothing this value gives the analogue a.g.c. voltage. Table II gives the conversion values applicable to this case.
Single-sideband demodulation requires a special configuration as given in patent application No. 8127797.
The local oscillator is nominally placed in the centre of the sideband and the phase of the output samples then needs to be shifted at a rate which is the equivalent of the offset frequency fr-om the originals (suppressed) carrier. Fig. 9 shows the required circuitry for the one-bit-at-a-time case. The phase is shifted by adding or subtracting a fixed number (depending on whether the signal is an upper or lower sideband) in the phase logic 24.
Claims (6)
1. A radio receiver having a first signal path in which a signal is mixed with a local oscillator frequency running at the main transmission frequency and then filtered to give a first mixed signal defined as an in-phase signal (I), a second signal path in which the received signal is mixed with the local oscillator frequency but with a relative phase shift and then filtered to give a second mixed signal defined as a quadrature signal (Q), each signal path including analogue-to-digital conversion means whereby the I and Q
signals are converted into pulse density modulated (PDM) digital data streams respectively, the receiver also including a logic means to which the outputs of the PDM
streams are applied, whereby the logic means output is a demodulation of the digital signals.
signals are converted into pulse density modulated (PDM) digital data streams respectively, the receiver also including a logic means to which the outputs of the PDM
streams are applied, whereby the logic means output is a demodulation of the digital signals.
2. A receiver according to claim 1 wherein the analogue-to-digital conversion means in each signal path comprises a delta-sigma modulator.
3. A receiver according to claim 1 wherein the logic means includes look-up table means addressed by the digital data and combinational logic wherein the output of the look-up operation is a binary weighted digital word defining the values of a sample of an analogue signal represented by the digital signals.
4. A method of demodulating quadrature signals formed in a zero I.F. or direct conversion radio receiver wherein the quadrature signals are each analogue-to-digital converted into respective pulse density modulated digital data streams and the data streams are applied to a logic means arranged to process the signals according to a predetermined table of input logic conditions.
5. A direct conversion radio receiver comprising means for receiving a modulated carrier frequency signal and for converting the signal to in-phase and quadrature-phase baseband signals; a pair of analog-to-digital conversion means connected to said receiving means for converting the in-phase and quadrature-phase signals into respective pulse density modulated (PDM) digital data streams; and logic means coupled to said pair of conversion means and responsive to said pulse density modulated digital data streams for providing a demodulated output signal.
6. A method of demodulating a pair of related in-phase and quadrature-phase signals provided by a zero I.F. or direct conversion radio receiver comprising analog-to-digital converting each of said in-phase and quadrature-phase signals into respective pulse density modulated (PDM) digital data streams; and logically processing said pulse density modulated digital data streams in accordance with a predetermined table of input logic conditions to provide a demodulated output signal.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB08328949A GB2149244B (en) | 1983-10-29 | 1983-10-29 | Digital demodulator arrangement for quadrature signals |
| GB8328949 | 1983-10-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1235754A true CA1235754A (en) | 1988-04-26 |
Family
ID=10550943
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000465960A Expired CA1235754A (en) | 1983-10-29 | 1984-10-19 | Digital demodulator arrangement for quadrature signals |
Country Status (11)
| Country | Link |
|---|---|
| US (1) | US4583239A (en) |
| EP (1) | EP0143539A3 (en) |
| JP (1) | JPS60112344A (en) |
| AU (1) | AU562232B2 (en) |
| CA (1) | CA1235754A (en) |
| ES (1) | ES8606963A1 (en) |
| FI (1) | FI79430C (en) |
| GB (1) | GB2149244B (en) |
| HK (1) | HK18588A (en) |
| NO (1) | NO844289L (en) |
| NZ (1) | NZ209885A (en) |
Families Citing this family (46)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2155262B (en) * | 1984-03-01 | 1988-01-20 | Standard Telephones Cables Ltd | Radio receiver |
| US4731796A (en) * | 1984-10-25 | 1988-03-15 | Stc, Plc | Multi-mode radio transceiver |
| GB2192506B (en) * | 1986-07-12 | 1990-05-30 | Stc Plc | Demodulation circuit |
| US4825452A (en) * | 1987-03-04 | 1989-04-25 | National Semiconductor Corporation | Digital FSK demodulator |
| EP0310796A1 (en) * | 1987-10-08 | 1989-04-12 | BBC Brown Boveri AG | FM-signal demodulation method |
| GB2215945A (en) * | 1988-03-26 | 1989-09-27 | Stc Plc | Digital direct conversion radio |
| GB2219899A (en) * | 1988-06-17 | 1989-12-20 | Philips Electronic Associated | A zero if receiver |
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| US3609555A (en) * | 1967-07-19 | 1971-09-28 | Ibm | Digital fm receiver |
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-
1983
- 1983-10-29 GB GB08328949A patent/GB2149244B/en not_active Expired
-
1984
- 1984-10-15 EP EP84307025A patent/EP0143539A3/en not_active Withdrawn
- 1984-10-15 NZ NZ209885A patent/NZ209885A/en unknown
- 1984-10-17 AU AU34444/84A patent/AU562232B2/en not_active Ceased
- 1984-10-17 FI FI844092A patent/FI79430C/en not_active IP Right Cessation
- 1984-10-18 US US06/662,050 patent/US4583239A/en not_active Expired - Fee Related
- 1984-10-19 CA CA000465960A patent/CA1235754A/en not_active Expired
- 1984-10-26 NO NO844289A patent/NO844289L/en unknown
- 1984-10-27 ES ES537156A patent/ES8606963A1/en not_active Expired
- 1984-10-29 JP JP59227625A patent/JPS60112344A/en active Pending
-
1988
- 1988-03-10 HK HK185/88A patent/HK18588A/en unknown
Also Published As
| Publication number | Publication date |
|---|---|
| AU562232B2 (en) | 1987-06-04 |
| EP0143539A2 (en) | 1985-06-05 |
| ES537156A0 (en) | 1986-05-16 |
| US4583239A (en) | 1986-04-15 |
| JPS60112344A (en) | 1985-06-18 |
| HK18588A (en) | 1988-03-18 |
| FI79430B (en) | 1989-08-31 |
| AU3444484A (en) | 1985-05-02 |
| GB8328949D0 (en) | 1983-11-30 |
| NO844289L (en) | 1985-04-30 |
| EP0143539A3 (en) | 1987-06-24 |
| ES8606963A1 (en) | 1986-05-16 |
| FI844092A0 (en) | 1984-10-17 |
| FI844092L (en) | 1985-04-30 |
| GB2149244B (en) | 1987-01-21 |
| GB2149244A (en) | 1985-06-05 |
| FI79430C (en) | 1989-12-11 |
| NZ209885A (en) | 1988-07-28 |
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