CA1236930A - Method for use in brazing an interconnect pin to a metallization pattern situated on a brittle dielectric - Google Patents
Method for use in brazing an interconnect pin to a metallization pattern situated on a brittle dielectricInfo
- Publication number
- CA1236930A CA1236930A CA000504664A CA504664A CA1236930A CA 1236930 A CA1236930 A CA 1236930A CA 000504664 A CA000504664 A CA 000504664A CA 504664 A CA504664 A CA 504664A CA 1236930 A CA1236930 A CA 1236930A
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- pad
- substrate
- dielectric
- layer
- dielectric layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49147—Assembling terminal to base
- Y10T29/49149—Assembling terminal to base by metal fusion bonding
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/12—All metal or with adjacent metals
- Y10T428/12493—Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]
- Y10T428/12535—Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.] with additional, spatially distinct nonmetal component
- Y10T428/12542—More than one such component
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- Engineering & Computer Science (AREA)
- Ceramic Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Multi-Conductor Connections (AREA)
- Coupling Device And Connection With Printed Circuit (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
A METHOD FOR USE IN BRAZING AN INTERCONNECT
PIN TO A METALLIZATION PATTERN
SITUATED ON A BRITTLE DIELECTRIC SUBSTRATE
Abstract A method for use in brazing an interconnect pin to a portion of metallization pattern (e.g. a pad) existing on a brittle dielectric substrate, such as a multi-layered ceramic (MLC) substrate, is disclosed. A dielectric layer is formed with appropriate annular openings. Each opening provides a closed containment wall, which extends around and above the pad, to hold the brazing alloy. Each circular containment wall is concentrically aligned with its associated pad and exposes an area, of each pad, having a smaller diameter than that of the entire pad. The containment walls serve to prevent the brazing alloy from coming into contact with any edge of the pads.
PIN TO A METALLIZATION PATTERN
SITUATED ON A BRITTLE DIELECTRIC SUBSTRATE
Abstract A method for use in brazing an interconnect pin to a portion of metallization pattern (e.g. a pad) existing on a brittle dielectric substrate, such as a multi-layered ceramic (MLC) substrate, is disclosed. A dielectric layer is formed with appropriate annular openings. Each opening provides a closed containment wall, which extends around and above the pad, to hold the brazing alloy. Each circular containment wall is concentrically aligned with its associated pad and exposes an area, of each pad, having a smaller diameter than that of the entire pad. The containment walls serve to prevent the brazing alloy from coming into contact with any edge of the pads.
Description
~-84-05~ 36~
2 lA METHOD FOR USE IN BRAZING AN INTERCONNECT
4 ¦SITUATED ON A BRITTLE DIELECTRIC SUBSTRATE
61 '.
8I 1. Field of the Invention -11 The invention relates to a method for use in brazing an 12¦ interconnect pin to a metallization pattern existing on a brittle 31 dielectric substrate, such as a multi-layered ceramic (MLC) 41 substrate.
16 2. Description of the Prior Art -18 A multi-chip integrated circuit package employing the well-l9j known "flip-chip" technique utilizes a multi-layer ceramic 20,, substrate (MLC) -- constructed of a plurality of laminated 21'1 ceramic layers. All the individual chips are mounted to the top 22,, layer of the MLC substrate. A pre-defined metallization pattern 23 I lies on each ceramic layer within the substrate. Metallization 24 patterns on certain layers act as voltage reference planes and 25 1 also provide power to the individual chips. Metallization 26 patterns on other layers route signals between individual chips.
27 Electrical connections to individual terminals of each chip 28 and/or between separate layers are made through well-known 29 vertical interconnects called "vias". Interconnect pins are bonded to metallic pads situated on the bottom surface of the MLC
., 1 I 1, [I 4-~51 ~3~0 l substrate and thereby connected to appropriate metallization 2 patterns existing within the substrate. These interconnect pins
4 ¦SITUATED ON A BRITTLE DIELECTRIC SUBSTRATE
61 '.
8I 1. Field of the Invention -11 The invention relates to a method for use in brazing an 12¦ interconnect pin to a metallization pattern existing on a brittle 31 dielectric substrate, such as a multi-layered ceramic (MLC) 41 substrate.
16 2. Description of the Prior Art -18 A multi-chip integrated circuit package employing the well-l9j known "flip-chip" technique utilizes a multi-layer ceramic 20,, substrate (MLC) -- constructed of a plurality of laminated 21'1 ceramic layers. All the individual chips are mounted to the top 22,, layer of the MLC substrate. A pre-defined metallization pattern 23 I lies on each ceramic layer within the substrate. Metallization 24 patterns on certain layers act as voltage reference planes and 25 1 also provide power to the individual chips. Metallization 26 patterns on other layers route signals between individual chips.
27 Electrical connections to individual terminals of each chip 28 and/or between separate layers are made through well-known 29 vertical interconnects called "vias". Interconnect pins are bonded to metallic pads situated on the bottom surface of the MLC
., 1 I 1, [I 4-~51 ~3~0 l substrate and thereby connected to appropriate metallization 2 patterns existing within the substrate. These interconnect pins
3 i route electrical signals between a multi-chip integrated circuit 41~ package and external devices.
5l 6 ! One well known technique of mounting an interconnect pin to 7 such a metallic pad involves coating the pad and the pin with a 81 protective metallic layer that serves as a diffusion barrier, and 9~ thereafter coating the pad and the head of the pin with an 10~ appropriate brazing alloy, and then brazing the pin to the pad.
11i Unfortunately, this technique often produces stress between the 1 12l pad and the underlying ceramic substrate that can lead to 13l fractures in the ceramic situated directly beneath the pad.
15l This stress originates from two sources: from the interface 16 between the metallic pad and the MLC substrate, and from the 171~ brazed joint itself. Specifically, the MLC substrate is rather 18 ll brittle and has a thermal coefficient of expansion different from 19il that of the pad. Consequently, due to the thermal expansion mis-20l match at the interface between the pad and the MLC substrate, the 21,I ceramic situated directly beneath the pad is placed in 22 considerable stress.
23!!
`I In addition, the brazed joint imparts considerable tensile stress to the pad which is directed through the pad to the 26 underlying MLC substrate. Although the predominant mechanism 27 causing this phenomenon is not completely known, it appears that 2g l l 'i1 , -9-84-051 ~3~3~
il 2 several factors are at least partially responsible. First, there 3 lis a thermal expansion mis-match between the braze and the pad.
5l 6 ! One well known technique of mounting an interconnect pin to 7 such a metallic pad involves coating the pad and the pin with a 81 protective metallic layer that serves as a diffusion barrier, and 9~ thereafter coating the pad and the head of the pin with an 10~ appropriate brazing alloy, and then brazing the pin to the pad.
11i Unfortunately, this technique often produces stress between the 1 12l pad and the underlying ceramic substrate that can lead to 13l fractures in the ceramic situated directly beneath the pad.
15l This stress originates from two sources: from the interface 16 between the metallic pad and the MLC substrate, and from the 171~ brazed joint itself. Specifically, the MLC substrate is rather 18 ll brittle and has a thermal coefficient of expansion different from 19il that of the pad. Consequently, due to the thermal expansion mis-20l match at the interface between the pad and the MLC substrate, the 21,I ceramic situated directly beneath the pad is placed in 22 considerable stress.
23!!
`I In addition, the brazed joint imparts considerable tensile stress to the pad which is directed through the pad to the 26 underlying MLC substrate. Although the predominant mechanism 27 causing this phenomenon is not completely known, it appears that 2g l l 'i1 , -9-84-051 ~3~3~
il 2 several factors are at least partially responsible. First, there 3 lis a thermal expansion mis-match between the braze and the pad.
4 Second, during brazing, various elemental constituents of the
5 1brazing alloy migrate into the pad and form inter-metallic
6 ll compounds therein which greatly increase the stress occurring
7 1within the pad. Third, the braze often becomes embrittled when
8 iit reacts with other materials to which the MLC substrate is gllexposed during its fabrication.
1 0 , 11 1 In any event, the tensile stress resulting from the braze 12 11 additively combines with the stress resulting from the thermal coefficient mis-match, between the pad and the MLC substrate, to produce the total tensile stress exerted on the substrate. A
15l ceramic layer is quite weak in tension. Furthermore, this total 16 l, stress is greatest around the edges of the pad. Consequently, at 17 il the edges, the total tensile stress exerted onto the MLC
18 Isubstrate often disadvantageously reaches a level sufficiently 19 high to fracture the ceramic situated directly under the pad.
This fracturing can cause the interconnect pin and the pad to 21 'mechanically separate from the substrate, thereby ruining the 22 Iintegrated circuit package.
24 The art has taught that this tensile stress can be reduced 25 by two techniques. First, as disclosed in N. Ainsle et al, 26 "Au/Sn/Ag Braze Alloy", IBM Technical Disclosure Bulletin, Vol.
27 21, No. 8, January 1979, page 3117, and in N. Ainsle et al, 28 "Au/Sn/Ag Braze Alloy", IBM Technical Disclosure Bulletin, Vol.
29 21, No. 8, January 1979, page 3118, the brazing alloy can be 30 changed to one which imparts a relatively low value of stress to * Registered trade mark
1 0 , 11 1 In any event, the tensile stress resulting from the braze 12 11 additively combines with the stress resulting from the thermal coefficient mis-match, between the pad and the MLC substrate, to produce the total tensile stress exerted on the substrate. A
15l ceramic layer is quite weak in tension. Furthermore, this total 16 l, stress is greatest around the edges of the pad. Consequently, at 17 il the edges, the total tensile stress exerted onto the MLC
18 Isubstrate often disadvantageously reaches a level sufficiently 19 high to fracture the ceramic situated directly under the pad.
This fracturing can cause the interconnect pin and the pad to 21 'mechanically separate from the substrate, thereby ruining the 22 Iintegrated circuit package.
24 The art has taught that this tensile stress can be reduced 25 by two techniques. First, as disclosed in N. Ainsle et al, 26 "Au/Sn/Ag Braze Alloy", IBM Technical Disclosure Bulletin, Vol.
27 21, No. 8, January 1979, page 3117, and in N. Ainsle et al, 28 "Au/Sn/Ag Braze Alloy", IBM Technical Disclosure Bulletin, Vol.
29 21, No. 8, January 1979, page 3118, the brazing alloy can be 30 changed to one which imparts a relatively low value of stress to * Registered trade mark
9-84-051 ~69?~
.
ia metallic pad. While this appears to be a theoretically simple 2 and ideal solution, it is often extrememly difficult to implement 3 in practice. First, a multi-chip integrated circuit package 4 contains a pre-determined thermal hierarchy, i.e. certain components of the package -- such as solder joints between individual chips and the MLC substrate -- must melt before other , components. This ensures that a chip can be heated to a temperature which will only weaken the solder joint between it land the MLC substrate and enable the chip to be removed from the '!substrate without damaging other portions of the package.
',Consequently, the operating temperatures of the chosen brazing 12 ll alloy must fall within certain prescribed ranges in this 13 il hierarchy. Second, both the pad and the interconnect pin are 14l generally fabricated using an underlying alloy having a multi-layered metallic, coating. Unfortunately, various elemental 16 I constituents (particularly tin) of the brazing alloy will often 17 migrate into one or more of the layers comprising the pin and/or 18 l the pad and form inter-metallic compounds which greatly increase 19 l the tensile stress occurring therein. To prevent this, an 20'' appropriate metallic diffusion barrier is applied over both the 21 pin and the pad before applying the brazing alloy. Although such 22 l diffusion barriers exist for many brazing alloys, appropriate 23~ barriers do not exist for others. Lastly, different brazing 24ll alloys become overly ductile or overly elastic when brazed and 25l are thus unsuitable to bond an interconnect pin to a metallic 26 l pad. Hence, choosing a different brazing alloy generally 27 ' requires that the metallurgy of many, if not all, of the 28 interconnects to the separate metallurgies comprising the so-29 called interconnect hierarchy) existing within the MLC substrate , '', , 4 .
9-84-051 ~3~3~
l be completely re-assessed and possibly re-designed. Thus, once 2 the metallurgy of all the interconnects has been determined which 3 of necessity includes selecting an appropriate brazing alloy, 4 substrate manufacturers are quite reluctant to change this alloy.
5,` ;
6' Second, each metallic pad can be divided into separate non-7 overlapping wettable segments each surrounded by a non-wettable 8 area. The brazing alloy would only adhere to the wettable areas.
g;~This technique produces a bond consisting of many individual
.
ia metallic pad. While this appears to be a theoretically simple 2 and ideal solution, it is often extrememly difficult to implement 3 in practice. First, a multi-chip integrated circuit package 4 contains a pre-determined thermal hierarchy, i.e. certain components of the package -- such as solder joints between individual chips and the MLC substrate -- must melt before other , components. This ensures that a chip can be heated to a temperature which will only weaken the solder joint between it land the MLC substrate and enable the chip to be removed from the '!substrate without damaging other portions of the package.
',Consequently, the operating temperatures of the chosen brazing 12 ll alloy must fall within certain prescribed ranges in this 13 il hierarchy. Second, both the pad and the interconnect pin are 14l generally fabricated using an underlying alloy having a multi-layered metallic, coating. Unfortunately, various elemental 16 I constituents (particularly tin) of the brazing alloy will often 17 migrate into one or more of the layers comprising the pin and/or 18 l the pad and form inter-metallic compounds which greatly increase 19 l the tensile stress occurring therein. To prevent this, an 20'' appropriate metallic diffusion barrier is applied over both the 21 pin and the pad before applying the brazing alloy. Although such 22 l diffusion barriers exist for many brazing alloys, appropriate 23~ barriers do not exist for others. Lastly, different brazing 24ll alloys become overly ductile or overly elastic when brazed and 25l are thus unsuitable to bond an interconnect pin to a metallic 26 l pad. Hence, choosing a different brazing alloy generally 27 ' requires that the metallurgy of many, if not all, of the 28 interconnects to the separate metallurgies comprising the so-29 called interconnect hierarchy) existing within the MLC substrate , '', , 4 .
9-84-051 ~3~3~
l be completely re-assessed and possibly re-designed. Thus, once 2 the metallurgy of all the interconnects has been determined which 3 of necessity includes selecting an appropriate brazing alloy, 4 substrate manufacturers are quite reluctant to change this alloy.
5,` ;
6' Second, each metallic pad can be divided into separate non-7 overlapping wettable segments each surrounded by a non-wettable 8 area. The brazing alloy would only adhere to the wettable areas.
g;~This technique produces a bond consisting of many individual
10 'brazed joints in which each joint extends over a very small area.
11 Inasmuch as the cross-sectional area of each joint is very small,
12 each of these joints is quite weak. In addition, as the pad is
13 divided into a greater number of increasingly smaller wettable 4 'segments, the effective cross-sectional area occupied by all the brazed joints becomes significantly less than that of the pad.
16 Hence, the electrical resistance of the entire bond between the 17 interconnect pin and t'he pad correspondingly increases.
Furthermore, this technique is very difficult and cumbersome to 19 implement in practice. This technique is described, in connection with a solder bond, in R. W. Roth, "Solder Bond", IBM
21 Technical Disclosure Bulletin, Vol. 17, No. 8, January 1975, page ~2 2214.
24 Hence, a need exists in the art for a method, suitable for use in brazing an interconnect pin to a metallic pad, which 26 will lower the tensile stress between the pad and an adjacent 27 dielectric ~e.g. MLC) substrate, occurring during a brazing 28 operation, while eliminating any need to change the brazing alloy 29 and simultaneously permitting a strong, reliable, minimally Z3e36 l resistive brazed joint to form between the interconnect pin and the pad.
i~SUMMARY OF THE INVENTION -Accordingly, an object of the present invention is to provide a method for use in brazing an interconnect pin to a 7 l portion of a metallization pattern, situated on a brittle 8 i ,¦dielectric substrate, such as an MLC substrate, which produces a llreliable bond between the metallization pattern and the pin.
Il 11 l A particular object is to reduce tensile stress, occurring ilat the interface between a metallic pad and the bottom surface of 13;l an MLC substrate and resulting from brazing, to a value which is less than that required to fracture the substrate.
Another particular object is to eliminate the need to change I the brazing alloy.
9~!
Another particular object is to provide a strong minimally resistive brazed joint between the pad and the pin.
l Another particular object is to increase the mechanical strength of both the MLC substrate and the interface between the pad and the dielectric substrate.
Lastly, another object is to provide a simple method that is easy to implement in a production environment.
2a _9-84-05 These and other objects are achieved in accordance with the teachings of the present invention by limiting the contact of the brazing alloy with the pad such that the brazed joint between the 4~
pin and the pad exists primarily in the center of the pad.
l In particular, we have discovered that brazing an inter-1l connect pin to a metallic pad causes the tensile stress occurring l at the edge of a pad to be greatest whenever the brazed joint is j allowed to extend to an edge of the pad.
10 I, 'i 11 '' Consequently, in accordance with the preferred embodiment of the present invention, a braze restricting dielectric layer is I, applied over the bottom surface of the MLC substrate and all the
16 Hence, the electrical resistance of the entire bond between the 17 interconnect pin and t'he pad correspondingly increases.
Furthermore, this technique is very difficult and cumbersome to 19 implement in practice. This technique is described, in connection with a solder bond, in R. W. Roth, "Solder Bond", IBM
21 Technical Disclosure Bulletin, Vol. 17, No. 8, January 1975, page ~2 2214.
24 Hence, a need exists in the art for a method, suitable for use in brazing an interconnect pin to a metallic pad, which 26 will lower the tensile stress between the pad and an adjacent 27 dielectric ~e.g. MLC) substrate, occurring during a brazing 28 operation, while eliminating any need to change the brazing alloy 29 and simultaneously permitting a strong, reliable, minimally Z3e36 l resistive brazed joint to form between the interconnect pin and the pad.
i~SUMMARY OF THE INVENTION -Accordingly, an object of the present invention is to provide a method for use in brazing an interconnect pin to a 7 l portion of a metallization pattern, situated on a brittle 8 i ,¦dielectric substrate, such as an MLC substrate, which produces a llreliable bond between the metallization pattern and the pin.
Il 11 l A particular object is to reduce tensile stress, occurring ilat the interface between a metallic pad and the bottom surface of 13;l an MLC substrate and resulting from brazing, to a value which is less than that required to fracture the substrate.
Another particular object is to eliminate the need to change I the brazing alloy.
9~!
Another particular object is to provide a strong minimally resistive brazed joint between the pad and the pin.
l Another particular object is to increase the mechanical strength of both the MLC substrate and the interface between the pad and the dielectric substrate.
Lastly, another object is to provide a simple method that is easy to implement in a production environment.
2a _9-84-05 These and other objects are achieved in accordance with the teachings of the present invention by limiting the contact of the brazing alloy with the pad such that the brazed joint between the 4~
pin and the pad exists primarily in the center of the pad.
l In particular, we have discovered that brazing an inter-1l connect pin to a metallic pad causes the tensile stress occurring l at the edge of a pad to be greatest whenever the brazed joint is j allowed to extend to an edge of the pad.
10 I, 'i 11 '' Consequently, in accordance with the preferred embodiment of the present invention, a braze restricting dielectric layer is I, applied over the bottom surface of the MLC substrate and all the
14 '! pads prior to applying the brazing alloy. The braze restricting :. 15 ' ;j layer is formed with appropriate annular openings. Each opening covers a closed peripheral portion, generally annularly shaped, of each associated pad. Each opening also provides a closed containment wall, which extends around and above the pad, to hold the brazing alloy. Each circular containment wall is concentrically aligned with its associated pad and exposes an area, of each pad, having a smaller diameter than that of the entire pad. Consequently, when the brazing alloy is applied over the braze restricting layer, this alloy will be restrained by the containment walls from coming into contact with any edge of any of the pads. Thus, the brazed joint for that pad will not extend to the edge of that pad. This advantageously lowers the tensile stress occurring at the interface between the pad and the MLC
substrate to a value, at the edge of the pad, below that required ~36~
1 to fracture the substrate. Advantageously, the main mechanism 2 for interconnect pin failures then becomes the shank of the pin 3 and not the pin/pad interface.
In accordance with a feature of the invention, the braze 6 restricting layer should advantageously be a compressive layer.
7 ISuch a layer is comprised of dielectric material having a lower 8 thermal coefficient of expansion than the MLC substrate. Use of g pa compressive layer, as taught by B. Schwartz "Making High -Strength Ceramics", IBM Technical Disclosure Bulletin, Vol. 11, ;lNo. 7, December 1968, page 848, places the bottom surface of the MLC substrate in a state of compression. Ceramic material is 3 considerably stronger in compression than in tension. Hence, we 4 have found that use of a compressive braze restricting layer partially offsets the tensile stress imparted to the MLC
16 substrate by the braze. Consequently, use of a compressive 17 dielectric braze restricting layer advantageously strengthens the 18 bottom surface of the ceramic substrate and in particular the 19 interface between the pad and the ceramic.
23 The principles of the present invention may be readily 24 understood by considering the following detailed description in conjunction with the drawing, in which:
27 FIG. 1 depicts a cross-sectional view of an 28 interconnect pin bonded to a metallic pad on a dielectric 29 substrate by a technique well known in the art; and 30 ' :
~-84-051 ~.3~
2 FIG. 2 depicts a cross-sectional view of an 3 interconnect pin bonded to a metallic pad on a dielectric 4 substrate in accordance with the teachings of the present invention.
g Applicants' inventive method for brazing an interconnect pin to a region of a metallization pattern is applicable in 11 fabricating any apparatus where a dielectric layer serves as the 12 substrate for the metallization pattern and a thermal expansion 13 mismatch exists at the interface between the metallization 14 pattern and the dielectric layer. For example, such a dielectric layer exists as the bottom layer of a MLC substrate used in a 16 "flip-chip" multi-chip package or as the substrate for a 17 metallization pattern (traces and pads) in a printed circuit 18 board. Hence, to simplify the ensuing discussion, any such 19 dielectric layer will be collectively referred to as a dielectric substrate.
22 FIG. 1 depicts a cross-sectional view of interconnect pin 10 23 brazed to a region of a metallization pattern (illustratively 24 circularly shaped pad 20) situated on a dielectric substrate by a technique well known in the art. Here, as shown, metallic pad 20 26 is first conventionally fabricated on surface 33 of dielectric 27 substrate 30. This surface could be the bottom surface of an MLC
28 substrate. Thereafter, the pad is coated with a metallic 29 protective (diffusion barrier) layer (not shown). This material 9-84-051 ~36~
used for this protective layer is determined by the metallurgies 2 of pad 20 and interconnect pin 10, and the brazing alloy. In 3 order to mount the pin to the pad, both pad 20 and head 12 of pin 4 10 are first completely coated (wetted) with a suitable well-known brazing alloy, then brought into contact with each other 6 'and thereafter brazed. As a result, once brazing has occurred, the brazed joint 13, as shown, extends to edges 25 of pad 20.
8 l g I Unfortunately, this prior art technique produces considerable tensile stress at the edges of the pad. This 11 stress, in turn, may cause the ceramic located directly beneath the pad, i.e. in the vicinity of interface 28 situated between 13 'the pad and the substrate, to fracture. As a result, the 14; interconnect pin and its brazed pad may mechanically separate from the substrate and thereby ruin the integrated circuit package. Specifically, dielectric substrate 30 is rather brittle and has a thermal coefficient of expansion different from that of pad 20. Consequently, a significant thermal expansion 19 coefficient mis-match exists at interface 28 between pad 20 and dielectric substrate 30 which, in turn, places that portion of 21 the dielectric substrate situated directly beneath the pad in 22 istress. This mismatch worsens once the pad is coated with the 23 metallic protective layer and then brazed. As a result, during 24 ,brazing the substrate is placed in considerable tension. The 25~tensile stress is greatest at edges 25 of pad 20. A ceramic 26 Ilayer is weak in tension. Consequently, the tensile stress 27 occurring at an edge of the pad often reaches a level sufficient 28`to fracture the substrate situated beneath the pad.
29 Disadvantageously, this fracturing may cause both interconnect 30`
, 1 .i 9-84-05 1~3~93~
pin 10 and pad 20, to which this pin is brazed, to separate from the substrate.
We have discovered that the tensile stress occurring at the interface between a metallic pad (e.g. pad 20) and a dielectric substrate (e.g. substrate 30), as a result of brazing a interconnect pin to the pad, is greatest whenever the brazed joint (e.g. brazed joint 13) is allowed to extend to an edge of the pad.
11 Consequently, in accordance with the principles of the present invention, we limit the contact of the brazing alloy with a pad such that the brazed joint between a pin and the pad exists primarily in the center of the pad and does not extend to any edges of the pad. In particular, we have found that the tensile ;stress imparted by the brazed joint to a pad, and transmitted ~therethrough to the underlying dielectric substrate, is greatest at the edge of the braze and increases nearly exponentially with distance away from the center of the braze and towards its edge.
Moreover, the stress imparted to the dielectric substrate by the pad itself is greatest at the edges of the pad and also increases nearly exponentially with distance away from the center of the ;pad and towards its edges. Since these stresses add to form the total stress exerted by the pad onto dielectric substrate 20, the brazing alloy need only be kept a small distance away from all the edges of the pad to provide a substantial reduction in tensile stress occurring along the edges (perimeter) of the pad.
This advantageously permits the brazed joint to extend over a significant portion of the pad and thereby form a strong reliable ' '.
:
~s~6 1 contact having minimal electrical resistance while minimizing any 2 additional tensile stress imparted by the brazed joint to the 3 edge of any pad. As a result of our inventive method, the main mechanism for pin failures advantageously becomes the shank of the interconnect pin. These failures can be easily remedied by merely replacing the pin.
FIG. 2 depicts a cross-sectional view of interconnect pin 70 bonded to circularly shaped pad 60 on dielectric substrate 40, in accordance with the teachings of the present invention. Here, as shown, metallic pad 60, similar to pad 20 shown in FIG. 1, is 2 ,bonded to surface 43 of dielectric substrate 40 using any one of 13 many well-known techniques. Braze restricting dielectric layer 14 50 is situated over both dielectric substrate 40 and all the pads located thereon. As explained in detail later, the braze 'restricting layer can be applied either coincident with or 17 subsequent to the fabrication of the dielectric substrate. Layer 18 50 can be any dielectric layer compatible with dielectric 19 substrate 40. However for reasons that will shortly become clear, braze restricting layer 50 should preferably be a 21 compressive layer and, as such, fabricated from a dielectric 22~ material having a lower thermal coefficient of expansion than 23 that of the dielectric substrate.
In addition, braze restricting layer 50 has a number of ; 26 ;circular openings, each of which is concentrically aligned over a corresponding pad. Inasmuch as all the openings are structurally 28 identical, for purposes of simplicity FIG. 2 only shows one such _9-84-05 6~3~3 opening, opening 55, and the following discussion will be limited to specifically discussing opening 55.
In particular, opening 55, has a smaller diameter than that of pad 60. As such, braze restricting layer 50 overlaps a closed annularly shaped peripherally located portion of pad 60 and exposes the remaining centrally located portion of the pad. This annularly shaped over-lapped portion comprises circular edge 65 9 ' , of pad 60 and that peripheral area of the pad contained within an distance "r" measured inward from edge 65. Ideally, if dielectric layer 50 is properly aligned with substrate 40, then the width ("r") of the over-lapped annularly shaped area should be the same all around the pad. However, in practice, the center of opening 55 and the center of pad 60 are likely to be slightly j mis-aligned (offset) with respect to each other, and hence some slight deviations in the width of this annular portion are bound to occur around the periphery of opening 55. As long as these ' deviations are kept small, no adverse results will occur.
21 Opening 55 has walls 58. These walls -- illustratively shown as being inwardly sloping for purposes of illustration but need not be in actuality -- completely encircle opening 55 and form a closed containment vehicle extending around and above pad 60. When the brazing alloy is applied within opening 55 of braze restricting layer 50, this alloy is totally confined within the containment vehicle and is thereby prevented from contacting edges 65 of pad 60. Hence, once head 72 of interconnect pin 70 is brazed to pad 60, brazed joint 73 advantageously does not extend to edges 65 of pad 60. As a result, the stress imparted :
_9-84-05 ~L~3G~36~
to pad 60 by brazed joint 73 does not reach the edges of the pad, where the stress occurring within the pad reaches a relatively large maximum value. Since the stress occurring within pad 60 decreases nearly exponentially as a function of distance away llfrom the edge of the pad and towards its center, a relatively low 6~ stress region within pad 60 begins at a small distance "r" away 7l from edge 65. As such, the total stress, imparted by the lladditive combination of the stress produced by brazed joint 73 and directed through pad 60 and the stress occurring within pad 60 by virtue of the thermal expansion coefficient mis-match between the pad and dielectric substrate 40, advantageously remains below the value required to fracture dielectric substrate 40. This is particularly true at edges 71 of brazed joint 73 ¦ where the stress imparted by the brazed joint reaches a maximum value. In practice, excellent results have been achieved if opening 55 encircles an area that is approximately 80~ of the ; total surface area of pad 60. Clearly, this percentage is not critical; however, to ensure adequate bond strength and minimal electrical contact resistance between interconnect pin 70 and pad 60, this percentage should be kept as high as possible. As such, this percentage will be governed, in part, by the magnitude of , any expected clamping forces that will be applied to the I I interconnect pin.
Moreover, both dielectric substrate 40 and the interface between pad 60 and the substrate can be advantageously strengthened if braze restricting layer 50 is a compressive layer. In particular, if braze restricting layer 50 has a lower thermal coefficient of expansion than the substrate, then this . .
1 a state of compression, thereby partially ofsetting the tensile 2 stress imparted to the substrate by the pad itself and the brazed 3 joint. A suitable compressive layer can be fabricated by 4 slightly altering the composition of the materials used for fabricating dielectric substrate 40 to yield a dielectric 6 material having a lower coefficient of thermal expansion than the 7 substrate.
B
g I The arrangement shown in FIG.2 can be manufactured using any one of three methods: co-fired pad and co-fired braze restricting ll layer, co-fired pad and post-fired braze restricting layer, and 12 post-fired pad and post-fired braze restricting layer.
14 ja. Co-fired Pad and Co-fired Braze Restricting Layer -16 Here, pad 60 can be any metallic pad suitable for a desired 17 dielectric substrate and can be fabricated using a suitable 18 metallic paste which contains appropriate well-known adhesives or 19 other metals which will co-sinter with the substrate.
21 Braze restricting layer 50 is implemented using a "green 22 sheet" made of the same dielectric material as that of the 23 dielectric substrate or preferably, for a compressive effect, a ; 24 dielectric material having a lower thermal expansion coefficient than the material comprising the dielectric substrate. ~11 the 26 openings, e.g. opening 55, in braze restricting layer 50 are 27 formed by appropriately punching out the green sheet. Once all 28 these openings are formed, then they are all filled with a 29 fugitive paste prior to laminating this dielectric layer with 1 other "green sheet" layers comprising dielectric substrate 40 (in 2 the case of an MLC substrate). Thereafter, the laminated 3 structure is sintered. The fugitive paste maintains the annular 4 shape of each opening during lamination and subsequent burnout of the MLC substrate during sintering.
6 ' 7 Ib. Co-fired Pad and Post-fired Braze Restricting Layer -8 ;
9 The pad is essentially the same as that described above in connection with the co-fired pad and co-fired braze restricting 11 layer. However, here, the entire surface of the dielectric 12 substrate, including the pads, is coated with dielectric 13 material, which forms the braze restricting layer, after the 14 dielectric substrate has been fired (sintered). This dielectric
substrate to a value, at the edge of the pad, below that required ~36~
1 to fracture the substrate. Advantageously, the main mechanism 2 for interconnect pin failures then becomes the shank of the pin 3 and not the pin/pad interface.
In accordance with a feature of the invention, the braze 6 restricting layer should advantageously be a compressive layer.
7 ISuch a layer is comprised of dielectric material having a lower 8 thermal coefficient of expansion than the MLC substrate. Use of g pa compressive layer, as taught by B. Schwartz "Making High -Strength Ceramics", IBM Technical Disclosure Bulletin, Vol. 11, ;lNo. 7, December 1968, page 848, places the bottom surface of the MLC substrate in a state of compression. Ceramic material is 3 considerably stronger in compression than in tension. Hence, we 4 have found that use of a compressive braze restricting layer partially offsets the tensile stress imparted to the MLC
16 substrate by the braze. Consequently, use of a compressive 17 dielectric braze restricting layer advantageously strengthens the 18 bottom surface of the ceramic substrate and in particular the 19 interface between the pad and the ceramic.
23 The principles of the present invention may be readily 24 understood by considering the following detailed description in conjunction with the drawing, in which:
27 FIG. 1 depicts a cross-sectional view of an 28 interconnect pin bonded to a metallic pad on a dielectric 29 substrate by a technique well known in the art; and 30 ' :
~-84-051 ~.3~
2 FIG. 2 depicts a cross-sectional view of an 3 interconnect pin bonded to a metallic pad on a dielectric 4 substrate in accordance with the teachings of the present invention.
g Applicants' inventive method for brazing an interconnect pin to a region of a metallization pattern is applicable in 11 fabricating any apparatus where a dielectric layer serves as the 12 substrate for the metallization pattern and a thermal expansion 13 mismatch exists at the interface between the metallization 14 pattern and the dielectric layer. For example, such a dielectric layer exists as the bottom layer of a MLC substrate used in a 16 "flip-chip" multi-chip package or as the substrate for a 17 metallization pattern (traces and pads) in a printed circuit 18 board. Hence, to simplify the ensuing discussion, any such 19 dielectric layer will be collectively referred to as a dielectric substrate.
22 FIG. 1 depicts a cross-sectional view of interconnect pin 10 23 brazed to a region of a metallization pattern (illustratively 24 circularly shaped pad 20) situated on a dielectric substrate by a technique well known in the art. Here, as shown, metallic pad 20 26 is first conventionally fabricated on surface 33 of dielectric 27 substrate 30. This surface could be the bottom surface of an MLC
28 substrate. Thereafter, the pad is coated with a metallic 29 protective (diffusion barrier) layer (not shown). This material 9-84-051 ~36~
used for this protective layer is determined by the metallurgies 2 of pad 20 and interconnect pin 10, and the brazing alloy. In 3 order to mount the pin to the pad, both pad 20 and head 12 of pin 4 10 are first completely coated (wetted) with a suitable well-known brazing alloy, then brought into contact with each other 6 'and thereafter brazed. As a result, once brazing has occurred, the brazed joint 13, as shown, extends to edges 25 of pad 20.
8 l g I Unfortunately, this prior art technique produces considerable tensile stress at the edges of the pad. This 11 stress, in turn, may cause the ceramic located directly beneath the pad, i.e. in the vicinity of interface 28 situated between 13 'the pad and the substrate, to fracture. As a result, the 14; interconnect pin and its brazed pad may mechanically separate from the substrate and thereby ruin the integrated circuit package. Specifically, dielectric substrate 30 is rather brittle and has a thermal coefficient of expansion different from that of pad 20. Consequently, a significant thermal expansion 19 coefficient mis-match exists at interface 28 between pad 20 and dielectric substrate 30 which, in turn, places that portion of 21 the dielectric substrate situated directly beneath the pad in 22 istress. This mismatch worsens once the pad is coated with the 23 metallic protective layer and then brazed. As a result, during 24 ,brazing the substrate is placed in considerable tension. The 25~tensile stress is greatest at edges 25 of pad 20. A ceramic 26 Ilayer is weak in tension. Consequently, the tensile stress 27 occurring at an edge of the pad often reaches a level sufficient 28`to fracture the substrate situated beneath the pad.
29 Disadvantageously, this fracturing may cause both interconnect 30`
, 1 .i 9-84-05 1~3~93~
pin 10 and pad 20, to which this pin is brazed, to separate from the substrate.
We have discovered that the tensile stress occurring at the interface between a metallic pad (e.g. pad 20) and a dielectric substrate (e.g. substrate 30), as a result of brazing a interconnect pin to the pad, is greatest whenever the brazed joint (e.g. brazed joint 13) is allowed to extend to an edge of the pad.
11 Consequently, in accordance with the principles of the present invention, we limit the contact of the brazing alloy with a pad such that the brazed joint between a pin and the pad exists primarily in the center of the pad and does not extend to any edges of the pad. In particular, we have found that the tensile ;stress imparted by the brazed joint to a pad, and transmitted ~therethrough to the underlying dielectric substrate, is greatest at the edge of the braze and increases nearly exponentially with distance away from the center of the braze and towards its edge.
Moreover, the stress imparted to the dielectric substrate by the pad itself is greatest at the edges of the pad and also increases nearly exponentially with distance away from the center of the ;pad and towards its edges. Since these stresses add to form the total stress exerted by the pad onto dielectric substrate 20, the brazing alloy need only be kept a small distance away from all the edges of the pad to provide a substantial reduction in tensile stress occurring along the edges (perimeter) of the pad.
This advantageously permits the brazed joint to extend over a significant portion of the pad and thereby form a strong reliable ' '.
:
~s~6 1 contact having minimal electrical resistance while minimizing any 2 additional tensile stress imparted by the brazed joint to the 3 edge of any pad. As a result of our inventive method, the main mechanism for pin failures advantageously becomes the shank of the interconnect pin. These failures can be easily remedied by merely replacing the pin.
FIG. 2 depicts a cross-sectional view of interconnect pin 70 bonded to circularly shaped pad 60 on dielectric substrate 40, in accordance with the teachings of the present invention. Here, as shown, metallic pad 60, similar to pad 20 shown in FIG. 1, is 2 ,bonded to surface 43 of dielectric substrate 40 using any one of 13 many well-known techniques. Braze restricting dielectric layer 14 50 is situated over both dielectric substrate 40 and all the pads located thereon. As explained in detail later, the braze 'restricting layer can be applied either coincident with or 17 subsequent to the fabrication of the dielectric substrate. Layer 18 50 can be any dielectric layer compatible with dielectric 19 substrate 40. However for reasons that will shortly become clear, braze restricting layer 50 should preferably be a 21 compressive layer and, as such, fabricated from a dielectric 22~ material having a lower thermal coefficient of expansion than 23 that of the dielectric substrate.
In addition, braze restricting layer 50 has a number of ; 26 ;circular openings, each of which is concentrically aligned over a corresponding pad. Inasmuch as all the openings are structurally 28 identical, for purposes of simplicity FIG. 2 only shows one such _9-84-05 6~3~3 opening, opening 55, and the following discussion will be limited to specifically discussing opening 55.
In particular, opening 55, has a smaller diameter than that of pad 60. As such, braze restricting layer 50 overlaps a closed annularly shaped peripherally located portion of pad 60 and exposes the remaining centrally located portion of the pad. This annularly shaped over-lapped portion comprises circular edge 65 9 ' , of pad 60 and that peripheral area of the pad contained within an distance "r" measured inward from edge 65. Ideally, if dielectric layer 50 is properly aligned with substrate 40, then the width ("r") of the over-lapped annularly shaped area should be the same all around the pad. However, in practice, the center of opening 55 and the center of pad 60 are likely to be slightly j mis-aligned (offset) with respect to each other, and hence some slight deviations in the width of this annular portion are bound to occur around the periphery of opening 55. As long as these ' deviations are kept small, no adverse results will occur.
21 Opening 55 has walls 58. These walls -- illustratively shown as being inwardly sloping for purposes of illustration but need not be in actuality -- completely encircle opening 55 and form a closed containment vehicle extending around and above pad 60. When the brazing alloy is applied within opening 55 of braze restricting layer 50, this alloy is totally confined within the containment vehicle and is thereby prevented from contacting edges 65 of pad 60. Hence, once head 72 of interconnect pin 70 is brazed to pad 60, brazed joint 73 advantageously does not extend to edges 65 of pad 60. As a result, the stress imparted :
_9-84-05 ~L~3G~36~
to pad 60 by brazed joint 73 does not reach the edges of the pad, where the stress occurring within the pad reaches a relatively large maximum value. Since the stress occurring within pad 60 decreases nearly exponentially as a function of distance away llfrom the edge of the pad and towards its center, a relatively low 6~ stress region within pad 60 begins at a small distance "r" away 7l from edge 65. As such, the total stress, imparted by the lladditive combination of the stress produced by brazed joint 73 and directed through pad 60 and the stress occurring within pad 60 by virtue of the thermal expansion coefficient mis-match between the pad and dielectric substrate 40, advantageously remains below the value required to fracture dielectric substrate 40. This is particularly true at edges 71 of brazed joint 73 ¦ where the stress imparted by the brazed joint reaches a maximum value. In practice, excellent results have been achieved if opening 55 encircles an area that is approximately 80~ of the ; total surface area of pad 60. Clearly, this percentage is not critical; however, to ensure adequate bond strength and minimal electrical contact resistance between interconnect pin 70 and pad 60, this percentage should be kept as high as possible. As such, this percentage will be governed, in part, by the magnitude of , any expected clamping forces that will be applied to the I I interconnect pin.
Moreover, both dielectric substrate 40 and the interface between pad 60 and the substrate can be advantageously strengthened if braze restricting layer 50 is a compressive layer. In particular, if braze restricting layer 50 has a lower thermal coefficient of expansion than the substrate, then this . .
1 a state of compression, thereby partially ofsetting the tensile 2 stress imparted to the substrate by the pad itself and the brazed 3 joint. A suitable compressive layer can be fabricated by 4 slightly altering the composition of the materials used for fabricating dielectric substrate 40 to yield a dielectric 6 material having a lower coefficient of thermal expansion than the 7 substrate.
B
g I The arrangement shown in FIG.2 can be manufactured using any one of three methods: co-fired pad and co-fired braze restricting ll layer, co-fired pad and post-fired braze restricting layer, and 12 post-fired pad and post-fired braze restricting layer.
14 ja. Co-fired Pad and Co-fired Braze Restricting Layer -16 Here, pad 60 can be any metallic pad suitable for a desired 17 dielectric substrate and can be fabricated using a suitable 18 metallic paste which contains appropriate well-known adhesives or 19 other metals which will co-sinter with the substrate.
21 Braze restricting layer 50 is implemented using a "green 22 sheet" made of the same dielectric material as that of the 23 dielectric substrate or preferably, for a compressive effect, a ; 24 dielectric material having a lower thermal expansion coefficient than the material comprising the dielectric substrate. ~11 the 26 openings, e.g. opening 55, in braze restricting layer 50 are 27 formed by appropriately punching out the green sheet. Once all 28 these openings are formed, then they are all filled with a 29 fugitive paste prior to laminating this dielectric layer with 1 other "green sheet" layers comprising dielectric substrate 40 (in 2 the case of an MLC substrate). Thereafter, the laminated 3 structure is sintered. The fugitive paste maintains the annular 4 shape of each opening during lamination and subsequent burnout of the MLC substrate during sintering.
6 ' 7 Ib. Co-fired Pad and Post-fired Braze Restricting Layer -8 ;
9 The pad is essentially the same as that described above in connection with the co-fired pad and co-fired braze restricting 11 layer. However, here, the entire surface of the dielectric 12 substrate, including the pads, is coated with dielectric 13 material, which forms the braze restricting layer, after the 14 dielectric substrate has been fired (sintered). This dielectric
15 material is then selectively etched away or patterned to produce
16 the openings.
17
18 Specifically, braze restricting layer 50 can be manufactured
19 using any one of several techniques. First, this layer can be sputtered quartz or a glass layer that has been previously 21 deposited, over surface 43 of dielectric substrate 40, by 22 chemical vapor deposition and thereafter etched back from the 23 center of the pads to form all the openings. The braze 24 restricting layer could also be deposited from a re-flowed slurry and then appropriately etched to form all the annular openings.
26 Alternatively, the openings could alternatively be formed, in the 27 re-flowed layer, through patterning. Specifically, a suitable 28 barrier would be placed over the pad, the pad would then be re-29 flowed and thereafter the barrier would be removed. If the 9~$~
1 viscosity of the molten braze restricting layer was sufficiently 2 high, then the barrier would not be needed. Additionally, to 3 increase the strength of the pad and lower its composite thermal 4 expansion coefficient, a metal, such as molybdenum or kovar, having a low coefficient of thermal expansion could also be post-6 fired onto the pad.
8 c. Post-fired Pad and Post-fired sraze restricting Layer -9 .
To apply post-fired pads to the dielectric (MLC) substrate, 11 a number of "green sheet" elements are first laminated together 12 and then fired to form the dielectric substrate. Thereafter, the 13 pads are applied to the substrate using any thin film technique 14 (such as ion plating, magnetron sputtering and the like) which lS provides high adhesion and low stress between the pad and a the 16 dielectric substrate. Inasmuch as the metal used in the pads 17 does not need to co-sinter with the ceramic in the dielectric 18 substrate, the pad can be fabricated out of a variety of alloys 19 such as Ti/Cu/Ni, Ti/Cu/Mo/Ni, Cr/Cu/Ni, Cr/Cu/Mo/Ni and many other metallic combinations. The post-fired braze restricting 21 layer is then fabricated using any of the techniques described 22 above in connection with the co-fired pad and post-fired braze 23 restricting layer.
26 Although a preferred embodiment has been shown and described I-; 27 above, many other embodiments containing the teachings of the 28 present invention can be readily devised by those skilled in the :
29 art.
,
26 Alternatively, the openings could alternatively be formed, in the 27 re-flowed layer, through patterning. Specifically, a suitable 28 barrier would be placed over the pad, the pad would then be re-29 flowed and thereafter the barrier would be removed. If the 9~$~
1 viscosity of the molten braze restricting layer was sufficiently 2 high, then the barrier would not be needed. Additionally, to 3 increase the strength of the pad and lower its composite thermal 4 expansion coefficient, a metal, such as molybdenum or kovar, having a low coefficient of thermal expansion could also be post-6 fired onto the pad.
8 c. Post-fired Pad and Post-fired sraze restricting Layer -9 .
To apply post-fired pads to the dielectric (MLC) substrate, 11 a number of "green sheet" elements are first laminated together 12 and then fired to form the dielectric substrate. Thereafter, the 13 pads are applied to the substrate using any thin film technique 14 (such as ion plating, magnetron sputtering and the like) which lS provides high adhesion and low stress between the pad and a the 16 dielectric substrate. Inasmuch as the metal used in the pads 17 does not need to co-sinter with the ceramic in the dielectric 18 substrate, the pad can be fabricated out of a variety of alloys 19 such as Ti/Cu/Ni, Ti/Cu/Mo/Ni, Cr/Cu/Ni, Cr/Cu/Mo/Ni and many other metallic combinations. The post-fired braze restricting 21 layer is then fabricated using any of the techniques described 22 above in connection with the co-fired pad and post-fired braze 23 restricting layer.
26 Although a preferred embodiment has been shown and described I-; 27 above, many other embodiments containing the teachings of the 28 present invention can be readily devised by those skilled in the :
29 art.
,
Claims (13)
1. In a method for brazing interconnect pins to metallic pads, each pad situated within a pattern of conductive metallurgy formed on a surface of a dielectric substrate, the improvement comprising the steps of:
forming a dielectric layer on the surface of said substrate, said dielectric layer having a lower coefficient of thermal expansion than that of said substrate and comprising a plurality of openings, wherein each of said openings is concentrically aligned with a corresponding pad and is smaller than the corresponding pad so as to overlap a closed peripheral portion thereof and thereby define a closed wall to contain brazing material such that brazing material is prevented from contacting an edge of the corresponding pad in order to reduce the stress occuring at an interface between the pad and the substrate;
seating a head of an interconnect pin in a corresponding one of said openings; and bonding the head of said pin to said pad by the brazing material contained within said closed wall.
forming a dielectric layer on the surface of said substrate, said dielectric layer having a lower coefficient of thermal expansion than that of said substrate and comprising a plurality of openings, wherein each of said openings is concentrically aligned with a corresponding pad and is smaller than the corresponding pad so as to overlap a closed peripheral portion thereof and thereby define a closed wall to contain brazing material such that brazing material is prevented from contacting an edge of the corresponding pad in order to reduce the stress occuring at an interface between the pad and the substrate;
seating a head of an interconnect pin in a corresponding one of said openings; and bonding the head of said pin to said pad by the brazing material contained within said closed wall.
2. The method of claim 1 wherein the forming step includes the step of aligning the dielectric layer with the dielectric substrate such that the dielectric layer overlaps a peripheral annularly shaped portion of said corresponding pad and exposes a central portion of said corresponding pad.
3. The method of claim 2 wherein the forming step comprises the steps of:
forming a multi-layered laminated structure comprising at least a first green sheet element to form said dielectric substrate, a layer of conductive paste defining said pattern of conductive metallurgy, and a second green sheet element impregnated with said dielectric material to form said dielectric layer; and sintering said laminated structure.
forming a multi-layered laminated structure comprising at least a first green sheet element to form said dielectric substrate, a layer of conductive paste defining said pattern of conductive metallurgy, and a second green sheet element impregnated with said dielectric material to form said dielectric layer; and sintering said laminated structure.
4. The method of claim 3 wherein the forming step includes the steps of:
removing material from said second green sheet to form said plurality of openings, and filling said openings with a fugitive paste prior to laminating said second green sheet to another layer and sintering said laminated structure.
removing material from said second green sheet to form said plurality of openings, and filling said openings with a fugitive paste prior to laminating said second green sheet to another layer and sintering said laminated structure.
5. The method of claim 2 further including the steps of:
forming a multi-layered laminated structure comprising at least a first green sheet element to form said dielectric substrate and a layer of conductive paste to define said pattern of conductive metallurgy;
sintering said laminated structure;
depositing the dielectric material over a surface of said laminated structure to define said dielectric layer;
and removing selected portions of said dielectric layer, subsequent to sintering, in order to define said plurality of openings.
forming a multi-layered laminated structure comprising at least a first green sheet element to form said dielectric substrate and a layer of conductive paste to define said pattern of conductive metallurgy;
sintering said laminated structure;
depositing the dielectric material over a surface of said laminated structure to define said dielectric layer;
and removing selected portions of said dielectric layer, subsequent to sintering, in order to define said plurality of openings.
6. The method of claim 5 wherein said selected portions are removed either through patterning or etching.
7. The method of claim 6 wherein said forming step further includes the step of post-firing a protective metallic layer onto said pad prior to brazing said pin to said pad.
8. The method of claim 7 wherein said forming step further includes the step of post-firing a metallic layer onto said pad wherein said metallic layer has a lower thermal coefficient of expansion than that of said pad.
9. The method of claim 2 wherein the forming step comprises the steps of:
firing at least a first green sheet element to form said dielectric substrate, applying said pattern of conductive metallurgy over said first fired green sheet element, depositing the dielectric material over said pattern and said first fired green sheet element to define said dielectric layer; and removing selected portions of said dielectric layer, in order to define said plurality of openings.
firing at least a first green sheet element to form said dielectric substrate, applying said pattern of conductive metallurgy over said first fired green sheet element, depositing the dielectric material over said pattern and said first fired green sheet element to define said dielectric layer; and removing selected portions of said dielectric layer, in order to define said plurality of openings.
10. The method of claim 9 wherein said selected portions are removed either through patterning or etching.
11. In an integrated circuit package wherein an interconnect pin is brazed to a metallic pad located on a dielectric substrate and situated within a pattern of conductive metallurgy formed on a surface of the dielectric substrate, the improvement comprising:
a dielectric layer, situated on the surface of the substrate and above said pattern, said dielectric layer having an opening wherein said opening is concentrically aligned with the pad and is smaller than the pad so as to overlap a closed peripheral portion thereof and thereby define a closed wall to contain brazing material;
a head of an interconnect pin situated in said opening; and a brazed bond between the head of said pin and said pad wherein said brazing material is contained within said closed wall.
a dielectric layer, situated on the surface of the substrate and above said pattern, said dielectric layer having an opening wherein said opening is concentrically aligned with the pad and is smaller than the pad so as to overlap a closed peripheral portion thereof and thereby define a closed wall to contain brazing material;
a head of an interconnect pin situated in said opening; and a brazed bond between the head of said pin and said pad wherein said brazing material is contained within said closed wall.
12. The improvement in claim 11 wherein the dielectric layer has a lower coefficient of thermal expansion than that of said dielectric substrate.
13. The improvement in claim 12 wherein the dielectric layer is aligned with the dielectric substrate such the opening overlaps a peripheral annularly shaped portion of the pad and exposes a central portion thereof.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US721,885 | 1976-09-09 | ||
| US06/721,885 US4672739A (en) | 1985-04-11 | 1985-04-11 | Method for use in brazing an interconnect pin to a metallization pattern situated on a brittle dielectric substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1236930A true CA1236930A (en) | 1988-05-17 |
Family
ID=24899716
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000504664A Expired CA1236930A (en) | 1985-04-11 | 1986-03-20 | Method for use in brazing an interconnect pin to a metallization pattern situated on a brittle dielectric |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US4672739A (en) |
| EP (1) | EP0198354B1 (en) |
| JP (1) | JPS61236148A (en) |
| CA (1) | CA1236930A (en) |
| DE (1) | DE3673850D1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4755631A (en) * | 1985-04-11 | 1988-07-05 | International Business Machines Corporation | Apparatus for providing an electrical connection to a metallic pad situated on a brittle dielectric substrate |
| US4756696A (en) * | 1985-12-06 | 1988-07-12 | Amp Incorporated | Solder joint inspection feature for surface mount connectors |
| US4970570A (en) * | 1986-10-28 | 1990-11-13 | International Business Machines Corporation | Use of tapered head pin design to improve the stress distribution in the braze joint |
| JP2573225B2 (en) * | 1987-02-10 | 1997-01-22 | 株式会社東芝 | Electronic component manufacturing method |
| DE68904214T2 (en) * | 1988-03-04 | 1993-05-19 | Toshiba Kawasaki Kk | HARD-LOCKING PASTE FOR CONNECTING METALS AND CERAMIC MATERIALS. |
| JPH0632367B2 (en) * | 1989-01-24 | 1994-04-27 | 富士通株式会社 | Method for forming I / O pad of ceramic substrate |
| JPH02304958A (en) * | 1989-05-19 | 1990-12-18 | Hitachi Ltd | Electronic circuit device |
| JP2514910Y2 (en) * | 1990-11-28 | 1996-10-23 | 京セラ株式会社 | Package for storing semiconductor devices |
| US5213877A (en) * | 1991-05-02 | 1993-05-25 | Mitsubishi Materials Corporation | Ceramic substrate used for fabricating electric or electronic circuit |
| US5483105A (en) * | 1994-04-25 | 1996-01-09 | International Business Machines Corporation | Module input-output pad having stepped set-back |
| JP3226752B2 (en) * | 1995-04-12 | 2001-11-05 | 株式会社東芝 | Method for manufacturing semiconductor device |
| US6555757B2 (en) * | 2000-04-10 | 2003-04-29 | Ngk Spark Plug Co., Ltd. | Pin solder jointed to a resin substrate, made having a predetermined hardness and dimensions |
| US20060182939A1 (en) * | 2005-02-11 | 2006-08-17 | Motorola, Inc. | Method and arrangement forming a solder mask on a ceramic module |
| JP5671237B2 (en) * | 2009-01-15 | 2015-02-18 | 日本特殊陶業株式会社 | Semiconductor device inspection substrate |
| TWI387420B (en) * | 2010-06-18 | 2013-02-21 | Askey Computer Corp | Edge-orientating soldering structure and method of preventing shift of pin |
| US9984960B2 (en) * | 2016-07-21 | 2018-05-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated fan-out package and method of fabricating the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3770529A (en) * | 1970-08-25 | 1973-11-06 | Ibm | Method of fabricating multilayer circuits |
| US3839727A (en) * | 1973-06-25 | 1974-10-01 | Ibm | Semiconductor chip to substrate solder bond using a locally dispersed, ternary intermetallic compound |
| JPS5851425B2 (en) * | 1975-08-22 | 1983-11-16 | 株式会社日立製作所 | Hand tie souchi |
| US4176443A (en) * | 1977-03-08 | 1979-12-04 | Sgs-Ates Componenti Elettronici S.P.A. | Method of connecting semiconductor structure to external circuits |
| DE2724641C2 (en) * | 1977-06-01 | 1986-04-03 | Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt | Process for applying soldering to gold layers |
| US4301324A (en) * | 1978-02-06 | 1981-11-17 | International Business Machines Corporation | Glass-ceramic structures and sintered multilayer substrates thereof with circuit patterns of gold, silver or copper |
| US4418857A (en) * | 1980-12-31 | 1983-12-06 | International Business Machines Corp. | High melting point process for Au:Sn:80:20 brazing alloy for chip carriers |
| US4434434A (en) * | 1981-03-30 | 1984-02-28 | International Business Machines Corporation | Solder mound formation on substrates |
| JPS5892242A (en) * | 1981-11-27 | 1983-06-01 | Mitsubishi Electric Corp | Ceramic multi-layer substrate |
| JPS58154293A (en) * | 1982-03-10 | 1983-09-13 | 株式会社日立製作所 | Method of stabilizing size of green sheet |
| JPS58191452A (en) * | 1982-05-06 | 1983-11-08 | Ngk Spark Plug Co Ltd | Ceramic ic package and manufacture thereof |
| JPS59211253A (en) * | 1983-05-17 | 1984-11-30 | Matsushita Electronics Corp | Electronic part package |
-
1985
- 1985-04-11 US US06/721,885 patent/US4672739A/en not_active Expired - Lifetime
-
1986
- 1986-03-11 JP JP61051603A patent/JPS61236148A/en active Pending
- 1986-03-20 CA CA000504664A patent/CA1236930A/en not_active Expired
- 1986-04-04 DE DE8686104601T patent/DE3673850D1/en not_active Expired - Fee Related
- 1986-04-04 EP EP86104601A patent/EP0198354B1/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| EP0198354A3 (en) | 1987-12-02 |
| DE3673850D1 (en) | 1990-10-11 |
| JPS61236148A (en) | 1986-10-21 |
| EP0198354A2 (en) | 1986-10-22 |
| US4672739A (en) | 1987-06-16 |
| EP0198354B1 (en) | 1990-09-05 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |