CA1236943A - Method and apparatus for controlling digital voice recording and playback over telephone lines and adapted for use with standard host computers - Google Patents

Abstract

ABSTRACT

A method of enabling the efficient use of any host computer with a voice message processing apparatus using a telephone interface and voice processing system, that comprises, providing a universal supervisory circuit between the host computer and the telephone interface and voice processing system, said circuit having a memory that stores data of a type useful to interface with said telephone and voice processing interface system, said circuit performing the steps of receiving standard serial data from any host computer such as telephone answering, voice message storing and other commands; storing in said supervisory circuit memory particular serial data commands tailored to command and control the telephone interface and voice processing system; using said data stored in the memory to translate said received standard serial data from the host computer into command and control language recognizable by the telephone interface and voice processing system; converting the translated language into parallel data; and prioritizing the application of said parallel data to said telephone interface and voice processing system for efficient transmission to the telephone interface system; the said telephone interface and voice processing system generating parallel data, such as line-ringing and other status data, translated by said supervisory circuit into standard serial data recognizable by the host computer; and prioritizing the transmission of the last-named standard serial data to the host computer.

Description

i~236943 METHOD AND APPARATUS FOR CONTROLLING DIGITAL VOICE
RECORDING AND PLAYBACK OVER TELEPHONE LINES AND ADAPTED
FOR USE WITH STANDARD HOST COMPUTERS
The present invention relates to a method for controlling digital audio recording and playback aystem~ designed for connection to telephone line, being more partioular1y directed to a controller or ~upervi~or used in connection with a hot computer, a telephone interface system and a voice proceasing system for receiving and 3ending digitized recording from over a telephone line.
Recording and playbaok of voice mea~ages is often u3eful in bu~ine~s applioations. this oapability i8 useful for order entry systems, for diotation for subsequent tran3cription, for obtaining spoken output from a oomputer data base, or simply to take the plaoe of written oommunioations in the transmittal of information. Numerous method have been proposed to satisfy this need. The present invention relates only to digital voioe messaging systems.
In the reoording mode, the digital voioe system auch a shown in U.S. Patent 4,371,752, first produoes a digital signal whioh represent the audio message signal; this stream of digital data it then reoorded on a digital memory, suoh as a magnetio disk recorder ("Winchester" disk).
In the playbaok mode, the Winohester disk is aoce~aed for a partioular message, the message ia oonverted into a atream of digital data whioh it, in turn, oonverted to an audio signal. Beoauae suoh a system operates at very high speed, up to 32 lines of reoording and playbaok oan be simultaneously aooommodated without the introduotion of delays whioh are peroeptible to the users.
A oommon ~ouroe of audio messages for reoording and a common method of accessing messages for playback it a telephone line.

.~.,.

pg/

The lines may be part of the public switched telephone network or they may be a part of a business telephone system under the control of a private branch exchange (PBX) in the business premise. However, prior systems required a custom or specific dedicated host computer, directly connected by a parallel bus device to all input/output, processing and memory hardware to provide the needed operational speed discussed above. Changes in the system, such as necessitated by increased message mode on the system, that would require a change in the capacity or type of hot computer, could therefore not be-accomplished without redesigning the entire system, or at least the internal communications bue system, to satisfy the communications protocol of the new computer. Additionally, the dedicated custom oomputer of prior bundle systems may lack flexibility to handle other processing needs and may not be suitable for the general needs or other needs of the user as well as expanded voice messaging needs.
The present invention relates to an unbundled system, whereby any host computer can be oonnected to the telephone lines and the voice storage and playback means and may be controlled by outside means (usually by a host oomputer) to provide a system which can be used for the purposes described above and other purposes. Such unbundling, or severing of the bus-connected custom system would normally entail a lost of efficiency and speed. However, the prevent invention provides for a general purpose host computer to be easily connected to a standary telephone line interface and a standard voice pg/

~236943 processing system without sacrificing speed or efficiency. Such connection is facilitated by a novel electronic communications supervisor that provides distributed processing from the host computer and allows for the utilization of any standard host computer as a voice messaging system controller, without substantial system re-design to facilitate changes in the computer.
herefore, it is an object of the present invention to provide a novel electronic communications supervisor for connection to a host computer, telephone line interfa¢e system and voice processing system that is not subject to prior limitations but instead allows for any standard host oomputer to be used as a voice messaging controller without 1088 of speed or efficiency.
Another object is to provide a novel electronic communications supervisor that provides distributed processing control functions to release the host oomputer from such functions.
Other and further objeots will be explained hereinafter and are more partioularly delineated in the appended claims.
In summary, from one of its important applications, the invention embraces an eleotronic oommunications supervisor for controlling digital recording and playback of voice messages for connection to a telephone line interface, a voice processor and a host computer, having, in combination, electronio digital signal processing means for oontrolling the operation of the supervisor; parallel means for reoeiving and transmitting digital control signals between the telephone interfaoe and said eleotronio digital signal processing means to provide aooess to the telephone lines for voice messages;
parallel means for receiving and transmitting digital control signals, pg/J~

~236943 for controlling voice messages, between the voice proce3sor and said electronic digital signal processing means, analog audio lines for transmitting voice messages between the telephone line interface and the voice processor under control of the electronic digital signal processing means; audio processing means associated with the voice processor for converting said voice message into the digital data signals representing voice messages and from digital data signals representing voice messages into voice messages, digital memory means controlled by said electronic digital signal processing means for storing said digital control signals, digital memory means controlled by said voice processor for storing digital data representations of the voice messages; means for storing in said memory means said digital representations of the voice messages from said voice processor; and serial means for receiving and transmitting digital control signals and said signals between the host computer and the electronic digital signal processing means. Other inventive features and preferred constructional details are hereinafter described.
The invention will now be described with reference to the accompanying drawings:
Fig. 1 of which is a schematic drawing of a voice messaging system having a universal supervisor circuit connected to a host computer, a telephone line interface and a voice processing system;
Fig. 2 is a more detailed schematic, similar to Fig. 1, ehowing the universal supervisor circuit of the present inven-tion;

pg/~c ~236943 Fig. 3 it a flow chart of a ctandard proce~ing routine used by the supervi~or~ and Fig. 4 how a direct memory access in the supervisor to facilitate the transfer of digitized voice me~age~ or long command to and from the hot computer.
Figs 5a-5g are the sohematio drawing of a preferred circuit of the present invention.
Referring now to Fig. 1, a voice messaging system l having a host oomputer 2 i8 ¢onneoted to a universal supervisor circuit 3 by serial communication lines 4; the supervisor circuit 3 is connected, in turn by a parallel bus communioation line 5 to a telephone interfaoe system (TIS) 6 and by a parallel bus oommunication line 7 to a voice prooessing system (VPS) 8 with ascociated Winchester disk 9.
In the typioal applioation, up to 32 telephone lines 10 are conneoted to the TIS 6 whioh it conneoted to up to 32 audio signal line ll to the VPS 8 as will be desoribed in more detail hereinafter.
The hot oomputer 2 may be any type of machine whioh oan exohange information using a standard serial protoool, such as RS
232-C, an attribute of almost all oomputers. the host computer 2 operates using a program whioh it designed to handle the partioular applioation for whioh the system is intended. lhe supervisor 3 will store oommand~ from the host oomputer 2 and command tailored to oommand and oontrol the TIS 6 and VPS 8 and translate such commands and data into a command and control language recognizable by the TIS 6 and VPS 8 and oonvert the translated language into parallel data signals as will be desoribed in detail hereinafter.

Pg/
_ 5 _ he TIS 6 provides a telephone line connection which meets the requirements of the Federal Commiunications Commiasion designed to protect the public switched network such a the model 50 sold by VoiceTek Corporation, Newton Massachusetts. me IS 6 contains no 'intelligence'; it simply serves to answer the telephone line 10 when the telephone line 10 calls for aervice (for instance, by imposing a ringing signal) by providing an audio path along lines 11 to the voice processing system 8. It is alao capable of collecting and providing various signals to the telephone lines 10 provided by or required by a switched network, such as a POX or Central Office, to establish and maintain such an audio path. me nature of these signals depends on the type of telephone lines; for the simplest type of line, a subscriber loop for instance, the telephone interface system 6 answers a ring by providing a low DC resistance across the line 10. The switched network interpret this as an "off hook" condition; that is, someone has answered the telephone. The ringing signal i9 tripped off the line at the switched network's central office or PBX and an audio connection may proceed. All of these actions on the part of the telephone interface system 6 are controlled by the host computer 2, as such status data repr6senting actions are sent between the TIS 6 and the host computer 2, however none are initiated by the telephone interface system 6 itself.
me voice processing system 8, such as the model 30 sold by VoiceTek Corporation, may have considerable internal 'inteIligence' related to the processing of the analog audio signals carried on line 11 and digital signals but it also relies on control signals, such as those sent in standard serial data format from the host computer 2, to function; it must be told whioh line 11 to service, whether the service involves recording or playing baok a message; and identifioation of the message itself by the host computer.
The supervisor oircuit 3 handles~the interface between the telephone interface system 6, the voice prooesaing system 8 and the host computer 2. The supervisor 3 also providec a oonsiderable intelligence whioh would otherwise require extensive programming at the host oomputer 2, thereby freeing the hot for dealing with the application.
The heart of the control system of the voice messaging system 1 is the supervisor 3. In order to understand its operation and the advantages of using this equipment one must consider the requirements of the communications linkc between the supervisor 3 and the other parts of the system 1.
The host computerls 2 universal method of communication is through the standard serial data RS 232-C serial protocol shown at communioation lines 4. To aend or reoeive information the computer 2 generates or expects to receive a 'text string', that is a series of digital pulses on it RS 232-C transmit or receive line which may be encoded as a series of ASCII (American Standard Code for Information Interchange) characters, such standard serial data would include signals oontrolling telephone answering, voice message storing and other commands as described below.
The telephone interface system 6 receives and sends information by using a "bus" structure designated at 5. The bus 5 is a set of parallel eleotrical lines on which a set of voltages may be ;~: impressed by the telephone interface systems 6 to send information ~:~ pg/

I, ~236943 or by the supervisor 3 for reoeption by the telephone interface ay~tem 6. As with standard bus struotures, the meaning of a given 3et of voltages on the bua 5 it unique to the particular telephone interface system 6 involved and is not oovered by any atandard protocol.
Additionally, the voice processing system 8 communicates by using a parallel bus in the same way as the telephone interface ayatem 6.
Thus one function of the supervisor 3 is to translate the RS
232-C commands ganerated by the hoat computer 2 into the appropriate form for oommunicating with the parallel bus 5 or 7 of either the telephone interface system 6 or the voice processing system 8, respeotively. m e supervisor 3 must also take the digital information generated by the telephone interface system 6 and the voice processing system 8 from their parallel busses 5 and 7 and translate that digital information into RS 232-C standard serial data charaoter strings for tranamittal to the host computer 2. The ability of the supervisor 3 to perform these tasks allows the system 1 to be used with any host computer 2, thereby greatly increasing the applicationa utility of the host computer 2.

Both the telephone interface system (TIS) 6 and the voice processing system (VPS) 8 use the parallel bus system for communication because it is mush faster than the serial system used for communication between the supervisor 3 and the host computer 2.
m e advantages of this speed are retained by using the supervisor 3, which can accumulate communications to and from the telephone interfaoe system 6 and the voioe processing system 8 and process ~;~ pg/

I-;

~36943 them when time i9 available. The supervisor 3 also stores particular serial data commands tailored to command and control the IS 6 and VPS
8, as described in more detail hereinafter lwo other important and let obvious ta~k~ can be supported by the supervisor 3s timing oircuits and di~k-to-disk transfer of information.
The protocol for handling telephone interface often involves the use of 'timeouts'. That is, the system 1 expects certain responses from the calling party; the calling party it given a limited (but generous) amount of time to provide these responses. If they are not forthcoming the system 1 must react, typically by providing a spoken prompt requesting the response or terminating the transaction by hanging up. Suoh timeouts are required beoause the aystem would otherwise beoome oompletely inoperable as lines remained open waiting for a response whioh never oomes. Timeouts are usually provided by the hoat oomputer 2. The use of the supervisor 3 allow the timeout operations to be preformed by the supervisor 3, thus relieving the host oomputer 2 of the programing required and speeding up the operation of the system 1.
m e supervisor 3 also makes a oonvenient pathway for passing information on the voice reoording disks 9 to the host computer 2 and of receiving information from the computer 2. This funotion is useful beoause it allows the voioe messages on the voioe recording disks 9 to be copied or 'baoked up' on the host computer's 2 disks (not shown).
Thus if a failure ooours in one of the voioe recording disks 9, the disk can be repaired and the information whioh was on it replaced _ 9 _ it from the host computer 2.
Finally, the superv$sor 3 is a ¢onvenient plaoe to generate various tones which are sometimes ~neoesaary in telephone oommunications; for instrance a busy tone, ringing tone, dial tone, and 80 forth. these tones are audio signals whioh the supervisor 3 can direct to the telephone interface aystem 6 and place on one of the telephone lines 10 instead of by requiring communication with the voice prooessing system 8.

Fig. 2 shows a detailed block diagram of the supervisor 3 similar to fig. 1, with like numerals designating like parts. For clarity, Fig. 2 omit control and addressing lines. As previously stated, supervisor 3 oontrols the ex¢hange of information between the host ¢omputer 2, the voi¢e processing system (VPS) 8 and the telephone interfa¢e system (TIS) 6 through the use of a mi¢roprocessor 12 operating under ¢ontrol of a program resident in read-only memory (ROM) 13.
Within the supervisor 3, digital information is passed from one part of the supervisor 3 to another by a ¢entral data bus l ¢ontrol of whioh is maintained by the mioroprocessor 12. Access to the bus 14 by the supervisor 3 auxiliary oomponents is made possible by enabling the bus oonneotors O 15. Thus, for instance, when the microprooessor 12 wishes to read the next instruotion in the program maintained in ROM 13, the bus oonneotor 15 between the mioroprocessor 12 and the ¢entral data bus 14 is enabled and the bus ¢onnector 15 between the ROM 13 and the ¢entral data bus 14 is enabled. The ROM 13 is then addressed at the location of the next instruction, places pg/

the instruction on the data bus 14~ and the microprocessor 12 can then read the instruction Prom the central data buy 14.
The microprocessor 12 may be any ox a number of devices such a9 the 8-bit Z80A; 16 or even 32-bit devioes may also be used to increase speed ox operation. The central data buy 14 will have 8 lines if any 8-bit processor is used; in such a case a good choice for a bus connector 15 when information must be passed in both directions is the LS245 device. To store the operating program for the ~y~tem, a suitable ROM 13 for the Z80A microprocessor is the 2732 or 27128 device.

Communication with the host computer 2 takes place over an RS 232-C line 4 which includes a receive line 16, a transmit line 17 and control lines 18. m ese lines 16-18 are connected to a universal asynchronous receiver/transmitter (UART) 19 which, under the control ox the microprocessor 12, will either take a character from the central data bus 14 and send it to the host computer 2 or accept a character from the host computer 2 and place it on the central data bus 14. If the Z80A is used as the microprocessor 12, a good choice for the UART 19 is the Z80A SIO/O device Communication with the VPS 8 takes place directly over the central data bus 14, assisted by control lines not shown in Fig. 2, when a VPS 8 such as the VoiceTek model 30 is used. The model 30 expect an 8-bit command on its data bus or supplies an ô-bit response on its data bus, and thus can be oonnected directly to the central data bus 14 when an 8-bit bus is used. Note, however, that these 8-bit codes are not necessarily representable a ASCII charac-ters;

pg/
it - 11 -:1236~43 they may take any form which it oonvenient.
Commun~¢ation with the TIS 6 it a little more involved when a TIS 6 such as the VoiceTek model 50 it used, since the model 50 expect to receive and supply information over a large number of lines; an internal TIS interface (ITI) 20 ia therefore neceaaary to translate between digital information signals which can be placed on the 8-bit central data buy 14 and oommand/atatus data signal input lines of bus 5 of the model 50 TIS 6. The model 50 TIS 6 alto requires the supervisor 3 to supply a set of telephone signaling tones: a dial tone, busy tone, rign, tone, and valid tone. A tone generator 21, coupled to the ITI 20 in the supervisor 3, provide these tones on command of the central microproce3sor 12 (the command ia pasaed through the ITI 20) to the TIS 6 over tone line bus 22 when required by the host computer 2.
Finally the microprocessor 12 may address the various components of the superviaor 3 through a conventional address bus 23.
Address information is decoded by a conventional decoder 24 and placed on lines 25 to various componenta of the aupervisor 3 using any conventional technique. A random access memory or RAM 26 is also required by the aupervisor 3 to handle intermediate storage of commanda and other information, such as serial data commands tailored to command and control the TIS 6 and VPS 8, as described below. When the Z80A microproceaaor 12 is used, the RAM 26 is made up of several 6264 chips or other RAM devices. Thus under the control of the host computer 2, voice messagea may be exchanged between the voice proceaaing system and telephone linea 10 by way of the TIS 6 and audio lines 11.

pg/
_ ~2 -.

~236943 The operation of the ~upervi~ory circuit 3 can best be understood by understanding the operation of the resident program, which prioritize the application of the parallel data signals to the TIS 6 and VPS 8, shown in simplified form in Fig. 3. The prioritizing of the parallel data provides efficient transmission to the TIS 6 and VPS 8, with the TIS 6 and VPS 8 generating parallel data such an line-ringing and other status data whioh it tran31ated by the supervisor 3 into standard serial data, as described previously, recognizable by the host ¢omputer 2. The supervisor 3 also prioritizes the transmission of the standard serial data to the host computer 2, as will be desoribed in more detail hereinafter.
Referring now to Fig. 3, upon powerup 27, the program directs a diagnostio cheok of the circuitry 28. Upon successful completion of the diagnostic check, the program directs a check on which of the telephone lines are active 29.
The VoiceTek Model 50 TIS 6, for instance, can be configured to interface with from 2 to 32 telephone lines 10 (in multiples of

2). The superviaor 3, as used with the model 50 TIS 6, therefore expects that up to 32 lines may be active. my sequentially polling the status of each line, the grogram determines if the line 10 position is active. As a result of the phone line map check 29 the program creates a table or "map" of the configuration of the TIS 6 which it places in RAM 26.
Upon completion of the TIS 6 map at 29, the program begins a loop, which, with the exception of certain interruptions (described below), will continue indefinitely. This loop may be set up in a number of different ways to service the tasks which must be performed;

pg/

~Z36943 different methods of programming the loop will address the same tasks, but will address them more or lets frequently depending on the details of the program. The system described in Fig. 3 is an example of a loop which works well with the VoioeTek Model 50 TIS 6 and VoiceTek Model 30 VPS 8.
The program polls each of the aotive telephone lines in turn, performing several tasks at each stop. then, before returning to poll the first telephone line again, the program will perform several other tasks. Typically each polling step will require lO0 mioroseconds; if the full compliment of 32 telephone lines is to be services, the entire loop will therefore take 4 millisecond. Thus some tasks are performed relatively often (every lO0 microseconds) and some tasks are performed lesa often (every 4 millisecond). By ohoosing the correct mix Or frequently performed tasks and less frequently performed tasks, system performance can be optimized.
When the program begins by polling the first active telephone line lO at 30, it first performs the task of transmitting waiting messages to the host computer 2 at 31. (Both the VPS 8 and the TIS 6 generate messages for the host computer 2). All communication from the VPS 8 to the supervisor 3 is accomplished by the introduction of an interrupt. The interrupt oauses the program to break out of the loop shown in jig. 3 between steps 30 and 36 and to exeoute a routine whioh serves the VPS 8 and then returns oontrol to the program of Fig. 3 at whatever point the interrupt broke in. This routine oauses the mioroprooessor 12 to read the message from the VPS
I, translate it into a text string for transmittal to the host computer 2, and store the message in RAM 26.

pg/

~236943 he TIS 6 alto generates mes~agea for the hoRt computer 2, for instance messages relating to the ~tatua of varioua timers and messages relating to the statua of the telephone linea 10 (aee below). In the normal course of the polling program, these messages are tranalated into text atringa and pla¢ed in RAM 26 awaiting transmission to the host computer 2, along with the messages from the VPS 8.
All VPS 8 and TIS 6 messages for the host computer 2 are maintained in a RAM 26 area called the "hoat command queue." At this point in the polling program, the first character waiting in the queue, if any, is sent to the host computer 2. ( m e next and subsequent characters are aent upon the next and aubaequent iteration of the polling program).

pg/

. .
,~

/~

Some memory space is assiF~ne-l in the R~r~ 2~ to pro-vide registers for maintaining times. ugh timing reels-ters are controlled by a tirnin~ routine 32. In a typical applicatlon, three resisters are assi~rle(l to each llne, thus up to 32 x 3 = 96 timers or "clocks" are avaiIable in the supervisor 3.
These resister clocks are controlled by a master clock. Since the tlmes of interest ror control ore never controlled with greater preclsion than a c tenths Or a second, the master cliock has a very on period, typically 30 mllliseconds. Thus the prosrarn generally cycles through several polll~¢ cycles withln a sin-rle master clock cycle.
The rnaster clock is used to once a chafe ox state ln a one-bit register each cycle. The re~¢ister clocks are updated by the program, which looks at t}le one~blt nets ter and determines lf it has chanted its state slice the last iterative Pass. If lt has, the ~ro~raln increments the contents of the three roisters which are timing actlvltles for the phone line l whlcll the program Is currently serviclng. The re~istPr clocks m~2y ye use-l or varlous purposes, depending upon the a~licatlon.

~236943 In a typlcal application, the first clock is reset and begins running when a request or service on the phone line 10 is answered, that is, wherl the line 10 goes off-hook. It is reset upon any subsequent comrnand activity on the line 10~ It thus times perlods Or inactivity. After incrementing the first clock, the program will read the reglster and report to the host computer 2 each time the reglster has recorded some establis~led increment Or time, for instance ten minutes. If thus warns the host computer that an unreasonable arnount Or ti!ne has passed wlthout actlvity on the llne and the transactiorl si~ould probably be terminated.
The second clock ls reset an updated when a request for servlce on the phone line 10 is answered, that is, when the line woes off-hook. It continues to record time until the calling party has suppliod appropriate in-orma-tion, as by touch-tone signals (typically his subscrlber number and the code designatln~ the type service the customer wants). After incrementln~ the clock the nro-gram reads the resister and lr the requlred inror~ation does not appear within some preset tl1ne tsaY thlrt~

seconds),the program inrorms tlle host computer 2, which t ~Z36943 /~

can then inltiate a voice message prompt for the missir~information or hang up the line 10.
The third clock controls the lnterval duff which one Or the telephone si~nalin~ tones ls placed on the llne 10 at the command Or the host corrputer 2. Thus lr the host computer 2 requests the placement of a "beep!' on the line 10, the tone generator 21 for the beep will be actuated and the third clock will be reset and updated.
The program will read the register arter each incrernent until the preset tlme for the "beep" elapses; the pro.~ram will then turn the tone off.
All communication from the host computer 2 to the supervisor 3 ls accompllshed by the lntroduction of an lnterrupt. The interrupt causes the pro~rarn to break out of the loop shown in Fly. 3 and to execute a com!nand to message system from TIS routine 33 whlch serves the host computer 2 and then returns control to the ?ro~ram of Fig. 3 at whatever point the interrupt broke in. This command routlne 33 causes the mlcro~rocessor 12 to deter-mine whether the command is inten(1ed for the TIS 5 ox the VPS 8 and wrltes the approprlate translation Or the corn-mand into a preassigned area ox Karl 26 for transmittaI to either the TIS 6 or VPS 8 as pre~-iously ~escrl~,ed.

~236943 At thls polnt in the program shown ln Fig. 3 the memory space ln RAM 26 and C 13 assigned to commands lntended for the TIS 6 ls checked to see it there are any commands ror the llne 10 which the program is currently serviclr~. If there are any they are executed at this polnt by puttln~ them on the data bus 14 to the ITI 20.
In addltlon to the messages to tile host Gomputer 2 deallng with tlmlng information note(l above the pollir~
program determines whether the line 10 currently being polled is calllng for service (a rink on the line 10) lr the calling party has hung up the most recent cllgit recorded by a touch-tone decoder and so forth. These messages are translated and placed ln the host computer 2 command queue descrlbed prevlousl~v at thls point in the polllng program.
The proKram no checks to see if it has reaclled tlle last actlve line at 34; if not it considers tlle next actlve llne at 35 and repeats the tasks descrlbed above.
If the last active line has been served however noted at 34, before returning to the f1rst llne at 3~ solve ad tional tasks are performed. I`~;ese tas~f~s~ calved a less frequent routine 36 may have many functlons such as a lZ36943 Jo command to VPS 8 routine and the activation OL a fourth timlng clock, as described in more detail below.
As indicated aboveJ cornmands rrom the host COmp!lter 2 to the TIS fi or VPS 8 may appear at any time in the asslgned area ox RAM 26 as a consequence of interrupts.
At thls polnt ln the program showrl in I 3, the mernory space assigned to cormnands intended for VPS ls checked to see lr there are any commands. lr there are any, they are executed at this point bv puttln!~ them on the data bus 14 to the VPS I. Additionaily, the rourth clock controls the ofr/on time for telephone si~,nalin~ tones which require interruptlon, for instance the busy tone and the ringlng tone. This clock runs continuously. The program will examlne the register after each incrernent arid will turn the tone off or on as approprlate whenever tne time exceeds a preset amount.
For varlous reasons, it ls sometlmes useful to trans-fer digltized volce messages froln the disk system Or the host computer 2 to disks 9 rnaintaine~ my the VPS I. Addi-tlonally, the.transfer of dl~itized voice rnessa~,es from the VPS dlsks 9 to the host cor~uter 2 dlsks ls a]so sometimes useful, such as for backup arld error checXln,~

12369~3 procedures, This process is ~reatlv assisted by the addltion ox a direct memory access devlce 37 to the super-visor 3, as shown in Fig. 4. For such a disk-to-disk com-munlcation, the microprocessor 12 is assisted by the direct memory access (DMA) device 37 in transferring data to the data bus 14 via the bus connector 15, directed by the address bus 23 through decodi~ device 24 to and from the VPS via lines 25. When a Z~OA rnicroprocessor is used, a Good DMA devlce 37 is the DMA chip.
Transfer operatlons rnay be pro~r-amme(l in various ways, dependlng on the character of the VMX I. The 'oice-Tek Model 30 transfers data in X bytes. Thus the system ox Fig. 4, when used with a rnodel 3~ as a VEX I, ls deslgned to handle data ln 6K batches.
In transferrlr~ data, a second US 232-C port may be used, which exists on rnany host computers 2, as well as on the UART 19 chip used ln the example supervisor 3. By dedlcatln~ this second data channel to dlsk-to-dlsk trans-fers, such operatlon may be carrled cut as ti,ne perrnits, wlthout disturbing the normal opera~cn Or the s~ste~ l.
Such operations are termed '~operatlorl~s in the baclc~round."

~2369~3 o2~

As with all data transfers, datfl, including status data, is cached in the supervisor RAr1 26 in the process of transfer. Voice data from the i-ost cornputer 2 is translated lnto a compatible 6K byte text string representation, sent over the second RS 232-C line, an cached in the supervisor JAM 26. When time permits, tire 6K byte Or voice data i8 transferred to ti]e VPS under control Or the direct rnemory access device 37. this process is continued untll the complete message has been transmitted.
he transmittal of voice data from the VPS 8 to the TIS 6 over lines 11 is therefore accomplished under the control of the dlrect memory access rlevlcr-~ 37 in passln~
6K byte batches to the supervlsor EM 37 cache. Such ciata ls then translated into text string, representatlon and passed to the host computer 2 throu~n the second RS 232-C
channel. Such a method can also be used to transrer extended command string 8 .
Referrir~ now to the schematic drawln~s Or Fits, 5, a preferred supervisor circult 3,1s silo~n with industry standard components desl~nate-l by numhers 011 Flgs. 5a-5~, ;
and without all poller connectlorls or unuse~l connectlons, ~Z36943 ~3 for simplicity. Fig. 5a shows a typical reallzation of the clrcuitry for the UART 19 which CO!nmUrliCateS with the host computer 2. The UART lq iliustrated ls the 7.~0A
SI0/0, a device which is designed to lnterface with most commonly used microprocessors 12, such as the Z80A (see Fly. 5b). The UART 19 supports communlcation lines 4, shown as two RS 232-C lines 3~ and 3q, to the host cornputer 2; line 3~ is used for com~T!arld and information exchange ~rlth the Yost computer 2, arld 39 is used f`or disk-to-disk transfers as descrlbed prevlously, or other transfers of large blocks of data. Some signal condltionlng may be required on lines 3~ and 39 depending on the nature Or the RS 232-C ports avai]able on the host computer 2 and the length Or the connecting llnes 4.
The two device ports of the ~lART 19 are labe'ed "A"
corresponding to line 38 and "I" cerrespondln~ to line 39~ F,ach has four lines: TXD, R.YD, Prs an curs. The TXL~
llne carrles data belng transrnitted frorn the supervLsor clrcuit 3 to the host computer 2 in the RS 232-C serlal format and corresponds to the transmit line 17 in Film. 2.
The RXD line carries data being transrnitted prom the host computer 2 to the supervlsor circuit 3 and the RS 2~2-C

, , ~Z36943 I/

serlal format and corresponds to the receive line lh in Flg. 2. Each port A and B a~.so has two control lines; R~S
(request to send) and CTS (clear to send), correspondinF, to the control llnes l ln Fix. 2. The PUS terminal is normally high, lndicating that the ~evlce can accept six nals from the host computer 2. It the lnternal buffer of the UART 19 is filled, this RT~ terminal will be switched to a low slgnal, warnlng the host computer 2 not to send another character urtll space is callable and the PUS
termlnal ls swltchec to hlgh. The host cornputer I, on the other hand, can warn the UART 19 not to sent c}laracters to it by supplyln~ a lcw slgnal on the ITS line, which i.s otherwlse malntained in the high state by the host com-puter 2. Thus the RTS and CTS terminals are used to control the flow ox informat.lon between host computer 2 and supervisor clrcuit 3 according to the PS 2~2 C pro-tocol.
The data bus 14 conslsts of the (data files VO throu~
D7. Thls data bus 14 will contain ?. charactor whlch is to be sent to the host computer 2 (ln parallel. rormat! or will have lmpressed on lt a character beln~ transmittod by the host computer (ln paral.lel ~orrl~t~ to the supervlsor ~236943 circult 3. These characters are yenerated and used as descrlbed prevlously ln reference to the VPS 8 TIS 6 and the timing routine 32.
The UART 19 requlres two clock signals. The first, carried by timlng line 41 originates from the master clock 42 used to operate the rnicroprocessor 12 (see Fig.
5b); belng used to synchronize the operatlon Or the UARr 19 with that Or the mi.croprocessor 12. The clock signal ls sharpened by the push-pull transistor amDlifier 43 using transistors 44 and 45 and their associated cir-cultry. Thls clock signal is therl applied to the Of (clock) terrninal of the UART 19. The second clock signal establlshes the speed at whlch bits are transferred between the host computer 2 and UAnr 19. Preferably the hl~hest standard speed .for transfer possible is used, this rate being approxlmately 19.2 kllz. his sl~nal J curried by limit line 46, is derived from the tone ~eneratl~
portlon ox the supervisor clrcult 3 ShOWtl in Flg. sr, and ls sharpened by a Schmidt trigger tyre not gate 47 and is dlvided down to the approprlate frequency by -rrequency divlder 48r~ and applied to UART lq terminals RYC TIC
(receive and transmit clocks and RXl~C~ by line 4q .

~Z36943 c Further reduction by division of this frequency is accompllshed ganglng the two unlts Or the frequency divider together through line 50; tho resultant low f`re-quency signal being applied to a second frequency divider 51 and the resultant still lower frequency being divided once more by a factor of two by the fllp-rlop latch 52.
The slgnal then carried by line 53 is the clock signal used to establish the tlmlng routines ~escrlbed previously ln regard to the tlming routine 32.
The frequency lmposed on the fIrst divIder 4~ is 4.gl52 mHz. The rrequenc~v supplied to the IT 19 (which ls rurther divided wlthin the UART 19) ls one-fourth this value) that ls 1.2288 mHz, to establish a 19.2 kHz transfer rate. Further divislon reduces the value of the slgnal on line 53 to 37.5 Hz (27 msec period).
The ~ST (reset) terminal Or the [IART 19 is drlven low to place the devlce ln an lnitlal. operatinfJ lode when power is applied or when a reset push button is actuated the reset clrcuitry being discussed In greater detail. in connection wlth Flg. 5B. Under normal operation this terminal is held high.

~36943 Line 54 IEO (interrupt enable output), line 55 INT
(interrupt), and line 56 IEI (interrupt enable input) con-nections to the UART l are used to lnterrupt the micro-processor 12 and to establish the ~rlority ox the UART 19, automatically generating an lnterru~t (IN terminal woes low) whenever the host computer 2 sends a character. This interrupt slgnal ls then carrled by line 55. As dlscussed ln more detail ln connection wlth the DMA 37 circuit shown ln Fig. 5g, a brief dela,y may occur before this character can be processed ir the hlgher priority nAM 37 has established its prl,orlty by driving the IEO low on line 56. Interrupts from the UART l9 take priorlty over those generated by the VPS 8 and the TIS 6, however, as established by the connectlon Or the I~O llne 54 from the UART 19.
The RD (read) termlnal Or the Jar lo is held low if the devlce 18 to read data from the date bus 14; it its held high if the ~AR~ 14 is to write data to the data bus 14~ The orlgin Or the signal is toe mlcroprocessor 12 (shown in Flg. 5b and carried thr3u~h bus 5~ ln Figs. 5c and 5d).

lZ36943 ~?~

The IORQ (input/output request terminal ox the UA~T
19 is drlven low by the microprocessor 12, carrled along bus 58, and llne IOR~ addresses an input~olltput device rather than the memory. When this IORQ line is low, the CE (chip enable) signal can activate the UART l9 as discussed below.
The MI (rnachine cycle lo term1nal of the UART 19, in conJunction with the CLK signal ~1sc~lssed previollsly, allows synchronizatlon Or the UAR'r 19 with the microprocessor '12 and 15 carries along bus 5~ and llne I, as shown ln Flus, pa - 5d.
Line ~7 CE (chlp enable) connection to the UART 19 allows the UA~T chlp 19 to read data from the data bus 14 and place data on the data bus 14 only when addressed by the microprocessor 12; the origin Or the signal beins the address bus 23 of the microprocessor 12, decoded as des-cribed ln connectlon with Fig. 5cl.
The B/A terminal Or the UART 19 causes the clevice to recoKnize either port A (low signal ~pplled) or port B
thigh slgnal applled). The signal is carrieA on llne Al of the address bus 23 of the microprocessor 12, as shown ln detail in is 5b and 5d.

~236943 The C/D terminal of the UA~T 19 causes the device to interrupt signals on the data bus 14 as data (low signal applied) or as commands to the UART 19 rrom the micropro-cessor 12 (high slgnal input). The sl~nal line AO of` the address bus 23 Or the microprocessor 12 carries the signal, as shown ln detail in Fits. ~b and 5d.
Referrinp~ now to Fig. 5b a t,vpical reallzation of the circuitry for the microprocessor l2 used in the super-visory circuit 3 is shown. As stated previously an Z~OA
may be used for thls purpose. The Z~qOA microprocessor 12 uses a 16 line address bus 23. The address bus 23 is spllt lnto two buses, the rlrst address bus 59 contains address lines AO through A7 and the second address bus 60 contains address llnes A8 through Al5. Both address buses 59 and 60 are passed directly to tile D?1A 37 fig, 5F, ) and, vla the permanently enabled line dr.lvers hl and 62 to the decoding clrcuitry descrlbed ln connection wlth Fig. 5c.
Slx of the control terr~lnals (Eli, r1~E~, IOR~, RD, WR, and REF, discussed briefly above) ox` the Z~OA micropro-cessor 12 are formed into a control bus 5~ and passed dlrectly to the MA ~7 (Fig. 5~ and, vla permanently enabled line drier 63, to the other circults ox tlle lZ36943

3~

supervisor circult 3 as shown in Flus. 5c, 5d, etc. The six slgnals in the control bus are:
MI (machine cycle 1): This output provldes a slgnal whlch occurs when the first cycle of the microprocessor 12 commences) allowing (along with the clock signal) the synchronization ox other devices with the operation Or the microprocessor 12.
MREQ (memory request: This output provides a (low) signal when the proP~ram addresses a loca-tion in toe memory section Or the supervisor circult 3 (see Flg. 5c).
IOREQ (lnput/output request: Thls output pro-vldes a (low) slgnal when the pro,~,ram addresses an lnput/out device ln the supervisor circuit 3, for instarce, the I~ART 19 (lescrihed ln Fig. 5a.
RD (read): This output provides a (low) signal when the program causes the memory location or device addressed to rea(l the contents of the data bus 14.
WR (write): This output provldes a (low) signal w~len the program causes the memory location or , , ~1236943 device addressed to write inforrnatlon to the data bus 14.
REF (refresh): This outpllt provides a (low) slgnal to allow dynamic memories to undergo the refreshment process. Dvnamic mernories are not used ln the ill.ustrated clrcuitry; the sl~nal being used only to disable operation durln~ the tlme that the microprocessor 12 has set side for the refreshment process.
The BUSACK and BUSRQ (bus acknowledye and Gus request) signals are used in connection with the operation ox the DMA 37 descrlbed ln connection with Fix. 5g. upon receivinF a low signal on the BUSRQ li.ne the mlcropro-cessor 12 turns the supervisor circu1t 3 buses 14 and 23 over the the control ox the DA~1 37 and acknowledges this action by providing a low signa:l on the BUSAC~ line . To Z~OA microprocessor 12 uses an line data bus 14. The data bus 14 is passed directly to the MA 37 figure 5 g) and, vla the bus connector device 15, to the rest of the supervisor clrcuit 3~ As explained previously ln relation to ~lg. 2, the bus connector 15 con lsolate the two sections ox the data bus 14 which lt conrlects if i ~23~43 3~

the EN (enable) input ls hlgh, or depending on the settlng of the DIR (directlon) lnput, can pass data in orle or the other dlrection along the sections Or the data bus 14 high it ls connected to lf the EN input is low.
The EN signal for the bus connector l ls derived from the not gate 64 and carried on llne 65 whlch, in turn, ls drlven rrom a decoded address siF~nal carried on llne 66 rrom a decoder 68 shown ln F1g. 5d. The same decoded address slgnal is passed by line 67 to the chlp enable terminal (CE) Or the DMA 37 (~1F~. 5~) which also requlres a low slgnal to opèrate. Because ox the lnver-slon produced by the not date 64, however, the bus con-nector 15 ls open whenever the D~IA ~7 is actuated and passes data to the rest Or the supervisor circuit 3 only when the DMA 37 is not enabled. The correct dlrection of data flow is established by the DIR signal car;ried by ]lne 70 to the bus connector 15, received no the gate f~9 whlch ls in turn drlven by the MI and Pi sl~nals frorn the microprocessor 12 as dlscussed above, and shown routed through bus 58 ln Flgs. 5b and 5c.
The INT (interrupt) siprlal Jay be aprlied to the mlcroprocessor 12~ along the 71~ by the DMA 37 (~`lg. 5p,~, ;

~2369~3 by the UART 19 (Fly. 5a~ by the VPS or by the TIS 6 in that order of priority. ~rhen the microprocessor- 12 receives an lnterruFt signal (INT low) lt looks on the data bus 14 to find the address ox the appropriate program routine to service the interrupt. The method of establishing the lnterrupt priority an placing the interrupt vector on the data bus 14 is descrlbed in connection ~lth Figs. 5a - 5~ descri~in~ each Or the devices, respectively.
The INT signal itself ls derlved from ancl gate 72 the output Or which is pulled high by the connection to the 5 line 73. The and gate 72 is driven by llnes 55 and 74.
The signal on llne 5~ ls generated bv the INT output of the DMA 37 (Fig. 5g) or by the INT output Or the UART 19 (Fig. 5a); the slgnal on line 74 is venerated by the INT
output Or the VPS 8 or the I~IT output of the TIS 6 as discussed hereinafter (Fig. 5d). Polarities and logic are set so that lf any ox the four devices (D;~A 37~ UART 19 VPS 8 or TIS 6) generates an interrupt sl~nal it wlll drlve the INT lnput of the microprocessor l2 lo thus lnltlatlng the interrupt process. tote however that the prlority setting system prevents more than on deice from slmu]taneo~sly supplyir~ an lnterrupt sl~nal.

~236943 3~1 The reset circultry 75, causlny a reset (RST) signal, is actuated by pushbuttorl 76 or in the process of applylng power to the sul)ervisor circult 3; the Rsr signal is cleaned by the rot gates 77 and applied to the ~ST (reset) tern71nal of the microprocessor 12 and passed to other cir-requlring a reset signal (Fi,~S. 5a and 5c) by line89, he clock signal (CLK) or driving the microprocessor 12 is derlved from a crystal controlled oscillator 78 of the masterclock 42 usln~ notates 79 an~7 ~0 as active elements- The CLX slgnal is cleaner, sharpene(7, and isolated by rllp-flop latches 81, not gate 82~ and the push-pull amplifier 83 whlch uses translstors 84 and R5 as active elements. l'he desired operating rrequency for the is 4 mHz, therefore be slop latches l divide the signal b~v four, the osci]lator 78 is operated at a crystal frequency Or 16 n7Hz. The lo mHz clock signal (CLK) is also passed to the delay circuit 86 by llne R7, as deserted ln connectiorl with Fly 5c, to the UART 19 ( lg . 5a) by line 41 tl~rough isolatin,~ not gate 88, and to the DMA ~7 Fig 5~ by line 90.

~Z36943 ig. 5c shows the memory circuit. Two types ox memory chip are used ln this typical realization: or 13 (read only memory) containing the program described ln detail ln connection with Fig. 3 and JAM 26 (random access memory) used to cache information being transferred between host computer 2 and VPS and TIS 6. Two remory chips are used for ROM 13, each one beinK organized as an 8K x 8-blt devlce, and rour rnemor~Y chlps are used for RAY
26, each also being organized as an x 8-bit device.
The data terminals DO-~7 Or each memory device 13 and 26 are attached dlrectly to a segment ox the central data bus 14. The address terminals of the me!nory chips 13 and 26 are all attached to the first address bus 59 containlng address lines A0 through A7 and to the first jive llnes ox the second address bus 60, beln~ address lines A8 through A12. The active memory chip 13 or 26 is selected hy drivlng the CS (chlp select) and OE (output enable termlnals Or the selected memory chlp low, using signals from decoders 91 and 92. These decoders 91 and 92, in turn, are drlven my sl~nals rrom address lines A12 throu~,h A15 of address bus 60.

lZ369~

The decoders 91 and 92 are also used to deactlvate memory circuits durlng the refresh cycles TV a signal from the REF line ox bus 5~ applied to terminal Gl of decoder 91 and, by way ox not gate 93, to terminal G2B Or decoder 92~ The memories 13 and 26 are only active if a low slgnal is placed by the microprocessor 12 on the MREQ line in bus 58. The ROMs 13 are activated by the M~EQ signal applled to terminal G2B Or decoder al. The jams 26 are actlvated by the MREQ signal applied to terminal CS2 (chip select 2) Or jams 26 by the lo~lc circuit forlned by gate 94 and not gate 95. Additional.l.y, the Rums 26 are instructed to read or write by a signal applied to their RD/WR (read/write) termlnals by or ¢ate 96 which, i.n turn, ls drlven by the WR line Or bus 58 in coincidence with the MREQ sl~nal dlscussed above.
The delay circult 86 formed by not gates g7 and 9~, or gates 99, 100 and 101, and flip-flop latches 102 and 103 ls driven by signals MI, IO~Q, We, and the 4 ml~z mlcroprocessor 12 clock signal ~7. The del.ay circuit ~6 introduces a slight delay in the writin,a of` data to the TIS 6 and VPS R through the si~n~ls cannel on ~lnes 104 and 105 as explained ln connection is 5d and 'ye. The lZ3G943 delay allows the data signal to settle, to a vold inter-ference, before it is clocked into the assigned memory location.
The VPS 8 interface circuitry ShOWIl in Fig. 5d requires address lines A0 through A6 on address bus 59 and an inverted signal from the signal carried on address line A7 on address bus 59. The inversion on line A7 is pro-duced by not gate 106 supplying address line 107, as shown in Fig. 5c. The ED, IORQ and MI lines are also supplied to the VPS 8 lnterrace circuitry shown in if 5D, for use as descrlbed below. The MI and ED lines are also supplied to the bus connector 15 clrcuitry shown ln Fig. 5b as described prevlously.
Flg. 5d shows a detailed realization Or the required clrcuit interface with the VoiceTek Corporation Model 30 VPS I. The Model 30 exchanges control information (not to be confused with the audio sl~n~ls which lt processes) by means of an 8-line control bus lQ8 driverl by a per-manently enabled llne drlver 10~, on 8-line data bus 7, a data ready line 111, a buffer ready line 11~, and a reset line 113, discussed in more detail hereinafter.

. , 3~

The UPS control bus 10~ lines are designated Lola through 108h. They have the following functions and are generated by the supervlsor circuit in the following ways:
Llne 108a WRDDS~L (wrlte data select): Wrlte slgnals are developed when the supervisor clr-cult 3 wlshes to pass data prom the host com-puter 2 to the VPS 8. A low WRDDSEL signal must colncide with the WR signal (line long, see below) to wrlte data to toe VPS 8. The WRDDSEL
signal is generated by decoder 114 which decodes the flrst three llnes A0, Al and A Or the address bus 59.
Line 108b RDDSEL (read data select): Read sly-nals are developed when the VPS wishes to pass data to the host computer 2 through t.he super-visor clrcuit 3. A low RDDSEL s1~nal must coin-clde with the ED slgnal (line 108h, see below) to allow the VPS 8 to place data on the data bus 7 for the host computer 2 to read. To .~DDSEL
signal is generated by the decoder 114 which decodes the flrst three llnes A0, Al and A ox toe address b~ls 59.

~Z3~943 ~,~

Line lO~c DATACK (data acknowledge: The super-visor circuit 3 drives thls line low in coin-cidence with a WR signal (line 10~ ee below) to indicate to the VPS that a complete command/data string has been received. The DATACK signal ls generated by the decoder 114 which decodes the rirst three lines A0, Al and A2 of the address bus 59.
Line 108d SERREQ (service re~uest~: The super-visor circuit 3 drives this line low in coln-cidence wlth a WS signal (line lore, see below) to indicate to the VPS that the end Or a command/data strlng from the host computer 2 has been reached. The SERREQ slgnal is venerated by the decoder 114 which decodes the first three lines A0, Al and A2 of the address bus 59.
Line lORe WRSYNC (write sync: The supervisor circuit 3 drives this line low in coincidence with a WS signal tline 10~, see below) to lndlcate to the VPS that a com~and/data strlng is about to be transmitted. the W~SYNC siF,na]
is generated by the decoder 114 which decodes ~236g43 the rlrst three llnes A0, Al and A2 Or the address bus 59.
Line 108f SYNC (read sync): The supervisor circult 3 drives this line low ln coincldence with a ~lS signal (llne long, see below) to syn-cronize a command/data string before iS is read. The signal is venerated by the decoder 114 which decodes the first three llnes A0, Al and A2 of the address bus ~9.
Line lore WS (write strobe): Thls ]ow sl~nal is carried by line 105 and gerlerated by the delay circuit 86, as describe in connectlon wlth Flg. 2c, to enable the placement of data.
Llne loch (read): This l ow signal is the read signal generate by tdle supervisor clrcuit's microprocessor 12 and carried on ]ine ED via Fig. 5c (see the description provided in con-nection wlth Fig. 5b).
The VPS 8 data bus 7 ~alns access to the supervlsor clrcuit's data bus 14 through bus co~rlector 15. The direction ox data flow ls determine bY the presence or absence Or the ED signal from the microprocessor 12. To t 12369~3 bus connector 15 is enabled by a signal carried on line 115 from decoder 116, which decodes address lines A3, A4 and A5 of address bus 59.
Llne lll DATRDY (data ready) provides a low signal from the VPS signlfying that it is holdin~¢ a command/
data strlng in lts buffer to be transferred to the super-visor clrcult 3. As lndlcated previously, such transfers are made by an lnterrupt. The DATPDY sl~nal is placed directly on line Dl of the data bus 14 when line driver 117 is enabled by a sl~nal from or Nate if whlch, in turn, ls actuated by the RD line an(1 a slKnal carried on llne ll9 from decoder 6~, decodlng address lines AO and Al of address bus 59.
Llne 111 carries an lnterrupt signal an it ls also applled to the second half of line drlver 117. This halt of the line drlver 117 is always actlve and venerates the interrupt bY driving not gate 12~ and rlip-flop .latch 121 whlch, ln turn, drlves the decoder 122. The decoder 122 generates a slgnal, carried on line 74 to interrupt the microprocessor 12 (as described ln connection with Fly.
5b) and also places a vector for the lnterrupt routine on the data bus 14 tl:rough llne driver 121. rl~ gate 110 resets rllp-flop latch 121 when activated by slsJnals rrom the wrlte strobe WS slgnal carried by line 105 and rrom decoder 114.
Line 112 carrles a BUFRDY (buffer read~v) low slgnal from the VPX 8 when lts burner is ready to recelve a command~data string from the supervisor clrcuit 3. Thls BUFRDY signal is placed dlrect3.y on line D2 ox the data bus 14 when llne drlver 117 ls enabled by a ~ir,nal from or gate 11~ whlch, in turn, is actuate hy the Rr~ llne and a signal carrled on line 119 from decoder k~, decoding address lines A0 and Al of address bus 59.
Line 113 carrles a RESET (reset signal to tile VPS
through line driver 117. The RESEr s~r.~nal is generated by or gate 124 which ls drlven by the write strobe WS slgnal carrled by line 105 and a signal carried on llne 125 and generated by the decoder 114 which dYcodes threw ad-3ress llnes A0, Al, and A2 of the address bus 5q.
The interrupt routi.ne describe above can be lnltiated by a sl~nal prom the 7'IS carried on line 12 from the TIS (in case a data trânsfer can be acco~n-pllshed more efficiently by interrupt rather tshan hy the polling process described prev.~ou~sly~. Pecallse decodel , ~;~36943 'I

122 generates a dirferent slgnal when an interrupt ls pro-duced by the TIS 6 a different vector is placed on the data bus 14, directing the microprocessor 12 to a routine suitable for servln~ a TIS 6 interrupt. The connections therefore establish the priorlty Or the VP~ lnterrupt over the TIS fi interrupt.
Llne 54 derive from the UART 19 (descrlbed in con-nection with Flg. 5a) and the signal lt carries establlshes the prlority of UART 19 interrupts over lnter-rupts from the VPS 8 and the TIS 6 by virtue ox its con-nectlon via not vate 127 and line 40 to decoder 1.22 and via or gate 128 to llne drlver 123 which is also controlled by not gate 129 in response to the IORQ and MI
slgnals generated by the mlcroprocessor 12.
The 37.5 Hz clock signal carried on line 53 described in connection with Fig. 5a is pl.ace-l on 1ine ~2 of the data bus 14 through the gated section of llne driver 117.
Other connections shown ln Fife d are provlded to gate the varlous decoders and other devices to operate only at approprlate tlmes in the program cycle.
Fig. 5e shows the lnterface bet.~een the supervisor circuit 3 and the telephone interface system (Tl~ 6; the 1236~43 I///

clrcuit shown is approprlate for connection to the VoiceTek Model 50 TIS 6.
The Model 50 can handle up to 32 telephone lines. In order to initiate inquiries on the status Or a telephone llne the model 50 expects the sur7er~isor clrcult 3 to address the telephone line in question. The telephone lines are divided into two groups of sixteen. Address llne A6 on bus 59 of the supervisor circult 3 is used to designate which group of telephone llnes is to be addressed. The particular telephone line is then desi~-nated by signals as describec~ below. When the signal on line A6 is high, the first group of 16 telephone llnes is enabled; when the signal on line A6 is low a high sigrlal ls developed by not gate 130 high enables the second group of 16 telephone lines.
Within each group of 16, a speclfic te'.ephone llne is selected by signals carried on the two R_line buses 131 and 132. Supervisor circuit 3 address bus lines A2 through A5 carried on bus 59 are used to address the individual telephone lines; the signals carrled by those lines are decoded by decoders 133, 134 and not Nate 135.

The llne buses 136 and 137 carrying the decoded sl~nals lZ3G943 are supplled to the 8 lone busses 131 an 132 and then to the TIS 6 by the two permanently enabled line drivers 138 and 13~.
Bus 140 and bus 141 transfer commands to the TIS h.
Bus 140 passes the signal contents of lines D4 through D7 Or the data bus 14 through the first half of llne drlver 142; these lines actuate Orr hook> reset digit/rin~, on hook, and trunk reset signals for the telephone llne addressed. The line driver 142 is enabled by a signal carrled on llne decoded by decoder 143, whlch is actuated by llnes A0 and Al Or the supervisor clrcuit 3 address bus 59. Bus 140 also contains a llne to the trunk strobe Or the Model 50 TIs 6; this signal is derived from decoder 143 and ls applied through the second halr Or line driver 142 by llne 145 when the line driver 142 is enabled by the wrlte strobe slgnal carried by line 10~. Decoder 143 is in turn enabled through or Nate 147 drlven by line 104 and by line 107.
Bus 141 passes the contents of llnes D0 throuF,h D3 Or the data bus 14 throuyh permanently enabled line drier 14~. These lines D0 through D3 actuate VPS-0 through VPS-4, asslgning one Or the varlolls voice paths that the '/~

TIS 6 can employ. The bus 141 also contalns a RST (Reset) llne to reset the TIs 6 and the address lines descrlbed above (A6 and inverted A6~.
Status inrormation about the telephone line addressed ls passed dlrectly to lines D0 through D7 of supervisor circuit 3 data bus 14 by bus 149 through llne drlver 150.
The slgnals, elght in number, are as follows: the first four are BCD (binary coded decimal representatlon ox decoded touch-tone slgnals on the telephone line; the others, in order, are a hook change signal, an ofr hook slgnal, a digit assembled signal, and a trunk lientlfica-tlon slgnal. Line drlver 150 is enabled through or gate 151 by a signal carrled by line 1~2, decode(3 from address bus llnes A0 and Al by decoder 143 and bv the ED signal.
Llnes D0 and Dl Or the supervisor clrcult 3 data bus 14 are used to clock the tone circuits whlch requlre interruptlon (see below). They are passed to the tone venerator clrcult see Fly. 5f) by line driver 153 whlch is enabled by a signal carrled on llne 154 from decoder 143 vla line 144 when the write strobe sl~nal carried on llne 105 enables line drlver 142.

~23 E;9~3 ~7 Fig. 5e also shows one Or the bus connectors 15 used to establish the flow of data on the supervisor circuit's data bus 14. The bus connector 15 ls enabled by the r~REQ
slgnal; directlon ls established by the RD slgnal.
Finally, note that the gating circuits of the decoders 143 and 134 are connected through line 104 to enable these clrcuits at the proper program segments, wnich may also lnclude the connection through not Nate 135.
Fig. 5f shows the tone generating circuit The TIS 6 will place one of fcur telephone tones on a telephone llne's audio circuit: a dial tone, a busy tone, a ring tone, or a valld tore. These tones are generated by the supervisor circuit 3 and passed to tne TIS I, as descrlbed generally, previousLy. The tones are venerated by tone venerating chips 155 using appropriate crystals 156 to establish the appropriate audio frequencies. The lines to the TIS h are driven by operational a~pliriers (op. amps) 157. The tones requiring interruptlon (busy and rink) are interrupted by signals placed on a segment Or the data bus 14 as described above. The crystal 5 hhlch esta~lislles the rrequency Or the valid tone i9 also carried hy line 46 and used to feed the clock circuit described in connecl;Lon with Fig. pa.

4~

The direct memory access (D~IA~ circuit us shown in Fly. 5~. The circuit consists of` a single DMA chip 37;
the zRoA DMA is lllustrated. The ~'1A chip 37 ls used to enable disk-to-disk or other bulk data transfers in the background of supervisor clrcult 3 oreration as descrlbed previously. Connections to the ?'rlA chlp 37 lnclude the supervlsor circult address buses 59 arl(1 60, control bus 2~, and data bus 14. It should be noted that one line Or the control bus 2~, the R~F line, is not required by the DMA chlp 37.
The DMA chip 37 functions by takir~, over control of the supervisor circult buses 14, 5~, 59 and 60 from the microprocessor 12; it then transfers data hetween I/0 devlces and memory wlthout the lnterventlon of the micro-processor 12, thereby speedln~ SUCIl transrers. It requests bus control by drlvlng llne the BUSPQ llne low;
thls llne ls connected dlrectly to the BUSRQ input Or the mlcroprocessor 12, as descrlbed pre~Jiously. After trans-ferring control Or the buses 14, 5R, 59 and fiO to the DrilA
37, the mlcroprocessor 12 places a low signal on its BUSACK (bus acknowledge) output; thls sl~rla1. is passed directly to the Sal input of tl,e f chip 37. The DMA

~236943 chip 37 also requires a clock input the CLK signal used by the microprocessor 12 is also passed to the ILK (clock) lnput of the DMA 37.
The DMA 37 lnterrupts operatlon Or the rnicroprocessor 12 by placing a low signal on line 55; the DMA chip 37 can then place a vector to the appropriate routine on the data hus 14. The priority of ~1A 37 interrupts is estahli.shed by holding the IEO (interrupt enabl.e output Or the DMA 37 high at all times. The IEO of tlle Diva 37 is connected by line 56 to the IEO lnput of the UART 19.
Operation of the DMA 37 ls enabled by a l.ow signal on line 67 to the CE (chip enable lnput of the DM~ 37; this signal is derived (vla Fix. 5b) f`rom a decoder 68 circuit descrlbed in connectlon with Fife. Ed. Finally the RDY
(ready) lnput of the DMA 37 is actuated by line 54 f`rom ; the IEO (input enable output) Or the UART ln to prevent overflow of the UART 19 buffer when the DMA ~7 is active.
The lnvention has now been described in connectl.on with a preferred embodiment. Further modifications will also occur to those skllled in this art. and such are con-sidered to fall within the spirit and scope ox the lnven- !
tion as defined in the appended clalms.

Claims (8)

What is claimed is:

1. An electronic communications supervisor for controlling digital recording and playback of voice messages for connection to a tele-phone line interface, a voice processor and a host computer, having, in combination, electronic digital signal processing means for controlling the operation of the super-visor; parallel means for receiving and transmitting digital control signals between the telephone interface and said electronic digital signal processing, means to provide access to the telephone lines for voice messages; parallel means for receiving and transmitting digital control signals for controlling voice messages, between the voice processor and said elec-tronic digital signal processing means;
analog audio lines for transmitting voice messages between the telephone line inter-face and the voice processor under control of the electronic digital. signal processing means; audio processing means associated with the voice processor for converting said voice messages into digital data signals representing voice messages and from digital data signals into voice mess-ages, digital memory means controlled by said electronic digital signal processing means for storing said digital control signals, digital memory means controlled by said voice processor for storing digital data representations of the voice messages from said voice processor; and serial. means for receiving and transmitting digital control signals and said signals between the host computer and the electronic digital signal processing means.

2. A supervisor as claimed in clown 1 which in-cludes a tone generator means for trans-mitting telephone supervisory tones between the electronic digital signal processing means and the telephone inter-face.

3. A supervisor as claimed in claim 2 in which the control signals transmitted between the electronic digital signal processing means and the telephone interface include dial, busy, ring and valid tones.

4. A supervisor as claimed in claim 1 and in which there is provided direct memory access means connected to said electronic digital signal processing means to process transfers of relatively large blocks of data, such as recorded messages and long command strings between said voice pro-cessor and said host computer.

5. A method of producing a voice message system for connection to telephone lines, that is compatible with any host computer that com-prises: receiving command signals in serial digital format from the host com-puter, translating the serial digital sig-nals intoparallel digital signals; creating an independent electronic digital signal processing communications supervisor for processing command and data signals in parallel digital format and translating to serial digital format, the data signals representing voice messages, receiving and sending data and command signals between the electronic digital signal processing communications supervisor and a voice pro-cessing system and a telephone interface system, transferring analog voice signals between the voice processing system and the telephone interface system under control of the electronic digital signal processing communications supervisor, storing data and command signals in electronic digital memory under control of the electronic digital signal processing, communications supervisor independent of the host computer, and sending command signals in serial digital format to the host computer to provide status information regarding the voice message system.

6. A method as claimed in claim 5 which in-cludes sending data signals in serial digital format to the host computer.

7. A method as claimed in claim 5 and in which subsidiary timing impulses are generated to control aspects of telephone operation timing such as time elapsing before response by the caller.

8. A method of enabling the efficient use of any host computer with a voice message pro-cessing apparatus using a telephone inter-face and voice processing system, that com-prises, providing a universal supervisory circuit between the host computer and the telephone interface and voice processing system, said circuit having a memory that stores data of a type useful to interface with said telephone and voice processing interface system, said circuit performing the steps of receiving standard serial data from any host computer such as telephone answering, voice message storing and other commands; storing in said supervisory circuit memory particular serial data commands tailored to command and control the telephone interface and voice processing system; using said data stored in the memory to translate said received standard serial data from the host computer into command and control language recognizable by the telephone interface and voice processing system; converting the translated language into parallel data; and prioritizing the application of said parallel data to said telephone interface and voice processing system for efficient transmission to the telephone interface system; the said telephone interface and voice processing system generating parallel data, such as line-ringing and other status data, translated by said supervisory circuit into standard serial data recognizable by the host computer; and prioritizing the transmission of the last-named standard serial data to the host computer.