CA1243422A - Contact vias in semiconductor devices - Google Patents
Contact vias in semiconductor devicesInfo
- Publication number
- CA1243422A CA1243422A CA000521705A CA521705A CA1243422A CA 1243422 A CA1243422 A CA 1243422A CA 000521705 A CA000521705 A CA 000521705A CA 521705 A CA521705 A CA 521705A CA 1243422 A CA1243422 A CA 1243422A
- Authority
- CA
- Canada
- Prior art keywords
- glass
- vias
- layer
- reflow
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/133—Reflow oxides and glasses
Abstract
CONTACT VIAS IN SEMICONDUCTOR DEVICES
Abstract A glass reflow step to round off sharp edges of contact vias is typically included in processes for making integrated-circuit devices. In the course of making such devices with closely spaced vias, it has been found that unacceptable overhangs occur on the sidewalls of the vias. Neither changes in the composition of the glass nor modifications in the processing parameters of reflow were effective to avoid the overhang phenomenon. In accordance with the invention, it has been discovered that the overhang problem can be consistently avoided if the ratio of glass thickness to via-to-via spacing is about ? 0.393.
(FIG. 2).
Abstract A glass reflow step to round off sharp edges of contact vias is typically included in processes for making integrated-circuit devices. In the course of making such devices with closely spaced vias, it has been found that unacceptable overhangs occur on the sidewalls of the vias. Neither changes in the composition of the glass nor modifications in the processing parameters of reflow were effective to avoid the overhang phenomenon. In accordance with the invention, it has been discovered that the overhang problem can be consistently avoided if the ratio of glass thickness to via-to-via spacing is about ? 0.393.
(FIG. 2).
Description
3~
CONTACT VIAS IN SEMICONDUCTOR DEVICES
Back~round oE the Invent This invention relates to microminiaturè
devices and, more particularly, to very-large-scale-integrated (VLSI~ semiconductor devices that include adielectric layer having closely spaced-apart contact vias formed therein.
Layers of glass such as phosphosilicate or borophosphosilicate glass are commonly utilized as dielectric materials in VLSI devices. After being deposited on a partially fabricated device, such a layer is typically planarized by heating the glass to cause it to flow. Contact vias or holes are then etched through the glass layer. Subsequently, a conductive pattern is formed on the planar top surface of the glass layer and in the vias to selectively connect the pattern to those portions of the device structure that directly underlie the vias.
In typical fabrication sequences, contact vias formed in glass layers by techniques such as reactive sputter (or ion) etching exhibit very steep ~near-vertical) sidewalls. Covering the sharp edges defined by the planar top surface of the glass layer and the steep via sidewalls with a continuous and uniform layer of conductive material is a challenging requirement. To facilitate such coverage, it is common practice to reflow the apertured glass layer before depositing conductive material thereon. Such reflow of the glass rounds off the aforementioned sharp edges and decreases the steepness of the sidewalls. Reflow thus ensures that subsequently deposited conductive material will make reliable electrical connections from the top surface of the glass layer through the vias to ~, , . ~
CONTACT VIAS IN SEMICONDUCTOR DEVICES
Back~round oE the Invent This invention relates to microminiaturè
devices and, more particularly, to very-large-scale-integrated (VLSI~ semiconductor devices that include adielectric layer having closely spaced-apart contact vias formed therein.
Layers of glass such as phosphosilicate or borophosphosilicate glass are commonly utilized as dielectric materials in VLSI devices. After being deposited on a partially fabricated device, such a layer is typically planarized by heating the glass to cause it to flow. Contact vias or holes are then etched through the glass layer. Subsequently, a conductive pattern is formed on the planar top surface of the glass layer and in the vias to selectively connect the pattern to those portions of the device structure that directly underlie the vias.
In typical fabrication sequences, contact vias formed in glass layers by techniques such as reactive sputter (or ion) etching exhibit very steep ~near-vertical) sidewalls. Covering the sharp edges defined by the planar top surface of the glass layer and the steep via sidewalls with a continuous and uniform layer of conductive material is a challenging requirement. To facilitate such coverage, it is common practice to reflow the apertured glass layer before depositing conductive material thereon. Such reflow of the glass rounds off the aforementioned sharp edges and decreases the steepness of the sidewalls. Reflow thus ensures that subsequently deposited conductive material will make reliable electrical connections from the top surface of the glass layer through the vias to ~, , . ~
- 2 - 12~3~Z'~
underlying portions of the clevice structure.
In the course oE fabricating VLSI devices with closely spaced vias formed in a gla99 layer, sidewall overhang in the vias was observ~d. Such overhang ~that is, bulging and, as a result, formation of a re-entrant angle at the base of a via) threatened to prevent proper contact from being achieved in the vias and, moreover, threatened to prevent the maintenance of prescribed design rules in VLSI device structures.
Attempts by workers skilled in the art to solve the overhang problem included altering the composition of the glass layer. Additionally, the parameters of the reflow process were changed. But neither approach alone or in combination succeeded in preventing the overhang phenomenon from occurring.
Preventing such overhangs is achieved by this invention.
Summary of the Invention Closely spaced contact vias with no overhangs are formed in a reflowed glass layer. Consistent achievement of such a device is based on the discovery that via overhangs will not occur as a result of reflow if the ratio of glass thickness to via-to-via spacing is established to be approximately equal to or less than 0.393. Thus, to achieve desired via features in a VLSI
devicet it is necessary to reduce the thickness of the glass layer when the spacing between vias is reduced below a specified value.
Brief Description of the Drawing FIG. l schematically depicts in idealized form a particular illustrative VLSI device to which the principles of the present invention are applicable;
FIG. 2 represents in simplified form, for a given glass thickness, a portion of a VLSI device both before and after reflow;
FIG. 3 illustrates, for the same glass thickness, the overhang problem that arises when vias are spaced too closely together;
underlying portions of the clevice structure.
In the course oE fabricating VLSI devices with closely spaced vias formed in a gla99 layer, sidewall overhang in the vias was observ~d. Such overhang ~that is, bulging and, as a result, formation of a re-entrant angle at the base of a via) threatened to prevent proper contact from being achieved in the vias and, moreover, threatened to prevent the maintenance of prescribed design rules in VLSI device structures.
Attempts by workers skilled in the art to solve the overhang problem included altering the composition of the glass layer. Additionally, the parameters of the reflow process were changed. But neither approach alone or in combination succeeded in preventing the overhang phenomenon from occurring.
Preventing such overhangs is achieved by this invention.
Summary of the Invention Closely spaced contact vias with no overhangs are formed in a reflowed glass layer. Consistent achievement of such a device is based on the discovery that via overhangs will not occur as a result of reflow if the ratio of glass thickness to via-to-via spacing is established to be approximately equal to or less than 0.393. Thus, to achieve desired via features in a VLSI
devicet it is necessary to reduce the thickness of the glass layer when the spacing between vias is reduced below a specified value.
Brief Description of the Drawing FIG. l schematically depicts in idealized form a particular illustrative VLSI device to which the principles of the present invention are applicable;
FIG. 2 represents in simplified form, for a given glass thickness, a portion of a VLSI device both before and after reflow;
FIG. 3 illustrates, for the same glass thickness, the overhang problem that arises when vias are spaced too closely together;
- 3 ~ 434~'~
FIG, ~ shows, Eox thc~ same glass thickness, the closest via-to-via spacing that can be achieved without overhang;
and FIG. 5 represents a portion oE a VLSI
device modified in accordance with the present invention to achieve, without overhang, via-to-via spacing of the dimension illustrated in FIG. 3 Detailed Description _ The particular illustrative VLSI device schematically represented in FIG. 1 is of the conventional metal-oxide-semiconductor (MOS) type. The illustrative device includes a silicon body 10 having standard source and drain regions 12 and 14 formed therein. A conventional gate electrode comprising, for example, a metallic silicide layer 16 and a doped polysilicon layer 18 overlies the top surface of the body 10 and is insulated therefrom by a relatively thin gate-oxide layer 20 made of silicon dioxide. (Metallic gate electrodes made, for example, of tungsten or molybdenum are also feasible.) The device represented in FIG. 1 also includes conventional so-called field-oxide portions 22 and 24 made of silicon dioxide. ~dditionally, a relatively thick dielectric layer 26 made, for example, of a glass material such as phosphosilicate glass, borophosphosilicate glass, germanophosphosilicate glass or arsenophosphosilicate glass covers the entire top surface of the depicted device structure. In FIG. 1, the maximum thickness of the glass layer 26 is designated t.
As is well known, the glass layer 26 of FIG. 1 is typically heated after being deposited on the device structure. During this heating step, the glass layer flows and assumes a substantially planar top surace, as indicated in FIG. 1.
1~3~ZZ
Subsequently, in standard ways such as by reactive ion (or sputter) ~tchiny, vias or through-holes are formed in selected portions oE the glass layer 26.
rrhree such vias 28, 30 and 32 are shown in FIG. 1.
~hrough these vias, conductive interconnects will be established between a conductive pattern (not shown) defined on the top surface of the layer 26 and respective underlying portions of the device structure.
In FIG. 1, the vias 28 and 32 provide access for conductive connections to the source and drain regions 12 and 14, and the via 30 provides access for connection to the depicted gate electrode. In FIG. 1, the smallest via-to-via spacing is designated s.
In practice, the vias 28, 30 and 32 included in the herein-specified typical V1SI device exhibit vertical or near-vertical sidewalls, as indicated in FIG. 1. To ensure adequate coverage of these sidewalls and of the sharp upper edges of the vias by a subsequently deposited conductive material, it is usually advantageous to heat the device structure to cause the glass layer 26 to flow again. As a result of this second heating or reflow step, the contour of the via sidewalls is modified and the aforementioned sharp edges are rounded off, in the particular way discussed in detail later below~
~ portion of the aforespecified glass layer included in the device structure of FIG. 1 is shown in simplified form in FIG. 2. For purposes of analysi~ and discussion, the apertured glass layer 26 of FIG, 1 is represented in FIG. 2 as comprising infinitely long parallel rectangular slabs 34, 36 and 38 on a substrate 40. Openings 42 and 44 between adjacent slabs correspond approximately to two adjacent vertically walled vias in a device of the type shown in FIG. 1.
Thus, the designations t (glass thickness) and s (via-to-via spacing) employed in FIG. 1 are also utilized in the simplified representation of FIG. 2.
_ 5 _ ~'~43~
The structures shown in FIGS. 1 and 2 are each characterized by an aspect ratio deeined as t/s. For the particular structure illustrated in FIG. 2, this ~atio has a value of about 0.2 Due to the action of surface tension eorces, reflow of the ylass portions shown in FIG. 2 produces a viscous movement of the glass material. More specifically, viscous flow occurs to produce minimum energy configurations.
In typical VLSI device fabrication sequences, the lines of contact between the glass portions and the underlying structure do not move during reflow. (In FIG. 2, these contact lines include Z-direction lines 46 and 48.) Moreover, the volume of glass remains constant during reflow. Therefore, it is seen that a constant curvature of the reflowed glass material will represent a minimum free surface area and therefore also a minimum-energy stable configuration. Such a stable configuration at equilibrium, for the particular case of an aspect ratio of approximately 0.2, is represented in FIG. 2 by dash line 50. And, assuming that the glass portions 34 and 38 of FIG. 2 have the same X-direction extent as the portion 36, the portions 34 and 38 will be similarly reconfigured during reflow, as respectively indicated by dash lines 52 and 54.
In practice~ it i8 considerably easier to apply a conductive covering to the reflowed glass portions represented in FIG. 2 by dash lines 50, 52 and 54 than it is to achieve adequate coverage of the portions 34, 36 and 38. Thus, reflow usually facilitates the fabrication of VLSI devices.
However, as the via-to-via-equivalent width s shown in FIG. 2 is decreased, a point is reached at which the equilibrium configuration of the reflowed glass exhibits an undesirable overhang condition. Such a condition is illustrated in FIG. 3 wherein the shapes of glass portions 56, 58 and 60 after reflow are 6~ 43~ZZ
represented by dash lines 57, 59 and 61, respectively.
The aspect ratio t/s of the glass structure depicted in FIG. 3 is approximately 0.9. It is apparent that the contours oE the glass porti~ns 56, 58 and 60 after reflow each include a siynificant ov0rhang region.
As seen in FIG. 3, these overhang or bulging portions each form a re-entrant angle at the bottoms of the openings 42 and 44.
Overhangs of the type represented in FIG. 3 considerably complicate the task of achieving reliable conductive connections in the openings 42 and 44.
Additionally, overhangs extending to the contact lines can result in transverse forces at the contact lines that can lead to contact line movement. Such movement can cause a reduction in the area of the via or even closure of the via. Furthermore, in small-via devices, these bulging overhangs may actually touch each other and thereby cause closure of the vias. For these and other reasons~ via overhangs are to be avoided in fabrication sequences aimed at achieving reliable low-cost VLSI devices.
Attempts by workers skilled in the art to make devices having glass layers with extremely small via-to-via spacings and no via overhangs have included various expedients. These have included altering the composition of the glass material and changing the parameters of the reflow step. But none of these attempts has been effective in practice to prevent the occurrence of via overhang in VLSI devices.
Applicants have discovered that sidewall overhang in vias will not occ~r after reflow if the aspect ratio t/s is maintained approximately at or below a critical value. Applicants have determined, based on the particular considerations specified later below, that this critical value is about 0.393. In other words, this value i5 the largest aspect ratio that does not result in a via overhang at equilibrium after ` ~ 7 - 1Z~3~
reElow.
It is noted that even apertured glass layers whose aspect ratios are ~ 0.393 form via overhangs during reElow. In fact, every glas~ cross section passes through a temporary condition in which an overhang occurs and every glass cross section with an aspect ratio of less than ~.5 passes through a temporary condition in which this overhang extends down to the contact line. The extent oE this latter overhang is ]0 about 0.066 times the glass thickness. But, significantly, for glass layers whose aspect ratios are 0.393, the overhang disappears completely by the time viscous flow produces the aforedescribed equilibrium minimum-energy shape.
FIG. 4 shows another simplified structure of the type depicted in FIGS. 2 and 3O For comparison purposes, the thickness t of the apertured glass layer in each of FIGS. 2 through 4 is assumed to be the same.
As previously discussed, the equivalent via-to-via spacing in FIG. 2 is sufficiently large that no via overhang exists at equilibrium after reflow. By contrast, in FIG. 3 the equivalent via-to-via spacing is so small that unacceptable via overhang does exist at equilibrium after reflow.
As indicated in the paragraph immediately below, the aspect ratio t/s of the particular structure shown in FIG. 4 is approximately 0.393. Thus, FIG~ 4 represents in effect the closest equivalent via-to-via spacing that can be achieved in a particular glass thickness without causing via overhang at equilibrium after reflow. The contours of the reflowed glass portions are indicated by dash lines 62, 64 and 66 in FIG. 4.
In the particular structure shown in FIG. 4, the cross-sectional area of the semicircle indicated by the dash line 64 is l/2 ~(s/2~2O In this limiting case for no overhang, with right angles at the aforespecified contact lines~ this area is equal to the cross-sectional area (s t) of the glass beEore reElow. The aspect ratio t/s for this specific case is therefore ~/8 or 0.393.
The simplified structure shown in FIG. ~ is consistent with observations made on actual VLSI
devices. Thus, for example, in devices having a one-micrometer (~m)-thick glass layer with a 2.5-~m via-to-via spacing (aspect ratio = 0.4), acceptable glass contours of the very type illustrated in FIG. 4 are in fact obtained at equilibrium after reflow.
On the other hand, in actual devices having a l-~m-thick glass layer with a via-to-via spacing of only about l.l ~m (aspect ratio = 0.9), unacceptable glass contours of the type shown in EIG. 3 are obtained at equilibrium after reflow.
In accordance with the principles of the present invention, otherwise ~nacceptably small via-to-via spacings are achieved in VLSI devices without the occurrence of via overhangs at equilibrium after reflow.
This is illustrated in FIG. 5 wherein the via-to-via spacing s is assumed to be equal to the spacing s shown in FIG. 3. But, in the FIG. 5 structure, the thickness t of the depicted glass layer has been purposely reduced to achieve an aspect ratio t/s approximately ~ 0.393.
Thus, for example, assume that the via-to-via spacing s shown in FIG. 5 is about 1.25 ~m. If the thickness t of the glass layer were maintained at the -previously specified illustrative value of 1 ~ml the aspect ratio of the structure would be 0.8. But, based on the discussion and analysis above, it is apparent that such a structure with an aspect ratio of 0.8 would include unacceptable via overhangs at equilibrium after reflow.
9- 1243~Z'~
In accordance with applicants' invention, a structure acceptab]e Eor a VL,SI device haviny v;a-to-via spacings of only 1.25 ~m is obtained by reducing the glass thickness t to a value such that t/s ~ 0.393.
Thus, for example, if t is established at 0.5 ~m~ the aspect ratio of the resulting structure is seen to be 0.4 which in practice is acceptable. Such a structure with a reduced glass thickness relative to the thicknesses represented in FIGS. 2 through 4 is illustrated in FIG. 5~
The necessity to reduce glass thickness in a VLSI device to achieve specified via-to-via spacings, in the manner taught by applicants, may require in practice a proportional reduction in the height of the gate electrode. Thus, by way of a specific illustrative example, and referring to FIG. 1, as the thickness t of the glass layer 26 is reduced to 0.5 ~m to achieve the aforespecified via-to-via spacinq of 1.25 ~m, it is necessary in practice to reduce the thickness of the depicted gate electrode from typical values employed in such devices. For example, the thickness of the conductive layer 16 may have to be reduced to about 0.2 ~m (from a more conventional value of about 0.3 ~m), and the thickness of the doped polysilicon layer 18 may have to be reduced to about 0.1 ~m (from a more conventional value of about Q.3 ~m). ~n overlying 0.5-~m-thick layer of glass will provide adequate coverage of such a reduced-height gate electrode.
FIG, ~ shows, Eox thc~ same glass thickness, the closest via-to-via spacing that can be achieved without overhang;
and FIG. 5 represents a portion oE a VLSI
device modified in accordance with the present invention to achieve, without overhang, via-to-via spacing of the dimension illustrated in FIG. 3 Detailed Description _ The particular illustrative VLSI device schematically represented in FIG. 1 is of the conventional metal-oxide-semiconductor (MOS) type. The illustrative device includes a silicon body 10 having standard source and drain regions 12 and 14 formed therein. A conventional gate electrode comprising, for example, a metallic silicide layer 16 and a doped polysilicon layer 18 overlies the top surface of the body 10 and is insulated therefrom by a relatively thin gate-oxide layer 20 made of silicon dioxide. (Metallic gate electrodes made, for example, of tungsten or molybdenum are also feasible.) The device represented in FIG. 1 also includes conventional so-called field-oxide portions 22 and 24 made of silicon dioxide. ~dditionally, a relatively thick dielectric layer 26 made, for example, of a glass material such as phosphosilicate glass, borophosphosilicate glass, germanophosphosilicate glass or arsenophosphosilicate glass covers the entire top surface of the depicted device structure. In FIG. 1, the maximum thickness of the glass layer 26 is designated t.
As is well known, the glass layer 26 of FIG. 1 is typically heated after being deposited on the device structure. During this heating step, the glass layer flows and assumes a substantially planar top surace, as indicated in FIG. 1.
1~3~ZZ
Subsequently, in standard ways such as by reactive ion (or sputter) ~tchiny, vias or through-holes are formed in selected portions oE the glass layer 26.
rrhree such vias 28, 30 and 32 are shown in FIG. 1.
~hrough these vias, conductive interconnects will be established between a conductive pattern (not shown) defined on the top surface of the layer 26 and respective underlying portions of the device structure.
In FIG. 1, the vias 28 and 32 provide access for conductive connections to the source and drain regions 12 and 14, and the via 30 provides access for connection to the depicted gate electrode. In FIG. 1, the smallest via-to-via spacing is designated s.
In practice, the vias 28, 30 and 32 included in the herein-specified typical V1SI device exhibit vertical or near-vertical sidewalls, as indicated in FIG. 1. To ensure adequate coverage of these sidewalls and of the sharp upper edges of the vias by a subsequently deposited conductive material, it is usually advantageous to heat the device structure to cause the glass layer 26 to flow again. As a result of this second heating or reflow step, the contour of the via sidewalls is modified and the aforementioned sharp edges are rounded off, in the particular way discussed in detail later below~
~ portion of the aforespecified glass layer included in the device structure of FIG. 1 is shown in simplified form in FIG. 2. For purposes of analysi~ and discussion, the apertured glass layer 26 of FIG, 1 is represented in FIG. 2 as comprising infinitely long parallel rectangular slabs 34, 36 and 38 on a substrate 40. Openings 42 and 44 between adjacent slabs correspond approximately to two adjacent vertically walled vias in a device of the type shown in FIG. 1.
Thus, the designations t (glass thickness) and s (via-to-via spacing) employed in FIG. 1 are also utilized in the simplified representation of FIG. 2.
_ 5 _ ~'~43~
The structures shown in FIGS. 1 and 2 are each characterized by an aspect ratio deeined as t/s. For the particular structure illustrated in FIG. 2, this ~atio has a value of about 0.2 Due to the action of surface tension eorces, reflow of the ylass portions shown in FIG. 2 produces a viscous movement of the glass material. More specifically, viscous flow occurs to produce minimum energy configurations.
In typical VLSI device fabrication sequences, the lines of contact between the glass portions and the underlying structure do not move during reflow. (In FIG. 2, these contact lines include Z-direction lines 46 and 48.) Moreover, the volume of glass remains constant during reflow. Therefore, it is seen that a constant curvature of the reflowed glass material will represent a minimum free surface area and therefore also a minimum-energy stable configuration. Such a stable configuration at equilibrium, for the particular case of an aspect ratio of approximately 0.2, is represented in FIG. 2 by dash line 50. And, assuming that the glass portions 34 and 38 of FIG. 2 have the same X-direction extent as the portion 36, the portions 34 and 38 will be similarly reconfigured during reflow, as respectively indicated by dash lines 52 and 54.
In practice~ it i8 considerably easier to apply a conductive covering to the reflowed glass portions represented in FIG. 2 by dash lines 50, 52 and 54 than it is to achieve adequate coverage of the portions 34, 36 and 38. Thus, reflow usually facilitates the fabrication of VLSI devices.
However, as the via-to-via-equivalent width s shown in FIG. 2 is decreased, a point is reached at which the equilibrium configuration of the reflowed glass exhibits an undesirable overhang condition. Such a condition is illustrated in FIG. 3 wherein the shapes of glass portions 56, 58 and 60 after reflow are 6~ 43~ZZ
represented by dash lines 57, 59 and 61, respectively.
The aspect ratio t/s of the glass structure depicted in FIG. 3 is approximately 0.9. It is apparent that the contours oE the glass porti~ns 56, 58 and 60 after reflow each include a siynificant ov0rhang region.
As seen in FIG. 3, these overhang or bulging portions each form a re-entrant angle at the bottoms of the openings 42 and 44.
Overhangs of the type represented in FIG. 3 considerably complicate the task of achieving reliable conductive connections in the openings 42 and 44.
Additionally, overhangs extending to the contact lines can result in transverse forces at the contact lines that can lead to contact line movement. Such movement can cause a reduction in the area of the via or even closure of the via. Furthermore, in small-via devices, these bulging overhangs may actually touch each other and thereby cause closure of the vias. For these and other reasons~ via overhangs are to be avoided in fabrication sequences aimed at achieving reliable low-cost VLSI devices.
Attempts by workers skilled in the art to make devices having glass layers with extremely small via-to-via spacings and no via overhangs have included various expedients. These have included altering the composition of the glass material and changing the parameters of the reflow step. But none of these attempts has been effective in practice to prevent the occurrence of via overhang in VLSI devices.
Applicants have discovered that sidewall overhang in vias will not occ~r after reflow if the aspect ratio t/s is maintained approximately at or below a critical value. Applicants have determined, based on the particular considerations specified later below, that this critical value is about 0.393. In other words, this value i5 the largest aspect ratio that does not result in a via overhang at equilibrium after ` ~ 7 - 1Z~3~
reElow.
It is noted that even apertured glass layers whose aspect ratios are ~ 0.393 form via overhangs during reElow. In fact, every glas~ cross section passes through a temporary condition in which an overhang occurs and every glass cross section with an aspect ratio of less than ~.5 passes through a temporary condition in which this overhang extends down to the contact line. The extent oE this latter overhang is ]0 about 0.066 times the glass thickness. But, significantly, for glass layers whose aspect ratios are 0.393, the overhang disappears completely by the time viscous flow produces the aforedescribed equilibrium minimum-energy shape.
FIG. 4 shows another simplified structure of the type depicted in FIGS. 2 and 3O For comparison purposes, the thickness t of the apertured glass layer in each of FIGS. 2 through 4 is assumed to be the same.
As previously discussed, the equivalent via-to-via spacing in FIG. 2 is sufficiently large that no via overhang exists at equilibrium after reflow. By contrast, in FIG. 3 the equivalent via-to-via spacing is so small that unacceptable via overhang does exist at equilibrium after reflow.
As indicated in the paragraph immediately below, the aspect ratio t/s of the particular structure shown in FIG. 4 is approximately 0.393. Thus, FIG~ 4 represents in effect the closest equivalent via-to-via spacing that can be achieved in a particular glass thickness without causing via overhang at equilibrium after reflow. The contours of the reflowed glass portions are indicated by dash lines 62, 64 and 66 in FIG. 4.
In the particular structure shown in FIG. 4, the cross-sectional area of the semicircle indicated by the dash line 64 is l/2 ~(s/2~2O In this limiting case for no overhang, with right angles at the aforespecified contact lines~ this area is equal to the cross-sectional area (s t) of the glass beEore reElow. The aspect ratio t/s for this specific case is therefore ~/8 or 0.393.
The simplified structure shown in FIG. ~ is consistent with observations made on actual VLSI
devices. Thus, for example, in devices having a one-micrometer (~m)-thick glass layer with a 2.5-~m via-to-via spacing (aspect ratio = 0.4), acceptable glass contours of the very type illustrated in FIG. 4 are in fact obtained at equilibrium after reflow.
On the other hand, in actual devices having a l-~m-thick glass layer with a via-to-via spacing of only about l.l ~m (aspect ratio = 0.9), unacceptable glass contours of the type shown in EIG. 3 are obtained at equilibrium after reflow.
In accordance with the principles of the present invention, otherwise ~nacceptably small via-to-via spacings are achieved in VLSI devices without the occurrence of via overhangs at equilibrium after reflow.
This is illustrated in FIG. 5 wherein the via-to-via spacing s is assumed to be equal to the spacing s shown in FIG. 3. But, in the FIG. 5 structure, the thickness t of the depicted glass layer has been purposely reduced to achieve an aspect ratio t/s approximately ~ 0.393.
Thus, for example, assume that the via-to-via spacing s shown in FIG. 5 is about 1.25 ~m. If the thickness t of the glass layer were maintained at the -previously specified illustrative value of 1 ~ml the aspect ratio of the structure would be 0.8. But, based on the discussion and analysis above, it is apparent that such a structure with an aspect ratio of 0.8 would include unacceptable via overhangs at equilibrium after reflow.
9- 1243~Z'~
In accordance with applicants' invention, a structure acceptab]e Eor a VL,SI device haviny v;a-to-via spacings of only 1.25 ~m is obtained by reducing the glass thickness t to a value such that t/s ~ 0.393.
Thus, for example, if t is established at 0.5 ~m~ the aspect ratio of the resulting structure is seen to be 0.4 which in practice is acceptable. Such a structure with a reduced glass thickness relative to the thicknesses represented in FIGS. 2 through 4 is illustrated in FIG. 5~
The necessity to reduce glass thickness in a VLSI device to achieve specified via-to-via spacings, in the manner taught by applicants, may require in practice a proportional reduction in the height of the gate electrode. Thus, by way of a specific illustrative example, and referring to FIG. 1, as the thickness t of the glass layer 26 is reduced to 0.5 ~m to achieve the aforespecified via-to-via spacinq of 1.25 ~m, it is necessary in practice to reduce the thickness of the depicted gate electrode from typical values employed in such devices. For example, the thickness of the conductive layer 16 may have to be reduced to about 0.2 ~m (from a more conventional value of about 0.3 ~m), and the thickness of the doped polysilicon layer 18 may have to be reduced to about 0.1 ~m (from a more conventional value of about Q.3 ~m). ~n overlying 0.5-~m-thick layer of glass will provide adequate coverage of such a reduced-height gate electrode.
Claims (6)
1. A microminiature device comprising a dielectric layer having a thickness t, said layer being made of a reflowable material, spaced-apart vias in said layer, said vias having no overhangs therein at equilibrium after reflow, the smallest spacing s between vias being approximately ? 1.75 µm, CHARACTERIZED IN THAT
t/s is approximately ? 0.393.
t/s is approximately ? 0.393.
2. A device as in claim 1 wherein said reflowable material comprises glass.
3. A device as in claim 2 wherein said reflowable glass is selected from the group consisting of phosphosilicate glass, borophosphosilicate glass, germanophosphosilicate glass and arsenophosphosilicate glass.
4. A device as in claim 1 further including a gate electrode underlying said layer, at least one of the vias in said layer exposing a portion of the top surface of said gate electrode.
5. A device as in claim 4 wherein said gate electrode comprises a metallic layer.
6. A device as in claim 5 wherein the thickness t of said dielectric layer sufficiently exceeds the thickness of said gate electrode to provide effective insulating coverage thereof.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US798,422 | 1985-11-15 | ||
| US06/798,422 US4733291A (en) | 1985-11-15 | 1985-11-15 | Contact vias in semiconductor devices |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1243422A true CA1243422A (en) | 1988-10-18 |
Family
ID=25173361
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000521705A Expired CA1243422A (en) | 1985-11-15 | 1986-10-29 | Contact vias in semiconductor devices |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US4733291A (en) |
| EP (1) | EP0223527B1 (en) |
| JP (1) | JP2599128B2 (en) |
| CA (1) | CA1243422A (en) |
| DE (1) | DE3683731D1 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4948743A (en) * | 1988-06-29 | 1990-08-14 | Matsushita Electronics Corporation | Method of manufacturing a semiconductor device |
| JPH07109873B2 (en) * | 1988-07-05 | 1995-11-22 | 株式会社東芝 | Semiconductor memory device |
| JPH02186636A (en) * | 1989-01-12 | 1990-07-20 | Seiko Epson Corp | Wiring of integrated circuit device |
| JP2783259B2 (en) * | 1996-07-18 | 1998-08-06 | 日本電気株式会社 | Semiconductor package and manufacturing method thereof |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3925572A (en) * | 1972-10-12 | 1975-12-09 | Ncr Co | Multilevel conductor structure and method |
| DE2414520A1 (en) * | 1973-07-30 | 1975-02-20 | Hitachi Ltd | Process for the production of tightly adjacent electrodes on a semiconductor substrate |
| US4192059A (en) * | 1978-06-06 | 1980-03-11 | Rockwell International Corporation | Process for and structure of high density VLSI circuits, having inherently self-aligned gates and contacts for FET devices and conducting lines |
| JPS55138874A (en) * | 1979-04-18 | 1980-10-30 | Fujitsu Ltd | Semiconductor device and method of fabricating the same |
| JPS5898934A (en) * | 1981-12-08 | 1983-06-13 | Matsushita Electronics Corp | Manufacture of semiconductor device |
| JPS593964A (en) * | 1982-06-29 | 1984-01-10 | Semiconductor Res Found | Semiconductor integrated circuit |
| US4535528A (en) * | 1983-12-02 | 1985-08-20 | Hewlett-Packard Company | Method for improving reflow of phosphosilicate glass by arsenic implantation |
| JPS60198847A (en) * | 1984-03-23 | 1985-10-08 | Nec Corp | Semiconductor device and manufacture thereof |
-
1985
- 1985-11-15 US US06/798,422 patent/US4733291A/en not_active Expired - Lifetime
-
1986
- 1986-10-29 CA CA000521705A patent/CA1243422A/en not_active Expired
- 1986-11-07 DE DE8686308709T patent/DE3683731D1/en not_active Expired - Fee Related
- 1986-11-07 EP EP86308709A patent/EP0223527B1/en not_active Expired
- 1986-11-14 JP JP61269990A patent/JP2599128B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JP2599128B2 (en) | 1997-04-09 |
| EP0223527A3 (en) | 1988-05-18 |
| EP0223527B1 (en) | 1992-01-29 |
| JPS62136858A (en) | 1987-06-19 |
| DE3683731D1 (en) | 1992-03-12 |
| US4733291A (en) | 1988-03-22 |
| EP0223527A2 (en) | 1987-05-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5930667A (en) | Method for fabricating multilevel interconnection structure for semiconductor devices | |
| EP0176010B1 (en) | Integrated circuit fabrication process and device | |
| US5576576A (en) | Above via metal-to-metal antifuse | |
| US5612252A (en) | Method of forming metallization to improve electromigration resistance | |
| KR100373804B1 (en) | Dual masking for selective gap fill of submicron interconnects | |
| US5719084A (en) | Method for the controlled formation of voids in doped glass dielectric films | |
| KR910006370B1 (en) | Method of forming holes in semiconductor intergrated circuit device | |
| US20020121651A1 (en) | Method of making a metallization line layout | |
| US5006484A (en) | Making a semiconductor device with contact holes having different depths | |
| EP0718879B1 (en) | Method of forming a landing pad structure in an integrated circuit | |
| US6136687A (en) | Method of forming air gaps for reducing interconnect capacitance | |
| JPH09199443A (en) | Method for manufacturing landing pad structure body in integrated circuit | |
| EP0558304B1 (en) | Method of forming submicron contacts | |
| US5094900A (en) | Self-aligned sloped contact | |
| CA1213075A (en) | Method for improving step coverage of dielectrics in vlsi circuits | |
| US5914518A (en) | Method of forming a metal contact to landing pad structure in an integrated circuit | |
| US6528411B2 (en) | Semiconductor device and method of its fabrication | |
| US5939335A (en) | Method for reducing stress in the metallization of an integrated circuit | |
| CA1243422A (en) | Contact vias in semiconductor devices | |
| US5578872A (en) | Planar contact with a void | |
| US6071812A (en) | Method of forming a modified metal contact opening to decrease its aspect ratio for deep sub-micron processes | |
| US4799992A (en) | Interlevel dielectric fabrication process | |
| US6107686A (en) | Interlevel dielectric structure | |
| US5663591A (en) | Antifuse with double via, spacer-defined contact | |
| US6316816B1 (en) | Film resistor and method of producing same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |