CA1247259A - Method of improving silicon-on-insulator uniformity - Google Patents
Method of improving silicon-on-insulator uniformityInfo
- Publication number
- CA1247259A CA1247259A CA000556671A CA556671A CA1247259A CA 1247259 A CA1247259 A CA 1247259A CA 000556671 A CA000556671 A CA 000556671A CA 556671 A CA556671 A CA 556671A CA 1247259 A CA1247259 A CA 1247259A
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- Canada
- Prior art keywords
- layer
- uniform thickness
- providing
- polishing
- polishing stop
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/764—Air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76275—Vertical isolation by bonding techniques
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76289—Lateral isolation by air gap
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/959—Mechanical polishing of wafer
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/97—Specified etch stop material
Abstract
ABSTRACT OF THE DISCLOSURE
A method of improving silicon-on-insulator unifor-mity using polishing. A polishing stop layer of substantially uniform thickness is provided having a first side which is made coplanar with a first side of a thicker layer of semiconductor material. A polishing process is applied to a second side of the semiconductor material until a second side of the polishing stop layer is encountered, such that the substantially uniform thickness of the polishing stop layer can be used to define the semiconductor material to a layer of uniform thickness.
A method of improving silicon-on-insulator unifor-mity using polishing. A polishing stop layer of substantially uniform thickness is provided having a first side which is made coplanar with a first side of a thicker layer of semiconductor material. A polishing process is applied to a second side of the semiconductor material until a second side of the polishing stop layer is encountered, such that the substantially uniform thickness of the polishing stop layer can be used to define the semiconductor material to a layer of uniform thickness.
Description
~2~7~59 METHOD OF IMPROVING SILICON-ON-INSULATOR UNIFORMITY
CROSS-REFERENCE TO ~ELATED APPLICATIONS
Reference is made to co-pending Canadian Patent Application Serial No. 509,373, entitled "Chem-Mech Polishing Method for Producing Coplanar Metal/Insulator Films On A Substrate," filed May 16, 1986 by Beyer et al, and assigned to the assignee of the present application.
This application is directed to forming apertures in an insulator layer, overfilling these apertures with metal, and polishing the metal back so that portions abo~e the surface of the insulator layer are removed.
Reference is made to co-pending Canadian Patent Application Serial No. ~08,583, entitled "Method For Re~oving Protuberances At The Surface Of A Semiconductor ~afer Using A Chem-Mech Polishing Technique," filed May 7, 1986 by Beyer et al, and assigned to the assignee of the present application. This application is directed to planarizing oxide protuberances by using a silicon nitride layer as an etch-stop.
Reference is made to co-pending Canadian Patent Application Serial No. 51~,222, entitled "Method For Producing Coplanar Multi-Level MetaltInsulator Films On A
Substrate And For Forming Patterne~ Conductive Lines Simultaneously With Stud ~ias," ~iled October 17, 1986 by C~ow et al, and assigned to the assignee of the present application. This application is directed to patterning a glass layer so that it simultaneously defines a wiring plane and an interconnection stud, filling the patterned glass ~ith metal so as to form the structures~ and polishing portions of the metal abo~e the sur~ace of the glass layer so that the metal is coplanar with the glass.
B~-86-010 ~725g TECHNICAL FIELD
The present invention relates to a method of improving silicon-on-insulator uniformity.
BACKGROUND ART
In the present era of very large scale integrated (VLSI) circuits, there has been a trend toward shrinking the dimensions of transistors and other semiconductor structures to facilitate greater packing densities. With this shrinkage and denser packing of semiconductor devices, substrate leakage currents and device interactions have become a concern which require some form of isolation between devices.
A number of approaches have been proposed to provide this isolation. For example, U.S. Patent No. 3,979,237, issued to Marcom et al, discloses a method of forming grooves in a semiconductor body, coating the grooves with an insulating layer, refilling the grooves with a silicon meterial, and then planarizing the top of the refilled grooves to ensure that the top of the silicon areas is planar. As a result, there are provided insulated grooves filled with semiconductor material.
A recent technology ~Yhich appears to be particularly promising in providing greater isolation is that of a silicon-on-insulator (SOI) approach. For example, IBM*
Technical Disclosure Bulletin, Volume 24, No. 9, February 19~2, authored by Chu, Tsang, and Joy, discloses a method ~here~y isolated silicon regions are embedded in indentations in a dielectric substrate.
* ~egistered trade mark ~U~-~6-010 7~59 Similarly, IBM Technical Disclosure Bulletin, Volume 27, No.
8, January 1985, authored by Silvestri, discloses a method of forming fully isolated epitaxial silicon growth regions on an insulator, which are then used to facilitate the construction of fully isolated FET, Bipolar, and MOSFET
integrated circuits. Often in achieving the desired SOI
structure, bonding methods are applied to fuse one silicon wafer to a second "Handle" wafer. Examples of these bonding methods can be seen in Laskey, "Wa er Bonding for Silicon-On-Insulator Technologies", Appl Phys. Lett., 48(1), 6 January 1986; and Laskey, Stiffer, White, Abernathey, "Silicon-On-Insulator (SOI) by Bonding and Etch-Back", IEDM
28.4, 1-4 December, 1985.
Summary Of_The Invention The present invention provides a method of polishing a silicon-on-insulator layer to satisfy the aforementioned needs.
More particularly, a silicon-on-insulator structure having improved planarity and thickness uniformity is produced by using a polishing stop layer of substantially uniform thickness. The polishing stop layer has a first surface which is coplanar with the first surface of a thicker layer of semiconductor material. The second surface of the thicker layer of semiconductor material is then chemically-mechanically polished in a planar mode to a point where the second surface of the thinner polishing stop layer ~9-~6-01~
1~7~59`
is encountered. As a result, the substantially uniform thickness of the thinner stop layer is used to deine the thicker semiconductor layer to a layer of uniform thickness.
Accordingly, the present invention relates to a process of planarizing a layer of material, comprising the steps of patterning said layer of material to form apertures therein;
forming in each of said apertures a polishing stop layer of uniform thickness which is thinner than said layer of material; and polishing said layer of material to a point where its surfaces are substantially coplanar with the surfaces of said polishing stop layer, such that said uniform thickness of said polishing stop layer is used to define said layer of material to a layer of uniform thickness.
Thus, the broad object of the present invention is to provide an improved silicon-on-insulator fabrication process.
A second object of this invention is to provide a fabrication process whereby the top surface of a silicon-on-insulator layer can be polished to a surface which is substantially planar.
It is another object of ~his invention to provide a fabrication process whereby a silicon-on-insulator layer can be constructed to have a substantially uniform thickness.
It is an additional object of the invention to provide a fabrication process ~hereby a polishing process is used to improve the uniformity of a silicon-on-insulator layer.
It is a further object of the invention to provide a ~abrication process ~hereby a thinner polishing stop layer of uniform thickness is used to define a thicker layer of semiconductor material to a layer of uniform thickness.
B~9-8~-Q10 i2~,7~59 --5~
BRIEF DESCRIPTION OF_THE: DRAWINGS
The foregoing and other advantages, structures, and teachings of the present invention will become more apparent from the following detailed description of the preferred e~.bodiment of the present invention. In the description to follow, reference will be made to the accompanying drawings, wherein:
Figure lA is a simplified cross-sectional view of a prior art silicon-on-insulator structure having a localized planar non-uniformity.
Figure lB is a simplified cross-sectional view of semiconductor devices formed from the silicon-on-insulator structure of Figure 1.
Figure 2A is a simplified cross-sectional view of silicon-on-insulator structure having a top surface which is substantially planar, and a body which is of substantially uniform thickness.
Figure 2B is a simplified cross-sectional view of semiconductor devices formea from the silicon-on-insulator structure of Figure 2A.
Figures 3A-3F are simplified cross-sectional views of a silicon-on-insulator structure being fabricated by a pre~erred embodiment of the process of the present invention.
One type of silicon-on-insulator construction with ~hich the present invention is concerned is illustrated in, and will be described with reference to, Figures lA and lB.
In Fig~re lA, a thin silicon layer 10~ is on top of a thin insulator 102. The insu~ator layer 102 can be formed of any insulating material~ and typically is silicon dioxide.
Mechanical support and integrity are also provided by formation on a support body 100, which is typically a silicon ~a~er.
BU~-~6-010 Z4~ ~'Z59 In Figure lB, the silicon-on-insulator layer of Figure lA
has been masked, etched, and otherwise processed to provide isolated devices 110, 112, 114 and 116 formed on silicon islands 120, 12~, 124, and 126, respectively. These silicon islands can be doped or otherwise treated to fabricate any of a multitude of semiconductor devices, for example, FET
amplifiers, bipolar amplifiers, MOSFETs, etc. Note that the devices are totally isolated from one another, thereby preventing stray substrate leakage currents, and also preventing undesirable interactions between devices.
Also, note that the height of the device 112 is different from the height of devices 110, 114 and 116. This non-uniformity is due to the localized planar non-uniformity 106 indicated in Figure lA. As the device 112 has a shorter silicon island 122 than the silicon islands 120, 124 and 126 of the devices 110, 114, and 116, respectively, the device 112 effectively has a smaller silicon substrate area which produces a device 112 having operational parameters different from those of the devices 110, 114, and 116. In order to facilitate construction of semiconductor devices having substantially the same operational parameters, it would be desirable to have an SOI layer which has a planar top surface and is of uniform thickness.
It is also desirable to have an SOI layer with a planar top surIace and a body of uniform thickness for several other reasons. First, projected photomask e~posures may be slightly out of focus at localized planar non-uniformities.
Second, if the tops of the resultant devices are planar, ~etalization wiring structure mask tolerances are somewhat r~lieved, and etch times to form stud-down structures to con~ect to the devices can be more accurately predicted.
sus-s6~nl0 7;~i9 Figure 2A illustrates a silicon-on-insulator (SOI) having the desired characteristics of a planar top surface and a body of uniform thickness. In particular, a silicon layer 204 is on top of the insulator layer 102 which, in turn, is provided on top o~ the support body 100. In Figure 2B, the silicon-on-insulator layer of Figure 2A has been masked, etched, and otherwise processed to provide isolated devices 210, 212, 214 and 216 constructed on uniform silicon islands 220, 222, 224, and 226, respectively. Since the silicon islands 220, 222, 224, and 226 are uniform in thickness, the devices 210, 212, 214 and 216, respectively, have su~stantially similar operating parameters. Also, as the tops of the resultant devices are substantially planar, tolerance requirements in the ena of the line processing to add a metalization wiring structure will be somewhat relaxed.
One prior art teaching which has achieved excellent results in producing a substantially uniform and planar SOI
layer is that of U.S. Patent No. 4,601,779, assigned to the present assignee, and issued to Abernathey et al. ~he resultant SOI structures by Abernathey et al serve as a preferred starting structure for the present invention.
~o~ever, there exists a need for a method which produces still greater planarity and thickness uniformity for silicon-on-insulator layers.
Description of the Preferred Embodiment Turning no~ to a description of the present invention, Figures 3A and 3F ~ill be used to illustrate and describe the processing steps in a pre~erred embodiment. It should be understood that the height, ~idth and thickness dimensions shown in Figures 3A-3F are for the sake of example and clarity only, and are BU9-8~-~10 ~7Z59 IBM DOCKET NO. BU9-86-010 not intended to designate relative or actual dimen-sions; i.e., some dimensions may be exaggerated to improve the clarity o~ the illustrations. Typical dimensions, which are known, will be revealed in the written description.
Referring now to Figure 3A, a simplified cross-section o an unprocessed prior art silicon-on-insulator structure is shown. More particularly, a silicon layer 304 is shown on an insulator layer 302 which, in turn, is on a support body 300. The insula-tor layer 302 is typically an oxide layer, and in a preferred embodiment is a silicon dioxide layer. The support body 300 provides support and integrity to the silicon-on-insulator layer, and is typically a silicon wafer. U.S. Patent No. 4,601,779, referenced pre-wiously, discloses a preferred method of forming the SOI structure illustrated in Figure 3A. Note that the silicon layer 304 has a locali~ed planar non-uniformity 306. A typical thickness non-uniformity achievable by the forming method of this prior patent would be about a 0.2 micron variation.
Also, note that the bottom or first surface of the silicon layer 304 is in contact with the top surface of the insulator layer 302. As will become more apparent ~5 in the following discussion, the top surface of the insulator layer 302 is, in efect, used as a reference plane.
Figure 3B is a simplified cross-sectional view of the silicon-on-insulator layer of Figure 3A ater it has been subjected to a first preferred processing step. More particularly, the silicon layer 304 has been processed by applying a resist layer 310 which is then masked and etched to define locations where IBM DOCKET NO. BU9-86-010 _g_ isolated silicon bodies for device constructions are desired.
Once the resist layer has been masked and defined, the silicon layer 304 is then directionally etched down S to the underlying insulator layer 302 to define the isolated silicon studs 320, 322, and 324. Any method of directionally etching the silicon layer 304 without disturbing the underlying insulator layer 302 can be used, for example, any well known RIE etch which provides a high etching selectivity between the silicon and the underlying oxide layer. An etchant providing this high etching selectivity is, in a preferred embodiment, a chlorine-based etchant.
After the etching of the silicon layer 304, the isolation re~ions formed between the silicon studs function as apertures to the underlying insulator layer 302. This function is important to the present inven-tion in that the exposed portions of the top s~rface of the insulator layer 302 are again a~ailable to be used as a reference plane.
At this point, it should be noted that the pro-cessing steps described thus far are not critical to the present invention. ~hey are merely meant to be exemplary of a preferred processing embodiment, and any method defining silicon bodies and apertures registered to the insulating ~ayer 302 could easily be substituted to achie~e excellent uniformity with the use of the present invention. Examples of alternative embodiments ~ould include silicon strips separated by etched grooves, and a silicon plane bordered by an etched moat.
Return~ng to the illustrated embodiment and Figure 3C, a thin insulator film 329 is then provided to coat ~,7~9 IBM DOCKET NO. BU9-86-010 the silicon studs, 320, 322, and 324. This insulator film 329 is important in protecting the exposed silicon stud sidewalls from chemical reactions in the process-ing steps to -follow. An example of a suitable insula-S tor film 329 would be a deposit of 200A of plasma enhanced chemical-vapor-deposited (PECVD) oxide.
Once the insulator film insulator 329 has been provided, a uniform layer 330 is directionally deposited to coat the tops of the silicon studs and the apertures th~erebetween. This layer 330 should be of uniform thic}~ess on all horizontal surfaces which are exposed. The uniform thickness of the layer within the isolation regions is important in that it will be used as a polishing stop layer to stop a polishing process.
As the polishing process will effectively be stopped at this uniform polishing stop layer, the polished silicon layer will effectively be defined`to a layer of uniorm thickness. ~ny method of dire`ctional deposition which results in a layer of uniform thickness on the horizontal surace can be used. ~or example, an evaporation process.
There are two additional constraints which must be applied to layeI 330. Eirst, as the layer 330 will be used as a polishing stop layer with which to define the polished silicon layer to a layer of uniform thickness, the conformal layer must be t~inner than the thinnest portion o the silicon layer. The second constraint is that, in order to provide an etch stop to the polishing process~ the layer 33~ must be of a material which has 3~ a polishin~ r~te w~ich is substantially slower than that o~ silicon. Examples of materials which would provide a lower polishing rate would include re~ractory metals such as tungsten, molybdenum, titanium, ~ . .
IBM DOCKET NO. BU9-86-010 tantalum, platinum, palladium, nickel and cobalt. In a preferred embodiment, a good material is tungsten which has a polishing rate ratio of approximately 200:1 when compared with-silicon. As an example of an appropriate layer, good results have been achieved by depositing 0.2 micrometers of tungsten via an evaporation process.
Once the layer 330 has been provided as illustrated in Figure 3C, note that the bottom surfaces of the layer 330 within the apertures or isolation regions are in contact with the top surface of the insulator layer 302. In effect, the bottom or first surfaces of the remaining silicon layer portions and the bottom or first surfaces of the conformal layer 330 ` lying within ~he isolation regions are made coplanar.
Thus, as mentioned previously, the underlying insulator layer 302 is, in ef~ect, u~ed as a reference plane with which to register the bottom or first surfaces of the remaini~g silicon layer and conformal layer 330 to one another.
Then, the caps of the layer 3~0 which cover the silicon studs are removed along with the resist layer portions 310. In a preferred embodiment, the caps are removed because, as was mentioned above, the conformal layer 330 is a material which has a slow polishing rate. Since the next processing step to be applied is a polishing process, unnecessary time and wear to the polishing apparatus would be encountered if the polishiny process were used to polish away the caps.
In the preferred embodiment~ the removal of the caps is accomplished via lift-off ~e.g. stripping in n-methyl pyrollidone~ of the resist layer 310. Note that~ in or~er for this lift-off method to be effective, resist 10 must be thi~ker than material 326.
~7259 IBM DOCKET NO. BU9-86-010 The resultant silicon-on-insulator structure having the caps removed is illustrated in Figure 3D.
Note in Figure 3D that the silicon stud 322 is slightly shorter than the silicon studs 320 and 324. This height variation is due to the original localized planar non-uniformity 306 which was described with reerence to Figure 3A. Also, note that the conformal layer 330 lying within the insulation regions is thinner than the shorter silicon stud 322.
10Before a polishing process is applied, experience has shown the need for further treatment of the layer 330. During experimentations using a tungsten layer 330, it was found that, unless the tungsten was annealed to improve adhesion, large pieces of the tungsten layer would be torn off during the polishing process. Thus, in a preferred embodiment, the semiconductor structure is annealed for 5 minutes at - 900C in a wet~orming gas anneal. In addition, during subsequent experimentations applying an annealing process, it was found that, unless an insulator ilm (329 in Figure 3C) was provided betwsen the tungs~en con~ormal layer 330 and the silicon studs, undesirable tungsten silicide would be formed. Thus, as described above, the insula~or film 329 is required to protect the exposed silicon sidewalls o the silicon studs ~rom undesirable chemical reactions.
~ nce the annealing process is completed, a polishing process is applied in a planar mode to the tops of the silicon studs until, in efect, an etch stop is encountared when the polishing apparatus reaches a point where it encounters the larger surface areas o~ layer 330 in the isolation regions. In genera~, the polishing process is a physical abrasion ~725'9 IBM DOCKET NO. BU9-86-010 process carried out in the presence of a slurry. A~ an example of a suitable polishing apparatus and method, during experimentations a Rodel IC40 Polishing Pad (at a pressure o approximately 1 PSI) was used to polish the wafers in the presence of a Cabosil slurry at a PH
of 10.8. "Cabosil" is the tradename of a fumed silica slurry sold by the Cabot Corp. In practice, any slurry having a high PH and having silicon, aluminium or other similar particulates should provide the~general results described below.
By using resistivity measurements during expari-mentations, it was found that 500A of tungsten was removed during 7 minutes of polishing for a polishing rate of 71A per minute. The same polishing procedure removes O.4 microns of polysilicon in 20 seconds, for a polishing rate o~ 1.33 microns per minute. These data support the calculation of a polishing rate of 200:1 for tungsten to silicon.
Once the etch-stop layer 330 is encountered and the polishing process stopped; the result is that the previous silicon studs 320, 322, and 324 have been polished down to silicon islands 370, 372, and 3i4 ~Figure 3E). ~hese silicon islands 370, 372 and 374 are of uniform thicknesses which correspond to the
CROSS-REFERENCE TO ~ELATED APPLICATIONS
Reference is made to co-pending Canadian Patent Application Serial No. 509,373, entitled "Chem-Mech Polishing Method for Producing Coplanar Metal/Insulator Films On A Substrate," filed May 16, 1986 by Beyer et al, and assigned to the assignee of the present application.
This application is directed to forming apertures in an insulator layer, overfilling these apertures with metal, and polishing the metal back so that portions abo~e the surface of the insulator layer are removed.
Reference is made to co-pending Canadian Patent Application Serial No. ~08,583, entitled "Method For Re~oving Protuberances At The Surface Of A Semiconductor ~afer Using A Chem-Mech Polishing Technique," filed May 7, 1986 by Beyer et al, and assigned to the assignee of the present application. This application is directed to planarizing oxide protuberances by using a silicon nitride layer as an etch-stop.
Reference is made to co-pending Canadian Patent Application Serial No. 51~,222, entitled "Method For Producing Coplanar Multi-Level MetaltInsulator Films On A
Substrate And For Forming Patterne~ Conductive Lines Simultaneously With Stud ~ias," ~iled October 17, 1986 by C~ow et al, and assigned to the assignee of the present application. This application is directed to patterning a glass layer so that it simultaneously defines a wiring plane and an interconnection stud, filling the patterned glass ~ith metal so as to form the structures~ and polishing portions of the metal abo~e the sur~ace of the glass layer so that the metal is coplanar with the glass.
B~-86-010 ~725g TECHNICAL FIELD
The present invention relates to a method of improving silicon-on-insulator uniformity.
BACKGROUND ART
In the present era of very large scale integrated (VLSI) circuits, there has been a trend toward shrinking the dimensions of transistors and other semiconductor structures to facilitate greater packing densities. With this shrinkage and denser packing of semiconductor devices, substrate leakage currents and device interactions have become a concern which require some form of isolation between devices.
A number of approaches have been proposed to provide this isolation. For example, U.S. Patent No. 3,979,237, issued to Marcom et al, discloses a method of forming grooves in a semiconductor body, coating the grooves with an insulating layer, refilling the grooves with a silicon meterial, and then planarizing the top of the refilled grooves to ensure that the top of the silicon areas is planar. As a result, there are provided insulated grooves filled with semiconductor material.
A recent technology ~Yhich appears to be particularly promising in providing greater isolation is that of a silicon-on-insulator (SOI) approach. For example, IBM*
Technical Disclosure Bulletin, Volume 24, No. 9, February 19~2, authored by Chu, Tsang, and Joy, discloses a method ~here~y isolated silicon regions are embedded in indentations in a dielectric substrate.
* ~egistered trade mark ~U~-~6-010 7~59 Similarly, IBM Technical Disclosure Bulletin, Volume 27, No.
8, January 1985, authored by Silvestri, discloses a method of forming fully isolated epitaxial silicon growth regions on an insulator, which are then used to facilitate the construction of fully isolated FET, Bipolar, and MOSFET
integrated circuits. Often in achieving the desired SOI
structure, bonding methods are applied to fuse one silicon wafer to a second "Handle" wafer. Examples of these bonding methods can be seen in Laskey, "Wa er Bonding for Silicon-On-Insulator Technologies", Appl Phys. Lett., 48(1), 6 January 1986; and Laskey, Stiffer, White, Abernathey, "Silicon-On-Insulator (SOI) by Bonding and Etch-Back", IEDM
28.4, 1-4 December, 1985.
Summary Of_The Invention The present invention provides a method of polishing a silicon-on-insulator layer to satisfy the aforementioned needs.
More particularly, a silicon-on-insulator structure having improved planarity and thickness uniformity is produced by using a polishing stop layer of substantially uniform thickness. The polishing stop layer has a first surface which is coplanar with the first surface of a thicker layer of semiconductor material. The second surface of the thicker layer of semiconductor material is then chemically-mechanically polished in a planar mode to a point where the second surface of the thinner polishing stop layer ~9-~6-01~
1~7~59`
is encountered. As a result, the substantially uniform thickness of the thinner stop layer is used to deine the thicker semiconductor layer to a layer of uniform thickness.
Accordingly, the present invention relates to a process of planarizing a layer of material, comprising the steps of patterning said layer of material to form apertures therein;
forming in each of said apertures a polishing stop layer of uniform thickness which is thinner than said layer of material; and polishing said layer of material to a point where its surfaces are substantially coplanar with the surfaces of said polishing stop layer, such that said uniform thickness of said polishing stop layer is used to define said layer of material to a layer of uniform thickness.
Thus, the broad object of the present invention is to provide an improved silicon-on-insulator fabrication process.
A second object of this invention is to provide a fabrication process whereby the top surface of a silicon-on-insulator layer can be polished to a surface which is substantially planar.
It is another object of ~his invention to provide a fabrication process whereby a silicon-on-insulator layer can be constructed to have a substantially uniform thickness.
It is an additional object of the invention to provide a fabrication process ~hereby a polishing process is used to improve the uniformity of a silicon-on-insulator layer.
It is a further object of the invention to provide a ~abrication process ~hereby a thinner polishing stop layer of uniform thickness is used to define a thicker layer of semiconductor material to a layer of uniform thickness.
B~9-8~-Q10 i2~,7~59 --5~
BRIEF DESCRIPTION OF_THE: DRAWINGS
The foregoing and other advantages, structures, and teachings of the present invention will become more apparent from the following detailed description of the preferred e~.bodiment of the present invention. In the description to follow, reference will be made to the accompanying drawings, wherein:
Figure lA is a simplified cross-sectional view of a prior art silicon-on-insulator structure having a localized planar non-uniformity.
Figure lB is a simplified cross-sectional view of semiconductor devices formed from the silicon-on-insulator structure of Figure 1.
Figure 2A is a simplified cross-sectional view of silicon-on-insulator structure having a top surface which is substantially planar, and a body which is of substantially uniform thickness.
Figure 2B is a simplified cross-sectional view of semiconductor devices formea from the silicon-on-insulator structure of Figure 2A.
Figures 3A-3F are simplified cross-sectional views of a silicon-on-insulator structure being fabricated by a pre~erred embodiment of the process of the present invention.
One type of silicon-on-insulator construction with ~hich the present invention is concerned is illustrated in, and will be described with reference to, Figures lA and lB.
In Fig~re lA, a thin silicon layer 10~ is on top of a thin insulator 102. The insu~ator layer 102 can be formed of any insulating material~ and typically is silicon dioxide.
Mechanical support and integrity are also provided by formation on a support body 100, which is typically a silicon ~a~er.
BU~-~6-010 Z4~ ~'Z59 In Figure lB, the silicon-on-insulator layer of Figure lA
has been masked, etched, and otherwise processed to provide isolated devices 110, 112, 114 and 116 formed on silicon islands 120, 12~, 124, and 126, respectively. These silicon islands can be doped or otherwise treated to fabricate any of a multitude of semiconductor devices, for example, FET
amplifiers, bipolar amplifiers, MOSFETs, etc. Note that the devices are totally isolated from one another, thereby preventing stray substrate leakage currents, and also preventing undesirable interactions between devices.
Also, note that the height of the device 112 is different from the height of devices 110, 114 and 116. This non-uniformity is due to the localized planar non-uniformity 106 indicated in Figure lA. As the device 112 has a shorter silicon island 122 than the silicon islands 120, 124 and 126 of the devices 110, 114, and 116, respectively, the device 112 effectively has a smaller silicon substrate area which produces a device 112 having operational parameters different from those of the devices 110, 114, and 116. In order to facilitate construction of semiconductor devices having substantially the same operational parameters, it would be desirable to have an SOI layer which has a planar top surface and is of uniform thickness.
It is also desirable to have an SOI layer with a planar top surIace and a body of uniform thickness for several other reasons. First, projected photomask e~posures may be slightly out of focus at localized planar non-uniformities.
Second, if the tops of the resultant devices are planar, ~etalization wiring structure mask tolerances are somewhat r~lieved, and etch times to form stud-down structures to con~ect to the devices can be more accurately predicted.
sus-s6~nl0 7;~i9 Figure 2A illustrates a silicon-on-insulator (SOI) having the desired characteristics of a planar top surface and a body of uniform thickness. In particular, a silicon layer 204 is on top of the insulator layer 102 which, in turn, is provided on top o~ the support body 100. In Figure 2B, the silicon-on-insulator layer of Figure 2A has been masked, etched, and otherwise processed to provide isolated devices 210, 212, 214 and 216 constructed on uniform silicon islands 220, 222, 224, and 226, respectively. Since the silicon islands 220, 222, 224, and 226 are uniform in thickness, the devices 210, 212, 214 and 216, respectively, have su~stantially similar operating parameters. Also, as the tops of the resultant devices are substantially planar, tolerance requirements in the ena of the line processing to add a metalization wiring structure will be somewhat relaxed.
One prior art teaching which has achieved excellent results in producing a substantially uniform and planar SOI
layer is that of U.S. Patent No. 4,601,779, assigned to the present assignee, and issued to Abernathey et al. ~he resultant SOI structures by Abernathey et al serve as a preferred starting structure for the present invention.
~o~ever, there exists a need for a method which produces still greater planarity and thickness uniformity for silicon-on-insulator layers.
Description of the Preferred Embodiment Turning no~ to a description of the present invention, Figures 3A and 3F ~ill be used to illustrate and describe the processing steps in a pre~erred embodiment. It should be understood that the height, ~idth and thickness dimensions shown in Figures 3A-3F are for the sake of example and clarity only, and are BU9-8~-~10 ~7Z59 IBM DOCKET NO. BU9-86-010 not intended to designate relative or actual dimen-sions; i.e., some dimensions may be exaggerated to improve the clarity o~ the illustrations. Typical dimensions, which are known, will be revealed in the written description.
Referring now to Figure 3A, a simplified cross-section o an unprocessed prior art silicon-on-insulator structure is shown. More particularly, a silicon layer 304 is shown on an insulator layer 302 which, in turn, is on a support body 300. The insula-tor layer 302 is typically an oxide layer, and in a preferred embodiment is a silicon dioxide layer. The support body 300 provides support and integrity to the silicon-on-insulator layer, and is typically a silicon wafer. U.S. Patent No. 4,601,779, referenced pre-wiously, discloses a preferred method of forming the SOI structure illustrated in Figure 3A. Note that the silicon layer 304 has a locali~ed planar non-uniformity 306. A typical thickness non-uniformity achievable by the forming method of this prior patent would be about a 0.2 micron variation.
Also, note that the bottom or first surface of the silicon layer 304 is in contact with the top surface of the insulator layer 302. As will become more apparent ~5 in the following discussion, the top surface of the insulator layer 302 is, in efect, used as a reference plane.
Figure 3B is a simplified cross-sectional view of the silicon-on-insulator layer of Figure 3A ater it has been subjected to a first preferred processing step. More particularly, the silicon layer 304 has been processed by applying a resist layer 310 which is then masked and etched to define locations where IBM DOCKET NO. BU9-86-010 _g_ isolated silicon bodies for device constructions are desired.
Once the resist layer has been masked and defined, the silicon layer 304 is then directionally etched down S to the underlying insulator layer 302 to define the isolated silicon studs 320, 322, and 324. Any method of directionally etching the silicon layer 304 without disturbing the underlying insulator layer 302 can be used, for example, any well known RIE etch which provides a high etching selectivity between the silicon and the underlying oxide layer. An etchant providing this high etching selectivity is, in a preferred embodiment, a chlorine-based etchant.
After the etching of the silicon layer 304, the isolation re~ions formed between the silicon studs function as apertures to the underlying insulator layer 302. This function is important to the present inven-tion in that the exposed portions of the top s~rface of the insulator layer 302 are again a~ailable to be used as a reference plane.
At this point, it should be noted that the pro-cessing steps described thus far are not critical to the present invention. ~hey are merely meant to be exemplary of a preferred processing embodiment, and any method defining silicon bodies and apertures registered to the insulating ~ayer 302 could easily be substituted to achie~e excellent uniformity with the use of the present invention. Examples of alternative embodiments ~ould include silicon strips separated by etched grooves, and a silicon plane bordered by an etched moat.
Return~ng to the illustrated embodiment and Figure 3C, a thin insulator film 329 is then provided to coat ~,7~9 IBM DOCKET NO. BU9-86-010 the silicon studs, 320, 322, and 324. This insulator film 329 is important in protecting the exposed silicon stud sidewalls from chemical reactions in the process-ing steps to -follow. An example of a suitable insula-S tor film 329 would be a deposit of 200A of plasma enhanced chemical-vapor-deposited (PECVD) oxide.
Once the insulator film insulator 329 has been provided, a uniform layer 330 is directionally deposited to coat the tops of the silicon studs and the apertures th~erebetween. This layer 330 should be of uniform thic}~ess on all horizontal surfaces which are exposed. The uniform thickness of the layer within the isolation regions is important in that it will be used as a polishing stop layer to stop a polishing process.
As the polishing process will effectively be stopped at this uniform polishing stop layer, the polished silicon layer will effectively be defined`to a layer of uniorm thickness. ~ny method of dire`ctional deposition which results in a layer of uniform thickness on the horizontal surace can be used. ~or example, an evaporation process.
There are two additional constraints which must be applied to layeI 330. Eirst, as the layer 330 will be used as a polishing stop layer with which to define the polished silicon layer to a layer of uniform thickness, the conformal layer must be t~inner than the thinnest portion o the silicon layer. The second constraint is that, in order to provide an etch stop to the polishing process~ the layer 33~ must be of a material which has 3~ a polishin~ r~te w~ich is substantially slower than that o~ silicon. Examples of materials which would provide a lower polishing rate would include re~ractory metals such as tungsten, molybdenum, titanium, ~ . .
IBM DOCKET NO. BU9-86-010 tantalum, platinum, palladium, nickel and cobalt. In a preferred embodiment, a good material is tungsten which has a polishing rate ratio of approximately 200:1 when compared with-silicon. As an example of an appropriate layer, good results have been achieved by depositing 0.2 micrometers of tungsten via an evaporation process.
Once the layer 330 has been provided as illustrated in Figure 3C, note that the bottom surfaces of the layer 330 within the apertures or isolation regions are in contact with the top surface of the insulator layer 302. In effect, the bottom or first surfaces of the remaining silicon layer portions and the bottom or first surfaces of the conformal layer 330 ` lying within ~he isolation regions are made coplanar.
Thus, as mentioned previously, the underlying insulator layer 302 is, in ef~ect, u~ed as a reference plane with which to register the bottom or first surfaces of the remaini~g silicon layer and conformal layer 330 to one another.
Then, the caps of the layer 3~0 which cover the silicon studs are removed along with the resist layer portions 310. In a preferred embodiment, the caps are removed because, as was mentioned above, the conformal layer 330 is a material which has a slow polishing rate. Since the next processing step to be applied is a polishing process, unnecessary time and wear to the polishing apparatus would be encountered if the polishiny process were used to polish away the caps.
In the preferred embodiment~ the removal of the caps is accomplished via lift-off ~e.g. stripping in n-methyl pyrollidone~ of the resist layer 310. Note that~ in or~er for this lift-off method to be effective, resist 10 must be thi~ker than material 326.
~7259 IBM DOCKET NO. BU9-86-010 The resultant silicon-on-insulator structure having the caps removed is illustrated in Figure 3D.
Note in Figure 3D that the silicon stud 322 is slightly shorter than the silicon studs 320 and 324. This height variation is due to the original localized planar non-uniformity 306 which was described with reerence to Figure 3A. Also, note that the conformal layer 330 lying within the insulation regions is thinner than the shorter silicon stud 322.
10Before a polishing process is applied, experience has shown the need for further treatment of the layer 330. During experimentations using a tungsten layer 330, it was found that, unless the tungsten was annealed to improve adhesion, large pieces of the tungsten layer would be torn off during the polishing process. Thus, in a preferred embodiment, the semiconductor structure is annealed for 5 minutes at - 900C in a wet~orming gas anneal. In addition, during subsequent experimentations applying an annealing process, it was found that, unless an insulator ilm (329 in Figure 3C) was provided betwsen the tungs~en con~ormal layer 330 and the silicon studs, undesirable tungsten silicide would be formed. Thus, as described above, the insula~or film 329 is required to protect the exposed silicon sidewalls o the silicon studs ~rom undesirable chemical reactions.
~ nce the annealing process is completed, a polishing process is applied in a planar mode to the tops of the silicon studs until, in efect, an etch stop is encountared when the polishing apparatus reaches a point where it encounters the larger surface areas o~ layer 330 in the isolation regions. In genera~, the polishing process is a physical abrasion ~725'9 IBM DOCKET NO. BU9-86-010 process carried out in the presence of a slurry. A~ an example of a suitable polishing apparatus and method, during experimentations a Rodel IC40 Polishing Pad (at a pressure o approximately 1 PSI) was used to polish the wafers in the presence of a Cabosil slurry at a PH
of 10.8. "Cabosil" is the tradename of a fumed silica slurry sold by the Cabot Corp. In practice, any slurry having a high PH and having silicon, aluminium or other similar particulates should provide the~general results described below.
By using resistivity measurements during expari-mentations, it was found that 500A of tungsten was removed during 7 minutes of polishing for a polishing rate of 71A per minute. The same polishing procedure removes O.4 microns of polysilicon in 20 seconds, for a polishing rate o~ 1.33 microns per minute. These data support the calculation of a polishing rate of 200:1 for tungsten to silicon.
Once the etch-stop layer 330 is encountered and the polishing process stopped; the result is that the previous silicon studs 320, 322, and 324 have been polished down to silicon islands 370, 372, and 3i4 ~Figure 3E). ~hese silicon islands 370, 372 and 374 are of uniform thicknesses which correspond to the
2~ uniform thickness of layer 330 provided in the isolation regions. Thus, it can be seen that the uniorm thickness of layer 330, which was provided in the isolation regions, is used as an exclusive function with which to define the thickness uniformity of the remainin~ silicon layer. As tha thickness of layer 330 can be highly controlled during the deposition process, the thickness of the polished silicon layers can, therefore, also ~e highly controlled. Thus, there is ~7~59 IBM DOCKET NO. BU9-86-010 provided a method whereby a uniform layer o~ slow polishing material can be used to mechanically stop a polishing process, such that thicker silicon layers can be polished to a layer o~ uniform thickness.
Once the silicon studs 320, 322, and 324 have been polished down to silicon islands 370, ~72, and 374 respectively, the remaining conformal layer 330 in the isolation regions, and the insulator films 329, are removed, thereby leaving isolated silicon islands with exposed sidewalls, thus facilitating sidewall implanta-tion, passivation, and processing in the usual manner.
In the final Figure 3F, the conformal layer 330 and the insulator films 329 are shown removed, and the silicon islands 370, 372, and 374 have been further processed to provide the devices 390, 392, and 394, respectively.
The fabrication process o~ the present invention and many of its attendant advantages will be understood ~rom the foregoing description of ~ preferred embodi-ment, and it will be apparent that various changes may be made in the form, construction and arrangement of the parts thereof, without departing from the spirit and scope of ~he invention which is defined and limited only ~y the ~ollowing claims.
Once the silicon studs 320, 322, and 324 have been polished down to silicon islands 370, ~72, and 374 respectively, the remaining conformal layer 330 in the isolation regions, and the insulator films 329, are removed, thereby leaving isolated silicon islands with exposed sidewalls, thus facilitating sidewall implanta-tion, passivation, and processing in the usual manner.
In the final Figure 3F, the conformal layer 330 and the insulator films 329 are shown removed, and the silicon islands 370, 372, and 374 have been further processed to provide the devices 390, 392, and 394, respectively.
The fabrication process o~ the present invention and many of its attendant advantages will be understood ~rom the foregoing description of ~ preferred embodi-ment, and it will be apparent that various changes may be made in the form, construction and arrangement of the parts thereof, without departing from the spirit and scope of ~he invention which is defined and limited only ~y the ~ollowing claims.
Claims (23)
1. A process of planarizing a layer of material, comprising the steps of:
patterning said layer of material to form aper-tures therein;
forming in each of said apertures a polishing stop layer of uniform thickness which is thinner than said layer of material; and polishing said layer of material to a point where its surfaces are substantially coplanar with the surfaces of said polishing stop layer> such that said uniform thickness of said polishing stop layer is used to define said layer of material to a layer of uniform thickness.
patterning said layer of material to form aper-tures therein;
forming in each of said apertures a polishing stop layer of uniform thickness which is thinner than said layer of material; and polishing said layer of material to a point where its surfaces are substantially coplanar with the surfaces of said polishing stop layer> such that said uniform thickness of said polishing stop layer is used to define said layer of material to a layer of uniform thickness.
2. A method of improving the thickness uni-formity of a layer of material, comprising the steps of:
applying a layer of material to a support struc-ture having a substantially planar surface to be used as a reference plane;
providing apertures in said layer of material to expose portions of said reference plane;
applying to said reference plane, through each of said apertures, a conformal layer of polishing stop material of uniform thickness, the thickness of said conformal layer being thinner than said layer of material; and polishing said layer of material in a planar mode to a point where it is substantially coplanar with the surface of said polishing stop material, such that the substantially uniform thickness of said conformal polishing stop layer is used to define said layer of material to a layer of uniform thickness.
IBM DOCKET NO. BU9-86-010
applying a layer of material to a support struc-ture having a substantially planar surface to be used as a reference plane;
providing apertures in said layer of material to expose portions of said reference plane;
applying to said reference plane, through each of said apertures, a conformal layer of polishing stop material of uniform thickness, the thickness of said conformal layer being thinner than said layer of material; and polishing said layer of material in a planar mode to a point where it is substantially coplanar with the surface of said polishing stop material, such that the substantially uniform thickness of said conformal polishing stop layer is used to define said layer of material to a layer of uniform thickness.
IBM DOCKET NO. BU9-86-010
3. A method of providing a layer of semiconduc-tor material of uniform thickness, comprising the steps of:
providing a layer of semiconductor material on a substrate, said material having at least at first surface and a second surface, said second surface extending above the level of said first surface;
providing a polishing stop layer of uniform thickness having an upper surface which is substantially coplanar with said first surface of said layer of semiconductor material; and polishing said second surface of said thicker layer of semiconductor material until said upper surface of said polishing stop layer is encountered, such that the uniform thickness of said polishing stop layer is used to define said layer of semiconductor material to a layer of uniform thickness.
providing a layer of semiconductor material on a substrate, said material having at least at first surface and a second surface, said second surface extending above the level of said first surface;
providing a polishing stop layer of uniform thickness having an upper surface which is substantially coplanar with said first surface of said layer of semiconductor material; and polishing said second surface of said thicker layer of semiconductor material until said upper surface of said polishing stop layer is encountered, such that the uniform thickness of said polishing stop layer is used to define said layer of semiconductor material to a layer of uniform thickness.
4. A method of providing a layer of semiconduc-tor material of uniform thickness, comprising the steps of:
providing a layer of semiconductor material on portions of a reference plane;
providing a polishing stop layer of substantially uniform thickness on different portions of said refer-ence plane such that a first surface of said layer of semiconductor material and a first surface of said polishing stop layer are substantially coplanar, said polishing stop layer being thinner than said layer of semiconductor material; and polishing the second surface of said layer of semiconductor material in a planar mode to a point where a second surface of said polishing stop layer is encountered, such that the substantially uniform IBM DOCKET NO. BU9-86-010 thickness of said polishing stop layer is used to define said layer of semiconductor material to a layer of uniform thickness.
providing a layer of semiconductor material on portions of a reference plane;
providing a polishing stop layer of substantially uniform thickness on different portions of said refer-ence plane such that a first surface of said layer of semiconductor material and a first surface of said polishing stop layer are substantially coplanar, said polishing stop layer being thinner than said layer of semiconductor material; and polishing the second surface of said layer of semiconductor material in a planar mode to a point where a second surface of said polishing stop layer is encountered, such that the substantially uniform IBM DOCKET NO. BU9-86-010 thickness of said polishing stop layer is used to define said layer of semiconductor material to a layer of uniform thickness.
5. A method of providing a layer of semiconduc-tor material of uniform thickness, comprising the steps of:
providing a support structure having a substan-tially planar surface representing a reference plane;
providing a layer of semiconductor material on portions of said reference plane;
providing a polishing stop layer of substantially uniform thickness on different portions of said refer-ence plane such that a first surface of said semicon-ductor material and a first surface of said polishing stop layer are substantially coplanar, said polish stop layer being thinner than said layer of semiconductor material; and polishing the second surface of said layer of semiconductor material in a planar mode to a point where a second surface of said polishing stop layer is encountered, such that the substantially uniform thickness of said polishing stop layer is used to define said semiconductor material to a layer of substantially uniform thickness.
providing a support structure having a substan-tially planar surface representing a reference plane;
providing a layer of semiconductor material on portions of said reference plane;
providing a polishing stop layer of substantially uniform thickness on different portions of said refer-ence plane such that a first surface of said semicon-ductor material and a first surface of said polishing stop layer are substantially coplanar, said polish stop layer being thinner than said layer of semiconductor material; and polishing the second surface of said layer of semiconductor material in a planar mode to a point where a second surface of said polishing stop layer is encountered, such that the substantially uniform thickness of said polishing stop layer is used to define said semiconductor material to a layer of substantially uniform thickness.
6. A method of providing a layer of semiconduc-tor material of uniform thickness, comprising the steps of:
providing a layer of semiconductor material on portions of a reference plane, leaving other portions of said reference plane exposed;
applying a conformal polishing stop layer of a substantially uniform thickness to said exposed por-tions of said reference plane, such that a first IBM DOCKET NO. BU9-86-010 surface of said layer of semiconductor material and a first surface of said conformal polishing stop layer are substantially coplanar, said conformal polishing stop layer being thinner than said semiconductor material; and polishing a second surface of said layer of semiconductor material in a planar mode to a point where a second surface of said conformal stop layer is encountered, such that the substantially uniform thickness of said conformal stop layer is used to define said semiconductor material to a layer of substantially uniform thickness.
providing a layer of semiconductor material on portions of a reference plane, leaving other portions of said reference plane exposed;
applying a conformal polishing stop layer of a substantially uniform thickness to said exposed por-tions of said reference plane, such that a first IBM DOCKET NO. BU9-86-010 surface of said layer of semiconductor material and a first surface of said conformal polishing stop layer are substantially coplanar, said conformal polishing stop layer being thinner than said semiconductor material; and polishing a second surface of said layer of semiconductor material in a planar mode to a point where a second surface of said conformal stop layer is encountered, such that the substantially uniform thickness of said conformal stop layer is used to define said semiconductor material to a layer of substantially uniform thickness.
7. A method of providing a layer of semiconduc-tor material of uniform thickness, comprising the steps of:
providing a layer of semiconductor material on portions of a reference plane, leaving other portions of said reference plane exposed;
applying a conformal polishing stop layer of a substantially uniform thickness upon said semiconductor material and said exposed portions of said reference plane, such that a first surface of said layer of semiconductor malarial and a first surface of said conformal polishing stop layer on said exposed portions of said reference plane are substantially coplanar, said conformal polishing stop layer being thinner than said semiconductor material;
removing portions of said conformal polishing stop layer from a second surface of said layer of semicon-ductor material; and polishing said second surface of said layer of semiconductor material to a point where a second surface of said conformal polishing stop layer on said IBM DOCKET NO. BU9-86-010 exposed portions of said reference plane is encoun-tered, such that the substantially uniform thickness of said conformal polishing stop layer on said exposed portions of said reference plane are used to define said semiconductor material to a layer of uniform thickness.
providing a layer of semiconductor material on portions of a reference plane, leaving other portions of said reference plane exposed;
applying a conformal polishing stop layer of a substantially uniform thickness upon said semiconductor material and said exposed portions of said reference plane, such that a first surface of said layer of semiconductor malarial and a first surface of said conformal polishing stop layer on said exposed portions of said reference plane are substantially coplanar, said conformal polishing stop layer being thinner than said semiconductor material;
removing portions of said conformal polishing stop layer from a second surface of said layer of semicon-ductor material; and polishing said second surface of said layer of semiconductor material to a point where a second surface of said conformal polishing stop layer on said IBM DOCKET NO. BU9-86-010 exposed portions of said reference plane is encoun-tered, such that the substantially uniform thickness of said conformal polishing stop layer on said exposed portions of said reference plane are used to define said semiconductor material to a layer of uniform thickness.
8. A method of providing a layer of semiconduc-tor material of uniform thickness, as claimed in Claim 7, wherein said polishing step comprises a physical abrasion process carried out in the presence of a slurry.
9. A method providing a layer of semiconductor material of uniform thickness, as claimed in Claim 8, wherein said slurry has a PH of greater than 7.
10. A method of providing a layer of semiconduc-tor material of uniform thickness, as claimed in Claim 9, wherein said slurry has silicon particulates.
11. A method of providing a layer of semiconduc-tor material of uniform thickness, as claimed in Claim 8, wherein said semiconductor material is silicon, and wherein said polishing stop layer is composed of a material which has polishing rate which is substantially slower than that of silicon.
12. A method of providing a layer of semiconduc-for material of uniform thickness, as claimed in Claim 7, wherein said polishing stop layer is selected from the group consisting of tungsten, millennium, titanium, tantalum, platinum, palladium, nickel and cobalt.
13. A method of providing a layer of semiconduc-tor material of uniform thickness, as claimed in Claim 7, wherein said polishing stop layer is made of tung-sten.
IBM DOCKET NO. BU9-86-010
IBM DOCKET NO. BU9-86-010
14. A method of providing a layer of semiconduc-tor material of uniform thickness, as claimed in Claim 13, wherein said polishing stop layer is subject to an annealing process prior to said polishing step.
15. A method of providing a layer of semiconduc-tor material of uniform thickness, as claimed in Claim 7, wherein said reference plane is the surface of a silicon dioxide layer.
16. A method of providing a layer of semiconduc-tor material of uniform thickness, as claimed in Claim 7, wherein said polishing stop layer is applied by evaporation.
17. A method of providing a layer of semiconduc-tor material of uniform thickness, as claimed in Claim 7, comprising the step of providing an insulator film on exposed portions of said semiconductor material before said applying step, to prevent chemical reaction between said semiconductor material and material of said polishing stop layer.
18. A method of providing a layer of semiconduc-tor material of uniform thickness, as claimed in Claim 7, wherein said portions of said polishing stop layer are removed by using a lift-off process.
19. A method of providing a layer of semiconduc-tor material of uniform thickness, as claimed in Claim 7, wherein said layer of semiconductor material on the portions of the reference plane are provided in the form of semiconductor studs separated by isolation regions.
20. A method of providing a layer of semiconduc-tor material of uniform thickness, as claimed in Claim 7, wherein said layer of semiconductor material on the portions of the reference plane are provided in the IBM DOCKET NO. BU9-86-010 form of semiconductor bodies bordered by isolation regions.
21. A method of providing a layer of semiconduc-tor material of uniform thickness, as claimed in Claim 7, wherein said layer of semiconductor material on the portions of the reference plane are provided in the form of semiconductor sheets separated by isolation regions.
22. A method of providing a layer of semiconduc-tor material of uniform thickness, as claimed in Claim 71 wherein said layer of semiconductor material on the portions of the reference plane are provided in the form of semiconductor strips separated by isolation regions.
23. A method as claimed in Claim 7 further comprising the step of removing the remaining portions of said stop layer from said reference plane.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US031,809 | 1987-03-30 | ||
| US07/031,809 US4735679A (en) | 1987-03-30 | 1987-03-30 | Method of improving silicon-on-insulator uniformity |
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| CA1247259A true CA1247259A (en) | 1988-12-20 |
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| CA000556671A Expired CA1247259A (en) | 1987-03-30 | 1988-01-15 | Method of improving silicon-on-insulator uniformity |
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| NL8700033A (en) * | 1987-01-09 | 1988-08-01 | Philips Nv | METHOD FOR MANUFACTURING A SEMICONDUCTOR SEMICONDUCTOR TYPE ON ISOLATOR |
| NL8800953A (en) * | 1988-04-13 | 1989-11-01 | Philips Nv | METHOD FOR MANUFACTURING A SEMICONDUCTOR BODY |
| EP0368584B1 (en) * | 1988-11-09 | 1997-03-19 | Sony Corporation | Method of manufacturing a semiconductor wafer |
| US4874463A (en) * | 1988-12-23 | 1989-10-17 | At&T Bell Laboratories | Integrated circuits from wafers having improved flatness |
| FR2651068B1 (en) * | 1989-08-16 | 1994-06-10 | France Etat | PROCESS FOR PRODUCING SILICON-ON-INSULATOR MOS MESA TRANSISTOR |
| US5110755A (en) * | 1990-01-04 | 1992-05-05 | Westinghouse Electric Corp. | Process for forming a component insulator on a silicon substrate |
| US5142828A (en) * | 1990-06-25 | 1992-09-01 | Microelectronics And Computer Technology Corporation | Correcting a defective metallization layer on an electronic component by polishing |
| US5085015A (en) * | 1990-06-26 | 1992-02-04 | E. I. Du Pont De Nemours And Company | Process for improving the surface of liquid crystal polymers |
| US5055158A (en) * | 1990-09-25 | 1991-10-08 | International Business Machines Corporation | Planarization of Josephson integrated circuit |
| JP3362397B2 (en) * | 1991-03-28 | 2003-01-07 | ソニー株式会社 | Manufacturing method of electronic device including polishing step by polishing |
| US5137597A (en) * | 1991-04-11 | 1992-08-11 | Microelectronics And Computer Technology Corporation | Fabrication of metal pillars in an electronic component using polishing |
| JP2833305B2 (en) * | 1991-12-05 | 1998-12-09 | 富士通株式会社 | Semiconductor substrate manufacturing method |
| JP3141486B2 (en) * | 1992-01-27 | 2001-03-05 | ソニー株式会社 | Semiconductor device |
| US5314843A (en) * | 1992-03-27 | 1994-05-24 | Micron Technology, Inc. | Integrated circuit polishing method |
| JP3060714B2 (en) * | 1992-04-15 | 2000-07-10 | 日本電気株式会社 | Manufacturing method of semiconductor integrated circuit |
| US5334281A (en) * | 1992-04-30 | 1994-08-02 | International Business Machines Corporation | Method of forming thin silicon mesas having uniform thickness |
| US5258318A (en) * | 1992-05-15 | 1993-11-02 | International Business Machines Corporation | Method of forming a BiCMOS SOI wafer having thin and thick SOI regions of silicon |
| US5445996A (en) * | 1992-05-26 | 1995-08-29 | Kabushiki Kaisha Toshiba | Method for planarizing a semiconductor device having a amorphous layer |
| US5264387A (en) * | 1992-10-27 | 1993-11-23 | International Business Machines Corporation | Method of forming uniformly thin, isolated silicon mesas on an insulating substrate |
| US5234868A (en) * | 1992-10-29 | 1993-08-10 | International Business Machines Corporation | Method for determining planarization endpoint during chemical-mechanical polishing |
| JPH07111962B2 (en) * | 1992-11-27 | 1995-11-29 | 日本電気株式会社 | Selective flattening polishing method |
| JPH06232141A (en) * | 1992-12-07 | 1994-08-19 | Sony Corp | Manufacture of semiconductor substrate and solid-state image pick up device |
| US5262346A (en) * | 1992-12-16 | 1993-11-16 | International Business Machines Corporation | Nitride polish stop for forming SOI wafers |
| US5264395A (en) * | 1992-12-16 | 1993-11-23 | International Business Machines Corporation | Thin SOI layer for fully depleted field effect transistors |
| US5318663A (en) * | 1992-12-23 | 1994-06-07 | International Business Machines Corporation | Method for thinning SOI films having improved thickness uniformity |
| JP3139877B2 (en) * | 1993-04-14 | 2001-03-05 | 株式会社東芝 | Apparatus and method for manufacturing semiconductor device |
| US5433650A (en) * | 1993-05-03 | 1995-07-18 | Motorola, Inc. | Method for polishing a substrate |
| US5310451A (en) * | 1993-08-19 | 1994-05-10 | International Business Machines Corporation | Method of forming an ultra-uniform silicon-on-insulator layer |
| US5395801A (en) * | 1993-09-29 | 1995-03-07 | Micron Semiconductor, Inc. | Chemical-mechanical polishing processes of planarizing insulating layers |
| US5422316A (en) * | 1994-03-18 | 1995-06-06 | Memc Electronic Materials, Inc. | Semiconductor wafer polisher and method |
| US5668045A (en) * | 1994-11-30 | 1997-09-16 | Sibond, L.L.C. | Process for stripping outer edge of BESOI wafers |
| US5494849A (en) * | 1995-03-23 | 1996-02-27 | Si Bond L.L.C. | Single-etch stop process for the manufacture of silicon-on-insulator substrates |
| US5937312A (en) * | 1995-03-23 | 1999-08-10 | Sibond L.L.C. | Single-etch stop process for the manufacture of silicon-on-insulator wafers |
| US6069081A (en) * | 1995-04-28 | 2000-05-30 | International Buiness Machines Corporation | Two-step chemical mechanical polish surface planarization technique |
| JP3230986B2 (en) * | 1995-11-13 | 2001-11-19 | 株式会社東芝 | Polishing method, semiconductor device manufacturing method, and semiconductor manufacturing apparatus. |
| JP3514908B2 (en) * | 1995-11-13 | 2004-04-05 | 株式会社東芝 | Abrasive |
| US5968239A (en) * | 1996-11-12 | 1999-10-19 | Kabushiki Kaisha Toshiba | Polishing slurry |
| US5882987A (en) * | 1997-08-26 | 1999-03-16 | International Business Machines Corporation | Smart-cut process for the production of thin semiconductor material films |
| JP3664987B2 (en) * | 2001-03-14 | 2005-06-29 | シャープ株式会社 | Electron microscope observation sample preparation method and semiconductor device analysis method |
| US20020163072A1 (en) * | 2001-05-01 | 2002-11-07 | Subhash Gupta | Method for bonding wafers to produce stacked integrated circuits |
| US7024756B2 (en) * | 2003-07-30 | 2006-04-11 | Hitachi Global Storage Technologies Netherlands, B.V. | Method of making a perpendicular recording magnetic head pole tip with an etchable adhesion CMP stop layer |
| JP4238097B2 (en) * | 2003-09-04 | 2009-03-11 | Ｔｄｋ株式会社 | Coil parts manufacturing method |
| JP4449076B2 (en) * | 2004-04-16 | 2010-04-14 | セイコーエプソン株式会社 | Manufacturing method of semiconductor device |
| US7829464B2 (en) * | 2006-10-20 | 2010-11-09 | Spansion Llc | Planarization method using hybrid oxide and polysilicon CMP |
| US8017451B2 (en) * | 2008-04-04 | 2011-09-13 | The Charles Stark Draper Laboratory, Inc. | Electronic modules and methods for forming the same |
| US7960247B2 (en) * | 2008-04-04 | 2011-06-14 | The Charles Stark Draper Laboratory, Inc. | Die thinning processes and structures |
| US8273603B2 (en) * | 2008-04-04 | 2012-09-25 | The Charles Stark Draper Laboratory, Inc. | Interposers, electronic modules, and methods for forming the same |
| US8602842B2 (en) * | 2010-03-12 | 2013-12-10 | Wayne O. Duescher | Three-point fixed-spindle floating-platen abrasive system |
| US8647171B2 (en) * | 2010-03-12 | 2014-02-11 | Wayne O. Duescher | Fixed-spindle floating-platen workpiece loader apparatus |
| US8500515B2 (en) * | 2010-03-12 | 2013-08-06 | Wayne O. Duescher | Fixed-spindle and floating-platen abrasive system using spherical mounts |
| US8740668B2 (en) * | 2010-03-12 | 2014-06-03 | Wayne O. Duescher | Three-point spindle-supported floating abrasive platen |
| US9806025B2 (en) * | 2015-12-29 | 2017-10-31 | Globalfoundries Inc. | SOI wafers with buried dielectric layers to prevent Cu diffusion |
Family Cites Families (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3009841A (en) * | 1959-03-06 | 1961-11-21 | Westinghouse Electric Corp | Preparation of semiconductor devices having uniform junctions |
| US3386864A (en) * | 1963-12-09 | 1968-06-04 | Ibm | Semiconductor-metal-semiconductor structure |
| US3740280A (en) * | 1971-05-14 | 1973-06-19 | Rca Corp | Method of making semiconductor device |
| US3979237A (en) * | 1972-04-24 | 1976-09-07 | Harris Corporation | Device isolation in integrated circuits |
| US3911562A (en) * | 1974-01-14 | 1975-10-14 | Signetics Corp | Method of chemical polishing of planar silicon structures having filled grooves therein |
| US4037306A (en) * | 1975-10-02 | 1977-07-26 | Motorola, Inc. | Integrated circuit and method |
| US4057939A (en) * | 1975-12-05 | 1977-11-15 | International Business Machines Corporation | Silicon wafer polishing |
| JPS5534442A (en) * | 1978-08-31 | 1980-03-11 | Fujitsu Ltd | Preparation of semiconductor device |
| DE3072040D1 (en) * | 1979-07-23 | 1987-11-05 | Fujitsu Ltd | Method of manufacturing a semiconductor device wherein first and second layers are formed |
| JPS57134961A (en) * | 1981-02-16 | 1982-08-20 | Nippon Telegr & Teleph Corp <Ntt> | Complementary type mis transistor device |
| JPS5939044A (en) * | 1982-08-26 | 1984-03-03 | Toko Inc | Manufacture of substrate for insulating isolation integrated circuit |
| JPS5982746A (en) * | 1982-11-04 | 1984-05-12 | Toshiba Corp | Electrode wiring method of semiconductor device |
| JPS59129439A (en) * | 1983-01-14 | 1984-07-25 | Nec Corp | Manufacture of substrate for semiconductor device |
| JPS6054450A (en) * | 1983-09-05 | 1985-03-28 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| US4571819A (en) * | 1984-11-01 | 1986-02-25 | Ncr Corporation | Method for forming trench isolation structures |
| JPS61120424A (en) * | 1984-11-16 | 1986-06-07 | Oki Electric Ind Co Ltd | Method of polishing dielectric isolated substrate |
| FR2582445B1 (en) * | 1985-05-21 | 1988-04-08 | Efcis | METHOD FOR MANUFACTURING METAL SILICIDE ELECTRODE MOS TRANSISTORS |
| US4601779A (en) * | 1985-06-24 | 1986-07-22 | International Business Machines Corporation | Method of producing a thin silicon-on-insulator layer |
-
1987
- 1987-03-30 US US07/031,809 patent/US4735679A/en not_active Expired - Lifetime
-
1988
- 1988-01-15 CA CA000556671A patent/CA1247259A/en not_active Expired
- 1988-01-18 JP JP63007091A patent/JP2661089B2/en not_active Expired - Fee Related
- 1988-03-08 EP EP88103610A patent/EP0284840B1/en not_active Expired - Lifetime
- 1988-03-08 DE DE88103610T patent/DE3885637T2/en not_active Expired - Fee Related
Also Published As
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|---|---|
| DE3885637T2 (en) | 1994-05-11 |
| JPS63250853A (en) | 1988-10-18 |
| JP2661089B2 (en) | 1997-10-08 |
| EP0284840A2 (en) | 1988-10-05 |
| DE3885637D1 (en) | 1993-12-23 |
| EP0284840B1 (en) | 1993-11-18 |
| EP0284840A3 (en) | 1990-10-31 |
| US4735679A (en) | 1988-04-05 |
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